drivers/ipack/carriers/tpci200.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * driver for the carrier TEWS TPCI-200
   4  *
   5  * Copyright (C) 2009-2012 CERN (www.cern.ch)
   6  * Author: Nicolas Serafini, EIC2 SA
   7  * Author: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
   8  */
   9
  10 #ifndef _TPCI200_H_
  11 #define _TPCI200_H_
  12
  13 #include <linux/limits.h>
  14 #include <linux/pci.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/swab.h>
  17 #include <linux/io.h>
  18 #include <linux/ipack.h>
  19
  20 #define TPCI200_NB_SLOT               0x4
  21 #define TPCI200_NB_BAR                0x6
  22
  23 #define TPCI200_VENDOR_ID             0x1498
  24 #define TPCI200_DEVICE_ID             0x30C8
  25 #define TPCI200_SUBVENDOR_ID          0x1498
  26 #define TPCI200_SUBDEVICE_ID          0x300A
  27
  28 #define TPCI200_CFG_MEM_BAR           0
  29 #define TPCI200_IP_INTERFACE_BAR      2
  30 #define TPCI200_IO_ID_INT_SPACES_BAR  3
  31 #define TPCI200_MEM16_SPACE_BAR       4
  32 #define TPCI200_MEM8_SPACE_BAR        5
  33
  34 struct tpci200_regs {
  35         __le16  revision;
  36         /* writes to control should occur with the mutex held to protect
  37          * read-modify-write operations */
  38         __le16  control[4];
  39         __le16  reset;
  40         __le16  status;
  41         u8      reserved[242];
  42 } __packed;
  43
  44 #define TPCI200_IFACE_SIZE            0x100
  45
  46 #define TPCI200_IO_SPACE_OFF          0x0000
  47 #define TPCI200_IO_SPACE_INTERVAL     0x0100
  48 #define TPCI200_IO_SPACE_SIZE         0x0080
  49 #define TPCI200_ID_SPACE_OFF          0x0080
  50 #define TPCI200_ID_SPACE_INTERVAL     0x0100
  51 #define TPCI200_ID_SPACE_SIZE         0x0040
  52 #define TPCI200_INT_SPACE_OFF         0x00C0
  53 #define TPCI200_INT_SPACE_INTERVAL    0x0100
  54 #define TPCI200_INT_SPACE_SIZE        0x0040
  55 #define TPCI200_IOIDINT_SIZE          0x0400
  56
  57 #define TPCI200_MEM8_SPACE_INTERVAL   0x00400000
  58 #define TPCI200_MEM8_SPACE_SIZE       0x00400000
  59 #define TPCI200_MEM16_SPACE_INTERVAL  0x00800000
  60 #define TPCI200_MEM16_SPACE_SIZE      0x00800000
  61
  62 /* control field in tpci200_regs */
  63 #define TPCI200_INT0_EN               0x0040
  64 #define TPCI200_INT1_EN               0x0080
  65 #define TPCI200_INT0_EDGE             0x0010
  66 #define TPCI200_INT1_EDGE             0x0020
  67 #define TPCI200_ERR_INT_EN            0x0008
  68 #define TPCI200_TIME_INT_EN           0x0004
  69 #define TPCI200_RECOVER_EN            0x0002
  70 #define TPCI200_CLK32                 0x0001
  71
  72 /* reset field in tpci200_regs */
  73 #define TPCI200_A_RESET               0x0001
  74 #define TPCI200_B_RESET               0x0002
  75 #define TPCI200_C_RESET               0x0004
  76 #define TPCI200_D_RESET               0x0008
  77
  78 /* status field in tpci200_regs */
  79 #define TPCI200_A_TIMEOUT             0x1000
  80 #define TPCI200_B_TIMEOUT             0x2000
  81 #define TPCI200_C_TIMEOUT             0x4000
  82 #define TPCI200_D_TIMEOUT             0x8000
  83
  84 #define TPCI200_A_ERROR               0x0100
  85 #define TPCI200_B_ERROR               0x0200
  86 #define TPCI200_C_ERROR               0x0400
  87 #define TPCI200_D_ERROR               0x0800
  88
  89 #define TPCI200_A_INT0                0x0001
  90 #define TPCI200_A_INT1                0x0002
  91 #define TPCI200_B_INT0                0x0004
  92 #define TPCI200_B_INT1                0x0008
  93 #define TPCI200_C_INT0                0x0010
  94 #define TPCI200_C_INT1                0x0020
  95 #define TPCI200_D_INT0                0x0040
  96 #define TPCI200_D_INT1                0x0080
  97
  98 #define TPCI200_SLOT_INT_MASK         0x00FF
  99
 100 /* PCI Configuration registers. The PCI bridge is a PLX Technology PCI9030. */
 101 #define LAS1_DESC                     0x2C
 102 #define LAS2_DESC                     0x30
 103
 104 /* Bits in the LAS?_DESC registers */
 105 #define LAS_BIT_BIGENDIAN             24
 106
 107 #define VME_IOID_SPACE  "IOID"
 108 #define VME_MEM_SPACE  "MEM"
 109
 110 /**
 111  * struct slot_irq - slot IRQ definition.
 112  * @vector      Vector number
 113  * @handler     Handler called when IRQ arrives
 114  * @arg         Handler argument
 115  *
 116  */
 117 struct slot_irq {
 118         struct ipack_device *holder;
 119         int             vector;
 120         irqreturn_t     (*handler)(void *);
 121         void            *arg;
 122 };
 123
 124 /**
 125  * struct tpci200_slot - data specific to the tpci200 slot.
 126  * @slot_id     Slot identification gived to external interface
 127  * @irq         Slot IRQ infos
 128  * @io_phys     IO physical base address register of the slot
 129  * @id_phys     ID physical base address register of the slot
 130  * @int_phys    INT physical base address register of the slot
 131  * @mem_phys    MEM physical base address register of the slot
 132  *
 133  */
 134 struct tpci200_slot {
 135         struct slot_irq     *irq;
 136 };
 137
 138 /**
 139  * struct tpci200_infos - informations specific of the TPCI200 tpci200.
 140  * @pci_dev             PCI device
 141  * @interface_regs      Pointer to IP interface space (Bar 2)
 142  * @ioidint_space       Pointer to IP ID, IO and INT space (Bar 3)
 143  * @mem8_space          Pointer to MEM space (Bar 4)
 144  *
 145  */
 146 struct tpci200_infos {
 147         struct pci_dev                  *pdev;
 148         struct pci_device_id            *id_table;
 149         struct tpci200_regs __iomem     *interface_regs;
 150         void __iomem                    *cfg_regs;
 151         struct ipack_bus_device         *ipack_bus;
 152 };
 153 struct tpci200_board {
 154         unsigned int            number;
 155         struct mutex            mutex;
 156         spinlock_t              regs_lock;
 157         struct tpci200_slot     *slots;
 158         struct tpci200_infos    *info;
 159         phys_addr_t             mod_mem[IPACK_SPACE_COUNT];
 160 };
 161
 162 #endif /* _TPCI200_H_ */