1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016,2017 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
7 #include <linux/interrupt.h>
9 #include <linux/irqdomain.h>
10 #include <linux/msi.h>
11 #include <linux/pid.h>
12 #include <linux/sched.h>
14 #include <linux/irqchip/arm-gic-v4.h>
17 * WARNING: The blurb below assumes that you understand the
18 * intricacies of GICv3, GICv4, and how a guest's view of a GICv3 gets
19 * translated into GICv4 commands. So it effectively targets at most
20 * two individuals. You know who you are.
22 * The core GICv4 code is designed to *avoid* exposing too much of the
23 * core GIC code (that would in turn leak into the hypervisor code),
24 * and instead provide a hypervisor agnostic interface to the HW (of
25 * course, the astute reader will quickly realize that hypervisor
26 * agnostic actually means KVM-specific - what were you thinking?).
28 * In order to achieve a modicum of isolation, we try to hide most of
29 * the GICv4 "stuff" behind normal irqchip operations:
31 * - Any guest-visible VLPI is backed by a Linux interrupt (and a
32 * physical LPI which gets unmapped when the guest maps the
33 * VLPI). This allows the same DevID/EventID pair to be either
34 * mapped to the LPI (host) or the VLPI (guest). Note that this is
35 * exclusive, and you cannot have both.
37 * - Enabling/disabling a VLPI is done by issuing mask/unmask calls.
39 * - Guest INT/CLEAR commands are implemented through
40 * irq_set_irqchip_state().
42 * - The *bizarre* stuff (mapping/unmapping an interrupt to a VLPI, or
43 * issuing an INV after changing a priority) gets shoved into the
44 * irq_set_vcpu_affinity() method. While this is quite horrible
45 * (let's face it, this is the irqchip version of an ioctl), it
46 * confines the crap to a single location. And map/unmap really is
47 * about setting the affinity of a VLPI to a vcpu, so only INV is
48 * majorly out of place. So there.
50 * A number of commands are simply not provided by this interface, as
51 * they do not make direct sense. For example, MAPD is purely local to
52 * the virtual ITS (because it references a virtual device, and the
53 * physical ITS is still very much in charge of the physical
54 * device). Same goes for things like MAPC (the physical ITS deals
55 * with the actual vPE affinity, and not the braindead concept of
56 * collection). SYNC is not provided either, as each and every command
57 * is followed by a VSYNC. This could be relaxed in the future, should
58 * this be seen as a bottleneck (yes, this means *never*).
60 * But handling VLPIs is only one side of the job of the GICv4
61 * code. The other (darker) side is to take care of the doorbell
62 * interrupts which are delivered when a VLPI targeting a non-running
63 * vcpu is being made pending.
65 * The choice made here is that each vcpu (VPE in old northern GICv4
66 * dialect) gets a single doorbell LPI, no matter how many interrupts
67 * are targeting it. This has a nice property, which is that the
68 * interrupt becomes a handle for the VPE, and that the hypervisor
69 * code can manipulate it through the normal interrupt API:
71 * - VMs (or rather the VM abstraction that matters to the GIC)
72 * contain an irq domain where each interrupt maps to a VPE. In
73 * turn, this domain sits on top of the normal LPI allocator, and a
74 * specially crafted irq_chip implementation.
76 * - mask/unmask do what is expected on the doorbell interrupt.
78 * - irq_set_affinity is used to move a VPE from one redistributor to
81 * - irq_set_vcpu_affinity once again gets hijacked for the purpose of
82 * creating a new sub-API, namely scheduling/descheduling a VPE
83 * (which involves programming GICR_V{PROP,PEND}BASER) and
84 * performing INVALL operations.
87 static struct irq_domain
*gic_domain
;
88 static const struct irq_domain_ops
*vpe_domain_ops
;
89 static const struct irq_domain_ops
*sgi_domain_ops
;
92 #include <asm/cpufeature.h>
94 bool gic_cpuif_has_vsgi(void)
96 unsigned long fld
, reg
= read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1
);
98 fld
= cpuid_feature_extract_unsigned_field(reg
, ID_AA64PFR0_EL1_GIC_SHIFT
);
100 return fld
>= ID_AA64PFR0_EL1_GIC_V4P1
;
103 bool gic_cpuif_has_vsgi(void)
109 static bool has_v4_1(void)
111 return !!sgi_domain_ops
;
114 static bool has_v4_1_sgi(void)
116 return has_v4_1() && gic_cpuif_has_vsgi();
119 static int its_alloc_vcpu_sgis(struct its_vpe
*vpe
, int idx
)
127 name
= kasprintf(GFP_KERNEL
, "GICv4-sgi-%d", task_pid_nr(current
));
131 vpe
->fwnode
= irq_domain_alloc_named_id_fwnode(name
, idx
);
138 vpe
->sgi_domain
= irq_domain_create_linear(vpe
->fwnode
, 16,
139 sgi_domain_ops
, vpe
);
140 if (!vpe
->sgi_domain
)
143 sgi_base
= irq_domain_alloc_irqs(vpe
->sgi_domain
, 16, NUMA_NO_NODE
, vpe
);
151 irq_domain_remove(vpe
->sgi_domain
);
153 irq_domain_free_fwnode(vpe
->fwnode
);
158 int its_alloc_vcpu_irqs(struct its_vm
*vm
)
162 vm
->fwnode
= irq_domain_alloc_named_id_fwnode("GICv4-vpe",
163 task_pid_nr(current
));
167 vm
->domain
= irq_domain_create_hierarchy(gic_domain
, 0, vm
->nr_vpes
,
168 vm
->fwnode
, vpe_domain_ops
,
173 for (i
= 0; i
< vm
->nr_vpes
; i
++) {
174 vm
->vpes
[i
]->its_vm
= vm
;
175 vm
->vpes
[i
]->idai
= true;
178 vpe_base_irq
= irq_domain_alloc_irqs(vm
->domain
, vm
->nr_vpes
,
180 if (vpe_base_irq
<= 0)
183 for (i
= 0; i
< vm
->nr_vpes
; i
++) {
185 vm
->vpes
[i
]->irq
= vpe_base_irq
+ i
;
186 ret
= its_alloc_vcpu_sgis(vm
->vpes
[i
], i
);
195 irq_domain_remove(vm
->domain
);
197 irq_domain_free_fwnode(vm
->fwnode
);
202 static void its_free_sgi_irqs(struct its_vm
*vm
)
209 for (i
= 0; i
< vm
->nr_vpes
; i
++) {
210 unsigned int irq
= irq_find_mapping(vm
->vpes
[i
]->sgi_domain
, 0);
215 irq_domain_free_irqs(irq
, 16);
216 irq_domain_remove(vm
->vpes
[i
]->sgi_domain
);
217 irq_domain_free_fwnode(vm
->vpes
[i
]->fwnode
);
221 void its_free_vcpu_irqs(struct its_vm
*vm
)
223 its_free_sgi_irqs(vm
);
224 irq_domain_free_irqs(vm
->vpes
[0]->irq
, vm
->nr_vpes
);
225 irq_domain_remove(vm
->domain
);
226 irq_domain_free_fwnode(vm
->fwnode
);
229 static int its_send_vpe_cmd(struct its_vpe
*vpe
, struct its_cmd_info
*info
)
231 return irq_set_vcpu_affinity(vpe
->irq
, info
);
234 int its_make_vpe_non_resident(struct its_vpe
*vpe
, bool db
)
236 struct irq_desc
*desc
= irq_to_desc(vpe
->irq
);
237 struct its_cmd_info info
= { };
240 WARN_ON(preemptible());
242 info
.cmd_type
= DESCHEDULE_VPE
;
244 /* GICv4.1 can directly deal with doorbells */
247 /* Undo the nested disable_irq() calls... */
248 while (db
&& irqd_irq_disabled(&desc
->irq_data
))
249 enable_irq(vpe
->irq
);
252 ret
= its_send_vpe_cmd(vpe
, &info
);
254 vpe
->resident
= false;
261 int its_make_vpe_resident(struct its_vpe
*vpe
, bool g0en
, bool g1en
)
263 struct its_cmd_info info
= { };
266 WARN_ON(preemptible());
268 info
.cmd_type
= SCHEDULE_VPE
;
273 /* Disabled the doorbell, as we're about to enter the guest */
274 disable_irq_nosync(vpe
->irq
);
277 ret
= its_send_vpe_cmd(vpe
, &info
);
279 vpe
->resident
= true;
284 int its_commit_vpe(struct its_vpe
*vpe
)
286 struct its_cmd_info info
= {
287 .cmd_type
= COMMIT_VPE
,
291 WARN_ON(preemptible());
293 ret
= its_send_vpe_cmd(vpe
, &info
);
301 int its_invall_vpe(struct its_vpe
*vpe
)
303 struct its_cmd_info info
= {
304 .cmd_type
= INVALL_VPE
,
307 return its_send_vpe_cmd(vpe
, &info
);
310 int its_map_vlpi(int irq
, struct its_vlpi_map
*map
)
312 struct its_cmd_info info
= {
313 .cmd_type
= MAP_VLPI
,
321 * The host will never see that interrupt firing again, so it
322 * is vital that we don't do any lazy masking.
324 irq_set_status_flags(irq
, IRQ_DISABLE_UNLAZY
);
326 ret
= irq_set_vcpu_affinity(irq
, &info
);
328 irq_clear_status_flags(irq
, IRQ_DISABLE_UNLAZY
);
333 int its_get_vlpi(int irq
, struct its_vlpi_map
*map
)
335 struct its_cmd_info info
= {
336 .cmd_type
= GET_VLPI
,
342 return irq_set_vcpu_affinity(irq
, &info
);
345 int its_unmap_vlpi(int irq
)
347 irq_clear_status_flags(irq
, IRQ_DISABLE_UNLAZY
);
348 return irq_set_vcpu_affinity(irq
, NULL
);
351 int its_prop_update_vlpi(int irq
, u8 config
, bool inv
)
353 struct its_cmd_info info
= {
354 .cmd_type
= inv
? PROP_UPDATE_AND_INV_VLPI
: PROP_UPDATE_VLPI
,
360 return irq_set_vcpu_affinity(irq
, &info
);
363 int its_prop_update_vsgi(int irq
, u8 priority
, bool group
)
365 struct its_cmd_info info
= {
366 .cmd_type
= PROP_UPDATE_VSGI
,
368 .priority
= priority
,
373 return irq_set_vcpu_affinity(irq
, &info
);
376 int its_init_v4(struct irq_domain
*domain
,
377 const struct irq_domain_ops
*vpe_ops
,
378 const struct irq_domain_ops
*sgi_ops
)
381 pr_info("ITS: Enabling GICv4 support\n");
383 vpe_domain_ops
= vpe_ops
;
384 sgi_domain_ops
= sgi_ops
;
388 pr_err("ITS: No GICv4 VPE domain allocated\n");