drivers/irqchip/irq-loongarch-cpu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
   4  */
   5
   6 #include <linux/init.h>
   7 #include <linux/kernel.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/irq.h>
  10 #include <linux/irqchip.h>
  11 #include <linux/irqdomain.h>
  12
  13 #include <asm/loongarch.h>
  14 #include <asm/setup.h>
  15
  16 #include "irq-loongson.h"
  17
  18 static struct irq_domain *irq_domain;
  19 struct fwnode_handle *cpuintc_handle;
  20
  21 static u32 lpic_gsi_to_irq(u32 gsi)
  22 {
  23         int irq = 0;
  24
  25         /* Only pch irqdomain transferring is required for LoongArch. */
  26         if (gsi >= GSI_MIN_PCH_IRQ && gsi <= GSI_MAX_PCH_IRQ)
  27                 irq = acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH);
  28
  29         return (irq > 0) ? irq : 0;
  30 }
  31
  32 static struct fwnode_handle *lpic_get_gsi_domain_id(u32 gsi)
  33 {
  34         int id;
  35         struct fwnode_handle *domain_handle = NULL;
  36
  37         switch (gsi) {
  38         case GSI_MIN_CPU_IRQ ... GSI_MAX_CPU_IRQ:
  39                 if (liointc_handle)
  40                         domain_handle = liointc_handle;
  41                 break;
  42
  43         case GSI_MIN_LPC_IRQ ... GSI_MAX_LPC_IRQ:
  44                 if (pch_lpc_handle)
  45                         domain_handle = pch_lpc_handle;
  46                 break;
  47
  48         case GSI_MIN_PCH_IRQ ... GSI_MAX_PCH_IRQ:
  49                 id = find_pch_pic(gsi);
  50                 if (id >= 0 && pch_pic_handle[id])
  51                         domain_handle = pch_pic_handle[id];
  52                 break;
  53         }
  54
  55         return domain_handle;
  56 }
  57
  58 static void mask_loongarch_irq(struct irq_data *d)
  59 {
  60         clear_csr_ecfg(ECFGF(d->hwirq));
  61 }
  62
  63 static void unmask_loongarch_irq(struct irq_data *d)
  64 {
  65         set_csr_ecfg(ECFGF(d->hwirq));
  66 }
  67
  68 static struct irq_chip cpu_irq_controller = {
  69         .name           = "CPUINTC",
  70         .irq_mask       = mask_loongarch_irq,
  71         .irq_unmask     = unmask_loongarch_irq,
  72 };
  73
  74 static void handle_cpu_irq(struct pt_regs *regs)
  75 {
  76         int hwirq;
  77         unsigned int estat = read_csr_estat() & CSR_ESTAT_IS;
  78
  79         while ((hwirq = ffs(estat))) {
  80                 estat &= ~BIT(hwirq - 1);
  81                 generic_handle_domain_irq(irq_domain, hwirq - 1);
  82         }
  83 }
  84
  85 static int loongarch_cpu_intc_map(struct irq_domain *d, unsigned int irq,
  86                              irq_hw_number_t hwirq)
  87 {
  88         irq_set_noprobe(irq);
  89         irq_set_chip_and_handler(irq, &cpu_irq_controller, handle_percpu_irq);
  90
  91         return 0;
  92 }
  93
  94 static const struct irq_domain_ops loongarch_cpu_intc_irq_domain_ops = {
  95         .map = loongarch_cpu_intc_map,
  96         .xlate = irq_domain_xlate_onecell,
  97 };
  98
  99 #ifdef CONFIG_OF
 100 static int __init cpuintc_of_init(struct device_node *of_node,
 101                                 struct device_node *parent)
 102 {
 103         cpuintc_handle = of_node_to_fwnode(of_node);
 104
 105         irq_domain = irq_domain_create_linear(cpuintc_handle, EXCCODE_INT_NUM,
 106                                 &loongarch_cpu_intc_irq_domain_ops, NULL);
 107         if (!irq_domain)
 108                 panic("Failed to add irqdomain for loongarch CPU");
 109
 110         set_handle_irq(&handle_cpu_irq);
 111
 112         return 0;
 113 }
 114 IRQCHIP_DECLARE(cpu_intc, "loongson,cpu-interrupt-controller", cpuintc_of_init);
 115 #endif
 116
 117 static int __init liointc_parse_madt(union acpi_subtable_headers *header,
 118                                         const unsigned long end)
 119 {
 120         struct acpi_madt_lio_pic *liointc_entry = (struct acpi_madt_lio_pic *)header;
 121
 122         return liointc_acpi_init(irq_domain, liointc_entry);
 123 }
 124
 125 static int __init eiointc_parse_madt(union acpi_subtable_headers *header,
 126                                         const unsigned long end)
 127 {
 128         struct acpi_madt_eio_pic *eiointc_entry = (struct acpi_madt_eio_pic *)header;
 129
 130         return eiointc_acpi_init(irq_domain, eiointc_entry);
 131 }
 132
 133 static int __init acpi_cascade_irqdomain_init(void)
 134 {
 135         int r;
 136
 137         r = acpi_table_parse_madt(ACPI_MADT_TYPE_LIO_PIC, liointc_parse_madt, 0);
 138         if (r < 0)
 139                 return r;
 140
 141         r = acpi_table_parse_madt(ACPI_MADT_TYPE_EIO_PIC, eiointc_parse_madt, 0);
 142         if (r < 0)
 143                 return r;
 144
 145         if (cpu_has_avecint)
 146                 r = avecintc_acpi_init(irq_domain);
 147
 148         return r;
 149 }
 150
 151 static int __init cpuintc_acpi_init(union acpi_subtable_headers *header,
 152                                    const unsigned long end)
 153 {
 154         int ret;
 155
 156         if (irq_domain)
 157                 return 0;
 158
 159         /* Mask interrupts. */
 160         clear_csr_ecfg(ECFG0_IM);
 161         clear_csr_estat(ESTATF_IP);
 162
 163         cpuintc_handle = irq_domain_alloc_named_fwnode("CPUINTC");
 164         irq_domain = irq_domain_create_linear(cpuintc_handle, EXCCODE_INT_NUM,
 165                                         &loongarch_cpu_intc_irq_domain_ops, NULL);
 166
 167         if (!irq_domain)
 168                 panic("Failed to add irqdomain for LoongArch CPU");
 169
 170         set_handle_irq(&handle_cpu_irq);
 171         acpi_set_irq_model(ACPI_IRQ_MODEL_LPIC, lpic_get_gsi_domain_id);
 172         acpi_set_gsi_to_irq_fallback(lpic_gsi_to_irq);
 173         ret = acpi_cascade_irqdomain_init();
 174
 175         return ret;
 176 }
 177
 178 IRQCHIP_ACPI_DECLARE(cpuintc_v1, ACPI_MADT_TYPE_CORE_PIC,
 179                 NULL, ACPI_MADT_CORE_PIC_VERSION_V1, cpuintc_acpi_init);