drivers/irqchip/irq-loongson-htvec.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
   4  *  Loongson HyperTransport Interrupt Vector support
   5  */
   6
   7 #define pr_fmt(fmt) "htvec: " fmt
   8
   9 #include <linux/interrupt.h>
  10 #include <linux/irq.h>
  11 #include <linux/irqchip.h>
  12 #include <linux/irqdomain.h>
  13 #include <linux/irqchip/chained_irq.h>
  14 #include <linux/kernel.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/syscore_ops.h>
  19
  20 #include "irq-loongson.h"
  21
  22 /* Registers */
  23 #define HTVEC_EN_OFF            0x20
  24 #define HTVEC_MAX_PARENT_IRQ    8
  25 #define VEC_COUNT_PER_REG       32
  26 #define VEC_REG_IDX(irq_id)     ((irq_id) / VEC_COUNT_PER_REG)
  27 #define VEC_REG_BIT(irq_id)     ((irq_id) % VEC_COUNT_PER_REG)
  28
  29 struct htvec {
  30         int                     num_parents;
  31         void __iomem            *base;
  32         struct irq_domain       *htvec_domain;
  33         raw_spinlock_t          htvec_lock;
  34         u32                     saved_vec_en[HTVEC_MAX_PARENT_IRQ];
  35 };
  36
  37 static struct htvec *htvec_priv;
  38
  39 static void htvec_irq_dispatch(struct irq_desc *desc)
  40 {
  41         int i;
  42         u32 pending;
  43         bool handled = false;
  44         struct irq_chip *chip = irq_desc_get_chip(desc);
  45         struct htvec *priv = irq_desc_get_handler_data(desc);
  46
  47         chained_irq_enter(chip, desc);
  48
  49         for (i = 0; i < priv->num_parents; i++) {
  50                 pending = readl(priv->base + 4 * i);
  51                 while (pending) {
  52                         int bit = __ffs(pending);
  53
  54                         generic_handle_domain_irq(priv->htvec_domain,
  55                                                   bit + VEC_COUNT_PER_REG * i);
  56                         pending &= ~BIT(bit);
  57                         handled = true;
  58                 }
  59         }
  60
  61         if (!handled)
  62                 spurious_interrupt();
  63
  64         chained_irq_exit(chip, desc);
  65 }
  66
  67 static void htvec_ack_irq(struct irq_data *d)
  68 {
  69         struct htvec *priv = irq_data_get_irq_chip_data(d);
  70
  71         writel(BIT(VEC_REG_BIT(d->hwirq)),
  72                priv->base + VEC_REG_IDX(d->hwirq) * 4);
  73 }
  74
  75 static void htvec_mask_irq(struct irq_data *d)
  76 {
  77         u32 reg;
  78         void __iomem *addr;
  79         struct htvec *priv = irq_data_get_irq_chip_data(d);
  80
  81         raw_spin_lock(&priv->htvec_lock);
  82         addr = priv->base + HTVEC_EN_OFF;
  83         addr += VEC_REG_IDX(d->hwirq) * 4;
  84         reg = readl(addr);
  85         reg &= ~BIT(VEC_REG_BIT(d->hwirq));
  86         writel(reg, addr);
  87         raw_spin_unlock(&priv->htvec_lock);
  88 }
  89
  90 static void htvec_unmask_irq(struct irq_data *d)
  91 {
  92         u32 reg;
  93         void __iomem *addr;
  94         struct htvec *priv = irq_data_get_irq_chip_data(d);
  95
  96         raw_spin_lock(&priv->htvec_lock);
  97         addr = priv->base + HTVEC_EN_OFF;
  98         addr += VEC_REG_IDX(d->hwirq) * 4;
  99         reg = readl(addr);
 100         reg |= BIT(VEC_REG_BIT(d->hwirq));
 101         writel(reg, addr);
 102         raw_spin_unlock(&priv->htvec_lock);
 103 }
 104
 105 static struct irq_chip htvec_irq_chip = {
 106         .name                   = "LOONGSON_HTVEC",
 107         .irq_mask               = htvec_mask_irq,
 108         .irq_unmask             = htvec_unmask_irq,
 109         .irq_ack                = htvec_ack_irq,
 110 };
 111
 112 static int htvec_domain_alloc(struct irq_domain *domain, unsigned int virq,
 113                               unsigned int nr_irqs, void *arg)
 114 {
 115         int ret;
 116         unsigned long hwirq;
 117         unsigned int type, i;
 118         struct htvec *priv = domain->host_data;
 119
 120         ret = irq_domain_translate_onecell(domain, arg, &hwirq, &type);
 121         if (ret)
 122                 return ret;
 123
 124         for (i = 0; i < nr_irqs; i++) {
 125                 irq_domain_set_info(domain, virq + i, hwirq + i, &htvec_irq_chip,
 126                                     priv, handle_edge_irq, NULL, NULL);
 127         }
 128
 129         return 0;
 130 }
 131
 132 static void htvec_domain_free(struct irq_domain *domain, unsigned int virq,
 133                                   unsigned int nr_irqs)
 134 {
 135         int i;
 136
 137         for (i = 0; i < nr_irqs; i++) {
 138                 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
 139
 140                 irq_set_handler(virq + i, NULL);
 141                 irq_domain_reset_irq_data(d);
 142         }
 143 }
 144
 145 static const struct irq_domain_ops htvec_domain_ops = {
 146         .translate      = irq_domain_translate_onecell,
 147         .alloc          = htvec_domain_alloc,
 148         .free           = htvec_domain_free,
 149 };
 150
 151 static void htvec_reset(struct htvec *priv)
 152 {
 153         u32 idx;
 154
 155         /* Clear IRQ cause registers, mask all interrupts */
 156         for (idx = 0; idx < priv->num_parents; idx++) {
 157                 writel_relaxed(0x0, priv->base + HTVEC_EN_OFF + 4 * idx);
 158                 writel_relaxed(0xFFFFFFFF, priv->base + 4 * idx);
 159         }
 160 }
 161
 162 static int htvec_suspend(void)
 163 {
 164         int i;
 165
 166         for (i = 0; i < htvec_priv->num_parents; i++)
 167                 htvec_priv->saved_vec_en[i] = readl(htvec_priv->base + HTVEC_EN_OFF + 4 * i);
 168
 169         return 0;
 170 }
 171
 172 static void htvec_resume(void)
 173 {
 174         int i;
 175
 176         for (i = 0; i < htvec_priv->num_parents; i++)
 177                 writel(htvec_priv->saved_vec_en[i], htvec_priv->base + HTVEC_EN_OFF + 4 * i);
 178 }
 179
 180 static struct syscore_ops htvec_syscore_ops = {
 181         .suspend = htvec_suspend,
 182         .resume = htvec_resume,
 183 };
 184
 185 static int htvec_init(phys_addr_t addr, unsigned long size,
 186                 int num_parents, int parent_irq[], struct fwnode_handle *domain_handle)
 187 {
 188         int i;
 189         struct htvec *priv;
 190
 191         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 192         if (!priv)
 193                 return -ENOMEM;
 194
 195         priv->num_parents = num_parents;
 196         priv->base = ioremap(addr, size);
 197         raw_spin_lock_init(&priv->htvec_lock);
 198
 199         /* Setup IRQ domain */
 200         priv->htvec_domain = irq_domain_create_linear(domain_handle,
 201                                         (VEC_COUNT_PER_REG * priv->num_parents),
 202                                         &htvec_domain_ops, priv);
 203         if (!priv->htvec_domain) {
 204                 pr_err("loongson-htvec: cannot add IRQ domain\n");
 205                 goto iounmap_base;
 206         }
 207
 208         htvec_reset(priv);
 209
 210         for (i = 0; i < priv->num_parents; i++) {
 211                 irq_set_chained_handler_and_data(parent_irq[i],
 212                                                  htvec_irq_dispatch, priv);
 213         }
 214
 215         htvec_priv = priv;
 216
 217         register_syscore_ops(&htvec_syscore_ops);
 218
 219         return 0;
 220
 221 iounmap_base:
 222         iounmap(priv->base);
 223         kfree(priv);
 224
 225         return -EINVAL;
 226 }
 227
 228 #ifdef CONFIG_OF
 229
 230 static int htvec_of_init(struct device_node *node,
 231                                 struct device_node *parent)
 232 {
 233         int i, err;
 234         int parent_irq[8];
 235         int num_parents = 0;
 236         struct resource res;
 237
 238         if (of_address_to_resource(node, 0, &res))
 239                 return -EINVAL;
 240
 241         /* Interrupt may come from any of the 8 interrupt lines */
 242         for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++) {
 243                 parent_irq[i] = irq_of_parse_and_map(node, i);
 244                 if (parent_irq[i] <= 0)
 245                         break;
 246
 247                 num_parents++;
 248         }
 249
 250         err = htvec_init(res.start, resource_size(&res),
 251                         num_parents, parent_irq, of_node_to_fwnode(node));
 252         if (err < 0)
 253                 return err;
 254
 255         return 0;
 256 }
 257
 258 IRQCHIP_DECLARE(htvec, "loongson,htvec-1.0", htvec_of_init);
 259
 260 #endif
 261
 262 #ifdef CONFIG_ACPI
 263 static int __init pch_pic_parse_madt(union acpi_subtable_headers *header,
 264                                         const unsigned long end)
 265 {
 266         struct acpi_madt_bio_pic *pchpic_entry = (struct acpi_madt_bio_pic *)header;
 267
 268         return pch_pic_acpi_init(htvec_priv->htvec_domain, pchpic_entry);
 269 }
 270
 271 static int __init pch_msi_parse_madt(union acpi_subtable_headers *header,
 272                                         const unsigned long end)
 273 {
 274         struct acpi_madt_msi_pic *pchmsi_entry = (struct acpi_madt_msi_pic *)header;
 275
 276         return pch_msi_acpi_init(htvec_priv->htvec_domain, pchmsi_entry);
 277 }
 278
 279 static int __init acpi_cascade_irqdomain_init(void)
 280 {
 281         int r;
 282
 283         r = acpi_table_parse_madt(ACPI_MADT_TYPE_BIO_PIC, pch_pic_parse_madt, 0);
 284         if (r < 0)
 285                 return r;
 286
 287         r = acpi_table_parse_madt(ACPI_MADT_TYPE_MSI_PIC, pch_msi_parse_madt, 0);
 288         if (r < 0)
 289                 return r;
 290
 291         return 0;
 292 }
 293
 294 int __init htvec_acpi_init(struct irq_domain *parent,
 295                                    struct acpi_madt_ht_pic *acpi_htvec)
 296 {
 297         int i, ret;
 298         int num_parents, parent_irq[8];
 299         struct fwnode_handle *domain_handle;
 300
 301         if (!acpi_htvec)
 302                 return -EINVAL;
 303
 304         num_parents = HTVEC_MAX_PARENT_IRQ;
 305
 306         domain_handle = irq_domain_alloc_fwnode(&acpi_htvec->address);
 307         if (!domain_handle) {
 308                 pr_err("Unable to allocate domain handle\n");
 309                 return -ENOMEM;
 310         }
 311
 312         /* Interrupt may come from any of the 8 interrupt lines */
 313         for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++)
 314                 parent_irq[i] = irq_create_mapping(parent, acpi_htvec->cascade[i]);
 315
 316         ret = htvec_init(acpi_htvec->address, acpi_htvec->size,
 317                         num_parents, parent_irq, domain_handle);
 318
 319         if (ret == 0)
 320                 ret = acpi_cascade_irqdomain_init();
 321         else
 322                 irq_domain_free_fwnode(domain_handle);
 323
 324         return ret;
 325 }
 326
 327 #endif