drivers/irqchip/irq-meson-gpio.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 Endless Mobile, Inc.
   4  * Author: Carlo Caione <carlo@endlessm.com>
   5  * Copyright (c) 2016 BayLibre, SAS.
   6  * Author: Jerome Brunet <jbrunet@baylibre.com>
   7  */
   8
   9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10
  11 #include <linux/io.h>
  12 #include <linux/module.h>
  13 #include <linux/irq.h>
  14 #include <linux/irqdomain.h>
  15 #include <linux/irqchip.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18
  19 #define MAX_NUM_CHANNEL 64
  20 #define MAX_INPUT_MUX 256
  21
  22 #define REG_EDGE_POL    0x00
  23 #define REG_PIN_03_SEL  0x04
  24 #define REG_PIN_47_SEL  0x08
  25 #define REG_FILTER_SEL  0x0c
  26
  27 /* use for A1 like chips */
  28 #define REG_PIN_A1_SEL  0x04
  29 /* Used for s4 chips */
  30 #define REG_EDGE_POL_S4 0x1c
  31
  32 /*
  33  * Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by
  34  * bits 24 to 31. Tests on the actual HW show that these bits are
  35  * stuck at 0. Bits 8 to 15 are responsive and have the expected
  36  * effect.
  37  */
  38 #define REG_EDGE_POL_EDGE(params, x)    BIT((params)->edge_single_offset + (x))
  39 #define REG_EDGE_POL_LOW(params, x)     BIT((params)->pol_low_offset + (x))
  40 #define REG_BOTH_EDGE(params, x)        BIT((params)->edge_both_offset + (x))
  41 #define REG_EDGE_POL_MASK(params, x)    (       \
  42                 REG_EDGE_POL_EDGE(params, x) |  \
  43                 REG_EDGE_POL_LOW(params, x)  |  \
  44                 REG_BOTH_EDGE(params, x))
  45 #define REG_PIN_SEL_SHIFT(x)    (((x) % 4) * 8)
  46 #define REG_FILTER_SEL_SHIFT(x) ((x) * 4)
  47
  48 struct meson_gpio_irq_controller;
  49 static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
  50                                     unsigned int channel, unsigned long hwirq);
  51 static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl);
  52 static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
  53                                       unsigned int channel,
  54                                       unsigned long hwirq);
  55 static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl);
  56 static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
  57                                     unsigned int type, u32 *channel_hwirq);
  58 static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
  59                                       unsigned int type, u32 *channel_hwirq);
  60
  61 struct irq_ctl_ops {
  62         void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
  63                                  unsigned int channel, unsigned long hwirq);
  64         void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl);
  65         int (*gpio_irq_set_type)(struct meson_gpio_irq_controller *ctl,
  66                                  unsigned int type, u32 *channel_hwirq);
  67 };
  68
  69 struct meson_gpio_irq_params {
  70         unsigned int nr_hwirq;
  71         unsigned int nr_channels;
  72         bool support_edge_both;
  73         unsigned int edge_both_offset;
  74         unsigned int edge_single_offset;
  75         unsigned int pol_low_offset;
  76         unsigned int pin_sel_mask;
  77         struct irq_ctl_ops ops;
  78 };
  79
  80 #define INIT_MESON_COMMON(irqs, init, sel, type)                \
  81         .nr_hwirq = irqs,                                       \
  82         .ops = {                                                \
  83                 .gpio_irq_init = init,                          \
  84                 .gpio_irq_sel_pin = sel,                        \
  85                 .gpio_irq_set_type = type,                      \
  86         },
  87
  88 #define INIT_MESON8_COMMON_DATA(irqs)                           \
  89         INIT_MESON_COMMON(irqs, meson_gpio_irq_init_dummy,      \
  90                           meson8_gpio_irq_sel_pin,              \
  91                           meson8_gpio_irq_set_type)             \
  92         .edge_single_offset = 0,                                \
  93         .pol_low_offset = 16,                                   \
  94         .pin_sel_mask = 0xff,                                   \
  95         .nr_channels = 8,                                       \
  96
  97 #define INIT_MESON_A1_COMMON_DATA(irqs)                         \
  98         INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init,         \
  99                           meson_a1_gpio_irq_sel_pin,            \
 100                           meson8_gpio_irq_set_type)             \
 101         .support_edge_both = true,                              \
 102         .edge_both_offset = 16,                                 \
 103         .edge_single_offset = 8,                                \
 104         .pol_low_offset = 0,                                    \
 105         .pin_sel_mask = 0x7f,                                   \
 106         .nr_channels = 8,                                       \
 107
 108 #define INIT_MESON_S4_COMMON_DATA(irqs)                         \
 109         INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init,         \
 110                           meson_a1_gpio_irq_sel_pin,            \
 111                           meson_s4_gpio_irq_set_type)           \
 112         .support_edge_both = true,                              \
 113         .edge_both_offset = 0,                                  \
 114         .edge_single_offset = 12,                               \
 115         .pol_low_offset = 0,                                    \
 116         .pin_sel_mask = 0xff,                                   \
 117         .nr_channels = 12,                                      \
 118
 119 static const struct meson_gpio_irq_params meson8_params = {
 120         INIT_MESON8_COMMON_DATA(134)
 121 };
 122
 123 static const struct meson_gpio_irq_params meson8b_params = {
 124         INIT_MESON8_COMMON_DATA(119)
 125 };
 126
 127 static const struct meson_gpio_irq_params gxbb_params = {
 128         INIT_MESON8_COMMON_DATA(133)
 129 };
 130
 131 static const struct meson_gpio_irq_params gxl_params = {
 132         INIT_MESON8_COMMON_DATA(110)
 133 };
 134
 135 static const struct meson_gpio_irq_params axg_params = {
 136         INIT_MESON8_COMMON_DATA(100)
 137 };
 138
 139 static const struct meson_gpio_irq_params sm1_params = {
 140         INIT_MESON8_COMMON_DATA(100)
 141         .support_edge_both = true,
 142         .edge_both_offset = 8,
 143 };
 144
 145 static const struct meson_gpio_irq_params a1_params = {
 146         INIT_MESON_A1_COMMON_DATA(62)
 147 };
 148
 149 static const struct meson_gpio_irq_params s4_params = {
 150         INIT_MESON_S4_COMMON_DATA(82)
 151 };
 152
 153 static const struct meson_gpio_irq_params c3_params = {
 154         INIT_MESON_S4_COMMON_DATA(55)
 155 };
 156
 157 static const struct meson_gpio_irq_params t7_params = {
 158         INIT_MESON_S4_COMMON_DATA(157)
 159 };
 160
 161 static const struct of_device_id meson_irq_gpio_matches[] __maybe_unused = {
 162         { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
 163         { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
 164         { .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params },
 165         { .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
 166         { .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
 167         { .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params },
 168         { .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
 169         { .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
 170         { .compatible = "amlogic,meson-s4-gpio-intc", .data = &s4_params },
 171         { .compatible = "amlogic,c3-gpio-intc", .data = &c3_params },
 172         { .compatible = "amlogic,t7-gpio-intc", .data = &t7_params },
 173         { }
 174 };
 175
 176 struct meson_gpio_irq_controller {
 177         const struct meson_gpio_irq_params *params;
 178         void __iomem *base;
 179         u32 channel_irqs[MAX_NUM_CHANNEL];
 180         DECLARE_BITMAP(channel_map, MAX_NUM_CHANNEL);
 181         raw_spinlock_t lock;
 182 };
 183
 184 static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl,
 185                                        unsigned int reg, u32 mask, u32 val)
 186 {
 187         unsigned long flags;
 188         u32 tmp;
 189
 190         raw_spin_lock_irqsave(&ctl->lock, flags);
 191
 192         tmp = readl_relaxed(ctl->base + reg);
 193         tmp &= ~mask;
 194         tmp |= val;
 195         writel_relaxed(tmp, ctl->base + reg);
 196
 197         raw_spin_unlock_irqrestore(&ctl->lock, flags);
 198 }
 199
 200 static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl)
 201 {
 202 }
 203
 204 static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
 205                                     unsigned int channel, unsigned long hwirq)
 206 {
 207         unsigned int reg_offset;
 208         unsigned int bit_offset;
 209
 210         reg_offset = (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL;
 211         bit_offset = REG_PIN_SEL_SHIFT(channel);
 212
 213         meson_gpio_irq_update_bits(ctl, reg_offset,
 214                                    ctl->params->pin_sel_mask << bit_offset,
 215                                    hwirq << bit_offset);
 216 }
 217
 218 static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
 219                                       unsigned int channel,
 220                                       unsigned long hwirq)
 221 {
 222         unsigned int reg_offset;
 223         unsigned int bit_offset;
 224
 225         bit_offset = ((channel % 2) == 0) ? 0 : 16;
 226         reg_offset = REG_PIN_A1_SEL + ((channel / 2) << 2);
 227
 228         meson_gpio_irq_update_bits(ctl, reg_offset,
 229                                    ctl->params->pin_sel_mask << bit_offset,
 230                                    hwirq << bit_offset);
 231 }
 232
 233 /* For a1 or later chips like a1 there is a switch to enable/disable irq */
 234 static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl)
 235 {
 236         meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(31), BIT(31));
 237 }
 238
 239 static int
 240 meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
 241                                unsigned long  hwirq,
 242                                u32 **channel_hwirq)
 243 {
 244         unsigned long flags;
 245         unsigned int idx;
 246
 247         raw_spin_lock_irqsave(&ctl->lock, flags);
 248
 249         /* Find a free channel */
 250         idx = find_first_zero_bit(ctl->channel_map, ctl->params->nr_channels);
 251         if (idx >= ctl->params->nr_channels) {
 252                 raw_spin_unlock_irqrestore(&ctl->lock, flags);
 253                 pr_err("No channel available\n");
 254                 return -ENOSPC;
 255         }
 256
 257         /* Mark the channel as used */
 258         set_bit(idx, ctl->channel_map);
 259
 260         raw_spin_unlock_irqrestore(&ctl->lock, flags);
 261
 262         /*
 263          * Setup the mux of the channel to route the signal of the pad
 264          * to the appropriate input of the GIC
 265          */
 266         ctl->params->ops.gpio_irq_sel_pin(ctl, idx, hwirq);
 267
 268         /*
 269          * Get the hwirq number assigned to this channel through
 270          * a pointer the channel_irq table. The added benefit of this
 271          * method is that we can also retrieve the channel index with
 272          * it, using the table base.
 273          */
 274         *channel_hwirq = &(ctl->channel_irqs[idx]);
 275
 276         pr_debug("hwirq %lu assigned to channel %d - irq %u\n",
 277                  hwirq, idx, **channel_hwirq);
 278
 279         return 0;
 280 }
 281
 282 static unsigned int
 283 meson_gpio_irq_get_channel_idx(struct meson_gpio_irq_controller *ctl,
 284                                u32 *channel_hwirq)
 285 {
 286         return channel_hwirq - ctl->channel_irqs;
 287 }
 288
 289 static void
 290 meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl,
 291                                u32 *channel_hwirq)
 292 {
 293         unsigned int idx;
 294
 295         idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
 296         clear_bit(idx, ctl->channel_map);
 297 }
 298
 299 static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
 300                                     unsigned int type, u32 *channel_hwirq)
 301 {
 302         u32 val = 0;
 303         unsigned int idx;
 304         const struct meson_gpio_irq_params *params;
 305
 306         params = ctl->params;
 307         idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
 308
 309         /*
 310          * The controller has a filter block to operate in either LEVEL or
 311          * EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW and
 312          * EDGE_FALLING support (which the GIC does not support), the filter
 313          * block is also able to invert the input signal it gets before
 314          * providing it to the GIC.
 315          */
 316         type &= IRQ_TYPE_SENSE_MASK;
 317
 318         /*
 319          * New controller support EDGE_BOTH trigger. This setting takes
 320          * precedence over the other edge/polarity settings
 321          */
 322         if (type == IRQ_TYPE_EDGE_BOTH) {
 323                 if (!params->support_edge_both)
 324                         return -EINVAL;
 325
 326                 val |= REG_BOTH_EDGE(params, idx);
 327         } else {
 328                 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 329                         val |= REG_EDGE_POL_EDGE(params, idx);
 330
 331                 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
 332                         val |= REG_EDGE_POL_LOW(params, idx);
 333         }
 334
 335         meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
 336                                    REG_EDGE_POL_MASK(params, idx), val);
 337
 338         return 0;
 339 }
 340
 341 /*
 342  * gpio irq relative registers for s4
 343  * -PADCTRL_GPIO_IRQ_CTRL0
 344  * bit[31]:    enable/disable all the irq lines
 345  * bit[12-23]: single edge trigger
 346  * bit[0-11]:  polarity trigger
 347  *
 348  * -PADCTRL_GPIO_IRQ_CTRL[X]
 349  * bit[0-16]: 7 bits to choose gpio source for irq line 2*[X] - 2
 350  * bit[16-22]:7 bits to choose gpio source for irq line 2*[X] - 1
 351  * where X = 1-6
 352  *
 353  * -PADCTRL_GPIO_IRQ_CTRL[7]
 354  * bit[0-11]: both edge trigger
 355  */
 356 static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
 357                                       unsigned int type, u32 *channel_hwirq)
 358 {
 359         u32 val = 0;
 360         unsigned int idx;
 361
 362         idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
 363
 364         type &= IRQ_TYPE_SENSE_MASK;
 365
 366         meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4, BIT(idx), 0);
 367
 368         if (type == IRQ_TYPE_EDGE_BOTH) {
 369                 val |= BIT(ctl->params->edge_both_offset + idx);
 370                 meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4,
 371                                            BIT(ctl->params->edge_both_offset + idx), val);
 372                 return 0;
 373         }
 374
 375         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
 376                 val |= BIT(ctl->params->pol_low_offset + idx);
 377
 378         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 379                 val |= BIT(ctl->params->edge_single_offset + idx);
 380
 381         meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
 382                                    BIT(idx) | BIT(12 + idx), val);
 383         return 0;
 384 };
 385
 386 static unsigned int meson_gpio_irq_type_output(unsigned int type)
 387 {
 388         unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
 389
 390         type &= ~IRQ_TYPE_SENSE_MASK;
 391
 392         /*
 393          * The polarity of the signal provided to the GIC should always
 394          * be high.
 395          */
 396         if (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
 397                 type |= IRQ_TYPE_LEVEL_HIGH;
 398         else
 399                 type |= IRQ_TYPE_EDGE_RISING;
 400
 401         return type;
 402 }
 403
 404 static int meson_gpio_irq_set_type(struct irq_data *data, unsigned int type)
 405 {
 406         struct meson_gpio_irq_controller *ctl = data->domain->host_data;
 407         u32 *channel_hwirq = irq_data_get_irq_chip_data(data);
 408         int ret;
 409
 410         ret = ctl->params->ops.gpio_irq_set_type(ctl, type, channel_hwirq);
 411         if (ret)
 412                 return ret;
 413
 414         return irq_chip_set_type_parent(data,
 415                                         meson_gpio_irq_type_output(type));
 416 }
 417
 418 static struct irq_chip meson_gpio_irq_chip = {
 419         .name                   = "meson-gpio-irqchip",
 420         .irq_mask               = irq_chip_mask_parent,
 421         .irq_unmask             = irq_chip_unmask_parent,
 422         .irq_eoi                = irq_chip_eoi_parent,
 423         .irq_set_type           = meson_gpio_irq_set_type,
 424         .irq_retrigger          = irq_chip_retrigger_hierarchy,
 425 #ifdef CONFIG_SMP
 426         .irq_set_affinity       = irq_chip_set_affinity_parent,
 427 #endif
 428         .flags                  = IRQCHIP_SET_TYPE_MASKED,
 429 };
 430
 431 static int meson_gpio_irq_domain_translate(struct irq_domain *domain,
 432                                            struct irq_fwspec *fwspec,
 433                                            unsigned long *hwirq,
 434                                            unsigned int *type)
 435 {
 436         if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
 437                 *hwirq  = fwspec->param[0];
 438                 *type   = fwspec->param[1];
 439                 return 0;
 440         }
 441
 442         return -EINVAL;
 443 }
 444
 445 static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain,
 446                                            unsigned int virq,
 447                                            u32 hwirq,
 448                                            unsigned int type)
 449 {
 450         struct irq_fwspec fwspec;
 451
 452         fwspec.fwnode = domain->parent->fwnode;
 453         fwspec.param_count = 3;
 454         fwspec.param[0] = 0;    /* SPI */
 455         fwspec.param[1] = hwirq;
 456         fwspec.param[2] = meson_gpio_irq_type_output(type);
 457
 458         return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
 459 }
 460
 461 static int meson_gpio_irq_domain_alloc(struct irq_domain *domain,
 462                                        unsigned int virq,
 463                                        unsigned int nr_irqs,
 464                                        void *data)
 465 {
 466         struct irq_fwspec *fwspec = data;
 467         struct meson_gpio_irq_controller *ctl = domain->host_data;
 468         unsigned long hwirq;
 469         u32 *channel_hwirq;
 470         unsigned int type;
 471         int ret;
 472
 473         if (WARN_ON(nr_irqs != 1))
 474                 return -EINVAL;
 475
 476         ret = meson_gpio_irq_domain_translate(domain, fwspec, &hwirq, &type);
 477         if (ret)
 478                 return ret;
 479
 480         ret = meson_gpio_irq_request_channel(ctl, hwirq, &channel_hwirq);
 481         if (ret)
 482                 return ret;
 483
 484         ret = meson_gpio_irq_allocate_gic_irq(domain, virq,
 485                                               *channel_hwirq, type);
 486         if (ret < 0) {
 487                 pr_err("failed to allocate gic irq %u\n", *channel_hwirq);
 488                 meson_gpio_irq_release_channel(ctl, channel_hwirq);
 489                 return ret;
 490         }
 491
 492         irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
 493                                       &meson_gpio_irq_chip, channel_hwirq);
 494
 495         return 0;
 496 }
 497
 498 static void meson_gpio_irq_domain_free(struct irq_domain *domain,
 499                                        unsigned int virq,
 500                                        unsigned int nr_irqs)
 501 {
 502         struct meson_gpio_irq_controller *ctl = domain->host_data;
 503         struct irq_data *irq_data;
 504         u32 *channel_hwirq;
 505
 506         if (WARN_ON(nr_irqs != 1))
 507                 return;
 508
 509         irq_domain_free_irqs_parent(domain, virq, 1);
 510
 511         irq_data = irq_domain_get_irq_data(domain, virq);
 512         channel_hwirq = irq_data_get_irq_chip_data(irq_data);
 513
 514         meson_gpio_irq_release_channel(ctl, channel_hwirq);
 515 }
 516
 517 static const struct irq_domain_ops meson_gpio_irq_domain_ops = {
 518         .alloc          = meson_gpio_irq_domain_alloc,
 519         .free           = meson_gpio_irq_domain_free,
 520         .translate      = meson_gpio_irq_domain_translate,
 521 };
 522
 523 static int meson_gpio_irq_parse_dt(struct device_node *node, struct meson_gpio_irq_controller *ctl)
 524 {
 525         const struct of_device_id *match;
 526         int ret;
 527
 528         match = of_match_node(meson_irq_gpio_matches, node);
 529         if (!match)
 530                 return -ENODEV;
 531
 532         ctl->params = match->data;
 533
 534         ret = of_property_read_variable_u32_array(node,
 535                                                   "amlogic,channel-interrupts",
 536                                                   ctl->channel_irqs,
 537                                                   ctl->params->nr_channels,
 538                                                   ctl->params->nr_channels);
 539         if (ret < 0) {
 540                 pr_err("can't get %d channel interrupts\n", ctl->params->nr_channels);
 541                 return ret;
 542         }
 543
 544         ctl->params->ops.gpio_irq_init(ctl);
 545
 546         return 0;
 547 }
 548
 549 static int meson_gpio_irq_of_init(struct device_node *node, struct device_node *parent)
 550 {
 551         struct irq_domain *domain, *parent_domain;
 552         struct meson_gpio_irq_controller *ctl;
 553         int ret;
 554
 555         if (!parent) {
 556                 pr_err("missing parent interrupt node\n");
 557                 return -ENODEV;
 558         }
 559
 560         parent_domain = irq_find_host(parent);
 561         if (!parent_domain) {
 562                 pr_err("unable to obtain parent domain\n");
 563                 return -ENXIO;
 564         }
 565
 566         ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
 567         if (!ctl)
 568                 return -ENOMEM;
 569
 570         raw_spin_lock_init(&ctl->lock);
 571
 572         ctl->base = of_iomap(node, 0);
 573         if (!ctl->base) {
 574                 ret = -ENOMEM;
 575                 goto free_ctl;
 576         }
 577
 578         ret = meson_gpio_irq_parse_dt(node, ctl);
 579         if (ret)
 580                 goto free_channel_irqs;
 581
 582         domain = irq_domain_create_hierarchy(parent_domain, 0,
 583                                              ctl->params->nr_hwirq,
 584                                              of_node_to_fwnode(node),
 585                                              &meson_gpio_irq_domain_ops,
 586                                              ctl);
 587         if (!domain) {
 588                 pr_err("failed to add domain\n");
 589                 ret = -ENODEV;
 590                 goto free_channel_irqs;
 591         }
 592
 593         pr_info("%d to %d gpio interrupt mux initialized\n",
 594                 ctl->params->nr_hwirq, ctl->params->nr_channels);
 595
 596         return 0;
 597
 598 free_channel_irqs:
 599         iounmap(ctl->base);
 600 free_ctl:
 601         kfree(ctl);
 602
 603         return ret;
 604 }
 605
 606 IRQCHIP_PLATFORM_DRIVER_BEGIN(meson_gpio_intc)
 607 IRQCHIP_MATCH("amlogic,meson-gpio-intc", meson_gpio_irq_of_init)
 608 IRQCHIP_PLATFORM_DRIVER_END(meson_gpio_intc)
 609
 610 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
 611 MODULE_DESCRIPTION("Meson GPIO Interrupt Multiplexer driver");
 612 MODULE_LICENSE("GPL v2");
 613 MODULE_ALIAS("platform:meson-gpio-intc");