drivers/irqchip/irq-mscc-ocelot.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Microsemi Ocelot IRQ controller driver
   4  *
   5  * Copyright (c) 2017 Microsemi Corporation
   6  */
   7 #include <linux/bitops.h>
   8 #include <linux/irq.h>
   9 #include <linux/of_address.h>
  10 #include <linux/of_irq.h>
  11 #include <linux/irqchip.h>
  12 #include <linux/irqchip/chained_irq.h>
  13 #include <linux/interrupt.h>
  14
  15 #define ICPU_CFG_INTR_DST_INTR_IDENT(_p, x) ((_p)->reg_off_ident + 0x4 * (x))
  16 #define ICPU_CFG_INTR_INTR_TRIGGER(_p, x)   ((_p)->reg_off_trigger + 0x4 * (x))
  17
  18 #define FLAGS_HAS_TRIGGER       BIT(0)
  19 #define FLAGS_NEED_INIT_ENABLE  BIT(1)
  20
  21 struct chip_props {
  22         u8 flags;
  23         u8 reg_off_sticky;
  24         u8 reg_off_ena;
  25         u8 reg_off_ena_clr;
  26         u8 reg_off_ena_set;
  27         u8 reg_off_ident;
  28         u8 reg_off_trigger;
  29         u8 reg_off_ena_irq0;
  30         u8 n_irq;
  31 };
  32
  33 static struct chip_props ocelot_props = {
  34         .flags                  = FLAGS_HAS_TRIGGER,
  35         .reg_off_sticky         = 0x10,
  36         .reg_off_ena            = 0x18,
  37         .reg_off_ena_clr        = 0x1c,
  38         .reg_off_ena_set        = 0x20,
  39         .reg_off_ident          = 0x38,
  40         .reg_off_trigger        = 0x4,
  41         .n_irq                  = 24,
  42 };
  43
  44 static struct chip_props serval_props = {
  45         .flags                  = FLAGS_HAS_TRIGGER,
  46         .reg_off_sticky         = 0xc,
  47         .reg_off_ena            = 0x14,
  48         .reg_off_ena_clr        = 0x18,
  49         .reg_off_ena_set        = 0x1c,
  50         .reg_off_ident          = 0x20,
  51         .reg_off_trigger        = 0x4,
  52         .n_irq                  = 24,
  53 };
  54
  55 static struct chip_props luton_props = {
  56         .flags                  = FLAGS_NEED_INIT_ENABLE,
  57         .reg_off_sticky         = 0,
  58         .reg_off_ena            = 0x4,
  59         .reg_off_ena_clr        = 0x8,
  60         .reg_off_ena_set        = 0xc,
  61         .reg_off_ident          = 0x18,
  62         .reg_off_ena_irq0       = 0x14,
  63         .n_irq                  = 28,
  64 };
  65
  66 static struct chip_props jaguar2_props = {
  67         .flags                  = FLAGS_HAS_TRIGGER,
  68         .reg_off_sticky         = 0x10,
  69         .reg_off_ena            = 0x18,
  70         .reg_off_ena_clr        = 0x1c,
  71         .reg_off_ena_set        = 0x20,
  72         .reg_off_ident          = 0x38,
  73         .reg_off_trigger        = 0x4,
  74         .n_irq                  = 29,
  75 };
  76
  77 static void ocelot_irq_unmask(struct irq_data *data)
  78 {
  79         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
  80         struct irq_domain *d = data->domain;
  81         struct chip_props *p = d->host_data;
  82         struct irq_chip_type *ct = irq_data_get_chip_type(data);
  83         unsigned int mask = data->mask;
  84         u32 val;
  85
  86         irq_gc_lock(gc);
  87         /*
  88          * Clear sticky bits for edge mode interrupts.
  89          * Serval has only one trigger register replication, but the adjacent
  90          * register is always read as zero, so there's no need to handle this
  91          * case separately.
  92          */
  93         val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 0)) |
  94                 irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 1));
  95         if (!(val & mask))
  96                 irq_reg_writel(gc, mask, p->reg_off_sticky);
  97
  98         *ct->mask_cache &= ~mask;
  99         irq_reg_writel(gc, mask, p->reg_off_ena_set);
 100         irq_gc_unlock(gc);
 101 }
 102
 103 static void ocelot_irq_handler(struct irq_desc *desc)
 104 {
 105         struct irq_chip *chip = irq_desc_get_chip(desc);
 106         struct irq_domain *d = irq_desc_get_handler_data(desc);
 107         struct chip_props *p = d->host_data;
 108         struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0);
 109         u32 reg = irq_reg_readl(gc, ICPU_CFG_INTR_DST_INTR_IDENT(p, 0));
 110
 111         chained_irq_enter(chip, desc);
 112
 113         while (reg) {
 114                 u32 hwirq = __fls(reg);
 115
 116                 generic_handle_domain_irq(d, hwirq);
 117                 reg &= ~(BIT(hwirq));
 118         }
 119
 120         chained_irq_exit(chip, desc);
 121 }
 122
 123 static int __init vcoreiii_irq_init(struct device_node *node,
 124                                     struct device_node *parent,
 125                                     struct chip_props *p)
 126 {
 127         struct irq_domain *domain;
 128         struct irq_chip_generic *gc;
 129         int parent_irq, ret;
 130
 131         parent_irq = irq_of_parse_and_map(node, 0);
 132         if (!parent_irq)
 133                 return -EINVAL;
 134
 135         domain = irq_domain_add_linear(node, p->n_irq,
 136                                        &irq_generic_chip_ops, NULL);
 137         if (!domain) {
 138                 pr_err("%pOFn: unable to add irq domain\n", node);
 139                 return -ENOMEM;
 140         }
 141
 142         ret = irq_alloc_domain_generic_chips(domain, p->n_irq, 1,
 143                                              "icpu", handle_level_irq,
 144                                              0, 0, 0);
 145         if (ret) {
 146                 pr_err("%pOFn: unable to alloc irq domain gc\n", node);
 147                 goto err_domain_remove;
 148         }
 149
 150         gc = irq_get_domain_generic_chip(domain, 0);
 151         gc->reg_base = of_iomap(node, 0);
 152         if (!gc->reg_base) {
 153                 pr_err("%pOFn: unable to map resource\n", node);
 154                 ret = -ENOMEM;
 155                 goto err_gc_free;
 156         }
 157
 158         gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
 159         gc->chip_types[0].regs.ack = p->reg_off_sticky;
 160         if (p->flags & FLAGS_HAS_TRIGGER) {
 161                 gc->chip_types[0].regs.mask = p->reg_off_ena_clr;
 162                 gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask;
 163                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
 164         } else {
 165                 gc->chip_types[0].regs.enable = p->reg_off_ena_set;
 166                 gc->chip_types[0].regs.disable = p->reg_off_ena_clr;
 167                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
 168                 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
 169         }
 170
 171         /* Mask and ack all interrupts */
 172         irq_reg_writel(gc, 0, p->reg_off_ena);
 173         irq_reg_writel(gc, 0xffffffff, p->reg_off_sticky);
 174
 175         /* Overall init */
 176         if (p->flags & FLAGS_NEED_INIT_ENABLE)
 177                 irq_reg_writel(gc, BIT(0), p->reg_off_ena_irq0);
 178
 179         domain->host_data = p;
 180         irq_set_chained_handler_and_data(parent_irq, ocelot_irq_handler,
 181                                          domain);
 182
 183         return 0;
 184
 185 err_gc_free:
 186         irq_free_generic_chip(gc);
 187
 188 err_domain_remove:
 189         irq_domain_remove(domain);
 190
 191         return ret;
 192 }
 193
 194 static int __init ocelot_irq_init(struct device_node *node,
 195                                   struct device_node *parent)
 196 {
 197         return vcoreiii_irq_init(node, parent, &ocelot_props);
 198 }
 199
 200 IRQCHIP_DECLARE(ocelot_icpu, "mscc,ocelot-icpu-intr", ocelot_irq_init);
 201
 202 static int __init serval_irq_init(struct device_node *node,
 203                                   struct device_node *parent)
 204 {
 205         return vcoreiii_irq_init(node, parent, &serval_props);
 206 }
 207
 208 IRQCHIP_DECLARE(serval_icpu, "mscc,serval-icpu-intr", serval_irq_init);
 209
 210 static int __init luton_irq_init(struct device_node *node,
 211                                  struct device_node *parent)
 212 {
 213         return vcoreiii_irq_init(node, parent, &luton_props);
 214 }
 215
 216 IRQCHIP_DECLARE(luton_icpu, "mscc,luton-icpu-intr", luton_irq_init);
 217
 218 static int __init jaguar2_irq_init(struct device_node *node,
 219                                    struct device_node *parent)
 220 {
 221         return vcoreiii_irq_init(node, parent, &jaguar2_props);
 222 }
 223
 224 IRQCHIP_DECLARE(jaguar2_icpu, "mscc,jaguar2-icpu-intr", jaguar2_irq_init);