1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2024 Inochi Amaoto <inochiama@gmail.com>
6 #define pr_fmt(fmt) "thead-c900-aclint-sswi: " fmt
8 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/irqchip.h>
12 #include <linux/irqchip/chained_irq.h>
13 #include <linux/module.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/pci.h>
18 #include <linux/spinlock.h>
19 #include <linux/smp.h>
20 #include <linux/string_choices.h>
22 #include <asm/vendorid_list.h>
24 #define THEAD_ACLINT_xSWI_REGISTER_SIZE 4
26 #define THEAD_C9XX_CSR_SXSTATUS 0x5c0
27 #define THEAD_C9XX_SXSTATUS_CLINTEE BIT(17)
29 static int sswi_ipi_virq __ro_after_init
;
30 static DEFINE_PER_CPU(void __iomem
*, sswi_cpu_regs
);
32 static void thead_aclint_sswi_ipi_send(unsigned int cpu
)
34 writel_relaxed(0x1, per_cpu(sswi_cpu_regs
, cpu
));
37 static void thead_aclint_sswi_ipi_clear(void)
39 writel_relaxed(0x0, this_cpu_read(sswi_cpu_regs
));
42 static void thead_aclint_sswi_ipi_handle(struct irq_desc
*desc
)
44 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
46 chained_irq_enter(chip
, desc
);
48 csr_clear(CSR_IP
, IE_SIE
);
49 thead_aclint_sswi_ipi_clear();
53 chained_irq_exit(chip
, desc
);
56 static int thead_aclint_sswi_starting_cpu(unsigned int cpu
)
58 enable_percpu_irq(sswi_ipi_virq
, irq_get_trigger_type(sswi_ipi_virq
));
63 static int thead_aclint_sswi_dying_cpu(unsigned int cpu
)
65 thead_aclint_sswi_ipi_clear();
67 disable_percpu_irq(sswi_ipi_virq
);
72 static int __init
thead_aclint_sswi_parse_irq(struct fwnode_handle
*fwnode
,
75 struct of_phandle_args parent
;
80 contexts
= of_irq_count(to_of_node(fwnode
));
82 pr_err("%pfwP: no ACLINT SSWI context available\n", fwnode
);
86 for (i
= 0; i
< contexts
; i
++) {
87 rc
= of_irq_parse_one(to_of_node(fwnode
), i
, &parent
);
91 rc
= riscv_of_parent_hartid(parent
.np
, &hartid
);
95 if (parent
.args
[0] != RV_IRQ_SOFT
)
98 cpu
= riscv_hartid_to_cpuid(hartid
);
100 per_cpu(sswi_cpu_regs
, cpu
) = reg
+ i
* THEAD_ACLINT_xSWI_REGISTER_SIZE
;
103 pr_info("%pfwP: register %u CPU%s\n", fwnode
, contexts
, str_plural(contexts
));
108 static int __init
thead_aclint_sswi_probe(struct fwnode_handle
*fwnode
)
110 struct irq_domain
*domain
;
114 /* If it is T-HEAD CPU, check whether SSWI is enabled */
115 if (riscv_cached_mvendorid(0) == THEAD_VENDOR_ID
&&
116 !(csr_read(THEAD_C9XX_CSR_SXSTATUS
) & THEAD_C9XX_SXSTATUS_CLINTEE
))
119 if (!is_of_node(fwnode
))
122 reg
= of_iomap(to_of_node(fwnode
), 0);
126 /* Parse SSWI setting */
127 rc
= thead_aclint_sswi_parse_irq(fwnode
, reg
);
131 /* If mulitple SSWI devices are present, do not register irq again */
135 /* Find riscv intc domain and create IPI irq mapping */
136 domain
= irq_find_matching_fwnode(riscv_get_intc_hwnode(), DOMAIN_BUS_ANY
);
138 pr_err("%pfwP: Failed to find INTC domain\n", fwnode
);
142 sswi_ipi_virq
= irq_create_mapping(domain
, RV_IRQ_SOFT
);
143 if (!sswi_ipi_virq
) {
144 pr_err("unable to create ACLINT SSWI IRQ mapping\n");
148 /* Register SSWI irq and handler */
149 virq
= ipi_mux_create(BITS_PER_BYTE
, thead_aclint_sswi_ipi_send
);
151 pr_err("unable to create muxed IPIs\n");
152 irq_dispose_mapping(sswi_ipi_virq
);
153 return virq
< 0 ? virq
: -ENOMEM
;
156 irq_set_chained_handler(sswi_ipi_virq
, thead_aclint_sswi_ipi_handle
);
158 cpuhp_setup_state(CPUHP_AP_IRQ_THEAD_ACLINT_SSWI_STARTING
,
159 "irqchip/thead-aclint-sswi:starting",
160 thead_aclint_sswi_starting_cpu
,
161 thead_aclint_sswi_dying_cpu
);
163 riscv_ipi_set_virq_range(virq
, BITS_PER_BYTE
);
165 /* Announce that SSWI is providing IPIs */
166 pr_info("providing IPIs using THEAD ACLINT SSWI\n");
171 static int __init
thead_aclint_sswi_early_probe(struct device_node
*node
,
172 struct device_node
*parent
)
174 return thead_aclint_sswi_probe(&node
->fwnode
);
176 IRQCHIP_DECLARE(thead_aclint_sswi
, "thead,c900-aclint-sswi", thead_aclint_sswi_early_probe
);