drivers/mailbox/omap-mailbox.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * OMAP mailbox driver
   4  *
   5  * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
   6  * Copyright (C) 2013-2021 Texas Instruments Incorporated - https://www.ti.com
   7  *
   8  * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
   9  *          Suman Anna <s-anna@ti.com>
  10  */
  11
  12 #include <linux/interrupt.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/mutex.h>
  15 #include <linux/slab.h>
  16 #include <linux/kfifo.h>
  17 #include <linux/err.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/mailbox_controller.h>
  24 #include <linux/mailbox_client.h>
  25
  26 #include "mailbox.h"
  27
  28 #define MAILBOX_REVISION                0x000
  29 #define MAILBOX_MESSAGE(m)              (0x040 + 4 * (m))
  30 #define MAILBOX_FIFOSTATUS(m)           (0x080 + 4 * (m))
  31 #define MAILBOX_MSGSTATUS(m)            (0x0c0 + 4 * (m))
  32
  33 #define OMAP2_MAILBOX_IRQSTATUS(u)      (0x100 + 8 * (u))
  34 #define OMAP2_MAILBOX_IRQENABLE(u)      (0x104 + 8 * (u))
  35
  36 #define OMAP4_MAILBOX_IRQSTATUS(u)      (0x104 + 0x10 * (u))
  37 #define OMAP4_MAILBOX_IRQENABLE(u)      (0x108 + 0x10 * (u))
  38 #define OMAP4_MAILBOX_IRQENABLE_CLR(u)  (0x10c + 0x10 * (u))
  39
  40 #define MAILBOX_IRQSTATUS(type, u)      (type ? OMAP4_MAILBOX_IRQSTATUS(u) : \
  41                                                 OMAP2_MAILBOX_IRQSTATUS(u))
  42 #define MAILBOX_IRQENABLE(type, u)      (type ? OMAP4_MAILBOX_IRQENABLE(u) : \
  43                                                 OMAP2_MAILBOX_IRQENABLE(u))
  44 #define MAILBOX_IRQDISABLE(type, u)     (type ? OMAP4_MAILBOX_IRQENABLE_CLR(u) \
  45                                                 : OMAP2_MAILBOX_IRQENABLE(u))
  46
  47 #define MAILBOX_IRQ_NEWMSG(m)           (1 << (2 * (m)))
  48 #define MAILBOX_IRQ_NOTFULL(m)          (1 << (2 * (m) + 1))
  49
  50 /* Interrupt register configuration types */
  51 #define MBOX_INTR_CFG_TYPE1             0
  52 #define MBOX_INTR_CFG_TYPE2             1
  53
  54 typedef enum {
  55         IRQ_TX = 1,
  56         IRQ_RX = 2,
  57 } omap_mbox_irq_t;
  58
  59 struct omap_mbox_fifo {
  60         unsigned long msg;
  61         unsigned long fifo_stat;
  62         unsigned long msg_stat;
  63         unsigned long irqenable;
  64         unsigned long irqstatus;
  65         unsigned long irqdisable;
  66         u32 intr_bit;
  67 };
  68
  69 struct omap_mbox_match_data {
  70         u32 intr_type;
  71 };
  72
  73 struct omap_mbox_device {
  74         struct device *dev;
  75         struct mutex cfg_lock;
  76         void __iomem *mbox_base;
  77         u32 *irq_ctx;
  78         u32 num_users;
  79         u32 num_fifos;
  80         u32 intr_type;
  81 };
  82
  83 struct omap_mbox {
  84         const char              *name;
  85         int                     irq;
  86         struct omap_mbox_device *parent;
  87         struct omap_mbox_fifo   tx_fifo;
  88         struct omap_mbox_fifo   rx_fifo;
  89         u32                     intr_type;
  90         struct mbox_chan        *chan;
  91         bool                    send_no_irq;
  92 };
  93
  94 static inline
  95 unsigned int mbox_read_reg(struct omap_mbox_device *mdev, size_t ofs)
  96 {
  97         return __raw_readl(mdev->mbox_base + ofs);
  98 }
  99
 100 static inline
 101 void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs)
 102 {
 103         __raw_writel(val, mdev->mbox_base + ofs);
 104 }
 105
 106 /* Mailbox FIFO handle functions */
 107 static u32 mbox_fifo_read(struct omap_mbox *mbox)
 108 {
 109         struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
 110
 111         return mbox_read_reg(mbox->parent, fifo->msg);
 112 }
 113
 114 static void mbox_fifo_write(struct omap_mbox *mbox, u32 msg)
 115 {
 116         struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
 117
 118         mbox_write_reg(mbox->parent, msg, fifo->msg);
 119 }
 120
 121 static int mbox_fifo_empty(struct omap_mbox *mbox)
 122 {
 123         struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
 124
 125         return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0);
 126 }
 127
 128 static int mbox_fifo_full(struct omap_mbox *mbox)
 129 {
 130         struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
 131
 132         return mbox_read_reg(mbox->parent, fifo->fifo_stat);
 133 }
 134
 135 /* Mailbox IRQ handle functions */
 136 static void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
 137 {
 138         struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
 139                                 &mbox->tx_fifo : &mbox->rx_fifo;
 140         u32 bit = fifo->intr_bit;
 141         u32 irqstatus = fifo->irqstatus;
 142
 143         mbox_write_reg(mbox->parent, bit, irqstatus);
 144
 145         /* Flush posted write for irq status to avoid spurious interrupts */
 146         mbox_read_reg(mbox->parent, irqstatus);
 147 }
 148
 149 static int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
 150 {
 151         struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
 152                                 &mbox->tx_fifo : &mbox->rx_fifo;
 153         u32 bit = fifo->intr_bit;
 154         u32 irqenable = fifo->irqenable;
 155         u32 irqstatus = fifo->irqstatus;
 156
 157         u32 enable = mbox_read_reg(mbox->parent, irqenable);
 158         u32 status = mbox_read_reg(mbox->parent, irqstatus);
 159
 160         return (int)(enable & status & bit);
 161 }
 162
 163 static void omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
 164 {
 165         u32 l;
 166         struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
 167                                 &mbox->tx_fifo : &mbox->rx_fifo;
 168         u32 bit = fifo->intr_bit;
 169         u32 irqenable = fifo->irqenable;
 170
 171         l = mbox_read_reg(mbox->parent, irqenable);
 172         l |= bit;
 173         mbox_write_reg(mbox->parent, l, irqenable);
 174 }
 175
 176 static void omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
 177 {
 178         struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
 179                                 &mbox->tx_fifo : &mbox->rx_fifo;
 180         u32 bit = fifo->intr_bit;
 181         u32 irqdisable = fifo->irqdisable;
 182
 183         /*
 184          * Read and update the interrupt configuration register for pre-OMAP4.
 185          * OMAP4 and later SoCs have a dedicated interrupt disabling register.
 186          */
 187         if (!mbox->intr_type)
 188                 bit = mbox_read_reg(mbox->parent, irqdisable) & ~bit;
 189
 190         mbox_write_reg(mbox->parent, bit, irqdisable);
 191 }
 192
 193 /*
 194  * Mailbox interrupt handler
 195  */
 196 static void __mbox_tx_interrupt(struct omap_mbox *mbox)
 197 {
 198         omap_mbox_disable_irq(mbox, IRQ_TX);
 199         ack_mbox_irq(mbox, IRQ_TX);
 200         mbox_chan_txdone(mbox->chan, 0);
 201 }
 202
 203 static void __mbox_rx_interrupt(struct omap_mbox *mbox)
 204 {
 205         u32 msg;
 206
 207         while (!mbox_fifo_empty(mbox)) {
 208                 msg = mbox_fifo_read(mbox);
 209                 mbox_chan_received_data(mbox->chan, (void *)(uintptr_t)msg);
 210         }
 211
 212         /* clear IRQ source. */
 213         ack_mbox_irq(mbox, IRQ_RX);
 214 }
 215
 216 static irqreturn_t mbox_interrupt(int irq, void *p)
 217 {
 218         struct omap_mbox *mbox = p;
 219
 220         if (is_mbox_irq(mbox, IRQ_TX))
 221                 __mbox_tx_interrupt(mbox);
 222
 223         if (is_mbox_irq(mbox, IRQ_RX))
 224                 __mbox_rx_interrupt(mbox);
 225
 226         return IRQ_HANDLED;
 227 }
 228
 229 static int omap_mbox_startup(struct omap_mbox *mbox)
 230 {
 231         int ret = 0;
 232
 233         ret = request_threaded_irq(mbox->irq, NULL, mbox_interrupt,
 234                                    IRQF_SHARED | IRQF_ONESHOT, mbox->name,
 235                                    mbox);
 236         if (unlikely(ret)) {
 237                 pr_err("failed to register mailbox interrupt:%d\n", ret);
 238                 return ret;
 239         }
 240
 241         if (mbox->send_no_irq)
 242                 mbox->chan->txdone_method = TXDONE_BY_ACK;
 243
 244         omap_mbox_enable_irq(mbox, IRQ_RX);
 245
 246         return 0;
 247 }
 248
 249 static void omap_mbox_fini(struct omap_mbox *mbox)
 250 {
 251         omap_mbox_disable_irq(mbox, IRQ_RX);
 252         free_irq(mbox->irq, mbox);
 253 }
 254
 255 static int omap_mbox_chan_startup(struct mbox_chan *chan)
 256 {
 257         struct omap_mbox *mbox = chan->con_priv;
 258         struct omap_mbox_device *mdev = mbox->parent;
 259         int ret = 0;
 260
 261         mutex_lock(&mdev->cfg_lock);
 262         pm_runtime_get_sync(mdev->dev);
 263         ret = omap_mbox_startup(mbox);
 264         if (ret)
 265                 pm_runtime_put_sync(mdev->dev);
 266         mutex_unlock(&mdev->cfg_lock);
 267         return ret;
 268 }
 269
 270 static void omap_mbox_chan_shutdown(struct mbox_chan *chan)
 271 {
 272         struct omap_mbox *mbox = chan->con_priv;
 273         struct omap_mbox_device *mdev = mbox->parent;
 274
 275         mutex_lock(&mdev->cfg_lock);
 276         omap_mbox_fini(mbox);
 277         pm_runtime_put_sync(mdev->dev);
 278         mutex_unlock(&mdev->cfg_lock);
 279 }
 280
 281 static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, u32 msg)
 282 {
 283         if (mbox_fifo_full(mbox))
 284                 return -EBUSY;
 285
 286         omap_mbox_enable_irq(mbox, IRQ_RX);
 287         mbox_fifo_write(mbox, msg);
 288         omap_mbox_disable_irq(mbox, IRQ_RX);
 289
 290         /* we must read and ack the interrupt directly from here */
 291         mbox_fifo_read(mbox);
 292         ack_mbox_irq(mbox, IRQ_RX);
 293
 294         return 0;
 295 }
 296
 297 static int omap_mbox_chan_send(struct omap_mbox *mbox, u32 msg)
 298 {
 299         if (mbox_fifo_full(mbox)) {
 300                 /* always enable the interrupt */
 301                 omap_mbox_enable_irq(mbox, IRQ_TX);
 302                 return -EBUSY;
 303         }
 304
 305         mbox_fifo_write(mbox, msg);
 306
 307         /* always enable the interrupt */
 308         omap_mbox_enable_irq(mbox, IRQ_TX);
 309         return 0;
 310 }
 311
 312 static int omap_mbox_chan_send_data(struct mbox_chan *chan, void *data)
 313 {
 314         struct omap_mbox *mbox = chan->con_priv;
 315         int ret;
 316         u32 msg = (u32)(uintptr_t)(data);
 317
 318         if (!mbox)
 319                 return -EINVAL;
 320
 321         if (mbox->send_no_irq)
 322                 ret = omap_mbox_chan_send_noirq(mbox, msg);
 323         else
 324                 ret = omap_mbox_chan_send(mbox, msg);
 325
 326         return ret;
 327 }
 328
 329 static const struct mbox_chan_ops omap_mbox_chan_ops = {
 330         .startup        = omap_mbox_chan_startup,
 331         .send_data      = omap_mbox_chan_send_data,
 332         .shutdown       = omap_mbox_chan_shutdown,
 333 };
 334
 335 #ifdef CONFIG_PM_SLEEP
 336 static int omap_mbox_suspend(struct device *dev)
 337 {
 338         struct omap_mbox_device *mdev = dev_get_drvdata(dev);
 339         u32 usr, fifo, reg;
 340
 341         if (pm_runtime_status_suspended(dev))
 342                 return 0;
 343
 344         for (fifo = 0; fifo < mdev->num_fifos; fifo++) {
 345                 if (mbox_read_reg(mdev, MAILBOX_MSGSTATUS(fifo))) {
 346                         dev_err(mdev->dev, "fifo %d has unexpected unread messages\n",
 347                                 fifo);
 348                         return -EBUSY;
 349                 }
 350         }
 351
 352         for (usr = 0; usr < mdev->num_users; usr++) {
 353                 reg = MAILBOX_IRQENABLE(mdev->intr_type, usr);
 354                 mdev->irq_ctx[usr] = mbox_read_reg(mdev, reg);
 355         }
 356
 357         return 0;
 358 }
 359
 360 static int omap_mbox_resume(struct device *dev)
 361 {
 362         struct omap_mbox_device *mdev = dev_get_drvdata(dev);
 363         u32 usr, reg;
 364
 365         if (pm_runtime_status_suspended(dev))
 366                 return 0;
 367
 368         for (usr = 0; usr < mdev->num_users; usr++) {
 369                 reg = MAILBOX_IRQENABLE(mdev->intr_type, usr);
 370                 mbox_write_reg(mdev, mdev->irq_ctx[usr], reg);
 371         }
 372
 373         return 0;
 374 }
 375 #endif
 376
 377 static const struct dev_pm_ops omap_mbox_pm_ops = {
 378         SET_SYSTEM_SLEEP_PM_OPS(omap_mbox_suspend, omap_mbox_resume)
 379 };
 380
 381 static const struct omap_mbox_match_data omap2_data = { MBOX_INTR_CFG_TYPE1 };
 382 static const struct omap_mbox_match_data omap4_data = { MBOX_INTR_CFG_TYPE2 };
 383
 384 static const struct of_device_id omap_mailbox_of_match[] = {
 385         {
 386                 .compatible     = "ti,omap2-mailbox",
 387                 .data           = &omap2_data,
 388         },
 389         {
 390                 .compatible     = "ti,omap3-mailbox",
 391                 .data           = &omap2_data,
 392         },
 393         {
 394                 .compatible     = "ti,omap4-mailbox",
 395                 .data           = &omap4_data,
 396         },
 397         {
 398                 .compatible     = "ti,am654-mailbox",
 399                 .data           = &omap4_data,
 400         },
 401         {
 402                 .compatible     = "ti,am64-mailbox",
 403                 .data           = &omap4_data,
 404         },
 405         {
 406                 /* end */
 407         },
 408 };
 409 MODULE_DEVICE_TABLE(of, omap_mailbox_of_match);
 410
 411 static struct mbox_chan *omap_mbox_of_xlate(struct mbox_controller *controller,
 412                                             const struct of_phandle_args *sp)
 413 {
 414         phandle phandle = sp->args[0];
 415         struct device_node *node;
 416         struct omap_mbox_device *mdev;
 417         struct omap_mbox *mbox;
 418         int i;
 419
 420         mdev = dev_get_drvdata(controller->dev);
 421         if (WARN_ON(!mdev))
 422                 return ERR_PTR(-EINVAL);
 423
 424         node = of_find_node_by_phandle(phandle);
 425         if (!node) {
 426                 pr_err("%s: could not find node phandle 0x%x\n",
 427                        __func__, phandle);
 428                 return ERR_PTR(-ENODEV);
 429         }
 430
 431         for (i = 0; i < controller->num_chans; i++) {
 432                 mbox = controller->chans[i].con_priv;
 433                 if (!strcmp(mbox->name, node->name)) {
 434                         of_node_put(node);
 435                         return &controller->chans[i];
 436                 }
 437         }
 438
 439         of_node_put(node);
 440         return ERR_PTR(-ENOENT);
 441 }
 442
 443 static int omap_mbox_probe(struct platform_device *pdev)
 444 {
 445         int ret;
 446         struct mbox_chan *chnls;
 447         struct omap_mbox *mbox;
 448         struct omap_mbox_device *mdev;
 449         struct omap_mbox_fifo *fifo;
 450         struct device_node *node = pdev->dev.of_node;
 451         struct device_node *child;
 452         const struct omap_mbox_match_data *match_data;
 453         struct mbox_controller *controller;
 454         u32 intr_type, info_count;
 455         u32 num_users, num_fifos;
 456         u32 tmp[3];
 457         u32 l;
 458         int i;
 459
 460         if (!node) {
 461                 pr_err("%s: only DT-based devices are supported\n", __func__);
 462                 return -ENODEV;
 463         }
 464
 465         match_data = of_device_get_match_data(&pdev->dev);
 466         if (!match_data)
 467                 return -ENODEV;
 468         intr_type = match_data->intr_type;
 469
 470         if (of_property_read_u32(node, "ti,mbox-num-users", &num_users))
 471                 return -ENODEV;
 472
 473         if (of_property_read_u32(node, "ti,mbox-num-fifos", &num_fifos))
 474                 return -ENODEV;
 475
 476         info_count = of_get_available_child_count(node);
 477         if (!info_count) {
 478                 dev_err(&pdev->dev, "no available mbox devices found\n");
 479                 return -ENODEV;
 480         }
 481
 482         mdev = devm_kzalloc(&pdev->dev, sizeof(*mdev), GFP_KERNEL);
 483         if (!mdev)
 484                 return -ENOMEM;
 485
 486         mdev->mbox_base = devm_platform_ioremap_resource(pdev, 0);
 487         if (IS_ERR(mdev->mbox_base))
 488                 return PTR_ERR(mdev->mbox_base);
 489
 490         mdev->irq_ctx = devm_kcalloc(&pdev->dev, num_users, sizeof(u32),
 491                                      GFP_KERNEL);
 492         if (!mdev->irq_ctx)
 493                 return -ENOMEM;
 494
 495         chnls = devm_kcalloc(&pdev->dev, info_count + 1, sizeof(*chnls),
 496                              GFP_KERNEL);
 497         if (!chnls)
 498                 return -ENOMEM;
 499
 500         child = NULL;
 501         for (i = 0; i < info_count; i++) {
 502                 int tx_id, tx_irq, tx_usr;
 503                 int rx_id,         rx_usr;
 504
 505                 mbox = devm_kzalloc(&pdev->dev, sizeof(*mbox), GFP_KERNEL);
 506                 if (!mbox)
 507                         return -ENOMEM;
 508
 509                 child = of_get_next_available_child(node, child);
 510                 ret = of_property_read_u32_array(child, "ti,mbox-tx", tmp,
 511                                                  ARRAY_SIZE(tmp));
 512                 if (ret)
 513                         return ret;
 514                 tx_id = tmp[0];
 515                 tx_irq = tmp[1];
 516                 tx_usr = tmp[2];
 517
 518                 ret = of_property_read_u32_array(child, "ti,mbox-rx", tmp,
 519                                                  ARRAY_SIZE(tmp));
 520                 if (ret)
 521                         return ret;
 522                 rx_id = tmp[0];
 523                 /* rx_irq = tmp[1]; */
 524                 rx_usr = tmp[2];
 525
 526                 if (tx_id >= num_fifos || rx_id >= num_fifos ||
 527                     tx_usr >= num_users || rx_usr >= num_users)
 528                         return -EINVAL;
 529
 530                 fifo = &mbox->tx_fifo;
 531                 fifo->msg = MAILBOX_MESSAGE(tx_id);
 532                 fifo->fifo_stat = MAILBOX_FIFOSTATUS(tx_id);
 533                 fifo->intr_bit = MAILBOX_IRQ_NOTFULL(tx_id);
 534                 fifo->irqenable = MAILBOX_IRQENABLE(intr_type, tx_usr);
 535                 fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, tx_usr);
 536                 fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, tx_usr);
 537
 538                 fifo = &mbox->rx_fifo;
 539                 fifo->msg = MAILBOX_MESSAGE(rx_id);
 540                 fifo->msg_stat =  MAILBOX_MSGSTATUS(rx_id);
 541                 fifo->intr_bit = MAILBOX_IRQ_NEWMSG(rx_id);
 542                 fifo->irqenable = MAILBOX_IRQENABLE(intr_type, rx_usr);
 543                 fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, rx_usr);
 544                 fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, rx_usr);
 545
 546                 mbox->send_no_irq = of_property_read_bool(child, "ti,mbox-send-noirq");
 547                 mbox->intr_type = intr_type;
 548
 549                 mbox->parent = mdev;
 550                 mbox->name = child->name;
 551                 mbox->irq = platform_get_irq(pdev, tx_irq);
 552                 if (mbox->irq < 0)
 553                         return mbox->irq;
 554                 mbox->chan = &chnls[i];
 555                 chnls[i].con_priv = mbox;
 556         }
 557
 558         mutex_init(&mdev->cfg_lock);
 559         mdev->dev = &pdev->dev;
 560         mdev->num_users = num_users;
 561         mdev->num_fifos = num_fifos;
 562         mdev->intr_type = intr_type;
 563
 564         controller = devm_kzalloc(&pdev->dev, sizeof(*controller), GFP_KERNEL);
 565         if (!controller)
 566                 return -ENOMEM;
 567         /*
 568          * OMAP/K3 Mailbox IP does not have a Tx-Done IRQ, but rather a Tx-Ready
 569          * IRQ and is needed to run the Tx state machine
 570          */
 571         controller->txdone_irq = true;
 572         controller->dev = mdev->dev;
 573         controller->ops = &omap_mbox_chan_ops;
 574         controller->chans = chnls;
 575         controller->num_chans = info_count;
 576         controller->of_xlate = omap_mbox_of_xlate;
 577         ret = devm_mbox_controller_register(mdev->dev, controller);
 578         if (ret)
 579                 return ret;
 580
 581         platform_set_drvdata(pdev, mdev);
 582         devm_pm_runtime_enable(mdev->dev);
 583
 584         ret = pm_runtime_resume_and_get(mdev->dev);
 585         if (ret < 0)
 586                 return ret;
 587
 588         /*
 589          * just print the raw revision register, the format is not
 590          * uniform across all SoCs
 591          */
 592         l = mbox_read_reg(mdev, MAILBOX_REVISION);
 593         dev_info(mdev->dev, "omap mailbox rev 0x%x\n", l);
 594
 595         ret = pm_runtime_put_sync(mdev->dev);
 596         if (ret < 0 && ret != -ENOSYS)
 597                 return ret;
 598
 599         return 0;
 600 }
 601
 602 static struct platform_driver omap_mbox_driver = {
 603         .probe  = omap_mbox_probe,
 604         .driver = {
 605                 .name = "omap-mailbox",
 606                 .pm = &omap_mbox_pm_ops,
 607                 .of_match_table = omap_mailbox_of_match,
 608         },
 609 };
 610 module_platform_driver(omap_mbox_driver);
 611
 612 MODULE_LICENSE("GPL v2");
 613 MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging");
 614 MODULE_AUTHOR("Toshihiro Kobayashi");
 615 MODULE_AUTHOR("Hiroshi DOYU");