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Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / media / i2c / adv7604.c
blobe271782b7b70bd15beff57aa5436d453e4d8ebab
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * adv7604 - Analog Devices ADV7604 video decoder driver
4 *
5 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
6 *
7 */
8
9 /*
10 * References (c = chapter, p = page):
11 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
12 * Revision 2.5, June 2010
13 * REF_02 - Analog devices, Register map documentation, Documentation of
14 * the register maps, Software manual, Rev. F, June 2010
15 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
16 */
17
18 #include <linux/delay.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/hdmi.h>
21 #include <linux/i2c.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/of_graph.h>
25 #include <linux/slab.h>
26 #include <linux/v4l2-dv-timings.h>
27 #include <linux/videodev2.h>
28 #include <linux/workqueue.h>
29 #include <linux/regmap.h>
30 #include <linux/interrupt.h>
31
32 #include <media/i2c/adv7604.h>
33 #include <media/cec.h>
34 #include <media/v4l2-ctrls.h>
35 #include <media/v4l2-device.h>
36 #include <media/v4l2-event.h>
37 #include <media/v4l2-dv-timings.h>
38 #include <media/v4l2-fwnode.h>
39
40 static int debug;
41 module_param(debug, int, 0644);
42 MODULE_PARM_DESC(debug, "debug level (0-2)");
43
44 MODULE_DESCRIPTION("Analog Devices ADV7604/10/11/12 video decoder driver");
45 MODULE_AUTHOR("Hans Verkuil <hansverk@cisco.com>");
46 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
47 MODULE_LICENSE("GPL");
48
49 /* ADV7604 system clock frequency */
50 #define ADV76XX_FSC (28636360)
51
52 #define ADV76XX_RGB_OUT (1 << 1)
53
54 #define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0)
55 #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
56 #define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0)
57
58 #define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5)
59 #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
60 #define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5)
61 #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5)
62 #define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5)
63 #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5)
64
65 #define ADV76XX_OP_CH_SEL_GBR (0 << 5)
66 #define ADV76XX_OP_CH_SEL_GRB (1 << 5)
67 #define ADV76XX_OP_CH_SEL_BGR (2 << 5)
68 #define ADV76XX_OP_CH_SEL_RGB (3 << 5)
69 #define ADV76XX_OP_CH_SEL_BRG (4 << 5)
70 #define ADV76XX_OP_CH_SEL_RBG (5 << 5)
71
72 #define ADV76XX_OP_SWAP_CB_CR (1 << 0)
73
74 #define ADV76XX_MAX_ADDRS (3)
75
76 #define ADV76XX_MAX_EDID_BLOCKS 4
77
78 enum adv76xx_type {
79 ADV7604,
80 ADV7611, // including ADV7610
81 ADV7612,
82 };
83
84 struct adv76xx_reg_seq {
85 unsigned int reg;
86 u8 val;
87 };
88
89 struct adv76xx_format_info {
90 u32 code;
91 u8 op_ch_sel;
92 bool rgb_out;
93 bool swap_cb_cr;
94 u8 op_format_sel;
95 };
96
97 struct adv76xx_cfg_read_infoframe {
98 const char *desc;
99 u8 present_mask;
100 u8 head_addr;
101 u8 payload_addr;
102 };
103
104 struct adv76xx_chip_info {
105 enum adv76xx_type type;
106
107 bool has_afe;
108 unsigned int max_port;
109 unsigned int num_dv_ports;
110
111 unsigned int edid_enable_reg;
112 unsigned int edid_status_reg;
113 unsigned int edid_segment_reg;
114 unsigned int edid_segment_mask;
115 unsigned int edid_spa_loc_reg;
116 unsigned int edid_spa_loc_msb_mask;
117 unsigned int edid_spa_port_b_reg;
118 unsigned int lcf_reg;
119
120 unsigned int cable_det_mask;
121 unsigned int tdms_lock_mask;
122 unsigned int fmt_change_digital_mask;
123 unsigned int cp_csc;
124
125 unsigned int cec_irq_status;
126 unsigned int cec_rx_enable;
127 unsigned int cec_rx_enable_mask;
128 bool cec_irq_swap;
129
130 const struct adv76xx_format_info *formats;
131 unsigned int nformats;
132
133 void (*set_termination)(struct v4l2_subdev *sd, bool enable);
134 void (*setup_irqs)(struct v4l2_subdev *sd);
135 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
136 unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
137
138 /* 0 = AFE, 1 = HDMI */
139 const struct adv76xx_reg_seq *recommended_settings[2];
140 unsigned int num_recommended_settings[2];
141
142 unsigned long page_mask;
143
144 /* Masks for timings */
145 unsigned int linewidth_mask;
146 unsigned int field0_height_mask;
147 unsigned int field1_height_mask;
148 unsigned int hfrontporch_mask;
149 unsigned int hsync_mask;
150 unsigned int hbackporch_mask;
151 unsigned int field0_vfrontporch_mask;
152 unsigned int field1_vfrontporch_mask;
153 unsigned int field0_vsync_mask;
154 unsigned int field1_vsync_mask;
155 unsigned int field0_vbackporch_mask;
156 unsigned int field1_vbackporch_mask;
157 };
158
159 /*
160 **********************************************************************
161 *
162 * Arrays with configuration parameters for the ADV7604
163 *
164 **********************************************************************
165 */
166
167 struct adv76xx_state {
168 const struct adv76xx_chip_info *info;
169 struct adv76xx_platform_data pdata;
170
171 struct gpio_desc *hpd_gpio[4];
172 struct gpio_desc *reset_gpio;
173
174 struct v4l2_subdev sd;
175 struct media_pad pads[ADV76XX_PAD_MAX];
176 unsigned int source_pad;
177
178 struct v4l2_ctrl_handler hdl;
179
180 enum adv76xx_pad selected_input;
181
182 struct v4l2_dv_timings timings;
183 const struct adv76xx_format_info *format;
184
185 struct {
186 u8 edid[ADV76XX_MAX_EDID_BLOCKS * 128];
187 u32 present;
188 unsigned blocks;
189 } edid;
190 u16 spa_port_a[2];
191 struct v4l2_fract aspect_ratio;
192 u32 rgb_quantization_range;
193 struct delayed_work delayed_work_enable_hotplug;
194 bool restart_stdi_once;
195
196 struct dentry *debugfs_dir;
197 struct v4l2_debugfs_if *infoframes;
198
199 /* CEC */
200 struct cec_adapter *cec_adap;
201 u8 cec_addr[ADV76XX_MAX_ADDRS];
202 u8 cec_valid_addrs;
203 bool cec_enabled_adap;
204
205 /* i2c clients */
206 struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
207
208 /* Regmaps */
209 struct regmap *regmap[ADV76XX_PAGE_MAX];
210
211 /* controls */
212 struct v4l2_ctrl *detect_tx_5v_ctrl;
213 struct v4l2_ctrl *analog_sampling_phase_ctrl;
214 struct v4l2_ctrl *free_run_color_manual_ctrl;
215 struct v4l2_ctrl *free_run_color_ctrl;
216 struct v4l2_ctrl *rgb_quantization_range_ctrl;
217 };
218
219 static bool adv76xx_has_afe(struct adv76xx_state *state)
220 {
221 return state->info->has_afe;
222 }
223
224 /* Unsupported timings. This device cannot support 720p30. */
225 static const struct v4l2_dv_timings adv76xx_timings_exceptions[] = {
226 V4L2_DV_BT_CEA_1280X720P30,
227 { }
228 };
229
230 static bool adv76xx_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
231 {
232 int i;
233
234 for (i = 0; adv76xx_timings_exceptions[i].bt.width; i++)
235 if (v4l2_match_dv_timings(t, adv76xx_timings_exceptions + i, 0, false))
236 return false;
237 return true;
238 }
239
240 struct adv76xx_video_standards {
241 struct v4l2_dv_timings timings;
242 u8 vid_std;
243 u8 v_freq;
244 };
245
246 /* sorted by number of lines */
247 static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
248 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
249 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
250 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
251 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
252 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
253 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
254 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
255 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
256 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
257 /* TODO add 1920x1080P60_RB (CVT timing) */
258 { },
259 };
260
261 /* sorted by number of lines */
262 static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
263 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
264 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
265 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
266 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
267 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
268 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
269 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
270 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
271 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
272 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
273 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
274 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
275 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
276 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
277 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
278 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
279 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
280 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
281 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
282 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
283 /* TODO add 1600X1200P60_RB (not a DMT timing) */
284 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
285 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
286 { },
287 };
288
289 /* sorted by number of lines */
290 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
291 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
292 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
293 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
294 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
295 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
296 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
297 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
298 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
299 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
300 { },
301 };
302
303 /* sorted by number of lines */
304 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
305 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
306 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
307 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
308 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
309 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
310 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
311 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
312 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
313 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
314 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
315 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
316 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
317 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
318 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
319 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
320 { },
321 };
322
323 static const struct v4l2_event adv76xx_ev_fmt = {
324 .type = V4L2_EVENT_SOURCE_CHANGE,
325 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
326 };
327
328 /* ----------------------------------------------------------------------- */
329
330 static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
331 {
332 return container_of(sd, struct adv76xx_state, sd);
333 }
334
335 static inline unsigned htotal(const struct v4l2_bt_timings *t)
336 {
337 return V4L2_DV_BT_FRAME_WIDTH(t);
338 }
339
340 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
341 {
342 return V4L2_DV_BT_FRAME_HEIGHT(t);
343 }
344
345 /* ----------------------------------------------------------------------- */
346
347 static int adv76xx_read_check(struct adv76xx_state *state,
348 int client_page, u8 reg)
349 {
350 struct i2c_client *client = state->i2c_clients[client_page];
351 int err;
352 unsigned int val;
353
354 err = regmap_read(state->regmap[client_page], reg, &val);
355
356 if (err) {
357 v4l_err(client, "error reading %02x, %02x\n",
358 client->addr, reg);
359 return err;
360 }
361 return val;
362 }
363
364 /* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX
365 * size to one or more registers.
366 *
367 * A value of zero will be returned on success, a negative errno will
368 * be returned in error cases.
369 */
370 static int adv76xx_write_block(struct adv76xx_state *state, int client_page,
371 unsigned int init_reg, const void *val,
372 size_t val_len)
373 {
374 struct regmap *regmap = state->regmap[client_page];
375
376 if (val_len > I2C_SMBUS_BLOCK_MAX)
377 val_len = I2C_SMBUS_BLOCK_MAX;
378
379 return regmap_raw_write(regmap, init_reg, val, val_len);
380 }
381
382 /* ----------------------------------------------------------------------- */
383
384 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
385 {
386 struct adv76xx_state *state = to_state(sd);
387
388 return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg);
389 }
390
391 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
392 {
393 struct adv76xx_state *state = to_state(sd);
394
395 return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val);
396 }
397
398 static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
399 u8 val)
400 {
401 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
402 }
403
404 static inline int __always_unused avlink_read(struct v4l2_subdev *sd, u8 reg)
405 {
406 struct adv76xx_state *state = to_state(sd);
407
408 return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg);
409 }
410
411 static inline int __always_unused avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
412 {
413 struct adv76xx_state *state = to_state(sd);
414
415 return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val);
416 }
417
418 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
419 {
420 struct adv76xx_state *state = to_state(sd);
421
422 return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg);
423 }
424
425 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
426 {
427 struct adv76xx_state *state = to_state(sd);
428
429 return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val);
430 }
431
432 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
433 u8 val)
434 {
435 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
436 }
437
438 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
439 {
440 struct adv76xx_state *state = to_state(sd);
441
442 return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg);
443 }
444
445 static inline int __always_unused infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
446 {
447 struct adv76xx_state *state = to_state(sd);
448
449 return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val);
450 }
451
452 static inline int __always_unused afe_read(struct v4l2_subdev *sd, u8 reg)
453 {
454 struct adv76xx_state *state = to_state(sd);
455
456 return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg);
457 }
458
459 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
460 {
461 struct adv76xx_state *state = to_state(sd);
462
463 return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val);
464 }
465
466 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
467 {
468 struct adv76xx_state *state = to_state(sd);
469
470 return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg);
471 }
472
473 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
474 {
475 struct adv76xx_state *state = to_state(sd);
476
477 return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val);
478 }
479
480 static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
481 {
482 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
483 }
484
485 static inline int __always_unused edid_read(struct v4l2_subdev *sd, u8 reg)
486 {
487 struct adv76xx_state *state = to_state(sd);
488
489 return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg);
490 }
491
492 static inline int __always_unused edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
493 {
494 struct adv76xx_state *state = to_state(sd);
495
496 return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val);
497 }
498
499 static inline int edid_write_block(struct v4l2_subdev *sd,
500 unsigned int total_len, const u8 *val)
501 {
502 struct adv76xx_state *state = to_state(sd);
503 int err = 0;
504 int i = 0;
505 int len = 0;
506
507 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n",
508 __func__, total_len);
509
510 while (!err && i < total_len) {
511 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ?
512 I2C_SMBUS_BLOCK_MAX :
513 (total_len - i);
514
515 err = adv76xx_write_block(state, ADV76XX_PAGE_EDID,
516 i, val + i, len);
517 i += len;
518 }
519
520 return err;
521 }
522
523 static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
524 {
525 const struct adv76xx_chip_info *info = state->info;
526 unsigned int i;
527
528 if (info->type == ADV7604) {
529 for (i = 0; i < state->info->num_dv_ports; ++i)
530 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
531 } else {
532 for (i = 0; i < state->info->num_dv_ports; ++i)
533 io_write_clr_set(&state->sd, 0x20, 0x80 >> i,
534 (!!(hpd & BIT(i))) << (7 - i));
535 }
536
537 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
538 }
539
540 static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
541 {
542 struct delayed_work *dwork = to_delayed_work(work);
543 struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
544 delayed_work_enable_hotplug);
545 struct v4l2_subdev *sd = &state->sd;
546
547 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
548
549 adv76xx_set_hpd(state, state->edid.present);
550 }
551
552 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
553 {
554 struct adv76xx_state *state = to_state(sd);
555
556 return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg);
557 }
558
559 static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
560 {
561 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
562 }
563
564 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
565 {
566 struct adv76xx_state *state = to_state(sd);
567
568 return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val);
569 }
570
571 static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
572 {
573 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
574 }
575
576 static inline int __always_unused test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
577 {
578 struct adv76xx_state *state = to_state(sd);
579
580 return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val);
581 }
582
583 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
584 {
585 struct adv76xx_state *state = to_state(sd);
586
587 return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg);
588 }
589
590 static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
591 {
592 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
593 }
594
595 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
596 {
597 struct adv76xx_state *state = to_state(sd);
598
599 return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val);
600 }
601
602 static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
603 {
604 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
605 }
606
607 static inline int __always_unused vdp_read(struct v4l2_subdev *sd, u8 reg)
608 {
609 struct adv76xx_state *state = to_state(sd);
610
611 return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg);
612 }
613
614 static inline int __always_unused vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
615 {
616 struct adv76xx_state *state = to_state(sd);
617
618 return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val);
619 }
620
621 #define ADV76XX_REG(page, offset) (((page) << 8) | (offset))
622 #define ADV76XX_REG_SEQ_TERM 0xffff
623
624 #ifdef CONFIG_VIDEO_ADV_DEBUG
625 static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
626 {
627 struct adv76xx_state *state = to_state(sd);
628 unsigned int page = reg >> 8;
629 unsigned int val;
630 int err;
631
632 if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask))
633 return -EINVAL;
634
635 reg &= 0xff;
636 err = regmap_read(state->regmap[page], reg, &val);
637
638 return err ? err : val;
639 }
640 #endif
641
642 static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
643 {
644 struct adv76xx_state *state = to_state(sd);
645 unsigned int page = reg >> 8;
646
647 if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask))
648 return -EINVAL;
649
650 reg &= 0xff;
651
652 return regmap_write(state->regmap[page], reg, val);
653 }
654
655 static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
656 const struct adv76xx_reg_seq *reg_seq)
657 {
658 unsigned int i;
659
660 for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
661 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
662 }
663
664 /* -----------------------------------------------------------------------------
665 * Format helpers
666 */
667
668 static const struct adv76xx_format_info adv7604_formats[] = {
669 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
670 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
671 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
672 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
673 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
674 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
675 { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
676 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
677 { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
678 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
679 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
680 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
681 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
682 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
683 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
684 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
685 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
686 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
687 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
688 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
689 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
690 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
691 { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
692 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
693 { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
694 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
695 { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
696 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
697 { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
698 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
699 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
700 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
701 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
702 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
703 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
704 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
705 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
706 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
707 };
708
709 static const struct adv76xx_format_info adv7611_formats[] = {
710 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
711 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
712 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
713 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
714 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
715 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
716 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
717 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
718 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
719 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
720 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
721 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
722 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
723 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
724 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
725 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
726 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
727 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
728 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
729 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
730 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
731 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
732 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
733 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
734 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
735 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
736 };
737
738 static const struct adv76xx_format_info adv7612_formats[] = {
739 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
740 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
741 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
742 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
743 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
744 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
745 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
746 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
747 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
748 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
749 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
750 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
751 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
752 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
753 };
754
755 static const struct adv76xx_format_info *
756 adv76xx_format_info(struct adv76xx_state *state, u32 code)
757 {
758 unsigned int i;
759
760 for (i = 0; i < state->info->nformats; ++i) {
761 if (state->info->formats[i].code == code)
762 return &state->info->formats[i];
763 }
764
765 return NULL;
766 }
767
768 /* ----------------------------------------------------------------------- */
769
770 static inline bool is_analog_input(struct v4l2_subdev *sd)
771 {
772 struct adv76xx_state *state = to_state(sd);
773
774 return state->selected_input == ADV7604_PAD_VGA_RGB ||
775 state->selected_input == ADV7604_PAD_VGA_COMP;
776 }
777
778 static inline bool is_digital_input(struct v4l2_subdev *sd)
779 {
780 struct adv76xx_state *state = to_state(sd);
781
782 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
783 state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
784 state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
785 state->selected_input == ADV7604_PAD_HDMI_PORT_D;
786 }
787
788 static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = {
789 .type = V4L2_DV_BT_656_1120,
790 /* keep this initialization for compatibility with GCC < 4.4.6 */
791 .reserved = { 0 },
792 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000,
793 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
794 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
795 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
796 V4L2_DV_BT_CAP_CUSTOM)
797 };
798
799 static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = {
800 .type = V4L2_DV_BT_656_1120,
801 /* keep this initialization for compatibility with GCC < 4.4.6 */
802 .reserved = { 0 },
803 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000,
804 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
805 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
806 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
807 V4L2_DV_BT_CAP_CUSTOM)
808 };
809
810 /*
811 * Return the DV timings capabilities for the requested sink pad. As a special
812 * case, pad value -1 returns the capabilities for the currently selected input.
813 */
814 static const struct v4l2_dv_timings_cap *
815 adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd, int pad)
816 {
817 if (pad == -1) {
818 struct adv76xx_state *state = to_state(sd);
819
820 pad = state->selected_input;
821 }
822
823 switch (pad) {
824 case ADV76XX_PAD_HDMI_PORT_A:
825 case ADV7604_PAD_HDMI_PORT_B:
826 case ADV7604_PAD_HDMI_PORT_C:
827 case ADV7604_PAD_HDMI_PORT_D:
828 return &adv76xx_timings_cap_digital;
829
830 case ADV7604_PAD_VGA_RGB:
831 case ADV7604_PAD_VGA_COMP:
832 default:
833 return &adv7604_timings_cap_analog;
834 }
835 }
836
837
838 /* ----------------------------------------------------------------------- */
839
840 #ifdef CONFIG_VIDEO_ADV_DEBUG
841 static void adv76xx_inv_register(struct v4l2_subdev *sd)
842 {
843 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
844 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
845 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
846 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
847 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
848 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
849 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
850 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
851 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
852 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
853 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
854 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
855 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
856 }
857
858 static int adv76xx_g_register(struct v4l2_subdev *sd,
859 struct v4l2_dbg_register *reg)
860 {
861 int ret;
862
863 ret = adv76xx_read_reg(sd, reg->reg);
864 if (ret < 0) {
865 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
866 adv76xx_inv_register(sd);
867 return ret;
868 }
869
870 reg->size = 1;
871 reg->val = ret;
872
873 return 0;
874 }
875
876 static int adv76xx_s_register(struct v4l2_subdev *sd,
877 const struct v4l2_dbg_register *reg)
878 {
879 int ret;
880
881 ret = adv76xx_write_reg(sd, reg->reg, reg->val);
882 if (ret < 0) {
883 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
884 adv76xx_inv_register(sd);
885 return ret;
886 }
887
888 return 0;
889 }
890 #endif
891
892 static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
893 {
894 u8 value = io_read(sd, 0x6f);
895
896 return ((value & 0x10) >> 4)
897 | ((value & 0x08) >> 2)
898 | ((value & 0x04) << 0)
899 | ((value & 0x02) << 2);
900 }
901
902 static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
903 {
904 u8 value = io_read(sd, 0x6f);
905
906 return value & 1;
907 }
908
909 static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd)
910 {
911 /* Reads CABLE_DET_A_RAW. For input B support, need to
912 * account for bit 7 [MSB] of 0x6a (ie. CABLE_DET_B_RAW)
913 */
914 u8 value = io_read(sd, 0x6f);
915
916 return value & 1;
917 }
918
919 static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
920 {
921 struct adv76xx_state *state = to_state(sd);
922 const struct adv76xx_chip_info *info = state->info;
923 u16 cable_det = info->read_cable_det(sd);
924
925 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det);
926 }
927
928 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
929 u8 prim_mode,
930 const struct adv76xx_video_standards *predef_vid_timings,
931 const struct v4l2_dv_timings *timings)
932 {
933 int i;
934
935 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
936 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
937 is_digital_input(sd) ? 250000 : 1000000, false))
938 continue;
939 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
940 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
941 prim_mode); /* v_freq and prim mode */
942 return 0;
943 }
944
945 return -1;
946 }
947
948 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
949 struct v4l2_dv_timings *timings)
950 {
951 struct adv76xx_state *state = to_state(sd);
952 int err;
953
954 v4l2_dbg(1, debug, sd, "%s", __func__);
955
956 if (adv76xx_has_afe(state)) {
957 /* reset to default values */
958 io_write(sd, 0x16, 0x43);
959 io_write(sd, 0x17, 0x5a);
960 }
961 /* disable embedded syncs for auto graphics mode */
962 cp_write_clr_set(sd, 0x81, 0x10, 0x00);
963 cp_write(sd, 0x8f, 0x00);
964 cp_write(sd, 0x90, 0x00);
965 cp_write(sd, 0xa2, 0x00);
966 cp_write(sd, 0xa3, 0x00);
967 cp_write(sd, 0xa4, 0x00);
968 cp_write(sd, 0xa5, 0x00);
969 cp_write(sd, 0xa6, 0x00);
970 cp_write(sd, 0xa7, 0x00);
971 cp_write(sd, 0xab, 0x00);
972 cp_write(sd, 0xac, 0x00);
973
974 if (is_analog_input(sd)) {
975 err = find_and_set_predefined_video_timings(sd,
976 0x01, adv7604_prim_mode_comp, timings);
977 if (err)
978 err = find_and_set_predefined_video_timings(sd,
979 0x02, adv7604_prim_mode_gr, timings);
980 } else if (is_digital_input(sd)) {
981 err = find_and_set_predefined_video_timings(sd,
982 0x05, adv76xx_prim_mode_hdmi_comp, timings);
983 if (err)
984 err = find_and_set_predefined_video_timings(sd,
985 0x06, adv76xx_prim_mode_hdmi_gr, timings);
986 } else {
987 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
988 __func__, state->selected_input);
989 err = -1;
990 }
991
992
993 return err;
994 }
995
996 static void configure_custom_video_timings(struct v4l2_subdev *sd,
997 const struct v4l2_bt_timings *bt)
998 {
999 struct adv76xx_state *state = to_state(sd);
1000 u32 width = htotal(bt);
1001 u32 height = vtotal(bt);
1002 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
1003 u16 cp_start_eav = width - bt->hfrontporch;
1004 u16 cp_start_vbi = height - bt->vfrontporch;
1005 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
1006 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
1007 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
1008 const u8 pll[2] = {
1009 0xc0 | ((width >> 8) & 0x1f),
1010 width & 0xff
1011 };
1012
1013 v4l2_dbg(2, debug, sd, "%s\n", __func__);
1014
1015 if (is_analog_input(sd)) {
1016 /* auto graphics */
1017 io_write(sd, 0x00, 0x07); /* video std */
1018 io_write(sd, 0x01, 0x02); /* prim mode */
1019 /* enable embedded syncs for auto graphics mode */
1020 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
1021
1022 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1023 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1024 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
1025 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO],
1026 0x16, pll, 2))
1027 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1028
1029 /* active video - horizontal timing */
1030 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
1031 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
1032 ((cp_start_eav >> 8) & 0x0f));
1033 cp_write(sd, 0xa4, cp_start_eav & 0xff);
1034
1035 /* active video - vertical timing */
1036 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1037 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1038 ((cp_end_vbi >> 8) & 0xf));
1039 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1040 } else if (is_digital_input(sd)) {
1041 /* set default prim_mode/vid_std for HDMI
1042 according to [REF_03, c. 4.2] */
1043 io_write(sd, 0x00, 0x02); /* video std */
1044 io_write(sd, 0x01, 0x06); /* prim mode */
1045 } else {
1046 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1047 __func__, state->selected_input);
1048 }
1049
1050 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1051 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1052 cp_write(sd, 0xab, (height >> 4) & 0xff);
1053 cp_write(sd, 0xac, (height & 0x0f) << 4);
1054 }
1055
1056 static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1057 {
1058 struct adv76xx_state *state = to_state(sd);
1059 u8 offset_buf[4];
1060
1061 if (auto_offset) {
1062 offset_a = 0x3ff;
1063 offset_b = 0x3ff;
1064 offset_c = 0x3ff;
1065 }
1066
1067 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1068 __func__, auto_offset ? "Auto" : "Manual",
1069 offset_a, offset_b, offset_c);
1070
1071 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1072 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1073 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1074 offset_buf[3] = offset_c & 0x0ff;
1075
1076 /* Registers must be written in this order with no i2c access in between */
1077 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1078 0x77, offset_buf, 4))
1079 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1080 }
1081
1082 static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1083 {
1084 struct adv76xx_state *state = to_state(sd);
1085 u8 gain_buf[4];
1086 u8 gain_man = 1;
1087 u8 agc_mode_man = 1;
1088
1089 if (auto_gain) {
1090 gain_man = 0;
1091 agc_mode_man = 0;
1092 gain_a = 0x100;
1093 gain_b = 0x100;
1094 gain_c = 0x100;
1095 }
1096
1097 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1098 __func__, auto_gain ? "Auto" : "Manual",
1099 gain_a, gain_b, gain_c);
1100
1101 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1102 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1103 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1104 gain_buf[3] = ((gain_c & 0x0ff));
1105
1106 /* Registers must be written in this order with no i2c access in between */
1107 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1108 0x73, gain_buf, 4))
1109 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1110 }
1111
1112 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1113 {
1114 struct adv76xx_state *state = to_state(sd);
1115 bool rgb_output = io_read(sd, 0x02) & 0x02;
1116 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1117 u8 y = HDMI_COLORSPACE_RGB;
1118
1119 if (hdmi_signal && (io_read(sd, 0x60) & 1))
1120 y = infoframe_read(sd, 0x01) >> 5;
1121
1122 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1123 __func__, state->rgb_quantization_range,
1124 rgb_output, hdmi_signal);
1125
1126 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1127 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
1128 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);
1129
1130 switch (state->rgb_quantization_range) {
1131 case V4L2_DV_RGB_RANGE_AUTO:
1132 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
1133 /* Receiving analog RGB signal
1134 * Set RGB full range (0-255) */
1135 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1136 break;
1137 }
1138
1139 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1140 /* Receiving analog YPbPr signal
1141 * Set automode */
1142 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1143 break;
1144 }
1145
1146 if (hdmi_signal) {
1147 /* Receiving HDMI signal
1148 * Set automode */
1149 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1150 break;
1151 }
1152
1153 /* Receiving DVI-D signal
1154 * ADV7604 selects RGB limited range regardless of
1155 * input format (CE/IT) in automatic mode */
1156 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
1157 /* RGB limited range (16-235) */
1158 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1159 } else {
1160 /* RGB full range (0-255) */
1161 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1162
1163 if (is_digital_input(sd) && rgb_output) {
1164 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1165 } else {
1166 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1167 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1168 }
1169 }
1170 break;
1171 case V4L2_DV_RGB_RANGE_LIMITED:
1172 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1173 /* YCrCb limited range (16-235) */
1174 io_write_clr_set(sd, 0x02, 0xf0, 0x20);
1175 break;
1176 }
1177
1178 if (y != HDMI_COLORSPACE_RGB)
1179 break;
1180
1181 /* RGB limited range (16-235) */
1182 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1183
1184 break;
1185 case V4L2_DV_RGB_RANGE_FULL:
1186 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1187 /* YCrCb full range (0-255) */
1188 io_write_clr_set(sd, 0x02, 0xf0, 0x60);
1189 break;
1190 }
1191
1192 if (y != HDMI_COLORSPACE_RGB)
1193 break;
1194
1195 /* RGB full range (0-255) */
1196 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1197
1198 if (is_analog_input(sd) || hdmi_signal)
1199 break;
1200
1201 /* Adjust gain/offset for DVI-D signals only */
1202 if (rgb_output) {
1203 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1204 } else {
1205 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1206 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1207 }
1208 break;
1209 }
1210 }
1211
1212 static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
1213 {
1214 struct v4l2_subdev *sd =
1215 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1216
1217 struct adv76xx_state *state = to_state(sd);
1218
1219 switch (ctrl->id) {
1220 case V4L2_CID_BRIGHTNESS:
1221 cp_write(sd, 0x3c, ctrl->val);
1222 return 0;
1223 case V4L2_CID_CONTRAST:
1224 cp_write(sd, 0x3a, ctrl->val);
1225 return 0;
1226 case V4L2_CID_SATURATION:
1227 cp_write(sd, 0x3b, ctrl->val);
1228 return 0;
1229 case V4L2_CID_HUE:
1230 cp_write(sd, 0x3d, ctrl->val);
1231 return 0;
1232 case V4L2_CID_DV_RX_RGB_RANGE:
1233 state->rgb_quantization_range = ctrl->val;
1234 set_rgb_quantization_range(sd);
1235 return 0;
1236 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1237 if (!adv76xx_has_afe(state))
1238 return -EINVAL;
1239 /* Set the analog sampling phase. This is needed to find the
1240 best sampling phase for analog video: an application or
1241 driver has to try a number of phases and analyze the picture
1242 quality before settling on the best performing phase. */
1243 afe_write(sd, 0xc8, ctrl->val);
1244 return 0;
1245 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1246 /* Use the default blue color for free running mode,
1247 or supply your own. */
1248 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
1249 return 0;
1250 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1251 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1252 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1253 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1254 return 0;
1255 }
1256 return -EINVAL;
1257 }
1258
1259 static int adv76xx_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1260 {
1261 struct v4l2_subdev *sd =
1262 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1263
1264 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
1265 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1266 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1267 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1268 return 0;
1269 }
1270 return -EINVAL;
1271 }
1272
1273 /* ----------------------------------------------------------------------- */
1274
1275 static inline bool no_power(struct v4l2_subdev *sd)
1276 {
1277 /* Entire chip or CP powered off */
1278 return io_read(sd, 0x0c) & 0x24;
1279 }
1280
1281 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1282 {
1283 struct adv76xx_state *state = to_state(sd);
1284
1285 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1286 }
1287
1288 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1289 {
1290 struct adv76xx_state *state = to_state(sd);
1291 const struct adv76xx_chip_info *info = state->info;
1292
1293 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
1294 }
1295
1296 static inline bool is_hdmi(struct v4l2_subdev *sd)
1297 {
1298 return hdmi_read(sd, 0x05) & 0x80;
1299 }
1300
1301 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1302 {
1303 struct adv76xx_state *state = to_state(sd);
1304
1305 /*
1306 * Chips without a AFE don't expose registers for the SSPD, so just assume
1307 * that we have a lock.
1308 */
1309 if (adv76xx_has_afe(state))
1310 return false;
1311
1312 /* TODO channel 2 */
1313 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1314 }
1315
1316 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1317 {
1318 /* TODO channel 2 */
1319 return !(cp_read(sd, 0xb1) & 0x80);
1320 }
1321
1322 static inline bool no_signal(struct v4l2_subdev *sd)
1323 {
1324 bool ret;
1325
1326 ret = no_power(sd);
1327
1328 ret |= no_lock_stdi(sd);
1329 ret |= no_lock_sspd(sd);
1330
1331 if (is_digital_input(sd)) {
1332 ret |= no_lock_tmds(sd);
1333 ret |= no_signal_tmds(sd);
1334 }
1335
1336 return ret;
1337 }
1338
1339 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1340 {
1341 struct adv76xx_state *state = to_state(sd);
1342
1343 if (!adv76xx_has_afe(state))
1344 return false;
1345
1346 /* CP has detected a non standard number of lines on the incoming
1347 video compared to what it is configured to receive by s_dv_timings */
1348 return io_read(sd, 0x12) & 0x01;
1349 }
1350
1351 static inline bool in_free_run(struct v4l2_subdev *sd)
1352 {
1353 return cp_read(sd, 0xff) & 0x10;
1354 }
1355
1356 static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
1357 {
1358 *status = 0;
1359 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1360 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1361 if (!in_free_run(sd) && no_lock_cp(sd))
1362 *status |= is_digital_input(sd) ?
1363 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1364
1365 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1366
1367 return 0;
1368 }
1369
1370 /* ----------------------------------------------------------------------- */
1371
1372 struct stdi_readback {
1373 u16 bl, lcf, lcvs;
1374 u8 hs_pol, vs_pol;
1375 bool interlaced;
1376 };
1377
1378 static int stdi2dv_timings(struct v4l2_subdev *sd,
1379 struct stdi_readback *stdi,
1380 struct v4l2_dv_timings *timings)
1381 {
1382 struct adv76xx_state *state = to_state(sd);
1383 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
1384 u32 pix_clk;
1385 int i;
1386
1387 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1388 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1389
1390 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1391 adv76xx_get_dv_timings_cap(sd, -1),
1392 adv76xx_check_dv_timings, NULL))
1393 continue;
1394 if (vtotal(bt) != stdi->lcf + 1)
1395 continue;
1396 if (bt->vsync != stdi->lcvs)
1397 continue;
1398
1399 pix_clk = hfreq * htotal(bt);
1400
1401 if ((pix_clk < bt->pixelclock + 1000000) &&
1402 (pix_clk > bt->pixelclock - 1000000)) {
1403 *timings = v4l2_dv_timings_presets[i];
1404 return 0;
1405 }
1406 }
1407
1408 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
1409 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1410 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1411 false, adv76xx_get_dv_timings_cap(sd, -1), timings))
1412 return 0;
1413 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1414 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1415 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1416 false, state->aspect_ratio,
1417 adv76xx_get_dv_timings_cap(sd, -1), timings))
1418 return 0;
1419
1420 v4l2_dbg(2, debug, sd,
1421 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1422 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1423 stdi->hs_pol, stdi->vs_pol);
1424 return -1;
1425 }
1426
1427
1428 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1429 {
1430 struct adv76xx_state *state = to_state(sd);
1431 const struct adv76xx_chip_info *info = state->info;
1432 u8 polarity;
1433
1434 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1435 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1436 return -1;
1437 }
1438
1439 /* read STDI */
1440 stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
1441 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
1442 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1443 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1444
1445 if (adv76xx_has_afe(state)) {
1446 /* read SSPD */
1447 polarity = cp_read(sd, 0xb5);
1448 if ((polarity & 0x03) == 0x01) {
1449 stdi->hs_pol = polarity & 0x10
1450 ? (polarity & 0x08 ? '+' : '-') : 'x';
1451 stdi->vs_pol = polarity & 0x40
1452 ? (polarity & 0x20 ? '+' : '-') : 'x';
1453 } else {
1454 stdi->hs_pol = 'x';
1455 stdi->vs_pol = 'x';
1456 }
1457 } else {
1458 polarity = hdmi_read(sd, 0x05);
1459 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1460 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
1461 }
1462
1463 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1464 v4l2_dbg(2, debug, sd,
1465 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1466 return -1;
1467 }
1468
1469 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1470 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1471 memset(stdi, 0, sizeof(struct stdi_readback));
1472 return -1;
1473 }
1474
1475 v4l2_dbg(2, debug, sd,
1476 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1477 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1478 stdi->hs_pol, stdi->vs_pol,
1479 stdi->interlaced ? "interlaced" : "progressive");
1480
1481 return 0;
1482 }
1483
1484 static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
1485 struct v4l2_enum_dv_timings *timings)
1486 {
1487 struct adv76xx_state *state = to_state(sd);
1488
1489 if (timings->pad >= state->source_pad)
1490 return -EINVAL;
1491
1492 return v4l2_enum_dv_timings_cap(timings,
1493 adv76xx_get_dv_timings_cap(sd, timings->pad),
1494 adv76xx_check_dv_timings, NULL);
1495 }
1496
1497 static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
1498 struct v4l2_dv_timings_cap *cap)
1499 {
1500 struct adv76xx_state *state = to_state(sd);
1501 unsigned int pad = cap->pad;
1502
1503 if (cap->pad >= state->source_pad)
1504 return -EINVAL;
1505
1506 *cap = *adv76xx_get_dv_timings_cap(sd, pad);
1507 cap->pad = pad;
1508
1509 return 0;
1510 }
1511
1512 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1513 if the format is listed in adv76xx_timings[] */
1514 static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1515 struct v4l2_dv_timings *timings)
1516 {
1517 v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd, -1),
1518 is_digital_input(sd) ? 250000 : 1000000,
1519 adv76xx_check_dv_timings, NULL);
1520 }
1521
1522 static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1523 {
1524 int a, b;
1525
1526 a = hdmi_read(sd, 0x06);
1527 b = hdmi_read(sd, 0x3b);
1528 if (a < 0 || b < 0)
1529 return 0;
1530
1531 return a * 1000000 + ((b & 0x30) >> 4) * 250000;
1532 }
1533
1534 static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1535 {
1536 int a, b;
1537
1538 a = hdmi_read(sd, 0x51);
1539 b = hdmi_read(sd, 0x52);
1540 if (a < 0 || b < 0)
1541 return 0;
1542
1543 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1544 }
1545
1546 static unsigned int adv76xx_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1547 {
1548 struct adv76xx_state *state = to_state(sd);
1549 const struct adv76xx_chip_info *info = state->info;
1550 unsigned int freq, bits_per_channel, pixelrepetition;
1551
1552 freq = info->read_hdmi_pixelclock(sd);
1553 if (is_hdmi(sd)) {
1554 /* adjust for deep color mode and pixel repetition */
1555 bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1556 pixelrepetition = (hdmi_read(sd, 0x05) & 0x0f) + 1;
1557
1558 freq = freq * 8 / bits_per_channel / pixelrepetition;
1559 }
1560
1561 return freq;
1562 }
1563
1564 static int adv76xx_query_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
1565 struct v4l2_dv_timings *timings)
1566 {
1567 struct adv76xx_state *state = to_state(sd);
1568 const struct adv76xx_chip_info *info = state->info;
1569 struct v4l2_bt_timings *bt = &timings->bt;
1570 struct stdi_readback stdi;
1571
1572 if (!timings)
1573 return -EINVAL;
1574
1575 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1576
1577 if (no_signal(sd)) {
1578 state->restart_stdi_once = true;
1579 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1580 return -ENOLINK;
1581 }
1582
1583 /* read STDI */
1584 if (read_stdi(sd, &stdi)) {
1585 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1586 return -ENOLINK;
1587 }
1588 bt->interlaced = stdi.interlaced ?
1589 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1590
1591 if (is_digital_input(sd)) {
1592 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1593 u8 vic = 0;
1594 u32 w, h;
1595
1596 w = hdmi_read16(sd, 0x07, info->linewidth_mask);
1597 h = hdmi_read16(sd, 0x09, info->field0_height_mask);
1598
1599 if (hdmi_signal && (io_read(sd, 0x60) & 1))
1600 vic = infoframe_read(sd, 0x04);
1601
1602 if (vic && v4l2_find_dv_timings_cea861_vic(timings, vic) &&
1603 bt->width == w && bt->height == h)
1604 goto found;
1605
1606 timings->type = V4L2_DV_BT_656_1120;
1607
1608 bt->width = w;
1609 bt->height = h;
1610 bt->pixelclock = adv76xx_read_hdmi_pixelclock(sd);
1611 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask);
1612 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask);
1613 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask);
1614 bt->vfrontporch = hdmi_read16(sd, 0x2a,
1615 info->field0_vfrontporch_mask) / 2;
1616 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2;
1617 bt->vbackporch = hdmi_read16(sd, 0x32,
1618 info->field0_vbackporch_mask) / 2;
1619 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1620 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1621 if (bt->interlaced == V4L2_DV_INTERLACED) {
1622 bt->height += hdmi_read16(sd, 0x0b,
1623 info->field1_height_mask);
1624 bt->il_vfrontporch = hdmi_read16(sd, 0x2c,
1625 info->field1_vfrontporch_mask) / 2;
1626 bt->il_vsync = hdmi_read16(sd, 0x30,
1627 info->field1_vsync_mask) / 2;
1628 bt->il_vbackporch = hdmi_read16(sd, 0x34,
1629 info->field1_vbackporch_mask) / 2;
1630 }
1631 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1632 } else {
1633 /* find format
1634 * Since LCVS values are inaccurate [REF_03, p. 275-276],
1635 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1636 */
1637 if (!stdi2dv_timings(sd, &stdi, timings))
1638 goto found;
1639 stdi.lcvs += 1;
1640 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1641 if (!stdi2dv_timings(sd, &stdi, timings))
1642 goto found;
1643 stdi.lcvs -= 2;
1644 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1645 if (stdi2dv_timings(sd, &stdi, timings)) {
1646 /*
1647 * The STDI block may measure wrong values, especially
1648 * for lcvs and lcf. If the driver can not find any
1649 * valid timing, the STDI block is restarted to measure
1650 * the video timings again. The function will return an
1651 * error, but the restart of STDI will generate a new
1652 * STDI interrupt and the format detection process will
1653 * restart.
1654 */
1655 if (state->restart_stdi_once) {
1656 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1657 /* TODO restart STDI for Sync Channel 2 */
1658 /* enter one-shot mode */
1659 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
1660 /* trigger STDI restart */
1661 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
1662 /* reset to continuous mode */
1663 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
1664 state->restart_stdi_once = false;
1665 return -ENOLINK;
1666 }
1667 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1668 return -ERANGE;
1669 }
1670 state->restart_stdi_once = true;
1671 }
1672 found:
1673
1674 if (no_signal(sd)) {
1675 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1676 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1677 return -ENOLINK;
1678 }
1679
1680 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1681 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1682 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1683 __func__, (u32)bt->pixelclock);
1684 return -ERANGE;
1685 }
1686
1687 if (debug > 1)
1688 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
1689 timings, true);
1690
1691 return 0;
1692 }
1693
1694 static int adv76xx_s_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
1695 struct v4l2_dv_timings *timings)
1696 {
1697 struct adv76xx_state *state = to_state(sd);
1698 struct v4l2_bt_timings *bt;
1699 int err;
1700
1701 if (!timings)
1702 return -EINVAL;
1703
1704 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1705 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1706 return 0;
1707 }
1708
1709 bt = &timings->bt;
1710
1711 if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd, -1),
1712 adv76xx_check_dv_timings, NULL))
1713 return -ERANGE;
1714
1715 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1716
1717 state->timings = *timings;
1718
1719 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
1720
1721 /* Use prim_mode and vid_std when available */
1722 err = configure_predefined_video_timings(sd, timings);
1723 if (err) {
1724 /* custom settings when the video format
1725 does not have prim_mode/vid_std */
1726 configure_custom_video_timings(sd, bt);
1727 }
1728
1729 set_rgb_quantization_range(sd);
1730
1731 if (debug > 1)
1732 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
1733 timings, true);
1734 return 0;
1735 }
1736
1737 static int adv76xx_g_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
1738 struct v4l2_dv_timings *timings)
1739 {
1740 struct adv76xx_state *state = to_state(sd);
1741
1742 *timings = state->timings;
1743 return 0;
1744 }
1745
1746 static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1747 {
1748 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1749 }
1750
1751 static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1752 {
1753 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1754 }
1755
1756 static void enable_input(struct v4l2_subdev *sd)
1757 {
1758 struct adv76xx_state *state = to_state(sd);
1759
1760 if (is_analog_input(sd)) {
1761 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1762 } else if (is_digital_input(sd)) {
1763 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
1764 state->info->set_termination(sd, true);
1765 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1766 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
1767 } else {
1768 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1769 __func__, state->selected_input);
1770 }
1771 }
1772
1773 static void disable_input(struct v4l2_subdev *sd)
1774 {
1775 struct adv76xx_state *state = to_state(sd);
1776
1777 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
1778 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
1779 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1780 state->info->set_termination(sd, false);
1781 }
1782
1783 static void select_input(struct v4l2_subdev *sd)
1784 {
1785 struct adv76xx_state *state = to_state(sd);
1786 const struct adv76xx_chip_info *info = state->info;
1787
1788 if (is_analog_input(sd)) {
1789 adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
1790
1791 afe_write(sd, 0x00, 0x08); /* power up ADC */
1792 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1793 afe_write(sd, 0xc8, 0x00); /* phase control */
1794 } else if (is_digital_input(sd)) {
1795 hdmi_write(sd, 0x00, state->selected_input & 0x03);
1796
1797 adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
1798
1799 if (adv76xx_has_afe(state)) {
1800 afe_write(sd, 0x00, 0xff); /* power down ADC */
1801 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1802 afe_write(sd, 0xc8, 0x40); /* phase control */
1803 }
1804
1805 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1806 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1807 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1808 } else {
1809 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1810 __func__, state->selected_input);
1811 }
1812
1813 /* Enable video adjustment (contrast, saturation, brightness and hue) */
1814 cp_write_clr_set(sd, 0x3e, 0x80, 0x80);
1815 }
1816
1817 static int adv76xx_s_routing(struct v4l2_subdev *sd,
1818 u32 input, u32 output, u32 config)
1819 {
1820 struct adv76xx_state *state = to_state(sd);
1821
1822 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1823 __func__, input, state->selected_input);
1824
1825 if (input == state->selected_input)
1826 return 0;
1827
1828 if (input > state->info->max_port)
1829 return -EINVAL;
1830
1831 state->selected_input = input;
1832
1833 disable_input(sd);
1834 select_input(sd);
1835 enable_input(sd);
1836
1837 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
1838
1839 return 0;
1840 }
1841
1842 static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
1843 struct v4l2_subdev_state *sd_state,
1844 struct v4l2_subdev_mbus_code_enum *code)
1845 {
1846 struct adv76xx_state *state = to_state(sd);
1847
1848 if (code->index >= state->info->nformats)
1849 return -EINVAL;
1850
1851 code->code = state->info->formats[code->index].code;
1852
1853 return 0;
1854 }
1855
1856 static void adv76xx_fill_format(struct adv76xx_state *state,
1857 struct v4l2_mbus_framefmt *format)
1858 {
1859 memset(format, 0, sizeof(*format));
1860
1861 format->width = state->timings.bt.width;
1862 format->height = state->timings.bt.height;
1863 format->field = V4L2_FIELD_NONE;
1864 format->colorspace = V4L2_COLORSPACE_SRGB;
1865
1866 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
1867 format->colorspace = (state->timings.bt.height <= 576) ?
1868 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1869 }
1870
1871 /*
1872 * Compute the op_ch_sel value required to obtain on the bus the component order
1873 * corresponding to the selected format taking into account bus reordering
1874 * applied by the board at the output of the device.
1875 *
1876 * The following table gives the op_ch_value from the format component order
1877 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
1878 * adv76xx_bus_order value in row).
1879 *
1880 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
1881 * ----------+-------------------------------------------------
1882 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
1883 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
1884 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
1885 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
1886 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
1887 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
1888 */
1889 static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
1890 {
1891 #define _SEL(a,b,c,d,e,f) { \
1892 ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1893 ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
1894 #define _BUS(x) [ADV7604_BUS_ORDER_##x]
1895
1896 static const unsigned int op_ch_sel[6][6] = {
1897 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1898 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1899 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1900 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1901 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1902 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1903 };
1904
1905 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1906 }
1907
1908 static void adv76xx_setup_format(struct adv76xx_state *state)
1909 {
1910 struct v4l2_subdev *sd = &state->sd;
1911
1912 io_write_clr_set(sd, 0x02, 0x02,
1913 state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
1914 io_write(sd, 0x03, state->format->op_format_sel |
1915 state->pdata.op_format_mode_sel);
1916 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
1917 io_write_clr_set(sd, 0x05, 0x01,
1918 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
1919 set_rgb_quantization_range(sd);
1920 }
1921
1922 static int adv76xx_get_format(struct v4l2_subdev *sd,
1923 struct v4l2_subdev_state *sd_state,
1924 struct v4l2_subdev_format *format)
1925 {
1926 struct adv76xx_state *state = to_state(sd);
1927
1928 if (format->pad != state->source_pad)
1929 return -EINVAL;
1930
1931 adv76xx_fill_format(state, &format->format);
1932
1933 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1934 struct v4l2_mbus_framefmt *fmt;
1935
1936 fmt = v4l2_subdev_state_get_format(sd_state, format->pad);
1937 format->format.code = fmt->code;
1938 } else {
1939 format->format.code = state->format->code;
1940 }
1941
1942 return 0;
1943 }
1944
1945 static int adv76xx_get_selection(struct v4l2_subdev *sd,
1946 struct v4l2_subdev_state *sd_state,
1947 struct v4l2_subdev_selection *sel)
1948 {
1949 struct adv76xx_state *state = to_state(sd);
1950
1951 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1952 return -EINVAL;
1953 /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported */
1954 if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS)
1955 return -EINVAL;
1956
1957 sel->r.left = 0;
1958 sel->r.top = 0;
1959 sel->r.width = state->timings.bt.width;
1960 sel->r.height = state->timings.bt.height;
1961
1962 return 0;
1963 }
1964
1965 static int adv76xx_set_format(struct v4l2_subdev *sd,
1966 struct v4l2_subdev_state *sd_state,
1967 struct v4l2_subdev_format *format)
1968 {
1969 struct adv76xx_state *state = to_state(sd);
1970 const struct adv76xx_format_info *info;
1971
1972 if (format->pad != state->source_pad)
1973 return -EINVAL;
1974
1975 info = adv76xx_format_info(state, format->format.code);
1976 if (!info)
1977 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
1978
1979 adv76xx_fill_format(state, &format->format);
1980 format->format.code = info->code;
1981
1982 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1983 struct v4l2_mbus_framefmt *fmt;
1984
1985 fmt = v4l2_subdev_state_get_format(sd_state, format->pad);
1986 fmt->code = format->format.code;
1987 } else {
1988 state->format = info;
1989 adv76xx_setup_format(state);
1990 }
1991
1992 return 0;
1993 }
1994
1995 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
1996 static void adv76xx_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
1997 {
1998 struct adv76xx_state *state = to_state(sd);
1999
2000 if ((cec_read(sd, 0x11) & 0x01) == 0) {
2001 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
2002 return;
2003 }
2004
2005 if (tx_raw_status & 0x02) {
2006 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",
2007 __func__);
2008 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,
2009 1, 0, 0, 0);
2010 return;
2011 }
2012 if (tx_raw_status & 0x04) {
2013 u8 status;
2014 u8 nack_cnt;
2015 u8 low_drive_cnt;
2016
2017 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
2018 /*
2019 * We set this status bit since this hardware performs
2020 * retransmissions.
2021 */
2022 status = CEC_TX_STATUS_MAX_RETRIES;
2023 nack_cnt = cec_read(sd, 0x14) & 0xf;
2024 if (nack_cnt)
2025 status |= CEC_TX_STATUS_NACK;
2026 low_drive_cnt = cec_read(sd, 0x14) >> 4;
2027 if (low_drive_cnt)
2028 status |= CEC_TX_STATUS_LOW_DRIVE;
2029 cec_transmit_done(state->cec_adap, status,
2030 0, nack_cnt, low_drive_cnt, 0);
2031 return;
2032 }
2033 if (tx_raw_status & 0x01) {
2034 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
2035 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
2036 return;
2037 }
2038 }
2039
2040 static void adv76xx_cec_isr(struct v4l2_subdev *sd, bool *handled)
2041 {
2042 struct adv76xx_state *state = to_state(sd);
2043 const struct adv76xx_chip_info *info = state->info;
2044 u8 cec_irq;
2045
2046 /* cec controller */
2047 cec_irq = io_read(sd, info->cec_irq_status) & 0x0f;
2048 if (!cec_irq)
2049 return;
2050
2051 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);
2052 adv76xx_cec_tx_raw_status(sd, cec_irq);
2053 if (cec_irq & 0x08) {
2054 struct cec_msg msg;
2055
2056 msg.len = cec_read(sd, 0x25) & 0x1f;
2057 if (msg.len > CEC_MAX_MSG_SIZE)
2058 msg.len = CEC_MAX_MSG_SIZE;
2059
2060 if (msg.len) {
2061 u8 i;
2062
2063 for (i = 0; i < msg.len; i++)
2064 msg.msg[i] = cec_read(sd, i + 0x15);
2065 cec_write(sd, info->cec_rx_enable,
2066 info->cec_rx_enable_mask); /* re-enable rx */
2067 cec_received_msg(state->cec_adap, &msg);
2068 }
2069 }
2070
2071 if (info->cec_irq_swap) {
2072 /*
2073 * Note: the bit order is swapped between 0x4d and 0x4e
2074 * on adv7604
2075 */
2076 cec_irq = ((cec_irq & 0x08) >> 3) | ((cec_irq & 0x04) >> 1) |
2077 ((cec_irq & 0x02) << 1) | ((cec_irq & 0x01) << 3);
2078 }
2079 io_write(sd, info->cec_irq_status + 1, cec_irq);
2080
2081 if (handled)
2082 *handled = true;
2083 }
2084
2085 static int adv76xx_cec_adap_enable(struct cec_adapter *adap, bool enable)
2086 {
2087 struct adv76xx_state *state = cec_get_drvdata(adap);
2088 const struct adv76xx_chip_info *info = state->info;
2089 struct v4l2_subdev *sd = &state->sd;
2090
2091 if (!state->cec_enabled_adap && enable) {
2092 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */
2093 cec_write(sd, 0x2c, 0x01); /* cec soft reset */
2094 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */
2095 /* enabled irqs: */
2096 /* tx: ready */
2097 /* tx: arbitration lost */
2098 /* tx: retry timeout */
2099 /* rx: ready */
2100 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x0f);
2101 cec_write(sd, info->cec_rx_enable, info->cec_rx_enable_mask);
2102 } else if (state->cec_enabled_adap && !enable) {
2103 /* disable cec interrupts */
2104 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x00);
2105 /* disable address mask 1-3 */
2106 cec_write_clr_set(sd, 0x27, 0x70, 0x00);
2107 /* power down cec section */
2108 cec_write_clr_set(sd, 0x2a, 0x01, 0x00);
2109 state->cec_valid_addrs = 0;
2110 }
2111 state->cec_enabled_adap = enable;
2112 adv76xx_s_detect_tx_5v_ctrl(sd);
2113 return 0;
2114 }
2115
2116 static int adv76xx_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
2117 {
2118 struct adv76xx_state *state = cec_get_drvdata(adap);
2119 struct v4l2_subdev *sd = &state->sd;
2120 unsigned int i, free_idx = ADV76XX_MAX_ADDRS;
2121
2122 if (!state->cec_enabled_adap)
2123 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
2124
2125 if (addr == CEC_LOG_ADDR_INVALID) {
2126 cec_write_clr_set(sd, 0x27, 0x70, 0);
2127 state->cec_valid_addrs = 0;
2128 return 0;
2129 }
2130
2131 for (i = 0; i < ADV76XX_MAX_ADDRS; i++) {
2132 bool is_valid = state->cec_valid_addrs & (1 << i);
2133
2134 if (free_idx == ADV76XX_MAX_ADDRS && !is_valid)
2135 free_idx = i;
2136 if (is_valid && state->cec_addr[i] == addr)
2137 return 0;
2138 }
2139 if (i == ADV76XX_MAX_ADDRS) {
2140 i = free_idx;
2141 if (i == ADV76XX_MAX_ADDRS)
2142 return -ENXIO;
2143 }
2144 state->cec_addr[i] = addr;
2145 state->cec_valid_addrs |= 1 << i;
2146
2147 switch (i) {
2148 case 0:
2149 /* enable address mask 0 */
2150 cec_write_clr_set(sd, 0x27, 0x10, 0x10);
2151 /* set address for mask 0 */
2152 cec_write_clr_set(sd, 0x28, 0x0f, addr);
2153 break;
2154 case 1:
2155 /* enable address mask 1 */
2156 cec_write_clr_set(sd, 0x27, 0x20, 0x20);
2157 /* set address for mask 1 */
2158 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);
2159 break;
2160 case 2:
2161 /* enable address mask 2 */
2162 cec_write_clr_set(sd, 0x27, 0x40, 0x40);
2163 /* set address for mask 1 */
2164 cec_write_clr_set(sd, 0x29, 0x0f, addr);
2165 break;
2166 }
2167 return 0;
2168 }
2169
2170 static int adv76xx_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2171 u32 signal_free_time, struct cec_msg *msg)
2172 {
2173 struct adv76xx_state *state = cec_get_drvdata(adap);
2174 struct v4l2_subdev *sd = &state->sd;
2175 u8 len = msg->len;
2176 unsigned int i;
2177
2178 /*
2179 * The number of retries is the number of attempts - 1, but retry
2180 * at least once. It's not clear if a value of 0 is allowed, so
2181 * let's do at least one retry.
2182 */
2183 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);
2184
2185 if (len > 16) {
2186 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
2187 return -EINVAL;
2188 }
2189
2190 /* write data */
2191 for (i = 0; i < len; i++)
2192 cec_write(sd, i, msg->msg[i]);
2193
2194 /* set length (data + header) */
2195 cec_write(sd, 0x10, len);
2196 /* start transmit, enable tx */
2197 cec_write(sd, 0x11, 0x01);
2198 return 0;
2199 }
2200
2201 static const struct cec_adap_ops adv76xx_cec_adap_ops = {
2202 .adap_enable = adv76xx_cec_adap_enable,
2203 .adap_log_addr = adv76xx_cec_adap_log_addr,
2204 .adap_transmit = adv76xx_cec_adap_transmit,
2205 };
2206 #endif
2207
2208 static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
2209 {
2210 struct adv76xx_state *state = to_state(sd);
2211 const struct adv76xx_chip_info *info = state->info;
2212 const u8 irq_reg_0x43 = io_read(sd, 0x43);
2213 const u8 irq_reg_0x6b = io_read(sd, 0x6b);
2214 const u8 irq_reg_0x70 = io_read(sd, 0x70);
2215 u8 fmt_change_digital;
2216 u8 fmt_change;
2217 u8 tx_5v;
2218
2219 if (irq_reg_0x43)
2220 io_write(sd, 0x44, irq_reg_0x43);
2221 if (irq_reg_0x70)
2222 io_write(sd, 0x71, irq_reg_0x70);
2223 if (irq_reg_0x6b)
2224 io_write(sd, 0x6c, irq_reg_0x6b);
2225
2226 v4l2_dbg(2, debug, sd, "%s: ", __func__);
2227
2228 /* format change */
2229 fmt_change = irq_reg_0x43 & 0x98;
2230 fmt_change_digital = is_digital_input(sd)
2231 ? irq_reg_0x6b & info->fmt_change_digital_mask
2232 : 0;
2233
2234 if (fmt_change || fmt_change_digital) {
2235 v4l2_dbg(1, debug, sd,
2236 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
2237 __func__, fmt_change, fmt_change_digital);
2238
2239 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
2240
2241 if (handled)
2242 *handled = true;
2243 }
2244 /* HDMI/DVI mode */
2245 if (irq_reg_0x6b & 0x01) {
2246 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2247 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
2248 set_rgb_quantization_range(sd);
2249 if (handled)
2250 *handled = true;
2251 }
2252
2253 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
2254 /* cec */
2255 adv76xx_cec_isr(sd, handled);
2256 #endif
2257
2258 /* tx 5v detect */
2259 tx_5v = irq_reg_0x70 & info->cable_det_mask;
2260 if (tx_5v) {
2261 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
2262 adv76xx_s_detect_tx_5v_ctrl(sd);
2263 if (handled)
2264 *handled = true;
2265 }
2266 return 0;
2267 }
2268
2269 static irqreturn_t adv76xx_irq_handler(int irq, void *dev_id)
2270 {
2271 struct adv76xx_state *state = dev_id;
2272 bool handled = false;
2273
2274 adv76xx_isr(&state->sd, 0, &handled);
2275
2276 return handled ? IRQ_HANDLED : IRQ_NONE;
2277 }
2278
2279 static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2280 {
2281 struct adv76xx_state *state = to_state(sd);
2282 u8 *data = NULL;
2283
2284 memset(edid->reserved, 0, sizeof(edid->reserved));
2285
2286 switch (edid->pad) {
2287 case ADV76XX_PAD_HDMI_PORT_A:
2288 case ADV7604_PAD_HDMI_PORT_B:
2289 case ADV7604_PAD_HDMI_PORT_C:
2290 case ADV7604_PAD_HDMI_PORT_D:
2291 if (state->edid.present & (1 << edid->pad))
2292 data = state->edid.edid;
2293 break;
2294 default:
2295 return -EINVAL;
2296 }
2297
2298 if (edid->start_block == 0 && edid->blocks == 0) {
2299 edid->blocks = data ? state->edid.blocks : 0;
2300 return 0;
2301 }
2302
2303 if (!data)
2304 return -ENODATA;
2305
2306 if (edid->start_block >= state->edid.blocks)
2307 return -EINVAL;
2308
2309 if (edid->start_block + edid->blocks > state->edid.blocks)
2310 edid->blocks = state->edid.blocks - edid->start_block;
2311
2312 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
2313
2314 return 0;
2315 }
2316
2317 static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2318 {
2319 struct adv76xx_state *state = to_state(sd);
2320 const struct adv76xx_chip_info *info = state->info;
2321 unsigned int spa_loc;
2322 u16 pa, parent_pa;
2323 int err;
2324 int i;
2325
2326 memset(edid->reserved, 0, sizeof(edid->reserved));
2327
2328 if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
2329 return -EINVAL;
2330 if (edid->start_block != 0)
2331 return -EINVAL;
2332 if (edid->blocks == 0) {
2333 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2334 state->edid.present &= ~(1 << edid->pad);
2335 adv76xx_set_hpd(state, state->edid.present);
2336 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2337
2338 /* Fall back to a 16:9 aspect ratio */
2339 state->aspect_ratio.numerator = 16;
2340 state->aspect_ratio.denominator = 9;
2341
2342 if (!state->edid.present) {
2343 state->edid.blocks = 0;
2344 cec_phys_addr_invalidate(state->cec_adap);
2345 }
2346
2347 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2348 __func__, edid->pad, state->edid.present);
2349 return 0;
2350 }
2351 if (edid->blocks > ADV76XX_MAX_EDID_BLOCKS) {
2352 edid->blocks = ADV76XX_MAX_EDID_BLOCKS;
2353 return -E2BIG;
2354 }
2355
2356 pa = v4l2_get_edid_phys_addr(edid->edid, edid->blocks * 128, &spa_loc);
2357 err = v4l2_phys_addr_validate(pa, &parent_pa, NULL);
2358 if (err)
2359 return err;
2360
2361 if (!spa_loc) {
2362 /*
2363 * There is no SPA, so just set spa_loc to 128 and pa to whatever
2364 * data is there.
2365 */
2366 spa_loc = 128;
2367 pa = (edid->edid[spa_loc] << 8) | edid->edid[spa_loc + 1];
2368 }
2369
2370 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2371 __func__, edid->pad, state->edid.present);
2372
2373 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2374 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2375 adv76xx_set_hpd(state, 0);
2376 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
2377
2378 switch (edid->pad) {
2379 case ADV76XX_PAD_HDMI_PORT_A:
2380 state->spa_port_a[0] = pa >> 8;
2381 state->spa_port_a[1] = pa & 0xff;
2382 break;
2383 case ADV7604_PAD_HDMI_PORT_B:
2384 rep_write(sd, info->edid_spa_port_b_reg, pa >> 8);
2385 rep_write(sd, info->edid_spa_port_b_reg + 1, pa & 0xff);
2386 break;
2387 case ADV7604_PAD_HDMI_PORT_C:
2388 rep_write(sd, info->edid_spa_port_b_reg + 2, pa >> 8);
2389 rep_write(sd, info->edid_spa_port_b_reg + 3, pa & 0xff);
2390 break;
2391 case ADV7604_PAD_HDMI_PORT_D:
2392 rep_write(sd, info->edid_spa_port_b_reg + 4, pa >> 8);
2393 rep_write(sd, info->edid_spa_port_b_reg + 5, pa & 0xff);
2394 break;
2395 default:
2396 return -EINVAL;
2397 }
2398
2399 if (info->edid_spa_loc_reg) {
2400 u8 mask = info->edid_spa_loc_msb_mask;
2401
2402 rep_write(sd, info->edid_spa_loc_reg, spa_loc & 0xff);
2403 rep_write_clr_set(sd, info->edid_spa_loc_reg + 1,
2404 mask, (spa_loc & 0x100) ? mask : 0);
2405 }
2406
2407 edid->edid[spa_loc] = state->spa_port_a[0];
2408 edid->edid[spa_loc + 1] = state->spa_port_a[1];
2409
2410 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2411 state->edid.blocks = edid->blocks;
2412 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2413 edid->edid[0x16]);
2414 state->edid.present |= 1 << edid->pad;
2415
2416 rep_write_clr_set(sd, info->edid_segment_reg,
2417 info->edid_segment_mask, 0);
2418 err = edid_write_block(sd, 128 * min(edid->blocks, 2U), state->edid.edid);
2419 if (err < 0) {
2420 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
2421 return err;
2422 }
2423 if (edid->blocks > 2) {
2424 rep_write_clr_set(sd, info->edid_segment_reg,
2425 info->edid_segment_mask,
2426 info->edid_segment_mask);
2427 err = edid_write_block(sd, 128 * (edid->blocks - 2),
2428 state->edid.edid + 256);
2429 if (err < 0) {
2430 v4l2_err(sd, "error %d writing edid pad %d\n",
2431 err, edid->pad);
2432 return err;
2433 }
2434 }
2435
2436 /* adv76xx calculates the checksums and enables I2C access to internal
2437 EDID RAM from DDC port. */
2438 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2439
2440 for (i = 0; i < 1000; i++) {
2441 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
2442 break;
2443 mdelay(1);
2444 }
2445 if (i == 1000) {
2446 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2447 return -EIO;
2448 }
2449 cec_s_phys_addr(state->cec_adap, parent_pa, false);
2450
2451 /* enable hotplug after 100 ms */
2452 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
2453 return 0;
2454 }
2455
2456 /*********** avi info frame CEA-861-E **************/
2457
2458 static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = {
2459 { "AVI", 0x01, 0xe0, 0x00 },
2460 { "Audio", 0x02, 0xe3, 0x1c },
2461 { "SDP", 0x04, 0xe6, 0x2a },
2462 { "Vendor", 0x10, 0xec, 0x54 }
2463 };
2464
2465 static int adv76xx_read_infoframe_buf(struct v4l2_subdev *sd, int index,
2466 u8 buf[V4L2_DEBUGFS_IF_MAX_LEN])
2467 {
2468 u8 len;
2469 int i;
2470
2471 if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) {
2472 v4l2_info(sd, "%s infoframe not received\n",
2473 adv76xx_cri[index].desc);
2474 return -ENOENT;
2475 }
2476
2477 for (i = 0; i < 3; i++)
2478 buf[i] = infoframe_read(sd, adv76xx_cri[index].head_addr + i);
2479
2480 len = buf[2] + 1;
2481
2482 if (len + 3 > V4L2_DEBUGFS_IF_MAX_LEN) {
2483 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__,
2484 adv76xx_cri[index].desc, len);
2485 return -ENOENT;
2486 }
2487
2488 for (i = 0; i < len; i++)
2489 buf[i + 3] = infoframe_read(sd,
2490 adv76xx_cri[index].payload_addr + i);
2491 return len + 3;
2492 }
2493
2494 static void adv76xx_log_infoframes(struct v4l2_subdev *sd)
2495 {
2496 int i;
2497
2498 if (!is_hdmi(sd)) {
2499 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2500 return;
2501 }
2502
2503 for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) {
2504 struct i2c_client *client = v4l2_get_subdevdata(sd);
2505 u8 buffer[V4L2_DEBUGFS_IF_MAX_LEN] = {};
2506 union hdmi_infoframe frame;
2507 int len;
2508
2509 len = adv76xx_read_infoframe_buf(sd, i, buffer);
2510 if (len < 0)
2511 continue;
2512
2513 if (hdmi_infoframe_unpack(&frame, buffer, len) < 0)
2514 v4l2_err(sd, "%s: unpack of %s infoframe failed\n",
2515 __func__, adv76xx_cri[i].desc);
2516 else
2517 hdmi_infoframe_log(KERN_INFO, &client->dev, &frame);
2518 }
2519 }
2520
2521 static int adv76xx_log_status(struct v4l2_subdev *sd)
2522 {
2523 struct adv76xx_state *state = to_state(sd);
2524 const struct adv76xx_chip_info *info = state->info;
2525 struct v4l2_dv_timings timings;
2526 struct stdi_readback stdi;
2527 int ret;
2528 u8 reg_io_0x02;
2529 u8 edid_enabled;
2530 u8 cable_det;
2531 static const char * const csc_coeff_sel_rb[16] = {
2532 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2533 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2534 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2535 "reserved", "reserved", "reserved", "reserved", "manual"
2536 };
2537 static const char * const input_color_space_txt[16] = {
2538 "RGB limited range (16-235)", "RGB full range (0-255)",
2539 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2540 "xvYCC Bt.601", "xvYCC Bt.709",
2541 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2542 "invalid", "invalid", "invalid", "invalid", "invalid",
2543 "invalid", "invalid", "automatic"
2544 };
2545 static const char * const hdmi_color_space_txt[16] = {
2546 "RGB limited range (16-235)", "RGB full range (0-255)",
2547 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2548 "xvYCC Bt.601", "xvYCC Bt.709",
2549 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2550 "sYCC", "opYCC 601", "opRGB", "invalid", "invalid",
2551 "invalid", "invalid", "invalid"
2552 };
2553 static const char * const rgb_quantization_range_txt[] = {
2554 "Automatic",
2555 "RGB limited range (16-235)",
2556 "RGB full range (0-255)",
2557 };
2558 static const char * const deep_color_mode_txt[4] = {
2559 "8-bits per channel",
2560 "10-bits per channel",
2561 "12-bits per channel",
2562 "16-bits per channel (not supported)"
2563 };
2564
2565 v4l2_info(sd, "-----Chip status-----\n");
2566 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2567 edid_enabled = rep_read(sd, info->edid_status_reg);
2568 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
2569 ((edid_enabled & 0x01) ? "Yes" : "No"),
2570 ((edid_enabled & 0x02) ? "Yes" : "No"),
2571 ((edid_enabled & 0x04) ? "Yes" : "No"),
2572 ((edid_enabled & 0x08) ? "Yes" : "No"));
2573 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
2574 "enabled" : "disabled");
2575 if (state->cec_enabled_adap) {
2576 int i;
2577
2578 for (i = 0; i < ADV76XX_MAX_ADDRS; i++) {
2579 bool is_valid = state->cec_valid_addrs & (1 << i);
2580
2581 if (is_valid)
2582 v4l2_info(sd, "CEC Logical Address: 0x%x\n",
2583 state->cec_addr[i]);
2584 }
2585 }
2586
2587 v4l2_info(sd, "-----Signal status-----\n");
2588 cable_det = info->read_cable_det(sd);
2589 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
2590 ((cable_det & 0x01) ? "Yes" : "No"),
2591 ((cable_det & 0x02) ? "Yes" : "No"),
2592 ((cable_det & 0x04) ? "Yes" : "No"),
2593 ((cable_det & 0x08) ? "Yes" : "No"));
2594 v4l2_info(sd, "TMDS signal detected: %s\n",
2595 no_signal_tmds(sd) ? "false" : "true");
2596 v4l2_info(sd, "TMDS signal locked: %s\n",
2597 no_lock_tmds(sd) ? "false" : "true");
2598 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2599 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2600 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2601 v4l2_info(sd, "CP free run: %s\n",
2602 (in_free_run(sd)) ? "on" : "off");
2603 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2604 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2605 (io_read(sd, 0x01) & 0x70) >> 4);
2606
2607 v4l2_info(sd, "-----Video Timings-----\n");
2608 if (read_stdi(sd, &stdi))
2609 v4l2_info(sd, "STDI: not locked\n");
2610 else
2611 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2612 stdi.lcf, stdi.bl, stdi.lcvs,
2613 stdi.interlaced ? "interlaced" : "progressive",
2614 stdi.hs_pol, stdi.vs_pol);
2615 if (adv76xx_query_dv_timings(sd, 0, &timings))
2616 v4l2_info(sd, "No video detected\n");
2617 else
2618 v4l2_print_dv_timings(sd->name, "Detected format: ",
2619 &timings, true);
2620 v4l2_print_dv_timings(sd->name, "Configured format: ",
2621 &state->timings, true);
2622
2623 if (no_signal(sd))
2624 return 0;
2625
2626 v4l2_info(sd, "-----Color space-----\n");
2627 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2628 rgb_quantization_range_txt[state->rgb_quantization_range]);
2629
2630 ret = io_read(sd, 0x02);
2631 if (ret < 0) {
2632 v4l2_info(sd, "Can't read Input/Output color space\n");
2633 } else {
2634 reg_io_0x02 = ret;
2635
2636 v4l2_info(sd, "Input color space: %s\n",
2637 input_color_space_txt[reg_io_0x02 >> 4]);
2638 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n",
2639 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2640 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
2641 "(16-235)" : "(0-255)",
2642 (reg_io_0x02 & 0x08) ? "enabled" : "disabled");
2643 }
2644 v4l2_info(sd, "Color space conversion: %s\n",
2645 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
2646
2647 if (!is_digital_input(sd))
2648 return 0;
2649
2650 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2651 v4l2_info(sd, "Digital video port selected: %c\n",
2652 (hdmi_read(sd, 0x00) & 0x03) + 'A');
2653 v4l2_info(sd, "HDCP encrypted content: %s\n",
2654 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2655 v4l2_info(sd, "HDCP keys read: %s%s\n",
2656 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2657 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2658 if (is_hdmi(sd)) {
2659 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2660 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2661 bool audio_mute = io_read(sd, 0x65) & 0x40;
2662
2663 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2664 audio_pll_locked ? "locked" : "not locked",
2665 audio_sample_packet_detect ? "detected" : "not detected",
2666 audio_mute ? "muted" : "enabled");
2667 if (audio_pll_locked && audio_sample_packet_detect) {
2668 v4l2_info(sd, "Audio format: %s\n",
2669 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2670 }
2671 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2672 (hdmi_read(sd, 0x5c) << 8) +
2673 (hdmi_read(sd, 0x5d) & 0xf0));
2674 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2675 (hdmi_read(sd, 0x5e) << 8) +
2676 hdmi_read(sd, 0x5f));
2677 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2678
2679 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2680 v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]);
2681
2682 adv76xx_log_infoframes(sd);
2683 }
2684
2685 return 0;
2686 }
2687
2688 static int adv76xx_subscribe_event(struct v4l2_subdev *sd,
2689 struct v4l2_fh *fh,
2690 struct v4l2_event_subscription *sub)
2691 {
2692 switch (sub->type) {
2693 case V4L2_EVENT_SOURCE_CHANGE:
2694 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
2695 case V4L2_EVENT_CTRL:
2696 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
2697 default:
2698 return -EINVAL;
2699 }
2700 }
2701
2702 static ssize_t
2703 adv76xx_debugfs_if_read(u32 type, void *priv, struct file *filp,
2704 char __user *ubuf, size_t count, loff_t *ppos)
2705 {
2706 u8 buf[V4L2_DEBUGFS_IF_MAX_LEN] = {};
2707 struct v4l2_subdev *sd = priv;
2708 int index;
2709 int len;
2710
2711 if (!is_hdmi(sd))
2712 return 0;
2713
2714 switch (type) {
2715 case V4L2_DEBUGFS_IF_AVI:
2716 index = 0;
2717 break;
2718 case V4L2_DEBUGFS_IF_AUDIO:
2719 index = 1;
2720 break;
2721 case V4L2_DEBUGFS_IF_SPD:
2722 index = 2;
2723 break;
2724 case V4L2_DEBUGFS_IF_HDMI:
2725 index = 3;
2726 break;
2727 default:
2728 return 0;
2729 }
2730
2731 len = adv76xx_read_infoframe_buf(sd, index, buf);
2732 if (len > 0)
2733 len = simple_read_from_buffer(ubuf, count, ppos, buf, len);
2734 return len < 0 ? 0 : len;
2735 }
2736
2737 static int adv76xx_registered(struct v4l2_subdev *sd)
2738 {
2739 struct adv76xx_state *state = to_state(sd);
2740 struct i2c_client *client = v4l2_get_subdevdata(sd);
2741 int err;
2742
2743 err = cec_register_adapter(state->cec_adap, &client->dev);
2744 if (err) {
2745 cec_delete_adapter(state->cec_adap);
2746 return err;
2747 }
2748 state->debugfs_dir = debugfs_create_dir(sd->name, v4l2_debugfs_root());
2749 state->infoframes = v4l2_debugfs_if_alloc(state->debugfs_dir,
2750 V4L2_DEBUGFS_IF_AVI | V4L2_DEBUGFS_IF_AUDIO |
2751 V4L2_DEBUGFS_IF_SPD | V4L2_DEBUGFS_IF_HDMI, sd,
2752 adv76xx_debugfs_if_read);
2753 return 0;
2754 }
2755
2756 static void adv76xx_unregistered(struct v4l2_subdev *sd)
2757 {
2758 struct adv76xx_state *state = to_state(sd);
2759
2760 cec_unregister_adapter(state->cec_adap);
2761 v4l2_debugfs_if_free(state->infoframes);
2762 state->infoframes = NULL;
2763 debugfs_remove_recursive(state->debugfs_dir);
2764 state->debugfs_dir = NULL;
2765 }
2766
2767 /* ----------------------------------------------------------------------- */
2768
2769 static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2770 .s_ctrl = adv76xx_s_ctrl,
2771 .g_volatile_ctrl = adv76xx_g_volatile_ctrl,
2772 };
2773
2774 static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2775 .log_status = adv76xx_log_status,
2776 .interrupt_service_routine = adv76xx_isr,
2777 .subscribe_event = adv76xx_subscribe_event,
2778 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
2779 #ifdef CONFIG_VIDEO_ADV_DEBUG
2780 .g_register = adv76xx_g_register,
2781 .s_register = adv76xx_s_register,
2782 #endif
2783 };
2784
2785 static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2786 .s_routing = adv76xx_s_routing,
2787 .g_input_status = adv76xx_g_input_status,
2788 };
2789
2790 static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2791 .enum_mbus_code = adv76xx_enum_mbus_code,
2792 .get_selection = adv76xx_get_selection,
2793 .get_fmt = adv76xx_get_format,
2794 .set_fmt = adv76xx_set_format,
2795 .get_edid = adv76xx_get_edid,
2796 .set_edid = adv76xx_set_edid,
2797 .s_dv_timings = adv76xx_s_dv_timings,
2798 .g_dv_timings = adv76xx_g_dv_timings,
2799 .query_dv_timings = adv76xx_query_dv_timings,
2800 .dv_timings_cap = adv76xx_dv_timings_cap,
2801 .enum_dv_timings = adv76xx_enum_dv_timings,
2802 };
2803
2804 static const struct v4l2_subdev_ops adv76xx_ops = {
2805 .core = &adv76xx_core_ops,
2806 .video = &adv76xx_video_ops,
2807 .pad = &adv76xx_pad_ops,
2808 };
2809
2810 static const struct v4l2_subdev_internal_ops adv76xx_int_ops = {
2811 .registered = adv76xx_registered,
2812 .unregistered = adv76xx_unregistered,
2813 };
2814
2815 /* -------------------------- custom ctrls ---------------------------------- */
2816
2817 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2818 .ops = &adv76xx_ctrl_ops,
2819 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2820 .name = "Analog Sampling Phase",
2821 .type = V4L2_CTRL_TYPE_INTEGER,
2822 .min = 0,
2823 .max = 0x1f,
2824 .step = 1,
2825 .def = 0,
2826 };
2827
2828 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2829 .ops = &adv76xx_ctrl_ops,
2830 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2831 .name = "Free Running Color, Manual",
2832 .type = V4L2_CTRL_TYPE_BOOLEAN,
2833 .min = false,
2834 .max = true,
2835 .step = 1,
2836 .def = false,
2837 };
2838
2839 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2840 .ops = &adv76xx_ctrl_ops,
2841 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2842 .name = "Free Running Color",
2843 .type = V4L2_CTRL_TYPE_INTEGER,
2844 .min = 0x0,
2845 .max = 0xffffff,
2846 .step = 0x1,
2847 .def = 0x0,
2848 };
2849
2850 /* ----------------------------------------------------------------------- */
2851
2852 struct adv76xx_register_map {
2853 const char *name;
2854 u8 default_addr;
2855 };
2856
2857 static const struct adv76xx_register_map adv76xx_default_addresses[] = {
2858 [ADV76XX_PAGE_IO] = { "main", 0x4c },
2859 [ADV7604_PAGE_AVLINK] = { "avlink", 0x42 },
2860 [ADV76XX_PAGE_CEC] = { "cec", 0x40 },
2861 [ADV76XX_PAGE_INFOFRAME] = { "infoframe", 0x3e },
2862 [ADV7604_PAGE_ESDP] = { "esdp", 0x38 },
2863 [ADV7604_PAGE_DPP] = { "dpp", 0x3c },
2864 [ADV76XX_PAGE_AFE] = { "afe", 0x26 },
2865 [ADV76XX_PAGE_REP] = { "rep", 0x32 },
2866 [ADV76XX_PAGE_EDID] = { "edid", 0x36 },
2867 [ADV76XX_PAGE_HDMI] = { "hdmi", 0x34 },
2868 [ADV76XX_PAGE_TEST] = { "test", 0x30 },
2869 [ADV76XX_PAGE_CP] = { "cp", 0x22 },
2870 [ADV7604_PAGE_VDP] = { "vdp", 0x24 },
2871 };
2872
2873 static int adv76xx_core_init(struct v4l2_subdev *sd)
2874 {
2875 struct adv76xx_state *state = to_state(sd);
2876 const struct adv76xx_chip_info *info = state->info;
2877 struct adv76xx_platform_data *pdata = &state->pdata;
2878
2879 hdmi_write(sd, 0x48,
2880 (pdata->disable_pwrdnb ? 0x80 : 0) |
2881 (pdata->disable_cable_det_rst ? 0x40 : 0));
2882
2883 disable_input(sd);
2884
2885 if (pdata->default_input >= 0 &&
2886 pdata->default_input < state->source_pad) {
2887 state->selected_input = pdata->default_input;
2888 select_input(sd);
2889 enable_input(sd);
2890 }
2891
2892 /* power */
2893 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2894 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
2895 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
2896
2897 /* HPD */
2898 if (info->type != ADV7604) {
2899 /* Set manual HPD values to 0 */
2900 io_write_clr_set(sd, 0x20, 0xc0, 0);
2901 /*
2902 * Set HPA_DELAY to 200 ms and set automatic HPD control
2903 * to: internal EDID is active AND a cable is detected
2904 * AND the manual HPD control is set to 1.
2905 */
2906 hdmi_write_clr_set(sd, 0x6c, 0xf6, 0x26);
2907 }
2908
2909 /* video format */
2910 io_write_clr_set(sd, 0x02, 0x0f, pdata->alt_gamma << 3);
2911 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
2912 pdata->insert_av_codes << 2 |
2913 pdata->replicate_av_codes << 1);
2914 adv76xx_setup_format(state);
2915
2916 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
2917
2918 /* VS, HS polarities */
2919 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2920 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
2921
2922 /* Adjust drive strength */
2923 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2924 pdata->dr_str_clk << 2 |
2925 pdata->dr_str_sync);
2926
2927 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2928 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2929 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
2930 ADI recommended setting [REF_01, c. 2.3.3] */
2931 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
2932 ADI recommended setting [REF_01, c. 2.3.3] */
2933 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2934 for digital formats */
2935
2936 /* HDMI audio */
2937 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2938 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2939 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2940
2941 /* TODO from platform data */
2942 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2943
2944 if (adv76xx_has_afe(state)) {
2945 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2946 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
2947 }
2948
2949 /* interrupts */
2950 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
2951 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2952 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2953 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2954 info->setup_irqs(sd);
2955
2956 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2957 }
2958
2959 static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2960 {
2961 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2962 }
2963
2964 static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2965 {
2966 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2967 }
2968
2969 static void adv7612_setup_irqs(struct v4l2_subdev *sd)
2970 {
2971 io_write(sd, 0x41, 0xd0); /* disable INT2 */
2972 }
2973
2974 static void adv76xx_unregister_clients(struct adv76xx_state *state)
2975 {
2976 unsigned int i;
2977
2978 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i)
2979 i2c_unregister_device(state->i2c_clients[i]);
2980 }
2981
2982 static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
2983 unsigned int page)
2984 {
2985 struct i2c_client *client = v4l2_get_subdevdata(sd);
2986 struct adv76xx_state *state = to_state(sd);
2987 struct adv76xx_platform_data *pdata = &state->pdata;
2988 unsigned int io_reg = 0xf2 + page;
2989 struct i2c_client *new_client;
2990
2991 if (pdata && pdata->i2c_addresses[page])
2992 new_client = i2c_new_dummy_device(client->adapter,
2993 pdata->i2c_addresses[page]);
2994 else
2995 new_client = i2c_new_ancillary_device(client,
2996 adv76xx_default_addresses[page].name,
2997 adv76xx_default_addresses[page].default_addr);
2998
2999 if (!IS_ERR(new_client))
3000 io_write(sd, io_reg, new_client->addr << 1);
3001
3002 return new_client;
3003 }
3004
3005 static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
3006 /* reset ADI recommended settings for HDMI: */
3007 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
3008 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
3009 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
3010 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
3011 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
3012 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
3013 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
3014 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
3015 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
3016 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
3017 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
3018 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
3019 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
3020
3021 /* set ADI recommended settings for digitizer */
3022 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
3023 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
3024 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
3025 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
3026 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
3027 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
3028
3029 { ADV76XX_REG_SEQ_TERM, 0 },
3030 };
3031
3032 static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
3033 /* set ADI recommended settings for HDMI: */
3034 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
3035 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
3036 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
3037 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
3038 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
3039 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
3040 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
3041 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
3042 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
3043 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
3044 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
3045 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
3046
3047 /* reset ADI recommended settings for digitizer */
3048 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
3049 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
3050 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
3051
3052 { ADV76XX_REG_SEQ_TERM, 0 },
3053 };
3054
3055 static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
3056 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
3057 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
3058 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
3059 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
3060 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
3061 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
3062 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
3063 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
3064 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
3065 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
3066 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
3067 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
3068
3069 { ADV76XX_REG_SEQ_TERM, 0 },
3070 };
3071
3072 static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = {
3073 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
3074 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
3075 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
3076 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
3077 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
3078 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
3079 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
3080 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
3081 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
3082 { ADV76XX_REG_SEQ_TERM, 0 },
3083 };
3084
3085 static const struct adv76xx_chip_info adv76xx_chip_info[] = {
3086 [ADV7604] = {
3087 .type = ADV7604,
3088 .has_afe = true,
3089 .max_port = ADV7604_PAD_VGA_COMP,
3090 .num_dv_ports = 4,
3091 .edid_enable_reg = 0x77,
3092 .edid_status_reg = 0x7d,
3093 .edid_segment_reg = 0x77,
3094 .edid_segment_mask = 0x10,
3095 .edid_spa_loc_reg = 0x76,
3096 .edid_spa_loc_msb_mask = 0x40,
3097 .edid_spa_port_b_reg = 0x70,
3098 .lcf_reg = 0xb3,
3099 .tdms_lock_mask = 0xe0,
3100 .cable_det_mask = 0x1e,
3101 .fmt_change_digital_mask = 0xc1,
3102 .cp_csc = 0xfc,
3103 .cec_irq_status = 0x4d,
3104 .cec_rx_enable = 0x26,
3105 .cec_rx_enable_mask = 0x01,
3106 .cec_irq_swap = true,
3107 .formats = adv7604_formats,
3108 .nformats = ARRAY_SIZE(adv7604_formats),
3109 .set_termination = adv7604_set_termination,
3110 .setup_irqs = adv7604_setup_irqs,
3111 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
3112 .read_cable_det = adv7604_read_cable_det,
3113 .recommended_settings = {
3114 [0] = adv7604_recommended_settings_afe,
3115 [1] = adv7604_recommended_settings_hdmi,
3116 },
3117 .num_recommended_settings = {
3118 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
3119 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
3120 },
3121 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
3122 BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
3123 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
3124 BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
3125 BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
3126 BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
3127 BIT(ADV7604_PAGE_VDP),
3128 .linewidth_mask = 0xfff,
3129 .field0_height_mask = 0xfff,
3130 .field1_height_mask = 0xfff,
3131 .hfrontporch_mask = 0x3ff,
3132 .hsync_mask = 0x3ff,
3133 .hbackporch_mask = 0x3ff,
3134 .field0_vfrontporch_mask = 0x1fff,
3135 .field0_vsync_mask = 0x1fff,
3136 .field0_vbackporch_mask = 0x1fff,
3137 .field1_vfrontporch_mask = 0x1fff,
3138 .field1_vsync_mask = 0x1fff,
3139 .field1_vbackporch_mask = 0x1fff,
3140 },
3141 [ADV7611] = {
3142 .type = ADV7611,
3143 .has_afe = false,
3144 .max_port = ADV76XX_PAD_HDMI_PORT_A,
3145 .num_dv_ports = 1,
3146 .edid_enable_reg = 0x74,
3147 .edid_status_reg = 0x76,
3148 .edid_segment_reg = 0x7a,
3149 .edid_segment_mask = 0x01,
3150 .lcf_reg = 0xa3,
3151 .tdms_lock_mask = 0x43,
3152 .cable_det_mask = 0x01,
3153 .fmt_change_digital_mask = 0x03,
3154 .cp_csc = 0xf4,
3155 .cec_irq_status = 0x93,
3156 .cec_rx_enable = 0x2c,
3157 .cec_rx_enable_mask = 0x02,
3158 .formats = adv7611_formats,
3159 .nformats = ARRAY_SIZE(adv7611_formats),
3160 .set_termination = adv7611_set_termination,
3161 .setup_irqs = adv7611_setup_irqs,
3162 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
3163 .read_cable_det = adv7611_read_cable_det,
3164 .recommended_settings = {
3165 [1] = adv7611_recommended_settings_hdmi,
3166 },
3167 .num_recommended_settings = {
3168 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
3169 },
3170 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
3171 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
3172 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
3173 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
3174 .linewidth_mask = 0x1fff,
3175 .field0_height_mask = 0x1fff,
3176 .field1_height_mask = 0x1fff,
3177 .hfrontporch_mask = 0x1fff,
3178 .hsync_mask = 0x1fff,
3179 .hbackporch_mask = 0x1fff,
3180 .field0_vfrontporch_mask = 0x3fff,
3181 .field0_vsync_mask = 0x3fff,
3182 .field0_vbackporch_mask = 0x3fff,
3183 .field1_vfrontporch_mask = 0x3fff,
3184 .field1_vsync_mask = 0x3fff,
3185 .field1_vbackporch_mask = 0x3fff,
3186 },
3187 [ADV7612] = {
3188 .type = ADV7612,
3189 .has_afe = false,
3190 .max_port = ADV76XX_PAD_HDMI_PORT_A, /* B not supported */
3191 .num_dv_ports = 1, /* normally 2 */
3192 .edid_enable_reg = 0x74,
3193 .edid_status_reg = 0x76,
3194 .edid_segment_reg = 0x7a,
3195 .edid_segment_mask = 0x01,
3196 .edid_spa_loc_reg = 0x70,
3197 .edid_spa_loc_msb_mask = 0x01,
3198 .edid_spa_port_b_reg = 0x52,
3199 .lcf_reg = 0xa3,
3200 .tdms_lock_mask = 0x43,
3201 .cable_det_mask = 0x01,
3202 .fmt_change_digital_mask = 0x03,
3203 .cp_csc = 0xf4,
3204 .cec_irq_status = 0x93,
3205 .cec_rx_enable = 0x2c,
3206 .cec_rx_enable_mask = 0x02,
3207 .formats = adv7612_formats,
3208 .nformats = ARRAY_SIZE(adv7612_formats),
3209 .set_termination = adv7611_set_termination,
3210 .setup_irqs = adv7612_setup_irqs,
3211 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
3212 .read_cable_det = adv7612_read_cable_det,
3213 .recommended_settings = {
3214 [1] = adv7612_recommended_settings_hdmi,
3215 },
3216 .num_recommended_settings = {
3217 [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi),
3218 },
3219 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
3220 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
3221 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
3222 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
3223 .linewidth_mask = 0x1fff,
3224 .field0_height_mask = 0x1fff,
3225 .field1_height_mask = 0x1fff,
3226 .hfrontporch_mask = 0x1fff,
3227 .hsync_mask = 0x1fff,
3228 .hbackporch_mask = 0x1fff,
3229 .field0_vfrontporch_mask = 0x3fff,
3230 .field0_vsync_mask = 0x3fff,
3231 .field0_vbackporch_mask = 0x3fff,
3232 .field1_vfrontporch_mask = 0x3fff,
3233 .field1_vsync_mask = 0x3fff,
3234 .field1_vbackporch_mask = 0x3fff,
3235 },
3236 };
3237
3238 static const struct i2c_device_id adv76xx_i2c_id[] = {
3239 { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
3240 { "adv7610", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
3241 { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
3242 { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] },
3243 { }
3244 };
3245 MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
3246
3247 static const struct of_device_id adv76xx_of_id[] __maybe_unused = {
3248 { .compatible = "adi,adv7610", .data = &adv76xx_chip_info[ADV7611] },
3249 { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
3250 { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] },
3251 { }
3252 };
3253 MODULE_DEVICE_TABLE(of, adv76xx_of_id);
3254
3255 static int adv76xx_parse_dt(struct adv76xx_state *state)
3256 {
3257 struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
3258 struct device_node *endpoint;
3259 struct device_node *np;
3260 unsigned int flags;
3261 int ret;
3262 u32 v;
3263
3264 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
3265
3266 /* FIXME: Parse the endpoint. */
3267 endpoint = of_graph_get_endpoint_by_regs(np, -1, -1);
3268 if (!endpoint)
3269 return -EINVAL;
3270
3271 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), &bus_cfg);
3272 of_node_put(endpoint);
3273 if (ret)
3274 return ret;
3275
3276 if (!of_property_read_u32(np, "default-input", &v))
3277 state->pdata.default_input = v;
3278 else
3279 state->pdata.default_input = -1;
3280
3281 flags = bus_cfg.bus.parallel.flags;
3282
3283 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
3284 state->pdata.inv_hs_pol = 1;
3285
3286 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
3287 state->pdata.inv_vs_pol = 1;
3288
3289 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
3290 state->pdata.inv_llc_pol = 1;
3291
3292 if (bus_cfg.bus_type == V4L2_MBUS_BT656)
3293 state->pdata.insert_av_codes = 1;
3294
3295 /* Disable the interrupt for now as no DT-based board uses it. */
3296 state->pdata.int1_config = ADV76XX_INT1_CONFIG_ACTIVE_HIGH;
3297
3298 /* Hardcode the remaining platform data fields. */
3299 state->pdata.disable_pwrdnb = 0;
3300 state->pdata.disable_cable_det_rst = 0;
3301 state->pdata.blank_data = 1;
3302 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
3303 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
3304 state->pdata.dr_str_data = ADV76XX_DR_STR_MEDIUM_HIGH;
3305 state->pdata.dr_str_clk = ADV76XX_DR_STR_MEDIUM_HIGH;
3306 state->pdata.dr_str_sync = ADV76XX_DR_STR_MEDIUM_HIGH;
3307
3308 return 0;
3309 }
3310
3311 static const struct regmap_config adv76xx_regmap_cnf[] = {
3312 {
3313 .name = "io",
3314 .reg_bits = 8,
3315 .val_bits = 8,
3316
3317 .max_register = 0xff,
3318 .cache_type = REGCACHE_NONE,
3319 },
3320 {
3321 .name = "avlink",
3322 .reg_bits = 8,
3323 .val_bits = 8,
3324
3325 .max_register = 0xff,
3326 .cache_type = REGCACHE_NONE,
3327 },
3328 {
3329 .name = "cec",
3330 .reg_bits = 8,
3331 .val_bits = 8,
3332
3333 .max_register = 0xff,
3334 .cache_type = REGCACHE_NONE,
3335 },
3336 {
3337 .name = "infoframe",
3338 .reg_bits = 8,
3339 .val_bits = 8,
3340
3341 .max_register = 0xff,
3342 .cache_type = REGCACHE_NONE,
3343 },
3344 {
3345 .name = "esdp",
3346 .reg_bits = 8,
3347 .val_bits = 8,
3348
3349 .max_register = 0xff,
3350 .cache_type = REGCACHE_NONE,
3351 },
3352 {
3353 .name = "epp",
3354 .reg_bits = 8,
3355 .val_bits = 8,
3356
3357 .max_register = 0xff,
3358 .cache_type = REGCACHE_NONE,
3359 },
3360 {
3361 .name = "afe",
3362 .reg_bits = 8,
3363 .val_bits = 8,
3364
3365 .max_register = 0xff,
3366 .cache_type = REGCACHE_NONE,
3367 },
3368 {
3369 .name = "rep",
3370 .reg_bits = 8,
3371 .val_bits = 8,
3372
3373 .max_register = 0xff,
3374 .cache_type = REGCACHE_NONE,
3375 },
3376 {
3377 .name = "edid",
3378 .reg_bits = 8,
3379 .val_bits = 8,
3380
3381 .max_register = 0xff,
3382 .cache_type = REGCACHE_NONE,
3383 },
3384
3385 {
3386 .name = "hdmi",
3387 .reg_bits = 8,
3388 .val_bits = 8,
3389
3390 .max_register = 0xff,
3391 .cache_type = REGCACHE_NONE,
3392 },
3393 {
3394 .name = "test",
3395 .reg_bits = 8,
3396 .val_bits = 8,
3397
3398 .max_register = 0xff,
3399 .cache_type = REGCACHE_NONE,
3400 },
3401 {
3402 .name = "cp",
3403 .reg_bits = 8,
3404 .val_bits = 8,
3405
3406 .max_register = 0xff,
3407 .cache_type = REGCACHE_NONE,
3408 },
3409 {
3410 .name = "vdp",
3411 .reg_bits = 8,
3412 .val_bits = 8,
3413
3414 .max_register = 0xff,
3415 .cache_type = REGCACHE_NONE,
3416 },
3417 };
3418
3419 static int configure_regmap(struct adv76xx_state *state, int region)
3420 {
3421 int err;
3422
3423 if (!state->i2c_clients[region])
3424 return -ENODEV;
3425
3426 state->regmap[region] =
3427 devm_regmap_init_i2c(state->i2c_clients[region],
3428 &adv76xx_regmap_cnf[region]);
3429
3430 if (IS_ERR(state->regmap[region])) {
3431 err = PTR_ERR(state->regmap[region]);
3432 v4l_err(state->i2c_clients[region],
3433 "Error initializing regmap %d with error %d\n",
3434 region, err);
3435 return -EINVAL;
3436 }
3437
3438 return 0;
3439 }
3440
3441 static int configure_regmaps(struct adv76xx_state *state)
3442 {
3443 int i, err;
3444
3445 for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) {
3446 err = configure_regmap(state, i);
3447 if (err && (err != -ENODEV))
3448 return err;
3449 }
3450 return 0;
3451 }
3452
3453 static void adv76xx_reset(struct adv76xx_state *state)
3454 {
3455 if (state->reset_gpio) {
3456 /* ADV76XX can be reset by a low reset pulse of minimum 5 ms. */
3457 gpiod_set_value_cansleep(state->reset_gpio, 0);
3458 usleep_range(5000, 10000);
3459 gpiod_set_value_cansleep(state->reset_gpio, 1);
3460 /* It is recommended to wait 5 ms after the low pulse before */
3461 /* an I2C write is performed to the ADV76XX. */
3462 usleep_range(5000, 10000);
3463 }
3464 }
3465
3466 static int adv76xx_probe(struct i2c_client *client)
3467 {
3468 const struct i2c_device_id *id = i2c_client_get_device_id(client);
3469 static const struct v4l2_dv_timings cea640x480 =
3470 V4L2_DV_BT_CEA_640X480P59_94;
3471 struct adv76xx_state *state;
3472 struct v4l2_ctrl_handler *hdl;
3473 struct v4l2_ctrl *ctrl;
3474 struct v4l2_subdev *sd;
3475 unsigned int i;
3476 unsigned int val, val2;
3477 int err;
3478
3479 /* Check if the adapter supports the needed features */
3480 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3481 return -EIO;
3482 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
3483 client->addr << 1);
3484
3485 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
3486 if (!state)
3487 return -ENOMEM;
3488
3489 state->i2c_clients[ADV76XX_PAGE_IO] = client;
3490
3491 /* initialize variables */
3492 state->restart_stdi_once = true;
3493 state->selected_input = ~0;
3494
3495 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
3496 const struct of_device_id *oid;
3497
3498 oid = of_match_node(adv76xx_of_id, client->dev.of_node);
3499 state->info = oid->data;
3500
3501 err = adv76xx_parse_dt(state);
3502 if (err < 0) {
3503 v4l_err(client, "DT parsing error\n");
3504 return err;
3505 }
3506 } else if (client->dev.platform_data) {
3507 struct adv76xx_platform_data *pdata = client->dev.platform_data;
3508
3509 state->info = (const struct adv76xx_chip_info *)id->driver_data;
3510 state->pdata = *pdata;
3511 } else {
3512 v4l_err(client, "No platform data!\n");
3513 return -ENODEV;
3514 }
3515
3516 /* Request GPIOs. */
3517 for (i = 0; i < state->info->num_dv_ports; ++i) {
3518 state->hpd_gpio[i] =
3519 devm_gpiod_get_index_optional(&client->dev, "hpd", i,
3520 GPIOD_OUT_LOW);
3521 if (IS_ERR(state->hpd_gpio[i]))
3522 return PTR_ERR(state->hpd_gpio[i]);
3523
3524 if (state->hpd_gpio[i])
3525 v4l_info(client, "Handling HPD %u GPIO\n", i);
3526 }
3527 state->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
3528 GPIOD_OUT_HIGH);
3529 if (IS_ERR(state->reset_gpio))
3530 return PTR_ERR(state->reset_gpio);
3531
3532 adv76xx_reset(state);
3533
3534 state->timings = cea640x480;
3535 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
3536
3537 sd = &state->sd;
3538 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
3539 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
3540 id->name, i2c_adapter_id(client->adapter),
3541 client->addr);
3542 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
3543 sd->internal_ops = &adv76xx_int_ops;
3544
3545 /* Configure IO Regmap region */
3546 err = configure_regmap(state, ADV76XX_PAGE_IO);
3547
3548 if (err) {
3549 v4l2_err(sd, "Error configuring IO regmap region\n");
3550 return -ENODEV;
3551 }
3552
3553 /*
3554 * Verify that the chip is present. On ADV7604 the RD_INFO register only
3555 * identifies the revision, while on ADV7611 it identifies the model as
3556 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
3557 */
3558 switch (state->info->type) {
3559 case ADV7604:
3560 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val);
3561 if (err) {
3562 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3563 return -ENODEV;
3564 }
3565 if (val != 0x68) {
3566 v4l2_err(sd, "not an ADV7604 on address 0x%x\n",
3567 client->addr << 1);
3568 return -ENODEV;
3569 }
3570 break;
3571 case ADV7611:
3572 case ADV7612:
3573 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3574 0xea,
3575 &val);
3576 if (err) {
3577 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3578 return -ENODEV;
3579 }
3580 val2 = val << 8;
3581 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3582 0xeb,
3583 &val);
3584 if (err) {
3585 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3586 return -ENODEV;
3587 }
3588 val |= val2;
3589 if ((state->info->type == ADV7611 && val != 0x2051) ||
3590 (state->info->type == ADV7612 && val != 0x2041)) {
3591 v4l2_err(sd, "not an %s on address 0x%x\n",
3592 state->info->type == ADV7611 ? "ADV7610/11" : "ADV7612",
3593 client->addr << 1);
3594 return -ENODEV;
3595 }
3596 break;
3597 }
3598
3599 /* control handlers */
3600 hdl = &state->hdl;
3601 v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
3602
3603 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3604 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3605 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3606 V4L2_CID_CONTRAST, 0, 255, 1, 128);
3607 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3608 V4L2_CID_SATURATION, 0, 255, 1, 128);
3609 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3610 V4L2_CID_HUE, 0, 255, 1, 0);
3611 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3612 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
3613 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
3614 if (ctrl)
3615 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
3616
3617 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3618 V4L2_CID_DV_RX_POWER_PRESENT, 0,
3619 (1 << state->info->num_dv_ports) - 1, 0, 0);
3620 state->rgb_quantization_range_ctrl =
3621 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3622 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3623 0, V4L2_DV_RGB_RANGE_AUTO);
3624
3625 /* custom controls */
3626 if (adv76xx_has_afe(state))
3627 state->analog_sampling_phase_ctrl =
3628 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
3629 state->free_run_color_manual_ctrl =
3630 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
3631 state->free_run_color_ctrl =
3632 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
3633
3634 sd->ctrl_handler = hdl;
3635 if (hdl->error) {
3636 err = hdl->error;
3637 goto err_hdl;
3638 }
3639 if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
3640 err = -ENODEV;
3641 goto err_hdl;
3642 }
3643
3644 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
3645 struct i2c_client *dummy_client;
3646
3647 if (!(BIT(i) & state->info->page_mask))
3648 continue;
3649
3650 dummy_client = adv76xx_dummy_client(sd, i);
3651 if (IS_ERR(dummy_client)) {
3652 err = PTR_ERR(dummy_client);
3653 v4l2_err(sd, "failed to create i2c client %u\n", i);
3654 goto err_i2c;
3655 }
3656
3657 state->i2c_clients[i] = dummy_client;
3658 }
3659
3660 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3661 adv76xx_delayed_work_enable_hotplug);
3662
3663 state->source_pad = state->info->num_dv_ports
3664 + (state->info->has_afe ? 2 : 0);
3665 for (i = 0; i < state->source_pad; ++i)
3666 state->pads[i].flags = MEDIA_PAD_FL_SINK;
3667 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
3668 sd->entity.function = MEDIA_ENT_F_DV_DECODER;
3669
3670 err = media_entity_pads_init(&sd->entity, state->source_pad + 1,
3671 state->pads);
3672 if (err)
3673 goto err_work_queues;
3674
3675 /* Configure regmaps */
3676 err = configure_regmaps(state);
3677 if (err)
3678 goto err_entity;
3679
3680 err = adv76xx_core_init(sd);
3681 if (err)
3682 goto err_entity;
3683
3684 if (client->irq) {
3685 err = devm_request_threaded_irq(&client->dev,
3686 client->irq,
3687 NULL, adv76xx_irq_handler,
3688 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
3689 client->name, state);
3690 if (err)
3691 goto err_entity;
3692 }
3693
3694 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
3695 state->cec_adap = cec_allocate_adapter(&adv76xx_cec_adap_ops,
3696 state, dev_name(&client->dev),
3697 CEC_CAP_DEFAULTS, ADV76XX_MAX_ADDRS);
3698 err = PTR_ERR_OR_ZERO(state->cec_adap);
3699 if (err)
3700 goto err_entity;
3701 #endif
3702
3703 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3704 client->addr << 1, client->adapter->name);
3705
3706 err = v4l2_async_register_subdev(sd);
3707 if (err)
3708 goto err_entity;
3709
3710 return 0;
3711
3712 err_entity:
3713 media_entity_cleanup(&sd->entity);
3714 err_work_queues:
3715 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3716 err_i2c:
3717 adv76xx_unregister_clients(state);
3718 err_hdl:
3719 v4l2_ctrl_handler_free(hdl);
3720 return err;
3721 }
3722
3723 /* ----------------------------------------------------------------------- */
3724
3725 static void adv76xx_remove(struct i2c_client *client)
3726 {
3727 struct v4l2_subdev *sd = i2c_get_clientdata(client);
3728 struct adv76xx_state *state = to_state(sd);
3729
3730 /* disable interrupts */
3731 io_write(sd, 0x40, 0);
3732 io_write(sd, 0x41, 0);
3733 io_write(sd, 0x46, 0);
3734 io_write(sd, 0x6e, 0);
3735 io_write(sd, 0x73, 0);
3736
3737 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
3738 v4l2_async_unregister_subdev(sd);
3739 media_entity_cleanup(&sd->entity);
3740 adv76xx_unregister_clients(to_state(sd));
3741 v4l2_ctrl_handler_free(sd->ctrl_handler);
3742 }
3743
3744 /* ----------------------------------------------------------------------- */
3745
3746 static struct i2c_driver adv76xx_driver = {
3747 .driver = {
3748 .name = "adv7604",
3749 .of_match_table = of_match_ptr(adv76xx_of_id),
3750 },
3751 .probe = adv76xx_probe,
3752 .remove = adv76xx_remove,
3753 .id_table = adv76xx_i2c_id,
3754 };
3755
3756 module_i2c_driver(adv76xx_driver);
Kernel DRM miscellaneous fixes and cross-tree changes