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Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / media / i2c / ar0521.c
blob24873149096c1a2251a9f63623f393542eecf193
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2021 Sieć Badawcza Łukasiewicz
4 * - Przemysłowy Instytut Automatyki i Pomiarów PIAP
5 * Written by Krzysztof Hałasa
6 */
7
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/pm_runtime.h>
11
12 #include <media/v4l2-ctrls.h>
13 #include <media/v4l2-fwnode.h>
14 #include <media/v4l2-subdev.h>
15
16 /* External clock (extclk) frequencies */
17 #define AR0521_EXTCLK_MIN (10 * 1000 * 1000)
18 #define AR0521_EXTCLK_MAX (48 * 1000 * 1000)
19
20 /* PLL and PLL2 */
21 #define AR0521_PLL_MIN (320 * 1000 * 1000)
22 #define AR0521_PLL_MAX (1280 * 1000 * 1000)
23
24 /* Effective pixel sample rate on the pixel array. */
25 #define AR0521_PIXEL_CLOCK_RATE (184 * 1000 * 1000)
26 #define AR0521_PIXEL_CLOCK_MIN (168 * 1000 * 1000)
27 #define AR0521_PIXEL_CLOCK_MAX (414 * 1000 * 1000)
28
29 #define AR0521_NATIVE_WIDTH 2604u
30 #define AR0521_NATIVE_HEIGHT 1964u
31 #define AR0521_MIN_X_ADDR_START 0u
32 #define AR0521_MIN_Y_ADDR_START 0u
33 #define AR0521_MAX_X_ADDR_END 2603u
34 #define AR0521_MAX_Y_ADDR_END 1955u
35
36 #define AR0521_WIDTH_MIN 8u
37 #define AR0521_WIDTH_MAX 2592u
38 #define AR0521_HEIGHT_MIN 8u
39 #define AR0521_HEIGHT_MAX 1944u
40
41 #define AR0521_WIDTH_BLANKING_MIN 572u
42 #define AR0521_HEIGHT_BLANKING_MIN 38u /* must be even */
43 #define AR0521_TOTAL_HEIGHT_MAX 65535u /* max_frame_length_lines */
44 #define AR0521_TOTAL_WIDTH_MAX 65532u /* max_line_length_pck */
45
46 #define AR0521_ANA_GAIN_MIN 0x00
47 #define AR0521_ANA_GAIN_MAX 0x3f
48 #define AR0521_ANA_GAIN_STEP 0x01
49 #define AR0521_ANA_GAIN_DEFAULT 0x00
50
51 /* AR0521 registers */
52 #define AR0521_REG_VT_PIX_CLK_DIV 0x0300
53 #define AR0521_REG_FRAME_LENGTH_LINES 0x0340
54
55 #define AR0521_REG_CHIP_ID 0x3000
56 #define AR0521_REG_COARSE_INTEGRATION_TIME 0x3012
57 #define AR0521_REG_ROW_SPEED 0x3016
58 #define AR0521_REG_EXTRA_DELAY 0x3018
59 #define AR0521_REG_RESET 0x301A
60 #define AR0521_REG_RESET_DEFAULTS 0x0238
61 #define AR0521_REG_RESET_GROUP_PARAM_HOLD 0x8000
62 #define AR0521_REG_RESET_STREAM BIT(2)
63 #define AR0521_REG_RESET_RESTART BIT(1)
64 #define AR0521_REG_RESET_INIT BIT(0)
65
66 #define AR0521_REG_ANA_GAIN_CODE_GLOBAL 0x3028
67
68 #define AR0521_REG_GREEN1_GAIN 0x3056
69 #define AR0521_REG_BLUE_GAIN 0x3058
70 #define AR0521_REG_RED_GAIN 0x305A
71 #define AR0521_REG_GREEN2_GAIN 0x305C
72 #define AR0521_REG_GLOBAL_GAIN 0x305E
73
74 #define AR0521_REG_HISPI_TEST_MODE 0x3066
75 #define AR0521_REG_HISPI_TEST_MODE_LP11 0x0004
76
77 #define AR0521_REG_TEST_PATTERN_MODE 0x3070
78
79 #define AR0521_REG_SERIAL_FORMAT 0x31AE
80 #define AR0521_REG_SERIAL_FORMAT_MIPI 0x0200
81
82 #define AR0521_REG_HISPI_CONTROL_STATUS 0x31C6
83 #define AR0521_REG_HISPI_CONTROL_STATUS_FRAMER_TEST_MODE_ENABLE 0x80
84
85 #define be cpu_to_be16
86
87 static const char * const ar0521_supply_names[] = {
88 "vdd_io", /* I/O (1.8V) supply */
89 "vdd", /* Core, PLL and MIPI (1.2V) supply */
90 "vaa", /* Analog (2.7V) supply */
91 };
92
93 static const s64 ar0521_link_frequencies[] = {
94 184000000,
95 };
96
97 struct ar0521_ctrls {
98 struct v4l2_ctrl_handler handler;
99 struct {
100 struct v4l2_ctrl *gain;
101 struct v4l2_ctrl *red_balance;
102 struct v4l2_ctrl *blue_balance;
103 };
104 struct {
105 struct v4l2_ctrl *hblank;
106 struct v4l2_ctrl *vblank;
107 };
108 struct v4l2_ctrl *pixrate;
109 struct v4l2_ctrl *exposure;
110 struct v4l2_ctrl *test_pattern;
111 };
112
113 struct ar0521_dev {
114 struct i2c_client *i2c_client;
115 struct v4l2_subdev sd;
116 struct media_pad pad;
117 struct clk *extclk;
118 u32 extclk_freq;
119
120 struct regulator *supplies[ARRAY_SIZE(ar0521_supply_names)];
121 struct gpio_desc *reset_gpio;
122
123 /* lock to protect all members below */
124 struct mutex lock;
125
126 struct v4l2_mbus_framefmt fmt;
127 struct ar0521_ctrls ctrls;
128 unsigned int lane_count;
129 struct {
130 u16 pre;
131 u16 mult;
132 u16 pre2;
133 u16 mult2;
134 u16 vt_pix;
135 } pll;
136 };
137
138 static inline struct ar0521_dev *to_ar0521_dev(struct v4l2_subdev *sd)
139 {
140 return container_of(sd, struct ar0521_dev, sd);
141 }
142
143 static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
144 {
145 return &container_of(ctrl->handler, struct ar0521_dev,
146 ctrls.handler)->sd;
147 }
148
149 static u32 div64_round(u64 v, u32 d)
150 {
151 return div_u64(v + (d >> 1), d);
152 }
153
154 static u32 div64_round_up(u64 v, u32 d)
155 {
156 return div_u64(v + d - 1, d);
157 }
158
159 static int ar0521_code_to_bpp(struct ar0521_dev *sensor)
160 {
161 switch (sensor->fmt.code) {
162 case MEDIA_BUS_FMT_SGRBG8_1X8:
163 return 8;
164 }
165
166 return -EINVAL;
167 }
168
169 /* Data must be BE16, the first value is the register address */
170 static int ar0521_write_regs(struct ar0521_dev *sensor, const __be16 *data,
171 unsigned int count)
172 {
173 struct i2c_client *client = sensor->i2c_client;
174 struct i2c_msg msg;
175 int ret;
176
177 msg.addr = client->addr;
178 msg.flags = client->flags;
179 msg.buf = (u8 *)data;
180 msg.len = count * sizeof(*data);
181
182 ret = i2c_transfer(client->adapter, &msg, 1);
183
184 if (ret < 0) {
185 v4l2_err(&sensor->sd, "%s: I2C write error\n", __func__);
186 return ret;
187 }
188
189 return 0;
190 }
191
192 static int ar0521_write_reg(struct ar0521_dev *sensor, u16 reg, u16 val)
193 {
194 __be16 buf[2] = {be(reg), be(val)};
195
196 return ar0521_write_regs(sensor, buf, 2);
197 }
198
199 static int ar0521_set_geometry(struct ar0521_dev *sensor)
200 {
201 /* Center the image in the visible output window. */
202 u16 x = clamp((AR0521_WIDTH_MAX - sensor->fmt.width) / 2,
203 AR0521_MIN_X_ADDR_START, AR0521_MAX_X_ADDR_END);
204 u16 y = clamp(((AR0521_HEIGHT_MAX - sensor->fmt.height) / 2) & ~1,
205 AR0521_MIN_Y_ADDR_START, AR0521_MAX_Y_ADDR_END);
206
207 /* All dimensions are unsigned 12-bit integers */
208 __be16 regs[] = {
209 be(AR0521_REG_FRAME_LENGTH_LINES),
210 be(sensor->fmt.height + sensor->ctrls.vblank->val),
211 be(sensor->fmt.width + sensor->ctrls.hblank->val),
212 be(x),
213 be(y),
214 be(x + sensor->fmt.width - 1),
215 be(y + sensor->fmt.height - 1),
216 be(sensor->fmt.width),
217 be(sensor->fmt.height)
218 };
219
220 return ar0521_write_regs(sensor, regs, ARRAY_SIZE(regs));
221 }
222
223 static int ar0521_set_gains(struct ar0521_dev *sensor)
224 {
225 int green = sensor->ctrls.gain->val;
226 int red = max(green + sensor->ctrls.red_balance->val, 0);
227 int blue = max(green + sensor->ctrls.blue_balance->val, 0);
228 unsigned int gain = min(red, min(green, blue));
229 unsigned int analog = min(gain, 64u); /* range is 0 - 127 */
230 __be16 regs[5];
231
232 red = min(red - analog + 64, 511u);
233 green = min(green - analog + 64, 511u);
234 blue = min(blue - analog + 64, 511u);
235 regs[0] = be(AR0521_REG_GREEN1_GAIN);
236 regs[1] = be(green << 7 | analog);
237 regs[2] = be(blue << 7 | analog);
238 regs[3] = be(red << 7 | analog);
239 regs[4] = be(green << 7 | analog);
240
241 return ar0521_write_regs(sensor, regs, ARRAY_SIZE(regs));
242 }
243
244 static u32 calc_pll(struct ar0521_dev *sensor, u32 freq, u16 *pre_ptr, u16 *mult_ptr)
245 {
246 u16 pre = 1, mult = 1, new_pre;
247 u32 pll = AR0521_PLL_MAX + 1;
248
249 for (new_pre = 1; new_pre < 64; new_pre++) {
250 u32 new_pll;
251 u32 new_mult = div64_round_up((u64)freq * new_pre,
252 sensor->extclk_freq);
253
254 if (new_mult < 32)
255 continue; /* Minimum value */
256 if (new_mult > 254)
257 break; /* Maximum, larger pre won't work either */
258 if (sensor->extclk_freq * (u64)new_mult < (u64)AR0521_PLL_MIN *
259 new_pre)
260 continue;
261 if (sensor->extclk_freq * (u64)new_mult > (u64)AR0521_PLL_MAX *
262 new_pre)
263 break; /* Larger pre won't work either */
264 new_pll = div64_round_up(sensor->extclk_freq * (u64)new_mult,
265 new_pre);
266 if (new_pll < pll) {
267 pll = new_pll;
268 pre = new_pre;
269 mult = new_mult;
270 }
271 }
272
273 pll = div64_round(sensor->extclk_freq * (u64)mult, pre);
274 *pre_ptr = pre;
275 *mult_ptr = mult;
276 return pll;
277 }
278
279 static void ar0521_calc_pll(struct ar0521_dev *sensor)
280 {
281 unsigned int pixel_clock;
282 u16 pre, mult;
283 u32 vco;
284 int bpp;
285
286 /*
287 * PLL1 and PLL2 are computed equally even if the application note
288 * suggests a slower PLL1 clock. Maintain pll1 and pll2 divider and
289 * multiplier separated to later specialize the calculation procedure.
290 *
291 * PLL1:
292 * - mclk -> / pre_div1 * pre_mul1 = VCO1 = COUNTER_CLOCK
293 *
294 * PLL2:
295 * - mclk -> / pre_div * pre_mul = VCO
296 *
297 * VCO -> / vt_pix = PIXEL_CLOCK
298 * VCO -> / vt_pix / 2 = WORD_CLOCK
299 * VCO -> / op_sys = SERIAL_CLOCK
300 *
301 * With:
302 * - vt_pix = bpp / 2
303 * - WORD_CLOCK = PIXEL_CLOCK / 2
304 * - SERIAL_CLOCK = MIPI data rate (Mbps / lane) = WORD_CLOCK * bpp
305 * NOTE: this implies the MIPI clock is divided internally by 2
306 * to account for DDR.
307 *
308 * As op_sys_div is fixed to 1:
309 *
310 * SERIAL_CLOCK = VCO
311 * VCO = 2 * MIPI_CLK
312 * VCO = PIXEL_CLOCK * bpp / 2
313 *
314 * In the clock tree:
315 * MIPI_CLK = PIXEL_CLOCK * bpp / 2 / 2
316 *
317 * Generic pixel_rate to bus clock frequency equation:
318 * MIPI_CLK = V4L2_CID_PIXEL_RATE * bpp / lanes / 2
319 *
320 * From which we derive the PIXEL_CLOCK to use in the clock tree:
321 * PIXEL_CLOCK = V4L2_CID_PIXEL_RATE * 2 / lanes
322 *
323 * Documented clock ranges:
324 * WORD_CLOCK = (35MHz - 120 MHz)
325 * PIXEL_CLOCK = (84MHz - 207MHz)
326 * VCO = (320MHz - 1280MHz)
327 *
328 * TODO: in case we have less data lanes we have to reduce the desired
329 * VCO not to exceed the limits specified by the datasheet and
330 * consequently reduce the obtained pixel clock.
331 */
332 pixel_clock = AR0521_PIXEL_CLOCK_RATE * 2 / sensor->lane_count;
333 bpp = ar0521_code_to_bpp(sensor);
334 sensor->pll.vt_pix = bpp / 2;
335 vco = pixel_clock * sensor->pll.vt_pix;
336
337 calc_pll(sensor, vco, &pre, &mult);
338
339 sensor->pll.pre = sensor->pll.pre2 = pre;
340 sensor->pll.mult = sensor->pll.mult2 = mult;
341 }
342
343 static int ar0521_pll_config(struct ar0521_dev *sensor)
344 {
345 __be16 pll_regs[] = {
346 be(AR0521_REG_VT_PIX_CLK_DIV),
347 /* 0x300 */ be(sensor->pll.vt_pix), /* vt_pix_clk_div = bpp / 2 */
348 /* 0x302 */ be(1), /* vt_sys_clk_div */
349 /* 0x304 */ be((sensor->pll.pre2 << 8) | sensor->pll.pre),
350 /* 0x306 */ be((sensor->pll.mult2 << 8) | sensor->pll.mult),
351 /* 0x308 */ be(sensor->pll.vt_pix * 2), /* op_pix_clk_div = 2 * vt_pix_clk_div */
352 /* 0x30A */ be(1) /* op_sys_clk_div */
353 };
354
355 ar0521_calc_pll(sensor);
356 return ar0521_write_regs(sensor, pll_regs, ARRAY_SIZE(pll_regs));
357 }
358
359 static int ar0521_set_stream(struct ar0521_dev *sensor, bool on)
360 {
361 int ret;
362
363 if (on) {
364 ret = pm_runtime_resume_and_get(&sensor->i2c_client->dev);
365 if (ret < 0)
366 return ret;
367
368 /* Stop streaming for just a moment */
369 ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
370 AR0521_REG_RESET_DEFAULTS);
371 if (ret)
372 return ret;
373
374 ret = ar0521_set_geometry(sensor);
375 if (ret)
376 return ret;
377
378 ret = ar0521_pll_config(sensor);
379 if (ret)
380 goto err;
381
382 ret = __v4l2_ctrl_handler_setup(&sensor->ctrls.handler);
383 if (ret)
384 goto err;
385
386 /* Exit LP-11 mode on clock and data lanes */
387 ret = ar0521_write_reg(sensor, AR0521_REG_HISPI_CONTROL_STATUS,
388 0);
389 if (ret)
390 goto err;
391
392 /* Start streaming */
393 ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
394 AR0521_REG_RESET_DEFAULTS |
395 AR0521_REG_RESET_STREAM);
396 if (ret)
397 goto err;
398
399 return 0;
400
401 err:
402 pm_runtime_put(&sensor->i2c_client->dev);
403 return ret;
404
405 } else {
406 /*
407 * Reset gain, the sensor may produce all white pixels without
408 * this
409 */
410 ret = ar0521_write_reg(sensor, AR0521_REG_GLOBAL_GAIN, 0x2000);
411 if (ret)
412 return ret;
413
414 /* Stop streaming */
415 ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
416 AR0521_REG_RESET_DEFAULTS);
417 if (ret)
418 return ret;
419
420 pm_runtime_put(&sensor->i2c_client->dev);
421 return 0;
422 }
423 }
424
425 static void ar0521_adj_fmt(struct v4l2_mbus_framefmt *fmt)
426 {
427 fmt->width = clamp(ALIGN(fmt->width, 4), AR0521_WIDTH_MIN,
428 AR0521_WIDTH_MAX);
429 fmt->height = clamp(ALIGN(fmt->height, 4), AR0521_HEIGHT_MIN,
430 AR0521_HEIGHT_MAX);
431 fmt->code = MEDIA_BUS_FMT_SGRBG8_1X8;
432 fmt->field = V4L2_FIELD_NONE;
433 fmt->colorspace = V4L2_COLORSPACE_SRGB;
434 fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
435 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
436 fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT;
437 }
438
439 static int ar0521_get_fmt(struct v4l2_subdev *sd,
440 struct v4l2_subdev_state *sd_state,
441 struct v4l2_subdev_format *format)
442 {
443 struct ar0521_dev *sensor = to_ar0521_dev(sd);
444 struct v4l2_mbus_framefmt *fmt;
445
446 mutex_lock(&sensor->lock);
447
448 if (format->which == V4L2_SUBDEV_FORMAT_TRY)
449 fmt = v4l2_subdev_state_get_format(sd_state, 0);
450 else
451 fmt = &sensor->fmt;
452
453 format->format = *fmt;
454
455 mutex_unlock(&sensor->lock);
456 return 0;
457 }
458
459 static int ar0521_set_fmt(struct v4l2_subdev *sd,
460 struct v4l2_subdev_state *sd_state,
461 struct v4l2_subdev_format *format)
462 {
463 struct ar0521_dev *sensor = to_ar0521_dev(sd);
464 int max_vblank, max_hblank, exposure_max;
465 int ret;
466
467 ar0521_adj_fmt(&format->format);
468
469 mutex_lock(&sensor->lock);
470
471 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
472 struct v4l2_mbus_framefmt *fmt;
473
474 fmt = v4l2_subdev_state_get_format(sd_state, 0);
475 *fmt = format->format;
476
477 mutex_unlock(&sensor->lock);
478
479 return 0;
480 }
481
482 sensor->fmt = format->format;
483 ar0521_calc_pll(sensor);
484
485 /*
486 * Update the exposure and blankings limits. Blankings are also reset
487 * to the minimum.
488 */
489 max_hblank = AR0521_TOTAL_WIDTH_MAX - sensor->fmt.width;
490 ret = __v4l2_ctrl_modify_range(sensor->ctrls.hblank,
491 sensor->ctrls.hblank->minimum,
492 max_hblank, sensor->ctrls.hblank->step,
493 sensor->ctrls.hblank->minimum);
494 if (ret)
495 goto unlock;
496
497 ret = __v4l2_ctrl_s_ctrl(sensor->ctrls.hblank,
498 sensor->ctrls.hblank->minimum);
499 if (ret)
500 goto unlock;
501
502 max_vblank = AR0521_TOTAL_HEIGHT_MAX - sensor->fmt.height;
503 ret = __v4l2_ctrl_modify_range(sensor->ctrls.vblank,
504 sensor->ctrls.vblank->minimum,
505 max_vblank, sensor->ctrls.vblank->step,
506 sensor->ctrls.vblank->minimum);
507 if (ret)
508 goto unlock;
509
510 ret = __v4l2_ctrl_s_ctrl(sensor->ctrls.vblank,
511 sensor->ctrls.vblank->minimum);
512 if (ret)
513 goto unlock;
514
515 exposure_max = sensor->fmt.height + AR0521_HEIGHT_BLANKING_MIN - 4;
516 ret = __v4l2_ctrl_modify_range(sensor->ctrls.exposure,
517 sensor->ctrls.exposure->minimum,
518 exposure_max,
519 sensor->ctrls.exposure->step,
520 sensor->ctrls.exposure->default_value);
521 unlock:
522 mutex_unlock(&sensor->lock);
523
524 return ret;
525 }
526
527 static int ar0521_s_ctrl(struct v4l2_ctrl *ctrl)
528 {
529 struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
530 struct ar0521_dev *sensor = to_ar0521_dev(sd);
531 int exp_max;
532 int ret;
533
534 /* v4l2_ctrl_lock() locks our own mutex */
535
536 switch (ctrl->id) {
537 case V4L2_CID_VBLANK:
538 exp_max = sensor->fmt.height + ctrl->val - 4;
539 __v4l2_ctrl_modify_range(sensor->ctrls.exposure,
540 sensor->ctrls.exposure->minimum,
541 exp_max, sensor->ctrls.exposure->step,
542 sensor->ctrls.exposure->default_value);
543 break;
544 }
545
546 /* access the sensor only if it's powered up */
547 if (!pm_runtime_get_if_in_use(&sensor->i2c_client->dev))
548 return 0;
549
550 switch (ctrl->id) {
551 case V4L2_CID_HBLANK:
552 case V4L2_CID_VBLANK:
553 ret = ar0521_set_geometry(sensor);
554 break;
555 case V4L2_CID_ANALOGUE_GAIN:
556 ret = ar0521_write_reg(sensor, AR0521_REG_ANA_GAIN_CODE_GLOBAL,
557 ctrl->val);
558 break;
559 case V4L2_CID_GAIN:
560 case V4L2_CID_RED_BALANCE:
561 case V4L2_CID_BLUE_BALANCE:
562 ret = ar0521_set_gains(sensor);
563 break;
564 case V4L2_CID_EXPOSURE:
565 ret = ar0521_write_reg(sensor,
566 AR0521_REG_COARSE_INTEGRATION_TIME,
567 ctrl->val);
568 break;
569 case V4L2_CID_TEST_PATTERN:
570 ret = ar0521_write_reg(sensor, AR0521_REG_TEST_PATTERN_MODE,
571 ctrl->val);
572 break;
573 default:
574 dev_err(&sensor->i2c_client->dev,
575 "Unsupported control %x\n", ctrl->id);
576 ret = -EINVAL;
577 break;
578 }
579
580 pm_runtime_put(&sensor->i2c_client->dev);
581 return ret;
582 }
583
584 static const struct v4l2_ctrl_ops ar0521_ctrl_ops = {
585 .s_ctrl = ar0521_s_ctrl,
586 };
587
588 static const char * const test_pattern_menu[] = {
589 "Disabled",
590 "Solid color",
591 "Color bars",
592 "Faded color bars"
593 };
594
595 static int ar0521_init_controls(struct ar0521_dev *sensor)
596 {
597 const struct v4l2_ctrl_ops *ops = &ar0521_ctrl_ops;
598 struct ar0521_ctrls *ctrls = &sensor->ctrls;
599 struct v4l2_ctrl_handler *hdl = &ctrls->handler;
600 int max_vblank, max_hblank, exposure_max;
601 struct v4l2_ctrl *link_freq;
602 int ret;
603
604 v4l2_ctrl_handler_init(hdl, 32);
605
606 /* We can use our own mutex for the ctrl lock */
607 hdl->lock = &sensor->lock;
608
609 /* Analog gain */
610 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN,
611 AR0521_ANA_GAIN_MIN, AR0521_ANA_GAIN_MAX,
612 AR0521_ANA_GAIN_STEP, AR0521_ANA_GAIN_DEFAULT);
613
614 /* Manual gain */
615 ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN, 0, 511, 1, 0);
616 ctrls->red_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
617 -512, 511, 1, 0);
618 ctrls->blue_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
619 -512, 511, 1, 0);
620 v4l2_ctrl_cluster(3, &ctrls->gain);
621
622 /* Initialize blanking limits using the default 2592x1944 format. */
623 max_hblank = AR0521_TOTAL_WIDTH_MAX - AR0521_WIDTH_MAX;
624 ctrls->hblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HBLANK,
625 AR0521_WIDTH_BLANKING_MIN,
626 max_hblank, 1,
627 AR0521_WIDTH_BLANKING_MIN);
628
629 max_vblank = AR0521_TOTAL_HEIGHT_MAX - AR0521_HEIGHT_MAX;
630 ctrls->vblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VBLANK,
631 AR0521_HEIGHT_BLANKING_MIN,
632 max_vblank, 2,
633 AR0521_HEIGHT_BLANKING_MIN);
634 v4l2_ctrl_cluster(2, &ctrls->hblank);
635
636 /* Read-only */
637 ctrls->pixrate = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_PIXEL_RATE,
638 AR0521_PIXEL_CLOCK_MIN,
639 AR0521_PIXEL_CLOCK_MAX, 1,
640 AR0521_PIXEL_CLOCK_RATE);
641
642 /* Manual exposure time: max exposure time = visible + blank - 4 */
643 exposure_max = AR0521_HEIGHT_MAX + AR0521_HEIGHT_BLANKING_MIN - 4;
644 ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE, 0,
645 exposure_max, 1, 0x70);
646
647 link_freq = v4l2_ctrl_new_int_menu(hdl, ops, V4L2_CID_LINK_FREQ,
648 ARRAY_SIZE(ar0521_link_frequencies) - 1,
649 0, ar0521_link_frequencies);
650 if (link_freq)
651 link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
652
653 ctrls->test_pattern = v4l2_ctrl_new_std_menu_items(hdl, ops,
654 V4L2_CID_TEST_PATTERN,
655 ARRAY_SIZE(test_pattern_menu) - 1,
656 0, 0, test_pattern_menu);
657
658 if (hdl->error) {
659 ret = hdl->error;
660 goto free_ctrls;
661 }
662
663 sensor->sd.ctrl_handler = hdl;
664 return 0;
665
666 free_ctrls:
667 v4l2_ctrl_handler_free(hdl);
668 return ret;
669 }
670
671 #define REGS_ENTRY(a) {(a), ARRAY_SIZE(a)}
672 #define REGS(...) REGS_ENTRY(((const __be16[]){__VA_ARGS__}))
673
674 static const struct initial_reg {
675 const __be16 *data; /* data[0] is register address */
676 unsigned int count;
677 } initial_regs[] = {
678 REGS(be(0x0112), be(0x0808)), /* 8-bit/8-bit mode */
679
680 /* PEDESTAL+2 :+2 is a workaround for 10bit mode +0.5 rounding */
681 REGS(be(0x301E), be(0x00AA)),
682
683 /* corrections_recommended_bayer */
684 REGS(be(0x3042),
685 be(0x0004), /* 3042: RNC: enable b/w rnc mode */
686 be(0x4580)), /* 3044: RNC: enable row noise correction */
687
688 REGS(be(0x30D2),
689 be(0x0000), /* 30D2: CRM/CC: enable crm on Visible and CC rows */
690 be(0x0000), /* 30D4: CC: CC enabled with 16 samples per column */
691 /* 30D6: CC: bw mode enabled/12 bit data resolution/bw mode */
692 be(0x2FFF)),
693
694 REGS(be(0x30DA),
695 be(0x0FFF), /* 30DA: CC: column correction clip level 2 is 0 */
696 be(0x0FFF), /* 30DC: CC: column correction clip level 3 is 0 */
697 be(0x0000)), /* 30DE: CC: Group FPN correction */
698
699 /* RNC: rnc scaling factor = * 54 / 64 (32 / 38 * 64 = 53.9) */
700 REGS(be(0x30EE), be(0x1136)),
701 REGS(be(0x30FA), be(0xFD00)), /* GPIO0 = flash, GPIO1 = shutter */
702 REGS(be(0x3120), be(0x0005)), /* p1 dither enabled for 10bit mode */
703 REGS(be(0x3172), be(0x0206)), /* txlo clk divider options */
704 /* FDOC:fdoc settings with fdoc every frame turned of */
705 REGS(be(0x3180), be(0x9434)),
706
707 REGS(be(0x31B0),
708 be(0x008B), /* 31B0: frame_preamble - FIXME check WRT lanes# */
709 be(0x0050)), /* 31B2: line_preamble - FIXME check WRT lanes# */
710
711 /* don't use continuous clock mode while shut down */
712 REGS(be(0x31BC), be(0x068C)),
713 REGS(be(0x31E0), be(0x0781)), /* Fuse/2DDC: enable 2ddc */
714
715 /* analog_setup_recommended_10bit */
716 REGS(be(0x341A), be(0x4735)), /* Samp&Hold pulse in ADC */
717 REGS(be(0x3420), be(0x4735)), /* Samp&Hold pulse in ADC */
718 REGS(be(0x3426), be(0x8A1A)), /* ADC offset distribution pulse */
719 REGS(be(0x342A), be(0x0018)), /* pulse_config */
720
721 /* pixel_timing_recommended */
722 REGS(be(0x3D00),
723 /* 3D00 */ be(0x043E), be(0x4760), be(0xFFFF), be(0xFFFF),
724 /* 3D08 */ be(0x8000), be(0x0510), be(0xAF08), be(0x0252),
725 /* 3D10 */ be(0x486F), be(0x5D5D), be(0x8056), be(0x8313),
726 /* 3D18 */ be(0x0087), be(0x6A48), be(0x6982), be(0x0280),
727 /* 3D20 */ be(0x8359), be(0x8D02), be(0x8020), be(0x4882),
728 /* 3D28 */ be(0x4269), be(0x6A95), be(0x5988), be(0x5A83),
729 /* 3D30 */ be(0x5885), be(0x6280), be(0x6289), be(0x6097),
730 /* 3D38 */ be(0x5782), be(0x605C), be(0xBF18), be(0x0961),
731 /* 3D40 */ be(0x5080), be(0x2090), be(0x4390), be(0x4382),
732 /* 3D48 */ be(0x5F8A), be(0x5D5D), be(0x9C63), be(0x8063),
733 /* 3D50 */ be(0xA960), be(0x9757), be(0x8260), be(0x5CFF),
734 /* 3D58 */ be(0xBF10), be(0x1681), be(0x0802), be(0x8000),
735 /* 3D60 */ be(0x141C), be(0x6000), be(0x6022), be(0x4D80),
736 /* 3D68 */ be(0x5C97), be(0x6A69), be(0xAC6F), be(0x4645),
737 /* 3D70 */ be(0x4400), be(0x0513), be(0x8069), be(0x6AC6),
738 /* 3D78 */ be(0x5F95), be(0x5F70), be(0x8040), be(0x4A81),
739 /* 3D80 */ be(0x0300), be(0xE703), be(0x0088), be(0x4A83),
740 /* 3D88 */ be(0x40FF), be(0xFFFF), be(0xFD70), be(0x8040),
741 /* 3D90 */ be(0x4A85), be(0x4FA8), be(0x4F8C), be(0x0070),
742 /* 3D98 */ be(0xBE47), be(0x8847), be(0xBC78), be(0x6B89),
743 /* 3DA0 */ be(0x6A80), be(0x6986), be(0x6B8E), be(0x6B80),
744 /* 3DA8 */ be(0x6980), be(0x6A88), be(0x7C9F), be(0x866B),
745 /* 3DB0 */ be(0x8765), be(0x46FF), be(0xE365), be(0xA679),
746 /* 3DB8 */ be(0x4A40), be(0x4580), be(0x44BC), be(0x7000),
747 /* 3DC0 */ be(0x8040), be(0x0802), be(0x10EF), be(0x0104),
748 /* 3DC8 */ be(0x3860), be(0x5D5D), be(0x5682), be(0x1300),
749 /* 3DD0 */ be(0x8648), be(0x8202), be(0x8082), be(0x598A),
750 /* 3DD8 */ be(0x0280), be(0x2048), be(0x3060), be(0x8042),
751 /* 3DE0 */ be(0x9259), be(0x865A), be(0x8258), be(0x8562),
752 /* 3DE8 */ be(0x8062), be(0x8560), be(0x9257), be(0x8221),
753 /* 3DF0 */ be(0x10FF), be(0xB757), be(0x9361), be(0x1019),
754 /* 3DF8 */ be(0x8020), be(0x9043), be(0x8E43), be(0x845F),
755 /* 3E00 */ be(0x835D), be(0x805D), be(0x8163), be(0x8063),
756 /* 3E08 */ be(0xA060), be(0x9157), be(0x8260), be(0x5CFF),
757 /* 3E10 */ be(0xFFFF), be(0xFFE5), be(0x1016), be(0x2048),
758 /* 3E18 */ be(0x0802), be(0x1C60), be(0x0014), be(0x0060),
759 /* 3E20 */ be(0x2205), be(0x8120), be(0x908F), be(0x6A80),
760 /* 3E28 */ be(0x6982), be(0x5F9F), be(0x6F46), be(0x4544),
761 /* 3E30 */ be(0x0005), be(0x8013), be(0x8069), be(0x6A80),
762 /* 3E38 */ be(0x7000), be(0x0000), be(0x0000), be(0x0000),
763 /* 3E40 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
764 /* 3E48 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
765 /* 3E50 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
766 /* 3E58 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
767 /* 3E60 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
768 /* 3E68 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
769 /* 3E70 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
770 /* 3E78 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
771 /* 3E80 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
772 /* 3E88 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
773 /* 3E90 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
774 /* 3E98 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
775 /* 3EA0 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
776 /* 3EA8 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
777 /* 3EB0 */ be(0x0000), be(0x0000), be(0x0000)),
778
779 REGS(be(0x3EB6), be(0x004C)), /* ECL */
780
781 REGS(be(0x3EBA),
782 be(0xAAAD), /* 3EBA */
783 be(0x0086)), /* 3EBC: Bias currents for FSC/ECL */
784
785 REGS(be(0x3EC0),
786 be(0x1E00), /* 3EC0: SFbin/SH mode settings */
787 be(0x100A), /* 3EC2: CLK divider for ramp for 10 bit 400MH */
788 /* 3EC4: FSC clamps for HDR mode and adc comp power down co */
789 be(0x3300),
790 be(0xEA44), /* 3EC6: VLN and clk gating controls */
791 be(0x6F6F), /* 3EC8: Txl0 and Txlo1 settings for normal mode */
792 be(0x2F4A), /* 3ECA: CDAC/Txlo2/RSTGHI/RSTGLO settings */
793 be(0x0506), /* 3ECC: RSTDHI/RSTDLO/CDAC/TXHI settings */
794 /* 3ECE: Ramp buffer settings and Booster enable (bits 0-5) */
795 be(0x203B),
796 be(0x13F0), /* 3ED0: TXLO from atest/sf bin settings */
797 be(0xA53D), /* 3ED2: Ramp offset */
798 be(0x862F), /* 3ED4: TXLO open loop/row driver settings */
799 be(0x4081), /* 3ED6: Txlatch fr cfpn rows/vln bias */
800 be(0x8003), /* 3ED8: Ramp step setting for 10 bit 400 Mhz */
801 be(0xA580), /* 3EDA: Ramp Offset */
802 be(0xC000), /* 3EDC: over range for rst and under range for sig */
803 be(0xC103)), /* 3EDE: over range for sig and col dec clk settings */
804
805 /* corrections_recommended_bayer */
806 REGS(be(0x3F00),
807 be(0x0017), /* 3F00: BM_T0 */
808 be(0x02DD), /* 3F02: BM_T1 */
809 /* 3F04: if Ana_gain less than 2, use noise_floor0, multiply */
810 be(0x0020),
811 /* 3F06: if Ana_gain between 4 and 7, use noise_floor2 and */
812 be(0x0040),
813 /* 3F08: if Ana_gain between 4 and 7, use noise_floor2 and */
814 be(0x0070),
815 /* 3F0A: Define noise_floor0(low address) and noise_floor1 */
816 be(0x0101),
817 be(0x0302)), /* 3F0C: Define noise_floor2 and noise_floor3 */
818
819 REGS(be(0x3F10),
820 be(0x0505), /* 3F10: single k factor 0 */
821 be(0x0505), /* 3F12: single k factor 1 */
822 be(0x0505), /* 3F14: single k factor 2 */
823 be(0x01FF), /* 3F16: cross factor 0 */
824 be(0x01FF), /* 3F18: cross factor 1 */
825 be(0x01FF), /* 3F1A: cross factor 2 */
826 be(0x0022)), /* 3F1E */
827
828 /* GTH_THRES_RTN: 4max,4min filtered out of every 46 samples and */
829 REGS(be(0x3F2C), be(0x442E)),
830
831 REGS(be(0x3F3E),
832 be(0x0000), /* 3F3E: Switch ADC from 12 bit to 10 bit mode */
833 be(0x1511), /* 3F40: couple k factor 0 */
834 be(0x1511), /* 3F42: couple k factor 1 */
835 be(0x0707)), /* 3F44: couple k factor 2 */
836 };
837
838 static void __ar0521_power_off(struct device *dev)
839 {
840 struct v4l2_subdev *sd = dev_get_drvdata(dev);
841 struct ar0521_dev *sensor = to_ar0521_dev(sd);
842 int i;
843
844 if (sensor->reset_gpio)
845 /* assert RESET signal */
846 gpiod_set_value_cansleep(sensor->reset_gpio, 1);
847
848 for (i = ARRAY_SIZE(ar0521_supply_names) - 1; i >= 0; i--) {
849 if (sensor->supplies[i])
850 regulator_disable(sensor->supplies[i]);
851 }
852 }
853
854 static int ar0521_power_off(struct device *dev)
855 {
856 struct v4l2_subdev *sd = dev_get_drvdata(dev);
857 struct ar0521_dev *sensor = to_ar0521_dev(sd);
858
859 clk_disable_unprepare(sensor->extclk);
860 __ar0521_power_off(dev);
861
862 return 0;
863 }
864
865 static int ar0521_power_on(struct device *dev)
866 {
867 struct v4l2_subdev *sd = dev_get_drvdata(dev);
868 struct ar0521_dev *sensor = to_ar0521_dev(sd);
869 unsigned int cnt;
870 int ret;
871
872 for (cnt = 0; cnt < ARRAY_SIZE(ar0521_supply_names); cnt++)
873 if (sensor->supplies[cnt]) {
874 ret = regulator_enable(sensor->supplies[cnt]);
875 if (ret < 0)
876 goto off;
877
878 usleep_range(1000, 1500); /* min 1 ms */
879 }
880
881 ret = clk_prepare_enable(sensor->extclk);
882 if (ret < 0) {
883 v4l2_err(&sensor->sd, "error enabling sensor clock\n");
884 goto off;
885 }
886 usleep_range(1000, 1500); /* min 1 ms */
887
888 if (sensor->reset_gpio)
889 /* deassert RESET signal */
890 gpiod_set_value_cansleep(sensor->reset_gpio, 0);
891 usleep_range(4500, 5000); /* min 45000 clocks */
892
893 for (cnt = 0; cnt < ARRAY_SIZE(initial_regs); cnt++) {
894 ret = ar0521_write_regs(sensor, initial_regs[cnt].data,
895 initial_regs[cnt].count);
896 if (ret)
897 goto off;
898 }
899
900 ret = ar0521_write_reg(sensor, AR0521_REG_SERIAL_FORMAT,
901 AR0521_REG_SERIAL_FORMAT_MIPI |
902 sensor->lane_count);
903 if (ret)
904 goto off;
905
906 /* set MIPI test mode - disabled for now */
907 ret = ar0521_write_reg(sensor, AR0521_REG_HISPI_TEST_MODE,
908 ((0x40 << sensor->lane_count) - 0x40) |
909 AR0521_REG_HISPI_TEST_MODE_LP11);
910 if (ret)
911 goto off;
912
913 ret = ar0521_write_reg(sensor, AR0521_REG_ROW_SPEED, 0x110 |
914 4 / sensor->lane_count);
915 if (ret)
916 goto off;
917
918 return 0;
919 off:
920 clk_disable_unprepare(sensor->extclk);
921 __ar0521_power_off(dev);
922 return ret;
923 }
924
925 static int ar0521_enum_mbus_code(struct v4l2_subdev *sd,
926 struct v4l2_subdev_state *sd_state,
927 struct v4l2_subdev_mbus_code_enum *code)
928 {
929 struct ar0521_dev *sensor = to_ar0521_dev(sd);
930
931 if (code->index)
932 return -EINVAL;
933
934 code->code = sensor->fmt.code;
935 return 0;
936 }
937
938 static int ar0521_enum_frame_size(struct v4l2_subdev *sd,
939 struct v4l2_subdev_state *sd_state,
940 struct v4l2_subdev_frame_size_enum *fse)
941 {
942 if (fse->index)
943 return -EINVAL;
944
945 if (fse->code != MEDIA_BUS_FMT_SGRBG8_1X8)
946 return -EINVAL;
947
948 fse->min_width = AR0521_WIDTH_MIN;
949 fse->max_width = AR0521_WIDTH_MAX;
950 fse->min_height = AR0521_HEIGHT_MIN;
951 fse->max_height = AR0521_HEIGHT_MAX;
952
953 return 0;
954 }
955
956 static int ar0521_pre_streamon(struct v4l2_subdev *sd, u32 flags)
957 {
958 struct ar0521_dev *sensor = to_ar0521_dev(sd);
959 int ret;
960
961 if (!(flags & V4L2_SUBDEV_PRE_STREAMON_FL_MANUAL_LP))
962 return -EACCES;
963
964 ret = pm_runtime_resume_and_get(&sensor->i2c_client->dev);
965 if (ret < 0)
966 return ret;
967
968 /* Set LP-11 on clock and data lanes */
969 ret = ar0521_write_reg(sensor, AR0521_REG_HISPI_CONTROL_STATUS,
970 AR0521_REG_HISPI_CONTROL_STATUS_FRAMER_TEST_MODE_ENABLE);
971 if (ret)
972 goto err;
973
974 /* Start streaming LP-11 */
975 ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
976 AR0521_REG_RESET_DEFAULTS |
977 AR0521_REG_RESET_STREAM);
978 if (ret)
979 goto err;
980 return 0;
981
982 err:
983 pm_runtime_put(&sensor->i2c_client->dev);
984 return ret;
985 }
986
987 static int ar0521_post_streamoff(struct v4l2_subdev *sd)
988 {
989 struct ar0521_dev *sensor = to_ar0521_dev(sd);
990
991 pm_runtime_put(&sensor->i2c_client->dev);
992 return 0;
993 }
994
995 static int ar0521_s_stream(struct v4l2_subdev *sd, int enable)
996 {
997 struct ar0521_dev *sensor = to_ar0521_dev(sd);
998 int ret;
999
1000 mutex_lock(&sensor->lock);
1001 ret = ar0521_set_stream(sensor, enable);
1002 mutex_unlock(&sensor->lock);
1003
1004 return ret;
1005 }
1006
1007 static const struct v4l2_subdev_core_ops ar0521_core_ops = {
1008 .log_status = v4l2_ctrl_subdev_log_status,
1009 };
1010
1011 static const struct v4l2_subdev_video_ops ar0521_video_ops = {
1012 .s_stream = ar0521_s_stream,
1013 .pre_streamon = ar0521_pre_streamon,
1014 .post_streamoff = ar0521_post_streamoff,
1015 };
1016
1017 static const struct v4l2_subdev_pad_ops ar0521_pad_ops = {
1018 .enum_mbus_code = ar0521_enum_mbus_code,
1019 .enum_frame_size = ar0521_enum_frame_size,
1020 .get_fmt = ar0521_get_fmt,
1021 .set_fmt = ar0521_set_fmt,
1022 };
1023
1024 static const struct v4l2_subdev_ops ar0521_subdev_ops = {
1025 .core = &ar0521_core_ops,
1026 .video = &ar0521_video_ops,
1027 .pad = &ar0521_pad_ops,
1028 };
1029
1030 static int ar0521_probe(struct i2c_client *client)
1031 {
1032 struct v4l2_fwnode_endpoint ep = {
1033 .bus_type = V4L2_MBUS_CSI2_DPHY
1034 };
1035 struct device *dev = &client->dev;
1036 struct fwnode_handle *endpoint;
1037 struct ar0521_dev *sensor;
1038 unsigned int cnt;
1039 int ret;
1040
1041 sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
1042 if (!sensor)
1043 return -ENOMEM;
1044
1045 sensor->i2c_client = client;
1046 sensor->fmt.width = AR0521_WIDTH_MAX;
1047 sensor->fmt.height = AR0521_HEIGHT_MAX;
1048
1049 endpoint = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0,
1050 FWNODE_GRAPH_ENDPOINT_NEXT);
1051 if (!endpoint) {
1052 dev_err(dev, "endpoint node not found\n");
1053 return -EINVAL;
1054 }
1055
1056 ret = v4l2_fwnode_endpoint_parse(endpoint, &ep);
1057 fwnode_handle_put(endpoint);
1058 if (ret) {
1059 dev_err(dev, "could not parse endpoint\n");
1060 return ret;
1061 }
1062
1063 if (ep.bus_type != V4L2_MBUS_CSI2_DPHY) {
1064 dev_err(dev, "invalid bus type, must be MIPI CSI2\n");
1065 return -EINVAL;
1066 }
1067
1068 sensor->lane_count = ep.bus.mipi_csi2.num_data_lanes;
1069 switch (sensor->lane_count) {
1070 case 1:
1071 case 2:
1072 case 4:
1073 break;
1074 default:
1075 dev_err(dev, "invalid number of MIPI data lanes\n");
1076 return -EINVAL;
1077 }
1078
1079 /* Get master clock (extclk) */
1080 sensor->extclk = devm_clk_get(dev, "extclk");
1081 if (IS_ERR(sensor->extclk)) {
1082 dev_err(dev, "failed to get extclk\n");
1083 return PTR_ERR(sensor->extclk);
1084 }
1085
1086 sensor->extclk_freq = clk_get_rate(sensor->extclk);
1087
1088 if (sensor->extclk_freq < AR0521_EXTCLK_MIN ||
1089 sensor->extclk_freq > AR0521_EXTCLK_MAX) {
1090 dev_err(dev, "extclk frequency out of range: %u Hz\n",
1091 sensor->extclk_freq);
1092 return -EINVAL;
1093 }
1094
1095 /* Request optional reset pin (usually active low) and assert it */
1096 sensor->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1097 GPIOD_OUT_HIGH);
1098
1099 v4l2_i2c_subdev_init(&sensor->sd, client, &ar0521_subdev_ops);
1100
1101 sensor->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
1102 sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
1103 sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1104 ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad);
1105 if (ret)
1106 return ret;
1107
1108 for (cnt = 0; cnt < ARRAY_SIZE(ar0521_supply_names); cnt++) {
1109 struct regulator *supply = devm_regulator_get(dev,
1110 ar0521_supply_names[cnt]);
1111
1112 if (IS_ERR(supply)) {
1113 dev_info(dev, "no %s regulator found: %li\n",
1114 ar0521_supply_names[cnt], PTR_ERR(supply));
1115 return PTR_ERR(supply);
1116 }
1117 sensor->supplies[cnt] = supply;
1118 }
1119
1120 mutex_init(&sensor->lock);
1121
1122 ret = ar0521_init_controls(sensor);
1123 if (ret)
1124 goto entity_cleanup;
1125
1126 ar0521_adj_fmt(&sensor->fmt);
1127
1128 ret = v4l2_async_register_subdev(&sensor->sd);
1129 if (ret)
1130 goto free_ctrls;
1131
1132 /* Turn on the device and enable runtime PM */
1133 ret = ar0521_power_on(&client->dev);
1134 if (ret)
1135 goto disable;
1136 pm_runtime_set_active(&client->dev);
1137 pm_runtime_enable(&client->dev);
1138 pm_runtime_idle(&client->dev);
1139 return 0;
1140
1141 disable:
1142 v4l2_async_unregister_subdev(&sensor->sd);
1143 media_entity_cleanup(&sensor->sd.entity);
1144 free_ctrls:
1145 v4l2_ctrl_handler_free(&sensor->ctrls.handler);
1146 entity_cleanup:
1147 media_entity_cleanup(&sensor->sd.entity);
1148 mutex_destroy(&sensor->lock);
1149 return ret;
1150 }
1151
1152 static void ar0521_remove(struct i2c_client *client)
1153 {
1154 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1155 struct ar0521_dev *sensor = to_ar0521_dev(sd);
1156
1157 v4l2_async_unregister_subdev(&sensor->sd);
1158 media_entity_cleanup(&sensor->sd.entity);
1159 v4l2_ctrl_handler_free(&sensor->ctrls.handler);
1160 pm_runtime_disable(&client->dev);
1161 if (!pm_runtime_status_suspended(&client->dev))
1162 ar0521_power_off(&client->dev);
1163 pm_runtime_set_suspended(&client->dev);
1164 mutex_destroy(&sensor->lock);
1165 }
1166
1167 static const struct dev_pm_ops ar0521_pm_ops = {
1168 SET_RUNTIME_PM_OPS(ar0521_power_off, ar0521_power_on, NULL)
1169 };
1170 static const struct of_device_id ar0521_dt_ids[] = {
1171 {.compatible = "onnn,ar0521"},
1172 {}
1173 };
1174 MODULE_DEVICE_TABLE(of, ar0521_dt_ids);
1175
1176 static struct i2c_driver ar0521_i2c_driver = {
1177 .driver = {
1178 .name = "ar0521",
1179 .pm = &ar0521_pm_ops,
1180 .of_match_table = ar0521_dt_ids,
1181 },
1182 .probe = ar0521_probe,
1183 .remove = ar0521_remove,
1184 };
1185
1186 module_i2c_driver(ar0521_i2c_driver);
1187
1188 MODULE_DESCRIPTION("AR0521 MIPI Camera subdev driver");
1189 MODULE_AUTHOR("Krzysztof Hałasa <khalasa@piap.pl>");
1190 MODULE_LICENSE("GPL");
Kernel DRM miscellaneous fixes and cross-tree changes