Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / media / i2c / imx219.c
blob2d54cea113e19f68e1553ffb2e4c78491dc80acf
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * A V4L2 driver for Sony IMX219 cameras.
4 * Copyright (C) 2019, Raspberry Pi (Trading) Ltd
6 * Based on Sony imx258 camera driver
7 * Copyright (C) 2018 Intel Corporation
9 * DT / fwnode changes, and regulator / GPIO control taken from imx214 driver
10 * Copyright 2018 Qtechnology A/S
12 * Flip handling taken from the Sony IMX319 driver.
13 * Copyright (C) 2018 Intel Corporation
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/i2c.h>
21 #include <linux/minmax.h>
22 #include <linux/module.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regulator/consumer.h>
26 #include <media/v4l2-cci.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-fwnode.h>
30 #include <media/v4l2-mediabus.h>
32 /* Chip ID */
33 #define IMX219_REG_CHIP_ID CCI_REG16(0x0000)
34 #define IMX219_CHIP_ID 0x0219
36 #define IMX219_REG_MODE_SELECT CCI_REG8(0x0100)
37 #define IMX219_MODE_STANDBY 0x00
38 #define IMX219_MODE_STREAMING 0x01
40 #define IMX219_REG_CSI_LANE_MODE CCI_REG8(0x0114)
41 #define IMX219_CSI_2_LANE_MODE 0x01
42 #define IMX219_CSI_4_LANE_MODE 0x03
44 #define IMX219_REG_DPHY_CTRL CCI_REG8(0x0128)
45 #define IMX219_DPHY_CTRL_TIMING_AUTO 0
46 #define IMX219_DPHY_CTRL_TIMING_MANUAL 1
48 #define IMX219_REG_EXCK_FREQ CCI_REG16(0x012a)
49 #define IMX219_EXCK_FREQ(n) ((n) * 256) /* n expressed in MHz */
51 /* Analog gain control */
52 #define IMX219_REG_ANALOG_GAIN CCI_REG8(0x0157)
53 #define IMX219_ANA_GAIN_MIN 0
54 #define IMX219_ANA_GAIN_MAX 232
55 #define IMX219_ANA_GAIN_STEP 1
56 #define IMX219_ANA_GAIN_DEFAULT 0x0
58 /* Digital gain control */
59 #define IMX219_REG_DIGITAL_GAIN CCI_REG16(0x0158)
60 #define IMX219_DGTL_GAIN_MIN 0x0100
61 #define IMX219_DGTL_GAIN_MAX 0x0fff
62 #define IMX219_DGTL_GAIN_DEFAULT 0x0100
63 #define IMX219_DGTL_GAIN_STEP 1
65 /* Exposure control */
66 #define IMX219_REG_EXPOSURE CCI_REG16(0x015a)
67 #define IMX219_EXPOSURE_MIN 4
68 #define IMX219_EXPOSURE_STEP 1
69 #define IMX219_EXPOSURE_DEFAULT 0x640
70 #define IMX219_EXPOSURE_MAX 65535
72 /* V_TIMING internal */
73 #define IMX219_REG_VTS CCI_REG16(0x0160)
74 #define IMX219_VTS_MAX 0xffff
76 #define IMX219_VBLANK_MIN 4
78 /* HBLANK control - read only */
79 #define IMX219_PPL_DEFAULT 3448
81 #define IMX219_REG_LINE_LENGTH_A CCI_REG16(0x0162)
82 #define IMX219_REG_X_ADD_STA_A CCI_REG16(0x0164)
83 #define IMX219_REG_X_ADD_END_A CCI_REG16(0x0166)
84 #define IMX219_REG_Y_ADD_STA_A CCI_REG16(0x0168)
85 #define IMX219_REG_Y_ADD_END_A CCI_REG16(0x016a)
86 #define IMX219_REG_X_OUTPUT_SIZE CCI_REG16(0x016c)
87 #define IMX219_REG_Y_OUTPUT_SIZE CCI_REG16(0x016e)
88 #define IMX219_REG_X_ODD_INC_A CCI_REG8(0x0170)
89 #define IMX219_REG_Y_ODD_INC_A CCI_REG8(0x0171)
90 #define IMX219_REG_ORIENTATION CCI_REG8(0x0172)
92 /* Binning Mode */
93 #define IMX219_REG_BINNING_MODE_H CCI_REG8(0x0174)
94 #define IMX219_REG_BINNING_MODE_V CCI_REG8(0x0175)
95 #define IMX219_BINNING_NONE 0x00
96 #define IMX219_BINNING_X2 0x01
97 #define IMX219_BINNING_X2_ANALOG 0x03
99 #define IMX219_REG_CSI_DATA_FORMAT_A CCI_REG16(0x018c)
101 /* PLL Settings */
102 #define IMX219_REG_VTPXCK_DIV CCI_REG8(0x0301)
103 #define IMX219_REG_VTSYCK_DIV CCI_REG8(0x0303)
104 #define IMX219_REG_PREPLLCK_VT_DIV CCI_REG8(0x0304)
105 #define IMX219_REG_PREPLLCK_OP_DIV CCI_REG8(0x0305)
106 #define IMX219_REG_PLL_VT_MPY CCI_REG16(0x0306)
107 #define IMX219_REG_OPPXCK_DIV CCI_REG8(0x0309)
108 #define IMX219_REG_OPSYCK_DIV CCI_REG8(0x030b)
109 #define IMX219_REG_PLL_OP_MPY CCI_REG16(0x030c)
111 /* Test Pattern Control */
112 #define IMX219_REG_TEST_PATTERN CCI_REG16(0x0600)
113 #define IMX219_TEST_PATTERN_DISABLE 0
114 #define IMX219_TEST_PATTERN_SOLID_COLOR 1
115 #define IMX219_TEST_PATTERN_COLOR_BARS 2
116 #define IMX219_TEST_PATTERN_GREY_COLOR 3
117 #define IMX219_TEST_PATTERN_PN9 4
119 /* Test pattern colour components */
120 #define IMX219_REG_TESTP_RED CCI_REG16(0x0602)
121 #define IMX219_REG_TESTP_GREENR CCI_REG16(0x0604)
122 #define IMX219_REG_TESTP_BLUE CCI_REG16(0x0606)
123 #define IMX219_REG_TESTP_GREENB CCI_REG16(0x0608)
124 #define IMX219_TESTP_COLOUR_MIN 0
125 #define IMX219_TESTP_COLOUR_MAX 0x03ff
126 #define IMX219_TESTP_COLOUR_STEP 1
128 #define IMX219_REG_TP_WINDOW_WIDTH CCI_REG16(0x0624)
129 #define IMX219_REG_TP_WINDOW_HEIGHT CCI_REG16(0x0626)
131 /* External clock frequency is 24.0M */
132 #define IMX219_XCLK_FREQ 24000000
134 /* Pixel rate is fixed for all the modes */
135 #define IMX219_PIXEL_RATE 182400000
136 #define IMX219_PIXEL_RATE_4LANE 280800000
138 #define IMX219_DEFAULT_LINK_FREQ 456000000
139 #define IMX219_DEFAULT_LINK_FREQ_4LANE 363000000
141 /* IMX219 native and active pixel array size. */
142 #define IMX219_NATIVE_WIDTH 3296U
143 #define IMX219_NATIVE_HEIGHT 2480U
144 #define IMX219_PIXEL_ARRAY_LEFT 8U
145 #define IMX219_PIXEL_ARRAY_TOP 8U
146 #define IMX219_PIXEL_ARRAY_WIDTH 3280U
147 #define IMX219_PIXEL_ARRAY_HEIGHT 2464U
149 /* Mode : resolution and related config&values */
150 struct imx219_mode {
151 /* Frame width */
152 unsigned int width;
153 /* Frame height */
154 unsigned int height;
156 /* V-timing */
157 unsigned int vts_def;
160 static const struct cci_reg_sequence imx219_common_regs[] = {
161 { IMX219_REG_MODE_SELECT, 0x00 }, /* Mode Select */
163 /* To Access Addresses 3000-5fff, send the following commands */
164 { CCI_REG8(0x30eb), 0x05 },
165 { CCI_REG8(0x30eb), 0x0c },
166 { CCI_REG8(0x300a), 0xff },
167 { CCI_REG8(0x300b), 0xff },
168 { CCI_REG8(0x30eb), 0x05 },
169 { CCI_REG8(0x30eb), 0x09 },
171 /* PLL Clock Table */
172 { IMX219_REG_VTPXCK_DIV, 5 },
173 { IMX219_REG_VTSYCK_DIV, 1 },
174 { IMX219_REG_PREPLLCK_VT_DIV, 3 }, /* 0x03 = AUTO set */
175 { IMX219_REG_PREPLLCK_OP_DIV, 3 }, /* 0x03 = AUTO set */
176 { IMX219_REG_PLL_VT_MPY, 57 },
177 { IMX219_REG_OPSYCK_DIV, 1 },
178 { IMX219_REG_PLL_OP_MPY, 114 },
180 /* Undocumented registers */
181 { CCI_REG8(0x455e), 0x00 },
182 { CCI_REG8(0x471e), 0x4b },
183 { CCI_REG8(0x4767), 0x0f },
184 { CCI_REG8(0x4750), 0x14 },
185 { CCI_REG8(0x4540), 0x00 },
186 { CCI_REG8(0x47b4), 0x14 },
187 { CCI_REG8(0x4713), 0x30 },
188 { CCI_REG8(0x478b), 0x10 },
189 { CCI_REG8(0x478f), 0x10 },
190 { CCI_REG8(0x4793), 0x10 },
191 { CCI_REG8(0x4797), 0x0e },
192 { CCI_REG8(0x479b), 0x0e },
194 /* Frame Bank Register Group "A" */
195 { IMX219_REG_LINE_LENGTH_A, 3448 },
196 { IMX219_REG_X_ODD_INC_A, 1 },
197 { IMX219_REG_Y_ODD_INC_A, 1 },
199 /* Output setup registers */
200 { IMX219_REG_DPHY_CTRL, IMX219_DPHY_CTRL_TIMING_AUTO },
201 { IMX219_REG_EXCK_FREQ, IMX219_EXCK_FREQ(IMX219_XCLK_FREQ / 1000000) },
204 static const s64 imx219_link_freq_menu[] = {
205 IMX219_DEFAULT_LINK_FREQ,
208 static const s64 imx219_link_freq_4lane_menu[] = {
209 IMX219_DEFAULT_LINK_FREQ_4LANE,
212 static const char * const imx219_test_pattern_menu[] = {
213 "Disabled",
214 "Color Bars",
215 "Solid Color",
216 "Grey Color Bars",
217 "PN9"
220 static const int imx219_test_pattern_val[] = {
221 IMX219_TEST_PATTERN_DISABLE,
222 IMX219_TEST_PATTERN_COLOR_BARS,
223 IMX219_TEST_PATTERN_SOLID_COLOR,
224 IMX219_TEST_PATTERN_GREY_COLOR,
225 IMX219_TEST_PATTERN_PN9,
228 /* regulator supplies */
229 static const char * const imx219_supply_name[] = {
230 /* Supplies can be enabled in any order */
231 "VANA", /* Analog (2.8V) supply */
232 "VDIG", /* Digital Core (1.8V) supply */
233 "VDDL", /* IF (1.2V) supply */
236 #define IMX219_NUM_SUPPLIES ARRAY_SIZE(imx219_supply_name)
239 * The supported formats.
240 * This table MUST contain 4 entries per format, to cover the various flip
241 * combinations in the order
242 * - no flip
243 * - h flip
244 * - v flip
245 * - h&v flips
247 static const u32 imx219_mbus_formats[] = {
248 MEDIA_BUS_FMT_SRGGB10_1X10,
249 MEDIA_BUS_FMT_SGRBG10_1X10,
250 MEDIA_BUS_FMT_SGBRG10_1X10,
251 MEDIA_BUS_FMT_SBGGR10_1X10,
253 MEDIA_BUS_FMT_SRGGB8_1X8,
254 MEDIA_BUS_FMT_SGRBG8_1X8,
255 MEDIA_BUS_FMT_SGBRG8_1X8,
256 MEDIA_BUS_FMT_SBGGR8_1X8,
260 * Initialisation delay between XCLR low->high and the moment when the sensor
261 * can start capture (i.e. can leave software stanby) must be not less than:
262 * t4 + max(t5, t6 + <time to initialize the sensor register over I2C>)
263 * where
264 * t4 is fixed, and is max 200uS,
265 * t5 is fixed, and is 6000uS,
266 * t6 depends on the sensor external clock, and is max 32000 clock periods.
267 * As per sensor datasheet, the external clock must be from 6MHz to 27MHz.
268 * So for any acceptable external clock t6 is always within the range of
269 * 1185 to 5333 uS, and is always less than t5.
270 * For this reason this is always safe to wait (t4 + t5) = 6200 uS, then
271 * initialize the sensor over I2C, and then exit the software standby.
273 * This start-up time can be optimized a bit more, if we start the writes
274 * over I2C after (t4+t6), but before (t4+t5) expires. But then sensor
275 * initialization over I2C may complete before (t4+t5) expires, and we must
276 * ensure that capture is not started before (t4+t5).
278 * This delay doesn't account for the power supply startup time. If needed,
279 * this should be taken care of via the regulator framework. E.g. in the
280 * case of DT for regulator-fixed one should define the startup-delay-us
281 * property.
283 #define IMX219_XCLR_MIN_DELAY_US 6200
284 #define IMX219_XCLR_DELAY_RANGE_US 1000
286 /* Mode configs */
287 static const struct imx219_mode supported_modes[] = {
289 /* 8MPix 15fps mode */
290 .width = 3280,
291 .height = 2464,
292 .vts_def = 3526,
295 /* 1080P 30fps cropped */
296 .width = 1920,
297 .height = 1080,
298 .vts_def = 1763,
301 /* 2x2 binned 30fps mode */
302 .width = 1640,
303 .height = 1232,
304 .vts_def = 1763,
307 /* 640x480 30fps mode */
308 .width = 640,
309 .height = 480,
310 .vts_def = 1763,
314 struct imx219 {
315 struct v4l2_subdev sd;
316 struct media_pad pad;
318 struct regmap *regmap;
319 struct clk *xclk; /* system clock to IMX219 */
320 u32 xclk_freq;
322 struct gpio_desc *reset_gpio;
323 struct regulator_bulk_data supplies[IMX219_NUM_SUPPLIES];
325 struct v4l2_ctrl_handler ctrl_handler;
326 /* V4L2 Controls */
327 struct v4l2_ctrl *pixel_rate;
328 struct v4l2_ctrl *link_freq;
329 struct v4l2_ctrl *exposure;
330 struct v4l2_ctrl *vflip;
331 struct v4l2_ctrl *hflip;
332 struct v4l2_ctrl *vblank;
333 struct v4l2_ctrl *hblank;
335 /* Two or Four lanes */
336 u8 lanes;
339 static inline struct imx219 *to_imx219(struct v4l2_subdev *_sd)
341 return container_of(_sd, struct imx219, sd);
344 /* Get bayer order based on flip setting. */
345 static u32 imx219_get_format_code(struct imx219 *imx219, u32 code)
347 unsigned int i;
349 for (i = 0; i < ARRAY_SIZE(imx219_mbus_formats); i++)
350 if (imx219_mbus_formats[i] == code)
351 break;
353 if (i >= ARRAY_SIZE(imx219_mbus_formats))
354 i = 0;
356 i = (i & ~3) | (imx219->vflip->val ? 2 : 0) |
357 (imx219->hflip->val ? 1 : 0);
359 return imx219_mbus_formats[i];
362 /* -----------------------------------------------------------------------------
363 * Controls
366 static int imx219_set_ctrl(struct v4l2_ctrl *ctrl)
368 struct imx219 *imx219 =
369 container_of(ctrl->handler, struct imx219, ctrl_handler);
370 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
371 const struct v4l2_mbus_framefmt *format;
372 struct v4l2_subdev_state *state;
373 int ret = 0;
375 state = v4l2_subdev_get_locked_active_state(&imx219->sd);
376 format = v4l2_subdev_state_get_format(state, 0);
378 if (ctrl->id == V4L2_CID_VBLANK) {
379 int exposure_max, exposure_def;
381 /* Update max exposure while meeting expected vblanking */
382 exposure_max = format->height + ctrl->val - 4;
383 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
384 exposure_max : IMX219_EXPOSURE_DEFAULT;
385 __v4l2_ctrl_modify_range(imx219->exposure,
386 imx219->exposure->minimum,
387 exposure_max, imx219->exposure->step,
388 exposure_def);
392 * Applying V4L2 control value only happens
393 * when power is up for streaming
395 if (pm_runtime_get_if_in_use(&client->dev) == 0)
396 return 0;
398 switch (ctrl->id) {
399 case V4L2_CID_ANALOGUE_GAIN:
400 cci_write(imx219->regmap, IMX219_REG_ANALOG_GAIN,
401 ctrl->val, &ret);
402 break;
403 case V4L2_CID_EXPOSURE:
404 cci_write(imx219->regmap, IMX219_REG_EXPOSURE,
405 ctrl->val, &ret);
406 break;
407 case V4L2_CID_DIGITAL_GAIN:
408 cci_write(imx219->regmap, IMX219_REG_DIGITAL_GAIN,
409 ctrl->val, &ret);
410 break;
411 case V4L2_CID_TEST_PATTERN:
412 cci_write(imx219->regmap, IMX219_REG_TEST_PATTERN,
413 imx219_test_pattern_val[ctrl->val], &ret);
414 break;
415 case V4L2_CID_HFLIP:
416 case V4L2_CID_VFLIP:
417 cci_write(imx219->regmap, IMX219_REG_ORIENTATION,
418 imx219->hflip->val | imx219->vflip->val << 1, &ret);
419 break;
420 case V4L2_CID_VBLANK:
421 cci_write(imx219->regmap, IMX219_REG_VTS,
422 format->height + ctrl->val, &ret);
423 break;
424 case V4L2_CID_TEST_PATTERN_RED:
425 cci_write(imx219->regmap, IMX219_REG_TESTP_RED,
426 ctrl->val, &ret);
427 break;
428 case V4L2_CID_TEST_PATTERN_GREENR:
429 cci_write(imx219->regmap, IMX219_REG_TESTP_GREENR,
430 ctrl->val, &ret);
431 break;
432 case V4L2_CID_TEST_PATTERN_BLUE:
433 cci_write(imx219->regmap, IMX219_REG_TESTP_BLUE,
434 ctrl->val, &ret);
435 break;
436 case V4L2_CID_TEST_PATTERN_GREENB:
437 cci_write(imx219->regmap, IMX219_REG_TESTP_GREENB,
438 ctrl->val, &ret);
439 break;
440 default:
441 dev_info(&client->dev,
442 "ctrl(id:0x%x,val:0x%x) is not handled\n",
443 ctrl->id, ctrl->val);
444 ret = -EINVAL;
445 break;
448 pm_runtime_put(&client->dev);
450 return ret;
453 static const struct v4l2_ctrl_ops imx219_ctrl_ops = {
454 .s_ctrl = imx219_set_ctrl,
457 static unsigned long imx219_get_pixel_rate(struct imx219 *imx219)
459 return (imx219->lanes == 2) ? IMX219_PIXEL_RATE : IMX219_PIXEL_RATE_4LANE;
462 /* Initialize control handlers */
463 static int imx219_init_controls(struct imx219 *imx219)
465 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
466 const struct imx219_mode *mode = &supported_modes[0];
467 struct v4l2_ctrl_handler *ctrl_hdlr;
468 struct v4l2_fwnode_device_properties props;
469 int exposure_max, exposure_def, hblank;
470 int i, ret;
472 ctrl_hdlr = &imx219->ctrl_handler;
473 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 12);
474 if (ret)
475 return ret;
477 /* By default, PIXEL_RATE is read only */
478 imx219->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
479 V4L2_CID_PIXEL_RATE,
480 imx219_get_pixel_rate(imx219),
481 imx219_get_pixel_rate(imx219), 1,
482 imx219_get_pixel_rate(imx219));
484 imx219->link_freq =
485 v4l2_ctrl_new_int_menu(ctrl_hdlr, &imx219_ctrl_ops,
486 V4L2_CID_LINK_FREQ,
487 ARRAY_SIZE(imx219_link_freq_menu) - 1, 0,
488 (imx219->lanes == 2) ? imx219_link_freq_menu :
489 imx219_link_freq_4lane_menu);
490 if (imx219->link_freq)
491 imx219->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
493 /* Initial vblank/hblank/exposure parameters based on current mode */
494 imx219->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
495 V4L2_CID_VBLANK, IMX219_VBLANK_MIN,
496 IMX219_VTS_MAX - mode->height, 1,
497 mode->vts_def - mode->height);
498 hblank = IMX219_PPL_DEFAULT - mode->width;
499 imx219->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
500 V4L2_CID_HBLANK, hblank, hblank,
501 1, hblank);
502 if (imx219->hblank)
503 imx219->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
504 exposure_max = mode->vts_def - 4;
505 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
506 exposure_max : IMX219_EXPOSURE_DEFAULT;
507 imx219->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
508 V4L2_CID_EXPOSURE,
509 IMX219_EXPOSURE_MIN, exposure_max,
510 IMX219_EXPOSURE_STEP,
511 exposure_def);
513 v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
514 IMX219_ANA_GAIN_MIN, IMX219_ANA_GAIN_MAX,
515 IMX219_ANA_GAIN_STEP, IMX219_ANA_GAIN_DEFAULT);
517 v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
518 IMX219_DGTL_GAIN_MIN, IMX219_DGTL_GAIN_MAX,
519 IMX219_DGTL_GAIN_STEP, IMX219_DGTL_GAIN_DEFAULT);
521 imx219->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
522 V4L2_CID_HFLIP, 0, 1, 1, 0);
523 if (imx219->hflip)
524 imx219->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
526 imx219->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
527 V4L2_CID_VFLIP, 0, 1, 1, 0);
528 if (imx219->vflip)
529 imx219->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
531 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx219_ctrl_ops,
532 V4L2_CID_TEST_PATTERN,
533 ARRAY_SIZE(imx219_test_pattern_menu) - 1,
534 0, 0, imx219_test_pattern_menu);
535 for (i = 0; i < 4; i++) {
537 * The assumption is that
538 * V4L2_CID_TEST_PATTERN_GREENR == V4L2_CID_TEST_PATTERN_RED + 1
539 * V4L2_CID_TEST_PATTERN_BLUE == V4L2_CID_TEST_PATTERN_RED + 2
540 * V4L2_CID_TEST_PATTERN_GREENB == V4L2_CID_TEST_PATTERN_RED + 3
542 v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
543 V4L2_CID_TEST_PATTERN_RED + i,
544 IMX219_TESTP_COLOUR_MIN,
545 IMX219_TESTP_COLOUR_MAX,
546 IMX219_TESTP_COLOUR_STEP,
547 IMX219_TESTP_COLOUR_MAX);
548 /* The "Solid color" pattern is white by default */
551 if (ctrl_hdlr->error) {
552 ret = ctrl_hdlr->error;
553 dev_err_probe(&client->dev, ret, "Control init failed\n");
554 goto error;
557 ret = v4l2_fwnode_device_parse(&client->dev, &props);
558 if (ret)
559 goto error;
561 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx219_ctrl_ops,
562 &props);
563 if (ret)
564 goto error;
566 imx219->sd.ctrl_handler = ctrl_hdlr;
568 return 0;
570 error:
571 v4l2_ctrl_handler_free(ctrl_hdlr);
573 return ret;
576 static void imx219_free_controls(struct imx219 *imx219)
578 v4l2_ctrl_handler_free(imx219->sd.ctrl_handler);
581 /* -----------------------------------------------------------------------------
582 * Subdev operations
585 static int imx219_set_framefmt(struct imx219 *imx219,
586 struct v4l2_subdev_state *state)
588 const struct v4l2_mbus_framefmt *format;
589 const struct v4l2_rect *crop;
590 unsigned int bpp;
591 u64 bin_h, bin_v;
592 int ret = 0;
594 format = v4l2_subdev_state_get_format(state, 0);
595 crop = v4l2_subdev_state_get_crop(state, 0);
597 switch (format->code) {
598 case MEDIA_BUS_FMT_SRGGB8_1X8:
599 case MEDIA_BUS_FMT_SGRBG8_1X8:
600 case MEDIA_BUS_FMT_SGBRG8_1X8:
601 case MEDIA_BUS_FMT_SBGGR8_1X8:
602 bpp = 8;
603 break;
605 case MEDIA_BUS_FMT_SRGGB10_1X10:
606 case MEDIA_BUS_FMT_SGRBG10_1X10:
607 case MEDIA_BUS_FMT_SGBRG10_1X10:
608 case MEDIA_BUS_FMT_SBGGR10_1X10:
609 default:
610 bpp = 10;
611 break;
614 cci_write(imx219->regmap, IMX219_REG_X_ADD_STA_A,
615 crop->left - IMX219_PIXEL_ARRAY_LEFT, &ret);
616 cci_write(imx219->regmap, IMX219_REG_X_ADD_END_A,
617 crop->left - IMX219_PIXEL_ARRAY_LEFT + crop->width - 1, &ret);
618 cci_write(imx219->regmap, IMX219_REG_Y_ADD_STA_A,
619 crop->top - IMX219_PIXEL_ARRAY_TOP, &ret);
620 cci_write(imx219->regmap, IMX219_REG_Y_ADD_END_A,
621 crop->top - IMX219_PIXEL_ARRAY_TOP + crop->height - 1, &ret);
623 switch (crop->width / format->width) {
624 case 1:
625 default:
626 bin_h = IMX219_BINNING_NONE;
627 break;
628 case 2:
629 bin_h = bpp == 8 ? IMX219_BINNING_X2_ANALOG : IMX219_BINNING_X2;
630 break;
633 switch (crop->height / format->height) {
634 case 1:
635 default:
636 bin_v = IMX219_BINNING_NONE;
637 break;
638 case 2:
639 bin_v = bpp == 8 ? IMX219_BINNING_X2_ANALOG : IMX219_BINNING_X2;
640 break;
643 cci_write(imx219->regmap, IMX219_REG_BINNING_MODE_H, bin_h, &ret);
644 cci_write(imx219->regmap, IMX219_REG_BINNING_MODE_V, bin_v, &ret);
646 cci_write(imx219->regmap, IMX219_REG_X_OUTPUT_SIZE,
647 format->width, &ret);
648 cci_write(imx219->regmap, IMX219_REG_Y_OUTPUT_SIZE,
649 format->height, &ret);
651 cci_write(imx219->regmap, IMX219_REG_TP_WINDOW_WIDTH,
652 format->width, &ret);
653 cci_write(imx219->regmap, IMX219_REG_TP_WINDOW_HEIGHT,
654 format->height, &ret);
656 cci_write(imx219->regmap, IMX219_REG_CSI_DATA_FORMAT_A,
657 (bpp << 8) | bpp, &ret);
658 cci_write(imx219->regmap, IMX219_REG_OPPXCK_DIV, bpp, &ret);
660 return ret;
663 static int imx219_configure_lanes(struct imx219 *imx219)
665 return cci_write(imx219->regmap, IMX219_REG_CSI_LANE_MODE,
666 imx219->lanes == 2 ? IMX219_CSI_2_LANE_MODE :
667 IMX219_CSI_4_LANE_MODE, NULL);
670 static int imx219_start_streaming(struct imx219 *imx219,
671 struct v4l2_subdev_state *state)
673 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
674 int ret;
676 ret = pm_runtime_resume_and_get(&client->dev);
677 if (ret < 0)
678 return ret;
680 /* Send all registers that are common to all modes */
681 ret = cci_multi_reg_write(imx219->regmap, imx219_common_regs,
682 ARRAY_SIZE(imx219_common_regs), NULL);
683 if (ret) {
684 dev_err(&client->dev, "%s failed to send mfg header\n", __func__);
685 goto err_rpm_put;
688 /* Configure two or four Lane mode */
689 ret = imx219_configure_lanes(imx219);
690 if (ret) {
691 dev_err(&client->dev, "%s failed to configure lanes\n", __func__);
692 goto err_rpm_put;
695 /* Apply format and crop settings. */
696 ret = imx219_set_framefmt(imx219, state);
697 if (ret) {
698 dev_err(&client->dev, "%s failed to set frame format: %d\n",
699 __func__, ret);
700 goto err_rpm_put;
703 /* Apply customized values from user */
704 ret = __v4l2_ctrl_handler_setup(imx219->sd.ctrl_handler);
705 if (ret)
706 goto err_rpm_put;
708 /* set stream on register */
709 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT,
710 IMX219_MODE_STREAMING, NULL);
711 if (ret)
712 goto err_rpm_put;
714 /* vflip and hflip cannot change during streaming */
715 __v4l2_ctrl_grab(imx219->vflip, true);
716 __v4l2_ctrl_grab(imx219->hflip, true);
718 return 0;
720 err_rpm_put:
721 pm_runtime_put(&client->dev);
722 return ret;
725 static void imx219_stop_streaming(struct imx219 *imx219)
727 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
728 int ret;
730 /* set stream off register */
731 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT,
732 IMX219_MODE_STANDBY, NULL);
733 if (ret)
734 dev_err(&client->dev, "%s failed to set stream\n", __func__);
736 __v4l2_ctrl_grab(imx219->vflip, false);
737 __v4l2_ctrl_grab(imx219->hflip, false);
739 pm_runtime_put(&client->dev);
742 static int imx219_set_stream(struct v4l2_subdev *sd, int enable)
744 struct imx219 *imx219 = to_imx219(sd);
745 struct v4l2_subdev_state *state;
746 int ret = 0;
748 state = v4l2_subdev_lock_and_get_active_state(sd);
750 if (enable)
751 ret = imx219_start_streaming(imx219, state);
752 else
753 imx219_stop_streaming(imx219);
755 v4l2_subdev_unlock_state(state);
756 return ret;
759 static void imx219_update_pad_format(struct imx219 *imx219,
760 const struct imx219_mode *mode,
761 struct v4l2_mbus_framefmt *fmt, u32 code)
763 /* Bayer order varies with flips */
764 fmt->code = imx219_get_format_code(imx219, code);
765 fmt->width = mode->width;
766 fmt->height = mode->height;
767 fmt->field = V4L2_FIELD_NONE;
768 fmt->colorspace = V4L2_COLORSPACE_RAW;
769 fmt->ycbcr_enc = V4L2_YCBCR_ENC_601;
770 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
771 fmt->xfer_func = V4L2_XFER_FUNC_NONE;
774 static int imx219_enum_mbus_code(struct v4l2_subdev *sd,
775 struct v4l2_subdev_state *state,
776 struct v4l2_subdev_mbus_code_enum *code)
778 struct imx219 *imx219 = to_imx219(sd);
780 if (code->index >= (ARRAY_SIZE(imx219_mbus_formats) / 4))
781 return -EINVAL;
783 code->code = imx219_get_format_code(imx219, imx219_mbus_formats[code->index * 4]);
785 return 0;
788 static int imx219_enum_frame_size(struct v4l2_subdev *sd,
789 struct v4l2_subdev_state *state,
790 struct v4l2_subdev_frame_size_enum *fse)
792 struct imx219 *imx219 = to_imx219(sd);
793 u32 code;
795 if (fse->index >= ARRAY_SIZE(supported_modes))
796 return -EINVAL;
798 code = imx219_get_format_code(imx219, fse->code);
799 if (fse->code != code)
800 return -EINVAL;
802 fse->min_width = supported_modes[fse->index].width;
803 fse->max_width = fse->min_width;
804 fse->min_height = supported_modes[fse->index].height;
805 fse->max_height = fse->min_height;
807 return 0;
810 static int imx219_set_pad_format(struct v4l2_subdev *sd,
811 struct v4l2_subdev_state *state,
812 struct v4l2_subdev_format *fmt)
814 struct imx219 *imx219 = to_imx219(sd);
815 const struct imx219_mode *mode;
816 struct v4l2_mbus_framefmt *format;
817 struct v4l2_rect *crop;
818 unsigned int bin_h, bin_v;
820 mode = v4l2_find_nearest_size(supported_modes,
821 ARRAY_SIZE(supported_modes),
822 width, height,
823 fmt->format.width, fmt->format.height);
825 imx219_update_pad_format(imx219, mode, &fmt->format, fmt->format.code);
827 format = v4l2_subdev_state_get_format(state, 0);
828 *format = fmt->format;
831 * Use binning to maximize the crop rectangle size, and centre it in the
832 * sensor.
834 bin_h = min(IMX219_PIXEL_ARRAY_WIDTH / format->width, 2U);
835 bin_v = min(IMX219_PIXEL_ARRAY_HEIGHT / format->height, 2U);
837 crop = v4l2_subdev_state_get_crop(state, 0);
838 crop->width = format->width * bin_h;
839 crop->height = format->height * bin_v;
840 crop->left = (IMX219_NATIVE_WIDTH - crop->width) / 2;
841 crop->top = (IMX219_NATIVE_HEIGHT - crop->height) / 2;
843 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
844 int exposure_max;
845 int exposure_def;
846 int hblank;
848 /* Update limits and set FPS to default */
849 __v4l2_ctrl_modify_range(imx219->vblank, IMX219_VBLANK_MIN,
850 IMX219_VTS_MAX - mode->height, 1,
851 mode->vts_def - mode->height);
852 __v4l2_ctrl_s_ctrl(imx219->vblank,
853 mode->vts_def - mode->height);
854 /* Update max exposure while meeting expected vblanking */
855 exposure_max = mode->vts_def - 4;
856 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
857 exposure_max : IMX219_EXPOSURE_DEFAULT;
858 __v4l2_ctrl_modify_range(imx219->exposure,
859 imx219->exposure->minimum,
860 exposure_max, imx219->exposure->step,
861 exposure_def);
863 * Currently PPL is fixed to IMX219_PPL_DEFAULT, so hblank
864 * depends on mode->width only, and is not changeble in any
865 * way other than changing the mode.
867 hblank = IMX219_PPL_DEFAULT - mode->width;
868 __v4l2_ctrl_modify_range(imx219->hblank, hblank, hblank, 1,
869 hblank);
872 return 0;
875 static int imx219_get_selection(struct v4l2_subdev *sd,
876 struct v4l2_subdev_state *state,
877 struct v4l2_subdev_selection *sel)
879 switch (sel->target) {
880 case V4L2_SEL_TGT_CROP: {
881 sel->r = *v4l2_subdev_state_get_crop(state, 0);
882 return 0;
885 case V4L2_SEL_TGT_NATIVE_SIZE:
886 sel->r.top = 0;
887 sel->r.left = 0;
888 sel->r.width = IMX219_NATIVE_WIDTH;
889 sel->r.height = IMX219_NATIVE_HEIGHT;
891 return 0;
893 case V4L2_SEL_TGT_CROP_DEFAULT:
894 case V4L2_SEL_TGT_CROP_BOUNDS:
895 sel->r.top = IMX219_PIXEL_ARRAY_TOP;
896 sel->r.left = IMX219_PIXEL_ARRAY_LEFT;
897 sel->r.width = IMX219_PIXEL_ARRAY_WIDTH;
898 sel->r.height = IMX219_PIXEL_ARRAY_HEIGHT;
900 return 0;
903 return -EINVAL;
906 static int imx219_init_state(struct v4l2_subdev *sd,
907 struct v4l2_subdev_state *state)
909 struct v4l2_subdev_format fmt = {
910 .which = V4L2_SUBDEV_FORMAT_TRY,
911 .pad = 0,
912 .format = {
913 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
914 .width = supported_modes[0].width,
915 .height = supported_modes[0].height,
919 imx219_set_pad_format(sd, state, &fmt);
921 return 0;
924 static const struct v4l2_subdev_video_ops imx219_video_ops = {
925 .s_stream = imx219_set_stream,
928 static const struct v4l2_subdev_pad_ops imx219_pad_ops = {
929 .enum_mbus_code = imx219_enum_mbus_code,
930 .get_fmt = v4l2_subdev_get_fmt,
931 .set_fmt = imx219_set_pad_format,
932 .get_selection = imx219_get_selection,
933 .enum_frame_size = imx219_enum_frame_size,
936 static const struct v4l2_subdev_ops imx219_subdev_ops = {
937 .video = &imx219_video_ops,
938 .pad = &imx219_pad_ops,
941 static const struct v4l2_subdev_internal_ops imx219_internal_ops = {
942 .init_state = imx219_init_state,
945 /* -----------------------------------------------------------------------------
946 * Power management
949 static int imx219_power_on(struct device *dev)
951 struct v4l2_subdev *sd = dev_get_drvdata(dev);
952 struct imx219 *imx219 = to_imx219(sd);
953 int ret;
955 ret = regulator_bulk_enable(IMX219_NUM_SUPPLIES,
956 imx219->supplies);
957 if (ret) {
958 dev_err(dev, "%s: failed to enable regulators\n",
959 __func__);
960 return ret;
963 ret = clk_prepare_enable(imx219->xclk);
964 if (ret) {
965 dev_err(dev, "%s: failed to enable clock\n",
966 __func__);
967 goto reg_off;
970 gpiod_set_value_cansleep(imx219->reset_gpio, 1);
971 usleep_range(IMX219_XCLR_MIN_DELAY_US,
972 IMX219_XCLR_MIN_DELAY_US + IMX219_XCLR_DELAY_RANGE_US);
974 return 0;
976 reg_off:
977 regulator_bulk_disable(IMX219_NUM_SUPPLIES, imx219->supplies);
979 return ret;
982 static int imx219_power_off(struct device *dev)
984 struct v4l2_subdev *sd = dev_get_drvdata(dev);
985 struct imx219 *imx219 = to_imx219(sd);
987 gpiod_set_value_cansleep(imx219->reset_gpio, 0);
988 regulator_bulk_disable(IMX219_NUM_SUPPLIES, imx219->supplies);
989 clk_disable_unprepare(imx219->xclk);
991 return 0;
994 /* -----------------------------------------------------------------------------
995 * Probe & remove
998 static int imx219_get_regulators(struct imx219 *imx219)
1000 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
1001 unsigned int i;
1003 for (i = 0; i < IMX219_NUM_SUPPLIES; i++)
1004 imx219->supplies[i].supply = imx219_supply_name[i];
1006 return devm_regulator_bulk_get(&client->dev,
1007 IMX219_NUM_SUPPLIES,
1008 imx219->supplies);
1011 /* Verify chip ID */
1012 static int imx219_identify_module(struct imx219 *imx219)
1014 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
1015 int ret;
1016 u64 val;
1018 ret = cci_read(imx219->regmap, IMX219_REG_CHIP_ID, &val, NULL);
1019 if (ret)
1020 return dev_err_probe(&client->dev, ret,
1021 "failed to read chip id %x\n",
1022 IMX219_CHIP_ID);
1024 if (val != IMX219_CHIP_ID)
1025 return dev_err_probe(&client->dev, -EIO,
1026 "chip id mismatch: %x!=%llx\n",
1027 IMX219_CHIP_ID, val);
1029 return 0;
1032 static int imx219_check_hwcfg(struct device *dev, struct imx219 *imx219)
1034 struct fwnode_handle *endpoint;
1035 struct v4l2_fwnode_endpoint ep_cfg = {
1036 .bus_type = V4L2_MBUS_CSI2_DPHY
1038 int ret = -EINVAL;
1040 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);
1041 if (!endpoint)
1042 return dev_err_probe(dev, -EINVAL, "endpoint node not found\n");
1044 if (v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep_cfg)) {
1045 dev_err_probe(dev, -EINVAL, "could not parse endpoint\n");
1046 goto error_out;
1049 /* Check the number of MIPI CSI2 data lanes */
1050 if (ep_cfg.bus.mipi_csi2.num_data_lanes != 2 &&
1051 ep_cfg.bus.mipi_csi2.num_data_lanes != 4) {
1052 dev_err_probe(dev, -EINVAL,
1053 "only 2 or 4 data lanes are currently supported\n");
1054 goto error_out;
1056 imx219->lanes = ep_cfg.bus.mipi_csi2.num_data_lanes;
1058 /* Check the link frequency set in device tree */
1059 if (!ep_cfg.nr_of_link_frequencies) {
1060 dev_err_probe(dev, -EINVAL,
1061 "link-frequency property not found in DT\n");
1062 goto error_out;
1065 if (ep_cfg.nr_of_link_frequencies != 1 ||
1066 (ep_cfg.link_frequencies[0] != ((imx219->lanes == 2) ?
1067 IMX219_DEFAULT_LINK_FREQ : IMX219_DEFAULT_LINK_FREQ_4LANE))) {
1068 dev_err_probe(dev, -EINVAL,
1069 "Link frequency not supported: %lld\n",
1070 ep_cfg.link_frequencies[0]);
1071 goto error_out;
1074 ret = 0;
1076 error_out:
1077 v4l2_fwnode_endpoint_free(&ep_cfg);
1078 fwnode_handle_put(endpoint);
1080 return ret;
1083 static int imx219_probe(struct i2c_client *client)
1085 struct device *dev = &client->dev;
1086 struct imx219 *imx219;
1087 int ret;
1089 imx219 = devm_kzalloc(&client->dev, sizeof(*imx219), GFP_KERNEL);
1090 if (!imx219)
1091 return -ENOMEM;
1093 v4l2_i2c_subdev_init(&imx219->sd, client, &imx219_subdev_ops);
1094 imx219->sd.internal_ops = &imx219_internal_ops;
1096 /* Check the hardware configuration in device tree */
1097 if (imx219_check_hwcfg(dev, imx219))
1098 return -EINVAL;
1100 imx219->regmap = devm_cci_regmap_init_i2c(client, 16);
1101 if (IS_ERR(imx219->regmap))
1102 return dev_err_probe(dev, PTR_ERR(imx219->regmap),
1103 "failed to initialize CCI\n");
1105 /* Get system clock (xclk) */
1106 imx219->xclk = devm_clk_get(dev, NULL);
1107 if (IS_ERR(imx219->xclk))
1108 return dev_err_probe(dev, PTR_ERR(imx219->xclk),
1109 "failed to get xclk\n");
1111 imx219->xclk_freq = clk_get_rate(imx219->xclk);
1112 if (imx219->xclk_freq != IMX219_XCLK_FREQ)
1113 return dev_err_probe(dev, -EINVAL,
1114 "xclk frequency not supported: %d Hz\n",
1115 imx219->xclk_freq);
1117 ret = imx219_get_regulators(imx219);
1118 if (ret)
1119 return dev_err_probe(dev, ret, "failed to get regulators\n");
1121 /* Request optional enable pin */
1122 imx219->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1123 GPIOD_OUT_HIGH);
1126 * The sensor must be powered for imx219_identify_module()
1127 * to be able to read the CHIP_ID register
1129 ret = imx219_power_on(dev);
1130 if (ret)
1131 return ret;
1133 ret = imx219_identify_module(imx219);
1134 if (ret)
1135 goto error_power_off;
1138 * Sensor doesn't enter LP-11 state upon power up until and unless
1139 * streaming is started, so upon power up switch the modes to:
1140 * streaming -> standby
1142 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT,
1143 IMX219_MODE_STREAMING, NULL);
1144 if (ret < 0)
1145 goto error_power_off;
1147 usleep_range(100, 110);
1149 /* put sensor back to standby mode */
1150 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT,
1151 IMX219_MODE_STANDBY, NULL);
1152 if (ret < 0)
1153 goto error_power_off;
1155 usleep_range(100, 110);
1157 ret = imx219_init_controls(imx219);
1158 if (ret)
1159 goto error_power_off;
1161 /* Initialize subdev */
1162 imx219->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1163 imx219->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1165 /* Initialize source pad */
1166 imx219->pad.flags = MEDIA_PAD_FL_SOURCE;
1168 ret = media_entity_pads_init(&imx219->sd.entity, 1, &imx219->pad);
1169 if (ret) {
1170 dev_err_probe(dev, ret, "failed to init entity pads\n");
1171 goto error_handler_free;
1174 imx219->sd.state_lock = imx219->ctrl_handler.lock;
1175 ret = v4l2_subdev_init_finalize(&imx219->sd);
1176 if (ret < 0) {
1177 dev_err_probe(dev, ret, "subdev init error\n");
1178 goto error_media_entity;
1181 ret = v4l2_async_register_subdev_sensor(&imx219->sd);
1182 if (ret < 0) {
1183 dev_err_probe(dev, ret,
1184 "failed to register sensor sub-device\n");
1185 goto error_subdev_cleanup;
1188 /* Enable runtime PM and turn off the device */
1189 pm_runtime_set_active(dev);
1190 pm_runtime_enable(dev);
1191 pm_runtime_idle(dev);
1193 return 0;
1195 error_subdev_cleanup:
1196 v4l2_subdev_cleanup(&imx219->sd);
1198 error_media_entity:
1199 media_entity_cleanup(&imx219->sd.entity);
1201 error_handler_free:
1202 imx219_free_controls(imx219);
1204 error_power_off:
1205 imx219_power_off(dev);
1207 return ret;
1210 static void imx219_remove(struct i2c_client *client)
1212 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1213 struct imx219 *imx219 = to_imx219(sd);
1215 v4l2_async_unregister_subdev(sd);
1216 v4l2_subdev_cleanup(sd);
1217 media_entity_cleanup(&sd->entity);
1218 imx219_free_controls(imx219);
1220 pm_runtime_disable(&client->dev);
1221 if (!pm_runtime_status_suspended(&client->dev))
1222 imx219_power_off(&client->dev);
1223 pm_runtime_set_suspended(&client->dev);
1226 static const struct of_device_id imx219_dt_ids[] = {
1227 { .compatible = "sony,imx219" },
1228 { /* sentinel */ }
1230 MODULE_DEVICE_TABLE(of, imx219_dt_ids);
1232 static const struct dev_pm_ops imx219_pm_ops = {
1233 SET_RUNTIME_PM_OPS(imx219_power_off, imx219_power_on, NULL)
1236 static struct i2c_driver imx219_i2c_driver = {
1237 .driver = {
1238 .name = "imx219",
1239 .of_match_table = imx219_dt_ids,
1240 .pm = &imx219_pm_ops,
1242 .probe = imx219_probe,
1243 .remove = imx219_remove,
1246 module_i2c_driver(imx219_i2c_driver);
1248 MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.com");
1249 MODULE_DESCRIPTION("Sony IMX219 sensor driver");
1250 MODULE_LICENSE("GPL v2");