drivers/media/i2c/ov01a10.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2023 Intel Corporation.
   4  */
   5
   6 #include <linux/unaligned.h>
   7
   8 #include <linux/acpi.h>
   9 #include <linux/bitfield.h>
  10 #include <linux/i2c.h>
  11 #include <linux/module.h>
  12 #include <linux/pm_runtime.h>
  13
  14 #include <media/v4l2-ctrls.h>
  15 #include <media/v4l2-device.h>
  16 #include <media/v4l2-fwnode.h>
  17
  18 #define OV01A10_LINK_FREQ_400MHZ        400000000ULL
  19 #define OV01A10_SCLK                    40000000LL
  20 #define OV01A10_DATA_LANES              1
  21
  22 #define OV01A10_REG_CHIP_ID             0x300a
  23 #define OV01A10_CHIP_ID                 0x560141
  24
  25 #define OV01A10_REG_MODE_SELECT         0x0100
  26 #define OV01A10_MODE_STANDBY            0x00
  27 #define OV01A10_MODE_STREAMING          0x01
  28
  29 /* pixel array */
  30 #define OV01A10_PIXEL_ARRAY_WIDTH       1296
  31 #define OV01A10_PIXEL_ARRAY_HEIGHT      816
  32 #define OV01A10_ACITVE_WIDTH            1280
  33 #define OV01A10_ACITVE_HEIGHT           800
  34
  35 /* vertical and horizontal timings */
  36 #define OV01A10_REG_VTS                 0x380e
  37 #define OV01A10_VTS_DEF                 0x0380
  38 #define OV01A10_VTS_MIN                 0x0380
  39 #define OV01A10_VTS_MAX                 0xffff
  40 #define OV01A10_HTS_DEF                 1488
  41
  42 /* exposure controls */
  43 #define OV01A10_REG_EXPOSURE            0x3501
  44 #define OV01A10_EXPOSURE_MIN            4
  45 #define OV01A10_EXPOSURE_MAX_MARGIN     8
  46 #define OV01A10_EXPOSURE_STEP           1
  47
  48 /* analog gain controls */
  49 #define OV01A10_REG_ANALOG_GAIN         0x3508
  50 #define OV01A10_ANAL_GAIN_MIN           0x100
  51 #define OV01A10_ANAL_GAIN_MAX           0xffff
  52 #define OV01A10_ANAL_GAIN_STEP          1
  53
  54 /* digital gain controls */
  55 #define OV01A10_REG_DIGITAL_GAIN_B      0x350a
  56 #define OV01A10_REG_DIGITAL_GAIN_GB     0x3510
  57 #define OV01A10_REG_DIGITAL_GAIN_GR     0x3513
  58 #define OV01A10_REG_DIGITAL_GAIN_R      0x3516
  59 #define OV01A10_DGTL_GAIN_MIN           0
  60 #define OV01A10_DGTL_GAIN_MAX           0x3ffff
  61 #define OV01A10_DGTL_GAIN_STEP          1
  62 #define OV01A10_DGTL_GAIN_DEFAULT       1024
  63
  64 /* test pattern control */
  65 #define OV01A10_REG_TEST_PATTERN        0x4503
  66 #define OV01A10_TEST_PATTERN_ENABLE     BIT(7)
  67 #define OV01A10_LINK_FREQ_400MHZ_INDEX  0
  68
  69 /* flip and mirror control */
  70 #define OV01A10_REG_FORMAT1             0x3820
  71 #define OV01A10_VFLIP_MASK              BIT(4)
  72 #define OV01A10_HFLIP_MASK              BIT(3)
  73
  74 /* window offset */
  75 #define OV01A10_REG_X_WIN               0x3811
  76 #define OV01A10_REG_Y_WIN               0x3813
  77
  78 struct ov01a10_reg {
  79         u16 address;
  80         u8 val;
  81 };
  82
  83 struct ov01a10_reg_list {
  84         u32 num_of_regs;
  85         const struct ov01a10_reg *regs;
  86 };
  87
  88 struct ov01a10_link_freq_config {
  89         const struct ov01a10_reg_list reg_list;
  90 };
  91
  92 struct ov01a10_mode {
  93         u32 width;
  94         u32 height;
  95         u32 hts;
  96         u32 vts_def;
  97         u32 vts_min;
  98         u32 link_freq_index;
  99
 100         const struct ov01a10_reg_list reg_list;
 101 };
 102
 103 static const struct ov01a10_reg mipi_data_rate_720mbps[] = {
 104         {0x0103, 0x01},
 105         {0x0302, 0x00},
 106         {0x0303, 0x06},
 107         {0x0304, 0x01},
 108         {0x0305, 0xe0},
 109         {0x0306, 0x00},
 110         {0x0308, 0x01},
 111         {0x0309, 0x00},
 112         {0x030c, 0x01},
 113         {0x0322, 0x01},
 114         {0x0323, 0x06},
 115         {0x0324, 0x01},
 116         {0x0325, 0x68},
 117 };
 118
 119 static const struct ov01a10_reg sensor_1280x800_setting[] = {
 120         {0x3002, 0xa1},
 121         {0x301e, 0xf0},
 122         {0x3022, 0x01},
 123         {0x3501, 0x03},
 124         {0x3502, 0x78},
 125         {0x3504, 0x0c},
 126         {0x3508, 0x01},
 127         {0x3509, 0x00},
 128         {0x3601, 0xc0},
 129         {0x3603, 0x71},
 130         {0x3610, 0x68},
 131         {0x3611, 0x86},
 132         {0x3640, 0x10},
 133         {0x3641, 0x80},
 134         {0x3642, 0xdc},
 135         {0x3646, 0x55},
 136         {0x3647, 0x57},
 137         {0x364b, 0x00},
 138         {0x3653, 0x10},
 139         {0x3655, 0x00},
 140         {0x3656, 0x00},
 141         {0x365f, 0x0f},
 142         {0x3661, 0x45},
 143         {0x3662, 0x24},
 144         {0x3663, 0x11},
 145         {0x3664, 0x07},
 146         {0x3709, 0x34},
 147         {0x370b, 0x6f},
 148         {0x3714, 0x22},
 149         {0x371b, 0x27},
 150         {0x371c, 0x67},
 151         {0x371d, 0xa7},
 152         {0x371e, 0xe7},
 153         {0x3730, 0x81},
 154         {0x3733, 0x10},
 155         {0x3734, 0x40},
 156         {0x3737, 0x04},
 157         {0x3739, 0x1c},
 158         {0x3767, 0x00},
 159         {0x376c, 0x81},
 160         {0x3772, 0x14},
 161         {0x37c2, 0x04},
 162         {0x37d8, 0x03},
 163         {0x37d9, 0x0c},
 164         {0x37e0, 0x00},
 165         {0x37e1, 0x08},
 166         {0x37e2, 0x10},
 167         {0x37e3, 0x04},
 168         {0x37e4, 0x04},
 169         {0x37e5, 0x03},
 170         {0x37e6, 0x04},
 171         {0x3800, 0x00},
 172         {0x3801, 0x00},
 173         {0x3802, 0x00},
 174         {0x3803, 0x00},
 175         {0x3804, 0x05},
 176         {0x3805, 0x0f},
 177         {0x3806, 0x03},
 178         {0x3807, 0x2f},
 179         {0x3808, 0x05},
 180         {0x3809, 0x00},
 181         {0x380a, 0x03},
 182         {0x380b, 0x20},
 183         {0x380c, 0x02},
 184         {0x380d, 0xe8},
 185         {0x380e, 0x03},
 186         {0x380f, 0x80},
 187         {0x3810, 0x00},
 188         {0x3811, 0x08},
 189         {0x3812, 0x00},
 190         {0x3813, 0x08},
 191         {0x3814, 0x01},
 192         {0x3815, 0x01},
 193         {0x3816, 0x01},
 194         {0x3817, 0x01},
 195         {0x3820, 0xa0},
 196         {0x3822, 0x13},
 197         {0x3832, 0x28},
 198         {0x3833, 0x10},
 199         {0x3b00, 0x00},
 200         {0x3c80, 0x00},
 201         {0x3c88, 0x02},
 202         {0x3c8c, 0x07},
 203         {0x3c8d, 0x40},
 204         {0x3cc7, 0x80},
 205         {0x4000, 0xc3},
 206         {0x4001, 0xe0},
 207         {0x4003, 0x40},
 208         {0x4008, 0x02},
 209         {0x4009, 0x19},
 210         {0x400a, 0x01},
 211         {0x400b, 0x6c},
 212         {0x4011, 0x00},
 213         {0x4041, 0x00},
 214         {0x4300, 0xff},
 215         {0x4301, 0x00},
 216         {0x4302, 0x0f},
 217         {0x4503, 0x00},
 218         {0x4601, 0x50},
 219         {0x4800, 0x64},
 220         {0x481f, 0x34},
 221         {0x4825, 0x33},
 222         {0x4837, 0x11},
 223         {0x4881, 0x40},
 224         {0x4883, 0x01},
 225         {0x4890, 0x00},
 226         {0x4901, 0x00},
 227         {0x4902, 0x00},
 228         {0x4b00, 0x2a},
 229         {0x4b0d, 0x00},
 230         {0x450a, 0x04},
 231         {0x450b, 0x00},
 232         {0x5000, 0x65},
 233         {0x5200, 0x18},
 234         {0x5004, 0x00},
 235         {0x5080, 0x40},
 236         {0x0305, 0xf4},
 237         {0x0325, 0xc2},
 238 };
 239
 240 static const char * const ov01a10_test_pattern_menu[] = {
 241         "Disabled",
 242         "Color Bar",
 243         "Top-Bottom Darker Color Bar",
 244         "Right-Left Darker Color Bar",
 245         "Color Bar type 4",
 246 };
 247
 248 static const s64 link_freq_menu_items[] = {
 249         OV01A10_LINK_FREQ_400MHZ,
 250 };
 251
 252 static const struct ov01a10_link_freq_config link_freq_configs[] = {
 253         [OV01A10_LINK_FREQ_400MHZ_INDEX] = {
 254                 .reg_list = {
 255                         .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps),
 256                         .regs = mipi_data_rate_720mbps,
 257                 }
 258         },
 259 };
 260
 261 static const struct ov01a10_mode supported_modes[] = {
 262         {
 263                 .width = OV01A10_ACITVE_WIDTH,
 264                 .height = OV01A10_ACITVE_HEIGHT,
 265                 .hts = OV01A10_HTS_DEF,
 266                 .vts_def = OV01A10_VTS_DEF,
 267                 .vts_min = OV01A10_VTS_MIN,
 268                 .reg_list = {
 269                         .num_of_regs = ARRAY_SIZE(sensor_1280x800_setting),
 270                         .regs = sensor_1280x800_setting,
 271                 },
 272                 .link_freq_index = OV01A10_LINK_FREQ_400MHZ_INDEX,
 273         },
 274 };
 275
 276 struct ov01a10 {
 277         struct v4l2_subdev sd;
 278         struct media_pad pad;
 279         struct v4l2_ctrl_handler ctrl_handler;
 280
 281         /* v4l2 controls */
 282         struct v4l2_ctrl *link_freq;
 283         struct v4l2_ctrl *pixel_rate;
 284         struct v4l2_ctrl *vblank;
 285         struct v4l2_ctrl *hblank;
 286         struct v4l2_ctrl *exposure;
 287
 288         const struct ov01a10_mode *cur_mode;
 289 };
 290
 291 static inline struct ov01a10 *to_ov01a10(struct v4l2_subdev *subdev)
 292 {
 293         return container_of(subdev, struct ov01a10, sd);
 294 }
 295
 296 static int ov01a10_read_reg(struct ov01a10 *ov01a10, u16 reg, u16 len, u32 *val)
 297 {
 298         struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
 299         struct i2c_msg msgs[2];
 300         u8 addr_buf[2];
 301         u8 data_buf[4] = {0};
 302         int ret = 0;
 303
 304         if (len > sizeof(data_buf))
 305                 return -EINVAL;
 306
 307         put_unaligned_be16(reg, addr_buf);
 308         msgs[0].addr = client->addr;
 309         msgs[0].flags = 0;
 310         msgs[0].len = sizeof(addr_buf);
 311         msgs[0].buf = addr_buf;
 312         msgs[1].addr = client->addr;
 313         msgs[1].flags = I2C_M_RD;
 314         msgs[1].len = len;
 315         msgs[1].buf = &data_buf[sizeof(data_buf) - len];
 316
 317         ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
 318
 319         if (ret != ARRAY_SIZE(msgs))
 320                 return ret < 0 ? ret : -EIO;
 321
 322         *val = get_unaligned_be32(data_buf);
 323
 324         return 0;
 325 }
 326
 327 static int ov01a10_write_reg(struct ov01a10 *ov01a10, u16 reg, u16 len, u32 val)
 328 {
 329         struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
 330         u8 buf[6];
 331         int ret = 0;
 332
 333         if (len > 4)
 334                 return -EINVAL;
 335
 336         put_unaligned_be16(reg, buf);
 337         put_unaligned_be32(val << 8 * (4 - len), buf + 2);
 338
 339         ret = i2c_master_send(client, buf, len + 2);
 340         if (ret != len + 2)
 341                 return ret < 0 ? ret : -EIO;
 342
 343         return 0;
 344 }
 345
 346 static int ov01a10_write_reg_list(struct ov01a10 *ov01a10,
 347                                   const struct ov01a10_reg_list *r_list)
 348 {
 349         struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
 350         unsigned int i;
 351         int ret = 0;
 352
 353         for (i = 0; i < r_list->num_of_regs; i++) {
 354                 ret = ov01a10_write_reg(ov01a10, r_list->regs[i].address, 1,
 355                                         r_list->regs[i].val);
 356                 if (ret) {
 357                         dev_err_ratelimited(&client->dev,
 358                                             "write reg 0x%4.4x err = %d\n",
 359                                             r_list->regs[i].address, ret);
 360                         return ret;
 361                 }
 362         }
 363
 364         return 0;
 365 }
 366
 367 static int ov01a10_update_digital_gain(struct ov01a10 *ov01a10, u32 d_gain)
 368 {
 369         struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
 370         u32 real = d_gain << 6;
 371         int ret = 0;
 372
 373         ret = ov01a10_write_reg(ov01a10, OV01A10_REG_DIGITAL_GAIN_B, 3, real);
 374         if (ret) {
 375                 dev_err(&client->dev, "failed to set DIGITAL_GAIN_B\n");
 376                 return ret;
 377         }
 378
 379         ret = ov01a10_write_reg(ov01a10, OV01A10_REG_DIGITAL_GAIN_GB, 3, real);
 380         if (ret) {
 381                 dev_err(&client->dev, "failed to set DIGITAL_GAIN_GB\n");
 382                 return ret;
 383         }
 384
 385         ret = ov01a10_write_reg(ov01a10, OV01A10_REG_DIGITAL_GAIN_GR, 3, real);
 386         if (ret) {
 387                 dev_err(&client->dev, "failed to set DIGITAL_GAIN_GR\n");
 388                 return ret;
 389         }
 390
 391         ret = ov01a10_write_reg(ov01a10, OV01A10_REG_DIGITAL_GAIN_R, 3, real);
 392         if (ret)
 393                 dev_err(&client->dev, "failed to set DIGITAL_GAIN_R\n");
 394
 395         return ret;
 396 }
 397
 398 static int ov01a10_test_pattern(struct ov01a10 *ov01a10, u32 pattern)
 399 {
 400         if (!pattern)
 401                 return 0;
 402
 403         pattern = (pattern - 1) | OV01A10_TEST_PATTERN_ENABLE;
 404
 405         return ov01a10_write_reg(ov01a10, OV01A10_REG_TEST_PATTERN, 1, pattern);
 406 }
 407
 408 /* for vflip and hflip, use 0x9 as window offset to keep the bayer */
 409 static int ov01a10_set_hflip(struct ov01a10 *ov01a10, u32 hflip)
 410 {
 411         int ret;
 412         u32 val, offset;
 413
 414         offset = hflip ? 0x9 : 0x8;
 415         ret = ov01a10_write_reg(ov01a10, OV01A10_REG_X_WIN, 1, offset);
 416         if (ret)
 417                 return ret;
 418
 419         ret = ov01a10_read_reg(ov01a10, OV01A10_REG_FORMAT1, 1, &val);
 420         if (ret)
 421                 return ret;
 422
 423         val = hflip ? val | FIELD_PREP(OV01A10_HFLIP_MASK, 0x1) :
 424                 val & ~OV01A10_HFLIP_MASK;
 425
 426         return ov01a10_write_reg(ov01a10, OV01A10_REG_FORMAT1, 1, val);
 427 }
 428
 429 static int ov01a10_set_vflip(struct ov01a10 *ov01a10, u32 vflip)
 430 {
 431         int ret;
 432         u32 val, offset;
 433
 434         offset = vflip ? 0x9 : 0x8;
 435         ret = ov01a10_write_reg(ov01a10, OV01A10_REG_Y_WIN, 1, offset);
 436         if (ret)
 437                 return ret;
 438
 439         ret = ov01a10_read_reg(ov01a10, OV01A10_REG_FORMAT1, 1, &val);
 440         if (ret)
 441                 return ret;
 442
 443         val = vflip ? val | FIELD_PREP(OV01A10_VFLIP_MASK, 0x1) :
 444                 val & ~OV01A10_VFLIP_MASK;
 445
 446         return ov01a10_write_reg(ov01a10, OV01A10_REG_FORMAT1, 1, val);
 447 }
 448
 449 static int ov01a10_set_ctrl(struct v4l2_ctrl *ctrl)
 450 {
 451         struct ov01a10 *ov01a10 = container_of(ctrl->handler,
 452                                                struct ov01a10, ctrl_handler);
 453         struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
 454         s64 exposure_max;
 455         int ret = 0;
 456
 457         if (ctrl->id == V4L2_CID_VBLANK) {
 458                 exposure_max = ov01a10->cur_mode->height + ctrl->val -
 459                         OV01A10_EXPOSURE_MAX_MARGIN;
 460                 __v4l2_ctrl_modify_range(ov01a10->exposure,
 461                                          ov01a10->exposure->minimum,
 462                                          exposure_max, ov01a10->exposure->step,
 463                                          exposure_max);
 464         }
 465
 466         if (!pm_runtime_get_if_in_use(&client->dev))
 467                 return 0;
 468
 469         switch (ctrl->id) {
 470         case V4L2_CID_ANALOGUE_GAIN:
 471                 ret = ov01a10_write_reg(ov01a10, OV01A10_REG_ANALOG_GAIN, 2,
 472                                         ctrl->val);
 473                 break;
 474
 475         case V4L2_CID_DIGITAL_GAIN:
 476                 ret = ov01a10_update_digital_gain(ov01a10, ctrl->val);
 477                 break;
 478
 479         case V4L2_CID_EXPOSURE:
 480                 ret = ov01a10_write_reg(ov01a10, OV01A10_REG_EXPOSURE, 2,
 481                                         ctrl->val);
 482                 break;
 483
 484         case V4L2_CID_VBLANK:
 485                 ret = ov01a10_write_reg(ov01a10, OV01A10_REG_VTS, 2,
 486                                         ov01a10->cur_mode->height + ctrl->val);
 487                 break;
 488
 489         case V4L2_CID_TEST_PATTERN:
 490                 ret = ov01a10_test_pattern(ov01a10, ctrl->val);
 491                 break;
 492
 493         case V4L2_CID_HFLIP:
 494                 ov01a10_set_hflip(ov01a10, ctrl->val);
 495                 break;
 496
 497         case V4L2_CID_VFLIP:
 498                 ov01a10_set_vflip(ov01a10, ctrl->val);
 499                 break;
 500
 501         default:
 502                 ret = -EINVAL;
 503                 break;
 504         }
 505
 506         pm_runtime_put(&client->dev);
 507
 508         return ret;
 509 }
 510
 511 static const struct v4l2_ctrl_ops ov01a10_ctrl_ops = {
 512         .s_ctrl = ov01a10_set_ctrl,
 513 };
 514
 515 static int ov01a10_init_controls(struct ov01a10 *ov01a10)
 516 {
 517         struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
 518         struct v4l2_fwnode_device_properties props;
 519         u32 vblank_min, vblank_max, vblank_default;
 520         struct v4l2_ctrl_handler *ctrl_hdlr;
 521         const struct ov01a10_mode *cur_mode;
 522         s64 exposure_max, h_blank;
 523         int ret = 0;
 524         int size;
 525
 526         ret = v4l2_fwnode_device_parse(&client->dev, &props);
 527         if (ret)
 528                 return ret;
 529
 530         ctrl_hdlr = &ov01a10->ctrl_handler;
 531         ret = v4l2_ctrl_handler_init(ctrl_hdlr, 12);
 532         if (ret)
 533                 return ret;
 534
 535         cur_mode = ov01a10->cur_mode;
 536         size = ARRAY_SIZE(link_freq_menu_items);
 537
 538         ov01a10->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
 539                                                     &ov01a10_ctrl_ops,
 540                                                     V4L2_CID_LINK_FREQ,
 541                                                     size - 1, 0,
 542                                                     link_freq_menu_items);
 543         if (ov01a10->link_freq)
 544                 ov01a10->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
 545
 546         ov01a10->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops,
 547                                                 V4L2_CID_PIXEL_RATE, 0,
 548                                                 OV01A10_SCLK, 1, OV01A10_SCLK);
 549
 550         vblank_min = cur_mode->vts_min - cur_mode->height;
 551         vblank_max = OV01A10_VTS_MAX - cur_mode->height;
 552         vblank_default = cur_mode->vts_def - cur_mode->height;
 553         ov01a10->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops,
 554                                             V4L2_CID_VBLANK, vblank_min,
 555                                             vblank_max, 1, vblank_default);
 556
 557         h_blank = cur_mode->hts - cur_mode->width;
 558         ov01a10->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops,
 559                                             V4L2_CID_HBLANK, h_blank, h_blank,
 560                                             1, h_blank);
 561         if (ov01a10->hblank)
 562                 ov01a10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
 563
 564         v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
 565                           OV01A10_ANAL_GAIN_MIN, OV01A10_ANAL_GAIN_MAX,
 566                           OV01A10_ANAL_GAIN_STEP, OV01A10_ANAL_GAIN_MIN);
 567         v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
 568                           OV01A10_DGTL_GAIN_MIN, OV01A10_DGTL_GAIN_MAX,
 569                           OV01A10_DGTL_GAIN_STEP, OV01A10_DGTL_GAIN_DEFAULT);
 570
 571         exposure_max = cur_mode->vts_def - OV01A10_EXPOSURE_MAX_MARGIN;
 572         ov01a10->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops,
 573                                               V4L2_CID_EXPOSURE,
 574                                               OV01A10_EXPOSURE_MIN,
 575                                               exposure_max,
 576                                               OV01A10_EXPOSURE_STEP,
 577                                               exposure_max);
 578
 579         v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov01a10_ctrl_ops,
 580                                      V4L2_CID_TEST_PATTERN,
 581                                      ARRAY_SIZE(ov01a10_test_pattern_menu) - 1,
 582                                      0, 0, ov01a10_test_pattern_menu);
 583
 584         v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops, V4L2_CID_HFLIP,
 585                           0, 1, 1, 0);
 586         v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops, V4L2_CID_VFLIP,
 587                           0, 1, 1, 0);
 588
 589         ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov01a10_ctrl_ops,
 590                                               &props);
 591         if (ret)
 592                 goto fail;
 593
 594         if (ctrl_hdlr->error) {
 595                 ret = ctrl_hdlr->error;
 596                 goto fail;
 597         }
 598
 599         ov01a10->sd.ctrl_handler = ctrl_hdlr;
 600
 601         return 0;
 602 fail:
 603         v4l2_ctrl_handler_free(ctrl_hdlr);
 604
 605         return ret;
 606 }
 607
 608 static void ov01a10_update_pad_format(const struct ov01a10_mode *mode,
 609                                       struct v4l2_mbus_framefmt *fmt)
 610 {
 611         fmt->width = mode->width;
 612         fmt->height = mode->height;
 613         fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
 614         fmt->field = V4L2_FIELD_NONE;
 615         fmt->colorspace = V4L2_COLORSPACE_RAW;
 616 }
 617
 618 static int ov01a10_start_streaming(struct ov01a10 *ov01a10)
 619 {
 620         struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
 621         const struct ov01a10_reg_list *reg_list;
 622         int link_freq_index;
 623         int ret = 0;
 624
 625         link_freq_index = ov01a10->cur_mode->link_freq_index;
 626         reg_list = &link_freq_configs[link_freq_index].reg_list;
 627         ret = ov01a10_write_reg_list(ov01a10, reg_list);
 628         if (ret) {
 629                 dev_err(&client->dev, "failed to set plls\n");
 630                 return ret;
 631         }
 632
 633         reg_list = &ov01a10->cur_mode->reg_list;
 634         ret = ov01a10_write_reg_list(ov01a10, reg_list);
 635         if (ret) {
 636                 dev_err(&client->dev, "failed to set mode\n");
 637                 return ret;
 638         }
 639
 640         ret = __v4l2_ctrl_handler_setup(ov01a10->sd.ctrl_handler);
 641         if (ret)
 642                 return ret;
 643
 644         ret = ov01a10_write_reg(ov01a10, OV01A10_REG_MODE_SELECT, 1,
 645                                 OV01A10_MODE_STREAMING);
 646         if (ret)
 647                 dev_err(&client->dev, "failed to start streaming\n");
 648
 649         return ret;
 650 }
 651
 652 static void ov01a10_stop_streaming(struct ov01a10 *ov01a10)
 653 {
 654         struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
 655         int ret = 0;
 656
 657         ret = ov01a10_write_reg(ov01a10, OV01A10_REG_MODE_SELECT, 1,
 658                                 OV01A10_MODE_STANDBY);
 659         if (ret)
 660                 dev_err(&client->dev, "failed to stop streaming\n");
 661 }
 662
 663 static int ov01a10_set_stream(struct v4l2_subdev *sd, int enable)
 664 {
 665         struct ov01a10 *ov01a10 = to_ov01a10(sd);
 666         struct i2c_client *client = v4l2_get_subdevdata(sd);
 667         struct v4l2_subdev_state *state;
 668         int ret = 0;
 669
 670         state = v4l2_subdev_lock_and_get_active_state(sd);
 671
 672         if (enable) {
 673                 ret = pm_runtime_resume_and_get(&client->dev);
 674                 if (ret < 0)
 675                         goto unlock;
 676
 677                 ret = ov01a10_start_streaming(ov01a10);
 678                 if (ret) {
 679                         pm_runtime_put(&client->dev);
 680                         goto unlock;
 681                 }
 682         } else {
 683                 ov01a10_stop_streaming(ov01a10);
 684                 pm_runtime_put(&client->dev);
 685         }
 686
 687 unlock:
 688         v4l2_subdev_unlock_state(state);
 689
 690         return ret;
 691 }
 692
 693 static int ov01a10_set_format(struct v4l2_subdev *sd,
 694                               struct v4l2_subdev_state *sd_state,
 695                               struct v4l2_subdev_format *fmt)
 696 {
 697         struct ov01a10 *ov01a10 = to_ov01a10(sd);
 698         const struct ov01a10_mode *mode;
 699         struct v4l2_mbus_framefmt *format;
 700         s32 vblank_def, h_blank;
 701
 702         mode = v4l2_find_nearest_size(supported_modes,
 703                                       ARRAY_SIZE(supported_modes), width,
 704                                       height, fmt->format.width,
 705                                       fmt->format.height);
 706
 707         ov01a10_update_pad_format(mode, &fmt->format);
 708
 709         if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
 710                 ov01a10->cur_mode = mode;
 711                 __v4l2_ctrl_s_ctrl(ov01a10->link_freq, mode->link_freq_index);
 712                 __v4l2_ctrl_s_ctrl_int64(ov01a10->pixel_rate, OV01A10_SCLK);
 713
 714                 vblank_def = mode->vts_def - mode->height;
 715                 __v4l2_ctrl_modify_range(ov01a10->vblank,
 716                                          mode->vts_min - mode->height,
 717                                          OV01A10_VTS_MAX - mode->height, 1,
 718                                          vblank_def);
 719                 __v4l2_ctrl_s_ctrl(ov01a10->vblank, vblank_def);
 720                 h_blank = mode->hts - mode->width;
 721                 __v4l2_ctrl_modify_range(ov01a10->hblank, h_blank, h_blank, 1,
 722                                          h_blank);
 723         }
 724
 725         format = v4l2_subdev_state_get_format(sd_state, fmt->stream);
 726         *format = fmt->format;
 727
 728         return 0;
 729 }
 730
 731 static int ov01a10_init_state(struct v4l2_subdev *sd,
 732                               struct v4l2_subdev_state *state)
 733 {
 734         struct v4l2_subdev_format fmt = {
 735                 .which = V4L2_SUBDEV_FORMAT_TRY,
 736                 .format = {
 737                         .width = OV01A10_ACITVE_WIDTH,
 738                         .height = OV01A10_ACITVE_HEIGHT,
 739                 },
 740         };
 741
 742         ov01a10_set_format(sd, state, &fmt);
 743
 744         return 0;
 745 }
 746
 747 static int ov01a10_enum_mbus_code(struct v4l2_subdev *sd,
 748                                   struct v4l2_subdev_state *sd_state,
 749                                   struct v4l2_subdev_mbus_code_enum *code)
 750 {
 751         if (code->index > 0)
 752                 return -EINVAL;
 753
 754         code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
 755
 756         return 0;
 757 }
 758
 759 static int ov01a10_enum_frame_size(struct v4l2_subdev *sd,
 760                                    struct v4l2_subdev_state *sd_state,
 761                                    struct v4l2_subdev_frame_size_enum *fse)
 762 {
 763         if (fse->index >= ARRAY_SIZE(supported_modes) ||
 764             fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
 765                 return -EINVAL;
 766
 767         fse->min_width = supported_modes[fse->index].width;
 768         fse->max_width = fse->min_width;
 769         fse->min_height = supported_modes[fse->index].height;
 770         fse->max_height = fse->min_height;
 771
 772         return 0;
 773 }
 774
 775 static int ov01a10_get_selection(struct v4l2_subdev *sd,
 776                                  struct v4l2_subdev_state *state,
 777                                  struct v4l2_subdev_selection *sel)
 778 {
 779         if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
 780                 return -EINVAL;
 781
 782         switch (sel->target) {
 783         case V4L2_SEL_TGT_NATIVE_SIZE:
 784         case V4L2_SEL_TGT_CROP_BOUNDS:
 785                 sel->r.top = 0;
 786                 sel->r.left = 0;
 787                 sel->r.width = OV01A10_PIXEL_ARRAY_WIDTH;
 788                 sel->r.height = OV01A10_PIXEL_ARRAY_HEIGHT;
 789                 return 0;
 790         case V4L2_SEL_TGT_CROP:
 791         case V4L2_SEL_TGT_CROP_DEFAULT:
 792                 sel->r.top = (OV01A10_PIXEL_ARRAY_HEIGHT -
 793                               OV01A10_ACITVE_HEIGHT) / 2;
 794                 sel->r.left = (OV01A10_PIXEL_ARRAY_WIDTH -
 795                                OV01A10_ACITVE_WIDTH) / 2;
 796                 sel->r.width = OV01A10_ACITVE_WIDTH;
 797                 sel->r.height = OV01A10_ACITVE_HEIGHT;
 798                 return 0;
 799         }
 800
 801         return -EINVAL;
 802 }
 803
 804 static const struct v4l2_subdev_core_ops ov01a10_core_ops = {
 805         .log_status = v4l2_ctrl_subdev_log_status,
 806 };
 807
 808 static const struct v4l2_subdev_video_ops ov01a10_video_ops = {
 809         .s_stream = ov01a10_set_stream,
 810 };
 811
 812 static const struct v4l2_subdev_pad_ops ov01a10_pad_ops = {
 813         .set_fmt = ov01a10_set_format,
 814         .get_fmt = v4l2_subdev_get_fmt,
 815         .get_selection = ov01a10_get_selection,
 816         .enum_mbus_code = ov01a10_enum_mbus_code,
 817         .enum_frame_size = ov01a10_enum_frame_size,
 818 };
 819
 820 static const struct v4l2_subdev_ops ov01a10_subdev_ops = {
 821         .core = &ov01a10_core_ops,
 822         .video = &ov01a10_video_ops,
 823         .pad = &ov01a10_pad_ops,
 824 };
 825
 826 static const struct v4l2_subdev_internal_ops ov01a10_internal_ops = {
 827         .init_state = ov01a10_init_state,
 828 };
 829
 830 static const struct media_entity_operations ov01a10_subdev_entity_ops = {
 831         .link_validate = v4l2_subdev_link_validate,
 832 };
 833
 834 static int ov01a10_identify_module(struct ov01a10 *ov01a10)
 835 {
 836         struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
 837         int ret;
 838         u32 val;
 839
 840         ret = ov01a10_read_reg(ov01a10, OV01A10_REG_CHIP_ID, 3, &val);
 841         if (ret)
 842                 return ret;
 843
 844         if (val != OV01A10_CHIP_ID) {
 845                 dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
 846                         OV01A10_CHIP_ID, val);
 847                 return -EIO;
 848         }
 849
 850         return 0;
 851 }
 852
 853 static void ov01a10_remove(struct i2c_client *client)
 854 {
 855         struct v4l2_subdev *sd = i2c_get_clientdata(client);
 856
 857         v4l2_async_unregister_subdev(sd);
 858         media_entity_cleanup(&sd->entity);
 859         v4l2_ctrl_handler_free(sd->ctrl_handler);
 860
 861         pm_runtime_disable(&client->dev);
 862         pm_runtime_set_suspended(&client->dev);
 863 }
 864
 865 static int ov01a10_probe(struct i2c_client *client)
 866 {
 867         struct device *dev = &client->dev;
 868         struct ov01a10 *ov01a10;
 869         int ret = 0;
 870
 871         ov01a10 = devm_kzalloc(dev, sizeof(*ov01a10), GFP_KERNEL);
 872         if (!ov01a10)
 873                 return -ENOMEM;
 874
 875         v4l2_i2c_subdev_init(&ov01a10->sd, client, &ov01a10_subdev_ops);
 876         ov01a10->sd.internal_ops = &ov01a10_internal_ops;
 877
 878         ret = ov01a10_identify_module(ov01a10);
 879         if (ret)
 880                 return dev_err_probe(dev, ret,
 881                                      "failed to find sensor\n");
 882
 883         ov01a10->cur_mode = &supported_modes[0];
 884
 885         ret = ov01a10_init_controls(ov01a10);
 886         if (ret) {
 887                 dev_err(dev, "failed to init controls: %d\n", ret);
 888                 return ret;
 889         }
 890
 891         ov01a10->sd.state_lock = ov01a10->ctrl_handler.lock;
 892         ov01a10->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
 893         ov01a10->sd.entity.ops = &ov01a10_subdev_entity_ops;
 894         ov01a10->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
 895         ov01a10->pad.flags = MEDIA_PAD_FL_SOURCE;
 896
 897         ret = media_entity_pads_init(&ov01a10->sd.entity, 1, &ov01a10->pad);
 898         if (ret) {
 899                 dev_err(dev, "Failed to init entity pads: %d\n", ret);
 900                 goto err_handler_free;
 901         }
 902
 903         ret = v4l2_subdev_init_finalize(&ov01a10->sd);
 904         if (ret) {
 905                 dev_err(dev, "Failed to allocate subdev state: %d\n", ret);
 906                 goto err_media_entity_cleanup;
 907         }
 908
 909         /*
 910          * Device is already turned on by i2c-core with ACPI domain PM.
 911          * Enable runtime PM and turn off the device.
 912          */
 913         pm_runtime_set_active(&client->dev);
 914         pm_runtime_enable(dev);
 915         pm_runtime_idle(dev);
 916
 917         ret = v4l2_async_register_subdev_sensor(&ov01a10->sd);
 918         if (ret < 0) {
 919                 dev_err(dev, "Failed to register subdev: %d\n", ret);
 920                 goto err_pm_disable;
 921         }
 922
 923         return 0;
 924
 925 err_pm_disable:
 926         pm_runtime_disable(dev);
 927         pm_runtime_set_suspended(&client->dev);
 928
 929 err_media_entity_cleanup:
 930         media_entity_cleanup(&ov01a10->sd.entity);
 931
 932 err_handler_free:
 933         v4l2_ctrl_handler_free(ov01a10->sd.ctrl_handler);
 934
 935         return ret;
 936 }
 937
 938 #ifdef CONFIG_ACPI
 939 static const struct acpi_device_id ov01a10_acpi_ids[] = {
 940         { "OVTI01A0" },
 941         { }
 942 };
 943
 944 MODULE_DEVICE_TABLE(acpi, ov01a10_acpi_ids);
 945 #endif
 946
 947 static struct i2c_driver ov01a10_i2c_driver = {
 948         .driver = {
 949                 .name = "ov01a10",
 950                 .acpi_match_table = ACPI_PTR(ov01a10_acpi_ids),
 951         },
 952         .probe = ov01a10_probe,
 953         .remove = ov01a10_remove,
 954 };
 955
 956 module_i2c_driver(ov01a10_i2c_driver);
 957
 958 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>");
 959 MODULE_AUTHOR("Wang Yating <yating.wang@intel.com>");
 960 MODULE_DESCRIPTION("OmniVision OV01A10 sensor driver");
 961 MODULE_LICENSE("GPL");