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Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / media / i2c / ov4689.c
blob1c3a449f935462400001aa46a4be2c391ca0e300
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ov4689 driver
4 *
5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6 * Copyright (C) 2022, 2024 Mikhail Rudenko
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/i2c.h>
13 #include <linux/module.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regulator/consumer.h>
16 #include <media/media-entity.h>
17 #include <media/v4l2-async.h>
18 #include <media/v4l2-cci.h>
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-subdev.h>
21 #include <media/v4l2-fwnode.h>
22
23 #define OV4689_REG_CTRL_MODE CCI_REG8(0x0100)
24 #define OV4689_MODE_SW_STANDBY 0x0
25 #define OV4689_MODE_STREAMING BIT(0)
26
27 #define OV4689_REG_CHIP_ID CCI_REG16(0x300a)
28 #define CHIP_ID 0x004688
29
30 #define OV4689_REG_EXPOSURE CCI_REG24(0x3500)
31 #define OV4689_EXPOSURE_MIN 4
32 #define OV4689_EXPOSURE_STEP 1
33
34 #define OV4689_REG_GAIN CCI_REG16(0x3508)
35 #define OV4689_GAIN_STEP 1
36 #define OV4689_GAIN_DEFAULT 0x80
37
38 #define OV4689_REG_DIG_GAIN CCI_REG16(0x352a)
39 #define OV4689_DIG_GAIN_MIN 1
40 #define OV4689_DIG_GAIN_MAX 0x7fff
41 #define OV4689_DIG_GAIN_STEP 1
42 #define OV4689_DIG_GAIN_DEFAULT 0x800
43
44 #define OV4689_REG_H_CROP_START CCI_REG16(0x3800)
45 #define OV4689_REG_V_CROP_START CCI_REG16(0x3802)
46 #define OV4689_REG_H_CROP_END CCI_REG16(0x3804)
47 #define OV4689_REG_V_CROP_END CCI_REG16(0x3806)
48 #define OV4689_REG_H_OUTPUT_SIZE CCI_REG16(0x3808)
49 #define OV4689_REG_V_OUTPUT_SIZE CCI_REG16(0x380a)
50
51 #define OV4689_REG_HTS CCI_REG16(0x380c)
52 #define OV4689_HTS_DIVIDER 4
53 #define OV4689_HTS_MAX 0x7fff
54
55 #define OV4689_REG_VTS CCI_REG16(0x380e)
56 #define OV4689_VTS_MAX 0x7fff
57
58 #define OV4689_REG_H_WIN_OFF CCI_REG16(0x3810)
59 #define OV4689_REG_V_WIN_OFF CCI_REG16(0x3812)
60
61 #define OV4689_REG_TIMING_FORMAT1 CCI_REG8(0x3820) /* Vertical */
62 #define OV4689_REG_TIMING_FORMAT2 CCI_REG8(0x3821) /* Horizontal */
63 #define OV4689_TIMING_FLIP_MASK GENMASK(2, 1)
64 #define OV4689_TIMING_FLIP_ARRAY BIT(1)
65 #define OV4689_TIMING_FLIP_DIGITAL BIT(2)
66 #define OV4689_TIMING_FLIP_BOTH (OV4689_TIMING_FLIP_ARRAY |\
67 OV4689_TIMING_FLIP_DIGITAL)
68
69 #define OV4689_REG_ANCHOR_LEFT_START CCI_REG16(0x4020)
70 #define OV4689_ANCHOR_LEFT_START_DEF 576
71 #define OV4689_REG_ANCHOR_LEFT_END CCI_REG16(0x4022)
72 #define OV4689_ANCHOR_LEFT_END_DEF 831
73 #define OV4689_REG_ANCHOR_RIGHT_START CCI_REG16(0x4024)
74 #define OV4689_ANCHOR_RIGHT_START_DEF 1984
75 #define OV4689_REG_ANCHOR_RIGHT_END CCI_REG16(0x4026)
76 #define OV4689_ANCHOR_RIGHT_END_DEF 2239
77
78 #define OV4689_REG_VFIFO_CTRL_01 CCI_REG8(0x4601)
79
80 #define OV4689_REG_WB_GAIN_RED CCI_REG16(0x500c)
81 #define OV4689_REG_WB_GAIN_BLUE CCI_REG16(0x5010)
82 #define OV4689_WB_GAIN_MIN 1
83 #define OV4689_WB_GAIN_MAX 0xfff
84 #define OV4689_WB_GAIN_STEP 1
85 #define OV4689_WB_GAIN_DEFAULT 0x400
86
87 #define OV4689_REG_TEST_PATTERN CCI_REG8(0x5040)
88 #define OV4689_TEST_PATTERN_ENABLE 0x80
89 #define OV4689_TEST_PATTERN_DISABLE 0x0
90
91 #define OV4689_LANES 4
92 #define OV4689_XVCLK_FREQ 24000000
93
94 #define OV4689_PIXEL_ARRAY_WIDTH 2720
95 #define OV4689_PIXEL_ARRAY_HEIGHT 1536
96 #define OV4689_DUMMY_ROWS 8 /* 8 dummy rows on each side */
97 #define OV4689_DUMMY_COLUMNS 16 /* 16 dummy columns on each side */
98
99 static const char *const ov4689_supply_names[] = {
100 "avdd", /* Analog power */
101 "dovdd", /* Digital I/O power */
102 "dvdd", /* Digital core power */
103 };
104
105 enum ov4689_mode_id {
106 OV4689_MODE_2688_1520 = 0,
107 OV4689_NUM_MODES,
108 };
109
110 struct ov4689_mode {
111 enum ov4689_mode_id id;
112 u32 width;
113 u32 height;
114 u32 hts_def;
115 u32 hts_min;
116 u32 vts_def;
117 u32 exp_def;
118 u32 pixel_rate;
119 const struct cci_reg_sequence *reg_list;
120 unsigned int num_regs;
121 };
122
123 struct ov4689 {
124 struct device *dev;
125 struct regmap *regmap;
126 struct clk *xvclk;
127 struct gpio_desc *reset_gpio;
128 struct gpio_desc *pwdn_gpio;
129 struct regulator_bulk_data supplies[ARRAY_SIZE(ov4689_supply_names)];
130
131 struct v4l2_subdev subdev;
132 struct media_pad pad;
133
134 u32 clock_rate;
135
136 struct v4l2_ctrl_handler ctrl_handler;
137 struct v4l2_ctrl *exposure;
138
139 const struct ov4689_mode *cur_mode;
140 };
141
142 #define to_ov4689(sd) container_of(sd, struct ov4689, subdev)
143
144 struct ov4689_gain_range {
145 u32 logical_min;
146 u32 logical_max;
147 u32 offset;
148 u32 divider;
149 u32 physical_min;
150 u32 physical_max;
151 };
152
153 /*
154 * Xclk 24Mhz
155 * max_framerate 90fps
156 * mipi_datarate per lane 1008Mbps
157 */
158 static const struct cci_reg_sequence ov4689_2688x1520_regs[] = {
159 /* System control*/
160 { CCI_REG8(0x0103), 0x01 }, /* SC_CTRL0103 software_reset = 1 */
161 { CCI_REG8(0x3000), 0x20 }, /* SC_CMMN_PAD_OEN0 FSIN_output_enable = 1 */
162 { CCI_REG8(0x3021), 0x03 }, /*
163 * SC_CMMN_MISC_CTRL fst_stby_ctr = 0,
164 * sleep_no_latch_enable = 0
165 */
166
167 /* AEC PK */
168 { CCI_REG8(0x3503), 0x04 }, /* AEC_MANUAL gain_input_as_sensor_gain_format = 1 */
169
170 /* ADC and analog control*/
171 { CCI_REG8(0x3603), 0x40 },
172 { CCI_REG8(0x3604), 0x02 },
173 { CCI_REG8(0x3609), 0x12 },
174 { CCI_REG8(0x360c), 0x08 },
175 { CCI_REG8(0x360f), 0xe5 },
176 { CCI_REG8(0x3608), 0x8f },
177 { CCI_REG8(0x3611), 0x00 },
178 { CCI_REG8(0x3613), 0xf7 },
179 { CCI_REG8(0x3616), 0x58 },
180 { CCI_REG8(0x3619), 0x99 },
181 { CCI_REG8(0x361b), 0x60 },
182 { CCI_REG8(0x361e), 0x79 },
183 { CCI_REG8(0x3634), 0x10 },
184 { CCI_REG8(0x3635), 0x10 },
185 { CCI_REG8(0x3636), 0x15 },
186 { CCI_REG8(0x3646), 0x86 },
187 { CCI_REG8(0x364a), 0x0b },
188
189 /* Sensor control */
190 { CCI_REG8(0x3700), 0x17 },
191 { CCI_REG8(0x3701), 0x22 },
192 { CCI_REG8(0x3703), 0x10 },
193 { CCI_REG8(0x370a), 0x37 },
194 { CCI_REG8(0x3706), 0x63 },
195 { CCI_REG8(0x3709), 0x3c },
196 { CCI_REG8(0x370c), 0x30 },
197 { CCI_REG8(0x3710), 0x24 },
198 { CCI_REG8(0x3720), 0x28 },
199 { CCI_REG8(0x3729), 0x7b },
200 { CCI_REG8(0x372b), 0xbd },
201 { CCI_REG8(0x372c), 0xbc },
202 { CCI_REG8(0x372e), 0x52 },
203 { CCI_REG8(0x373c), 0x0e },
204 { CCI_REG8(0x373e), 0x33 },
205 { CCI_REG8(0x3743), 0x10 },
206 { CCI_REG8(0x3744), 0x88 },
207 { CCI_REG8(0x3745), 0xc0 },
208 { CCI_REG8(0x374c), 0x00 },
209 { CCI_REG8(0x374e), 0x23 },
210 { CCI_REG8(0x3751), 0x7b },
211 { CCI_REG8(0x3753), 0xbd },
212 { CCI_REG8(0x3754), 0xbc },
213 { CCI_REG8(0x3756), 0x52 },
214 { CCI_REG8(0x376b), 0x20 },
215 { CCI_REG8(0x3774), 0x51 },
216 { CCI_REG8(0x3776), 0xbd },
217 { CCI_REG8(0x3777), 0xbd },
218 { CCI_REG8(0x3781), 0x18 },
219 { CCI_REG8(0x3783), 0x25 },
220 { CCI_REG8(0x3798), 0x1b },
221
222 /* Timing control */
223 { CCI_REG8(0x3819), 0x01 }, /* VSYNC_END_L vsync_end_point[7:0] = 0x01 */
224
225 /* OTP control */
226 { CCI_REG8(0x3d85), 0x36 }, /* OTP_REG85 OTP_power_up_load_setting_enable = 1,
227 * OTP_power_up_load_data_enable = 1,
228 * OTP_bist_select = 1 (compare with zero)
229 */
230 { CCI_REG8(0x3d8c), 0x71 }, /* OTP_SETTING_STT_ADDRESS_H */
231 { CCI_REG8(0x3d8d), 0xcb }, /* OTP_SETTING_STT_ADDRESS_L */
232
233 /* BLC registers*/
234 { CCI_REG8(0x4001), 0x40 }, /* DEBUG_MODE */
235 { CCI_REG8(0x401b), 0x00 }, /* DEBUG_MODE */
236 { CCI_REG8(0x401d), 0x00 }, /* DEBUG_MODE */
237 { CCI_REG8(0x401f), 0x00 }, /* DEBUG_MODE */
238
239 /* ADC sync control */
240 { CCI_REG8(0x4500), 0x6c }, /* ADC_SYNC_CTRL */
241 { CCI_REG8(0x4503), 0x01 }, /* ADC_SYNC_CTRL */
242
243 /* Temperature monitor */
244 { CCI_REG8(0x4d00), 0x04 }, /* TPM_CTRL_00 tmp_slope[15:8] = 0x04 */
245 { CCI_REG8(0x4d01), 0x42 }, /* TPM_CTRL_01 tmp_slope[7:0] = 0x42 */
246 { CCI_REG8(0x4d02), 0xd1 }, /* TPM_CTRL_02 tpm_offset[31:24] = 0xd1 */
247 { CCI_REG8(0x4d03), 0x93 }, /* TPM_CTRL_03 tpm_offset[23:16] = 0x93 */
248 { CCI_REG8(0x4d04), 0xf5 }, /* TPM_CTRL_04 tpm_offset[15:8] = 0xf5 */
249 { CCI_REG8(0x4d05), 0xc1 }, /* TPM_CTRL_05 tpm_offset[7:0] = 0xc1 */
250
251 /* pre-ISP control */
252 { CCI_REG8(0x5050), 0x0c }, /* DEBUG_MODE */
253
254 /* OTP-DPC control */
255 { CCI_REG8(0x5501), 0x10 }, /* OTP_DPC_START_L otp_start_address[7:0] = 0x10 */
256 { CCI_REG8(0x5503), 0x0f }, /* OTP_DPC_END_L otp_end_address[7:0] = 0x0f */
257 };
258
259 static const struct ov4689_mode supported_modes[] = {
260 {
261 .id = OV4689_MODE_2688_1520,
262 .width = 2688,
263 .height = 1520,
264 .exp_def = 1536,
265 .hts_def = 10296,
266 .hts_min = 3432,
267 .vts_def = 1554,
268 .pixel_rate = 480000000,
269 .reg_list = ov4689_2688x1520_regs,
270 .num_regs = ARRAY_SIZE(ov4689_2688x1520_regs),
271 },
272 };
273
274 static const u64 link_freq_menu_items[] = { 504000000 };
275
276 static const char *const ov4689_test_pattern_menu[] = {
277 "Disabled",
278 "Vertical Color Bar Type 1",
279 "Vertical Color Bar Type 2",
280 "Vertical Color Bar Type 3",
281 "Vertical Color Bar Type 4"
282 };
283
284 /*
285 * These coefficients are based on those used in Rockchip's camera
286 * engine, with minor tweaks for continuity.
287 */
288 static const struct ov4689_gain_range ov4689_gain_ranges[] = {
289 {
290 .logical_min = 0,
291 .logical_max = 255,
292 .offset = 0,
293 .divider = 1,
294 .physical_min = 0,
295 .physical_max = 255,
296 },
297 {
298 .logical_min = 256,
299 .logical_max = 511,
300 .offset = 252,
301 .divider = 2,
302 .physical_min = 376,
303 .physical_max = 504,
304 },
305 {
306 .logical_min = 512,
307 .logical_max = 1023,
308 .offset = 758,
309 .divider = 4,
310 .physical_min = 884,
311 .physical_max = 1012,
312 },
313 {
314 .logical_min = 1024,
315 .logical_max = 2047,
316 .offset = 1788,
317 .divider = 8,
318 .physical_min = 1912,
319 .physical_max = 2047,
320 },
321 };
322
323 static void ov4689_fill_fmt(const struct ov4689_mode *mode,
324 struct v4l2_mbus_framefmt *fmt)
325 {
326 fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
327 fmt->width = mode->width;
328 fmt->height = mode->height;
329 fmt->field = V4L2_FIELD_NONE;
330 }
331
332 static int ov4689_set_fmt(struct v4l2_subdev *sd,
333 struct v4l2_subdev_state *sd_state,
334 struct v4l2_subdev_format *fmt)
335 {
336 struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format;
337 struct ov4689 *ov4689 = to_ov4689(sd);
338
339 /* only one mode supported for now */
340 ov4689_fill_fmt(ov4689->cur_mode, mbus_fmt);
341
342 return 0;
343 }
344
345 static int ov4689_enum_mbus_code(struct v4l2_subdev *sd,
346 struct v4l2_subdev_state *sd_state,
347 struct v4l2_subdev_mbus_code_enum *code)
348 {
349 if (code->index != 0)
350 return -EINVAL;
351 code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
352
353 return 0;
354 }
355
356 static int ov4689_enum_frame_sizes(struct v4l2_subdev *sd,
357 struct v4l2_subdev_state *sd_state,
358 struct v4l2_subdev_frame_size_enum *fse)
359 {
360 if (fse->index >= ARRAY_SIZE(supported_modes))
361 return -EINVAL;
362
363 if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
364 return -EINVAL;
365
366 fse->min_width = supported_modes[fse->index].width;
367 fse->max_width = supported_modes[fse->index].width;
368 fse->max_height = supported_modes[fse->index].height;
369 fse->min_height = supported_modes[fse->index].height;
370
371 return 0;
372 }
373
374 static int ov4689_enable_test_pattern(struct ov4689 *ov4689, u32 pattern)
375 {
376 u32 val;
377
378 if (pattern)
379 val = (pattern - 1) | OV4689_TEST_PATTERN_ENABLE;
380 else
381 val = OV4689_TEST_PATTERN_DISABLE;
382
383 return cci_write(ov4689->regmap, OV4689_REG_TEST_PATTERN,
384 val, NULL);
385 }
386
387 static int ov4689_get_selection(struct v4l2_subdev *sd,
388 struct v4l2_subdev_state *state,
389 struct v4l2_subdev_selection *sel)
390 {
391 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
392 return -EINVAL;
393
394 switch (sel->target) {
395 case V4L2_SEL_TGT_CROP_BOUNDS:
396 sel->r.top = 0;
397 sel->r.left = 0;
398 sel->r.width = OV4689_PIXEL_ARRAY_WIDTH;
399 sel->r.height = OV4689_PIXEL_ARRAY_HEIGHT;
400 return 0;
401 case V4L2_SEL_TGT_CROP:
402 case V4L2_SEL_TGT_CROP_DEFAULT:
403 sel->r.top = OV4689_DUMMY_ROWS;
404 sel->r.left = OV4689_DUMMY_COLUMNS;
405 sel->r.width =
406 OV4689_PIXEL_ARRAY_WIDTH - 2 * OV4689_DUMMY_COLUMNS;
407 sel->r.height =
408 OV4689_PIXEL_ARRAY_HEIGHT - 2 * OV4689_DUMMY_ROWS;
409 return 0;
410 }
411
412 return -EINVAL;
413 }
414
415 static int ov4689_setup_timings(struct ov4689 *ov4689)
416 {
417 const struct ov4689_mode *mode = ov4689->cur_mode;
418 struct regmap *rm = ov4689->regmap;
419 int ret = 0;
420
421 cci_write(rm, OV4689_REG_H_CROP_START, 8, &ret);
422 cci_write(rm, OV4689_REG_V_CROP_START, 8, &ret);
423 cci_write(rm, OV4689_REG_H_CROP_END, 2711, &ret);
424 cci_write(rm, OV4689_REG_V_CROP_END, 1531, &ret);
425
426 cci_write(rm, OV4689_REG_H_OUTPUT_SIZE, mode->width, &ret);
427 cci_write(rm, OV4689_REG_V_OUTPUT_SIZE, mode->height, &ret);
428
429 cci_write(rm, OV4689_REG_H_WIN_OFF, 8, &ret);
430 cci_write(rm, OV4689_REG_V_WIN_OFF, 4, &ret);
431
432 cci_write(rm, OV4689_REG_VFIFO_CTRL_01, 167, &ret);
433
434 return ret;
435 }
436
437 static int ov4689_setup_blc_anchors(struct ov4689 *ov4689)
438 {
439 struct regmap *rm = ov4689->regmap;
440 int ret = 0;
441
442 cci_write(rm, OV4689_REG_ANCHOR_LEFT_START, 16, &ret);
443 cci_write(rm, OV4689_REG_ANCHOR_LEFT_END, 1999, &ret);
444 cci_write(rm, OV4689_REG_ANCHOR_RIGHT_START, 2400, &ret);
445 cci_write(rm, OV4689_REG_ANCHOR_RIGHT_END, 2415, &ret);
446
447 return ret;
448 }
449
450 static int ov4689_s_stream(struct v4l2_subdev *sd, int on)
451 {
452 struct ov4689 *ov4689 = to_ov4689(sd);
453 struct v4l2_subdev_state *sd_state;
454 struct device *dev = ov4689->dev;
455 int ret = 0;
456
457 sd_state = v4l2_subdev_lock_and_get_active_state(&ov4689->subdev);
458
459 if (on) {
460 ret = pm_runtime_resume_and_get(dev);
461 if (ret < 0)
462 goto unlock_and_return;
463
464 ret = cci_multi_reg_write(ov4689->regmap,
465 ov4689->cur_mode->reg_list,
466 ov4689->cur_mode->num_regs,
467 NULL);
468 if (ret) {
469 pm_runtime_put(dev);
470 goto unlock_and_return;
471 }
472
473 ret = ov4689_setup_timings(ov4689);
474 if (ret) {
475 pm_runtime_put(dev);
476 goto unlock_and_return;
477 }
478
479 ret = ov4689_setup_blc_anchors(ov4689);
480 if (ret) {
481 pm_runtime_put(dev);
482 goto unlock_and_return;
483 }
484
485 ret = __v4l2_ctrl_handler_setup(&ov4689->ctrl_handler);
486 if (ret) {
487 pm_runtime_put(dev);
488 goto unlock_and_return;
489 }
490
491 ret = cci_write(ov4689->regmap, OV4689_REG_CTRL_MODE,
492 OV4689_MODE_STREAMING, NULL);
493 if (ret) {
494 pm_runtime_put(dev);
495 goto unlock_and_return;
496 }
497 } else {
498 cci_write(ov4689->regmap, OV4689_REG_CTRL_MODE,
499 OV4689_MODE_SW_STANDBY, NULL);
500 pm_runtime_mark_last_busy(dev);
501 pm_runtime_put_autosuspend(dev);
502 }
503
504 unlock_and_return:
505 v4l2_subdev_unlock_state(sd_state);
506
507 return ret;
508 }
509
510 /* Calculate the delay in us by clock rate and clock cycles */
511 static inline u32 ov4689_cal_delay(struct ov4689 *ov4689, u32 cycles)
512 {
513 return DIV_ROUND_UP(cycles * 1000,
514 DIV_ROUND_UP(ov4689->clock_rate, 1000));
515 }
516
517 static int __maybe_unused ov4689_power_on(struct device *dev)
518 {
519 struct v4l2_subdev *sd = dev_get_drvdata(dev);
520 struct ov4689 *ov4689 = to_ov4689(sd);
521 u32 delay_us;
522 int ret;
523
524 ret = clk_prepare_enable(ov4689->xvclk);
525 if (ret < 0) {
526 dev_err(dev, "Failed to enable xvclk\n");
527 return ret;
528 }
529
530 gpiod_set_value_cansleep(ov4689->reset_gpio, 1);
531
532 ret = regulator_bulk_enable(ARRAY_SIZE(ov4689_supply_names),
533 ov4689->supplies);
534 if (ret < 0) {
535 dev_err(dev, "Failed to enable regulators\n");
536 goto disable_clk;
537 }
538
539 gpiod_set_value_cansleep(ov4689->reset_gpio, 0);
540 usleep_range(500, 1000);
541 gpiod_set_value_cansleep(ov4689->pwdn_gpio, 0);
542
543 /* 8192 cycles prior to first SCCB transaction */
544 delay_us = ov4689_cal_delay(ov4689, 8192);
545 usleep_range(delay_us, delay_us * 2);
546
547 return 0;
548
549 disable_clk:
550 clk_disable_unprepare(ov4689->xvclk);
551
552 return ret;
553 }
554
555 static int __maybe_unused ov4689_power_off(struct device *dev)
556 {
557 struct v4l2_subdev *sd = dev_get_drvdata(dev);
558 struct ov4689 *ov4689 = to_ov4689(sd);
559
560 gpiod_set_value_cansleep(ov4689->pwdn_gpio, 1);
561 clk_disable_unprepare(ov4689->xvclk);
562 gpiod_set_value_cansleep(ov4689->reset_gpio, 1);
563 regulator_bulk_disable(ARRAY_SIZE(ov4689_supply_names),
564 ov4689->supplies);
565 return 0;
566 }
567
568 static int ov4689_init_state(struct v4l2_subdev *sd,
569 struct v4l2_subdev_state *sd_state)
570 {
571 struct v4l2_mbus_framefmt *fmt =
572 v4l2_subdev_state_get_format(sd_state, 0);
573
574 ov4689_fill_fmt(&supported_modes[OV4689_MODE_2688_1520], fmt);
575
576 return 0;
577 }
578
579 static const struct dev_pm_ops ov4689_pm_ops = {
580 SET_RUNTIME_PM_OPS(ov4689_power_off, ov4689_power_on, NULL)
581 };
582
583 static const struct v4l2_subdev_video_ops ov4689_video_ops = {
584 .s_stream = ov4689_s_stream,
585 };
586
587 static const struct v4l2_subdev_pad_ops ov4689_pad_ops = {
588 .enum_mbus_code = ov4689_enum_mbus_code,
589 .enum_frame_size = ov4689_enum_frame_sizes,
590 .get_fmt = v4l2_subdev_get_fmt,
591 .set_fmt = ov4689_set_fmt,
592 .get_selection = ov4689_get_selection,
593 };
594
595 static const struct v4l2_subdev_internal_ops ov4689_internal_ops = {
596 .init_state = ov4689_init_state,
597 };
598
599 static const struct v4l2_subdev_ops ov4689_subdev_ops = {
600 .video = &ov4689_video_ops,
601 .pad = &ov4689_pad_ops,
602 };
603
604 /*
605 * Map userspace (logical) gain to sensor (physical) gain using
606 * ov4689_gain_ranges table.
607 */
608 static int ov4689_map_gain(struct ov4689 *ov4689, int logical_gain, int *result)
609 {
610 const struct ov4689_gain_range *range;
611 unsigned int n;
612
613 for (n = 0; n < ARRAY_SIZE(ov4689_gain_ranges); n++) {
614 if (logical_gain >= ov4689_gain_ranges[n].logical_min &&
615 logical_gain <= ov4689_gain_ranges[n].logical_max)
616 break;
617 }
618
619 if (n == ARRAY_SIZE(ov4689_gain_ranges)) {
620 dev_warn_ratelimited(ov4689->dev,
621 "no mapping found for gain %d\n",
622 logical_gain);
623 return -EINVAL;
624 }
625
626 range = &ov4689_gain_ranges[n];
627
628 *result = clamp(range->offset + (logical_gain) / range->divider,
629 range->physical_min, range->physical_max);
630 return 0;
631 }
632
633 static int ov4689_set_ctrl(struct v4l2_ctrl *ctrl)
634 {
635 struct ov4689 *ov4689 =
636 container_of(ctrl->handler, struct ov4689, ctrl_handler);
637 struct regmap *regmap = ov4689->regmap;
638 struct device *dev = ov4689->dev;
639 int sensor_gain = 0;
640 s64 max_expo;
641 int ret = 0;
642
643 /* Propagate change of current control to all related controls */
644 switch (ctrl->id) {
645 case V4L2_CID_VBLANK:
646 /* Update max exposure while meeting expected vblanking */
647 max_expo = ov4689->cur_mode->height + ctrl->val - 4;
648 __v4l2_ctrl_modify_range(ov4689->exposure,
649 ov4689->exposure->minimum, max_expo,
650 ov4689->exposure->step,
651 ov4689->exposure->default_value);
652 break;
653 }
654
655 if (!pm_runtime_get_if_in_use(dev))
656 return 0;
657
658 switch (ctrl->id) {
659 case V4L2_CID_EXPOSURE:
660 /* 4 least significant bits of exposure are fractional part */
661 cci_write(regmap, OV4689_REG_EXPOSURE, ctrl->val << 4, &ret);
662 break;
663 case V4L2_CID_ANALOGUE_GAIN:
664 ret = ov4689_map_gain(ov4689, ctrl->val, &sensor_gain);
665 cci_write(regmap, OV4689_REG_GAIN, sensor_gain, &ret);
666 break;
667 case V4L2_CID_VBLANK:
668 cci_write(regmap, OV4689_REG_VTS,
669 ctrl->val + ov4689->cur_mode->height, &ret);
670 break;
671 case V4L2_CID_TEST_PATTERN:
672 ret = ov4689_enable_test_pattern(ov4689, ctrl->val);
673 break;
674 case V4L2_CID_HBLANK:
675 cci_write(regmap, OV4689_REG_HTS,
676 (ctrl->val + ov4689->cur_mode->width) /
677 OV4689_HTS_DIVIDER, &ret);
678 break;
679 case V4L2_CID_VFLIP:
680 cci_update_bits(regmap, OV4689_REG_TIMING_FORMAT1,
681 OV4689_TIMING_FLIP_MASK,
682 ctrl->val ? OV4689_TIMING_FLIP_BOTH : 0, &ret);
683 break;
684 case V4L2_CID_HFLIP:
685 cci_update_bits(regmap, OV4689_REG_TIMING_FORMAT2,
686 OV4689_TIMING_FLIP_MASK,
687 ctrl->val ? 0 : OV4689_TIMING_FLIP_BOTH, &ret);
688 break;
689 case V4L2_CID_DIGITAL_GAIN:
690 cci_write(regmap, OV4689_REG_DIG_GAIN, ctrl->val, &ret);
691 break;
692 case V4L2_CID_RED_BALANCE:
693 cci_write(regmap, OV4689_REG_WB_GAIN_RED, ctrl->val, &ret);
694 break;
695 case V4L2_CID_BLUE_BALANCE:
696 cci_write(regmap, OV4689_REG_WB_GAIN_BLUE, ctrl->val, &ret);
697 break;
698 default:
699 dev_warn(dev, "%s Unhandled id:0x%x, val:0x%x\n",
700 __func__, ctrl->id, ctrl->val);
701 ret = -EINVAL;
702 break;
703 }
704
705 pm_runtime_mark_last_busy(dev);
706 pm_runtime_put_autosuspend(dev);
707
708 return ret;
709 }
710
711 static const struct v4l2_ctrl_ops ov4689_ctrl_ops = {
712 .s_ctrl = ov4689_set_ctrl,
713 };
714
715 static int ov4689_initialize_controls(struct ov4689 *ov4689)
716 {
717 struct i2c_client *client = v4l2_get_subdevdata(&ov4689->subdev);
718 struct v4l2_fwnode_device_properties props;
719 struct v4l2_ctrl_handler *handler;
720 const struct ov4689_mode *mode;
721 s64 exposure_max, vblank_def;
722 s64 hblank_def, hblank_min;
723 struct v4l2_ctrl *ctrl;
724 int ret;
725
726 handler = &ov4689->ctrl_handler;
727 mode = ov4689->cur_mode;
728 ret = v4l2_ctrl_handler_init(handler, 15);
729 if (ret)
730 return ret;
731
732 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ, 0, 0,
733 link_freq_menu_items);
734 if (ctrl)
735 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
736
737 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, 0,
738 mode->pixel_rate, 1, mode->pixel_rate);
739
740 hblank_def = mode->hts_def - mode->width;
741 hblank_min = mode->hts_min - mode->width;
742 v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_HBLANK,
743 hblank_min, OV4689_HTS_MAX - mode->width,
744 OV4689_HTS_DIVIDER, hblank_def);
745
746 vblank_def = mode->vts_def - mode->height;
747 v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_VBLANK,
748 vblank_def, OV4689_VTS_MAX - mode->height, 1,
749 vblank_def);
750
751 exposure_max = mode->vts_def - 4;
752 ov4689->exposure =
753 v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_EXPOSURE,
754 OV4689_EXPOSURE_MIN, exposure_max,
755 OV4689_EXPOSURE_STEP, mode->exp_def);
756
757 v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
758 ov4689_gain_ranges[0].logical_min,
759 ov4689_gain_ranges[ARRAY_SIZE(ov4689_gain_ranges) - 1]
760 .logical_max,
761 OV4689_GAIN_STEP, OV4689_GAIN_DEFAULT);
762
763 v4l2_ctrl_new_std_menu_items(handler, &ov4689_ctrl_ops,
764 V4L2_CID_TEST_PATTERN,
765 ARRAY_SIZE(ov4689_test_pattern_menu) - 1,
766 0, 0, ov4689_test_pattern_menu);
767
768 v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
769 v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
770
771 v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
772 OV4689_DIG_GAIN_MIN, OV4689_DIG_GAIN_MAX,
773 OV4689_DIG_GAIN_STEP, OV4689_DIG_GAIN_DEFAULT);
774
775 v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_RED_BALANCE,
776 OV4689_WB_GAIN_MIN, OV4689_WB_GAIN_MAX,
777 OV4689_WB_GAIN_STEP, OV4689_WB_GAIN_DEFAULT);
778
779 v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_BLUE_BALANCE,
780 OV4689_WB_GAIN_MIN, OV4689_WB_GAIN_MAX,
781 OV4689_WB_GAIN_STEP, OV4689_WB_GAIN_DEFAULT);
782
783 if (handler->error) {
784 ret = handler->error;
785 dev_err(ov4689->dev, "Failed to init controls(%d)\n", ret);
786 goto err_free_handler;
787 }
788
789 ret = v4l2_fwnode_device_parse(&client->dev, &props);
790 if (ret)
791 goto err_free_handler;
792
793 ret = v4l2_ctrl_new_fwnode_properties(handler, &ov4689_ctrl_ops,
794 &props);
795 if (ret)
796 goto err_free_handler;
797
798 ov4689->subdev.ctrl_handler = handler;
799
800 return 0;
801
802 err_free_handler:
803 v4l2_ctrl_handler_free(handler);
804
805 return ret;
806 }
807
808 static int ov4689_check_sensor_id(struct ov4689 *ov4689,
809 struct i2c_client *client)
810 {
811 struct device *dev = ov4689->dev;
812 u64 id = 0;
813 int ret;
814
815 ret = cci_read(ov4689->regmap, OV4689_REG_CHIP_ID, &id, NULL);
816 if (ret) {
817 dev_err(dev, "Cannot read sensor ID\n");
818 return ret;
819 }
820
821 if (id != CHIP_ID) {
822 dev_err(dev, "Unexpected sensor ID %06llx, expected %06x\n",
823 id, CHIP_ID);
824 return -ENODEV;
825 }
826
827 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
828
829 return 0;
830 }
831
832 static int ov4689_configure_regulators(struct ov4689 *ov4689)
833 {
834 unsigned int i;
835
836 for (i = 0; i < ARRAY_SIZE(ov4689_supply_names); i++)
837 ov4689->supplies[i].supply = ov4689_supply_names[i];
838
839 return devm_regulator_bulk_get(ov4689->dev,
840 ARRAY_SIZE(ov4689_supply_names),
841 ov4689->supplies);
842 }
843
844 static u64 ov4689_check_link_frequency(struct v4l2_fwnode_endpoint *ep)
845 {
846 const u64 *freqs = link_freq_menu_items;
847 unsigned int i, j;
848
849 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
850 for (j = 0; j < ep->nr_of_link_frequencies; j++)
851 if (freqs[i] == ep->link_frequencies[j])
852 return freqs[i];
853 }
854
855 return 0;
856 }
857
858 static int ov4689_check_hwcfg(struct device *dev)
859 {
860 struct fwnode_handle *fwnode = dev_fwnode(dev);
861 struct v4l2_fwnode_endpoint bus_cfg = {
862 .bus_type = V4L2_MBUS_CSI2_DPHY,
863 };
864 struct fwnode_handle *endpoint;
865 int ret;
866
867 endpoint = fwnode_graph_get_next_endpoint(fwnode, NULL);
868 if (!endpoint)
869 return -EINVAL;
870
871 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg);
872 fwnode_handle_put(endpoint);
873 if (ret)
874 return ret;
875
876 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV4689_LANES) {
877 dev_err(dev, "Only a 4-lane CSI2 config is supported");
878 ret = -EINVAL;
879 goto out_free_bus_cfg;
880 }
881
882 if (!ov4689_check_link_frequency(&bus_cfg)) {
883 dev_err(dev, "No supported link frequency found\n");
884 ret = -EINVAL;
885 }
886
887 out_free_bus_cfg:
888 v4l2_fwnode_endpoint_free(&bus_cfg);
889
890 return ret;
891 }
892
893 static int ov4689_probe(struct i2c_client *client)
894 {
895 struct device *dev = &client->dev;
896 struct v4l2_subdev *sd;
897 struct ov4689 *ov4689;
898 int ret;
899
900 ret = ov4689_check_hwcfg(dev);
901 if (ret)
902 return ret;
903
904 ov4689 = devm_kzalloc(dev, sizeof(*ov4689), GFP_KERNEL);
905 if (!ov4689)
906 return -ENOMEM;
907
908 ov4689->dev = dev;
909
910 ov4689->cur_mode = &supported_modes[OV4689_MODE_2688_1520];
911
912 ov4689->xvclk = devm_clk_get_optional(dev, NULL);
913 if (IS_ERR(ov4689->xvclk))
914 return dev_err_probe(dev, PTR_ERR(ov4689->xvclk),
915 "Failed to get external clock\n");
916
917 if (!ov4689->xvclk) {
918 dev_dbg(dev,
919 "No clock provided, using clock-frequency property\n");
920 device_property_read_u32(dev, "clock-frequency",
921 &ov4689->clock_rate);
922 } else {
923 ov4689->clock_rate = clk_get_rate(ov4689->xvclk);
924 }
925
926 if (ov4689->clock_rate != OV4689_XVCLK_FREQ) {
927 dev_err(dev,
928 "External clock rate mismatch: got %d Hz, expected %d Hz\n",
929 ov4689->clock_rate, OV4689_XVCLK_FREQ);
930 return -EINVAL;
931 }
932
933 ov4689->regmap = devm_cci_regmap_init_i2c(client, 16);
934 if (IS_ERR(ov4689->regmap)) {
935 ret = PTR_ERR(ov4689->regmap);
936 dev_err(dev, "failed to initialize CCI: %d\n", ret);
937 return ret;
938 }
939
940 ov4689->reset_gpio = devm_gpiod_get_optional(dev, "reset",
941 GPIOD_OUT_LOW);
942 if (IS_ERR(ov4689->reset_gpio)) {
943 dev_err(dev, "Failed to get reset-gpios\n");
944 return PTR_ERR(ov4689->reset_gpio);
945 }
946
947 ov4689->pwdn_gpio = devm_gpiod_get_optional(dev, "pwdn", GPIOD_OUT_LOW);
948 if (IS_ERR(ov4689->pwdn_gpio)) {
949 dev_err(dev, "Failed to get pwdn-gpios\n");
950 return PTR_ERR(ov4689->pwdn_gpio);
951 }
952
953 ret = ov4689_configure_regulators(ov4689);
954 if (ret)
955 return dev_err_probe(dev, ret,
956 "Failed to get power regulators\n");
957
958 sd = &ov4689->subdev;
959 v4l2_i2c_subdev_init(sd, client, &ov4689_subdev_ops);
960 sd->internal_ops = &ov4689_internal_ops;
961 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
962 ret = ov4689_initialize_controls(ov4689);
963 if (ret) {
964 dev_err(dev, "Failed to initialize controls\n");
965 return ret;
966 }
967
968 ret = ov4689_power_on(dev);
969 if (ret)
970 goto err_free_handler;
971
972 ret = ov4689_check_sensor_id(ov4689, client);
973 if (ret)
974 goto err_power_off;
975
976
977 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
978 ov4689->pad.flags = MEDIA_PAD_FL_SOURCE;
979 ret = media_entity_pads_init(&sd->entity, 1, &ov4689->pad);
980 if (ret < 0)
981 goto err_power_off;
982
983 sd->state_lock = ov4689->ctrl_handler.lock;
984 ret = v4l2_subdev_init_finalize(sd);
985 if (ret) {
986 dev_err(dev, "Could not register v4l2 device\n");
987 goto err_clean_entity;
988 }
989
990 pm_runtime_set_active(dev);
991 pm_runtime_get_noresume(dev);
992 pm_runtime_enable(dev);
993 pm_runtime_set_autosuspend_delay(dev, 1000);
994 pm_runtime_use_autosuspend(dev);
995
996 ret = v4l2_async_register_subdev_sensor(sd);
997 if (ret) {
998 dev_err(dev, "v4l2 async register subdev failed\n");
999 goto err_clean_subdev_pm;
1000 }
1001
1002 pm_runtime_mark_last_busy(dev);
1003 pm_runtime_put_autosuspend(dev);
1004
1005 return 0;
1006
1007 err_clean_subdev_pm:
1008 pm_runtime_disable(dev);
1009 pm_runtime_put_noidle(dev);
1010 v4l2_subdev_cleanup(sd);
1011 err_clean_entity:
1012 media_entity_cleanup(&sd->entity);
1013 err_power_off:
1014 ov4689_power_off(dev);
1015 err_free_handler:
1016 v4l2_ctrl_handler_free(&ov4689->ctrl_handler);
1017
1018 return ret;
1019 }
1020
1021 static void ov4689_remove(struct i2c_client *client)
1022 {
1023 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1024 struct ov4689 *ov4689 = to_ov4689(sd);
1025
1026 v4l2_async_unregister_subdev(sd);
1027 media_entity_cleanup(&sd->entity);
1028 v4l2_subdev_cleanup(sd);
1029 v4l2_ctrl_handler_free(&ov4689->ctrl_handler);
1030
1031 pm_runtime_disable(&client->dev);
1032 if (!pm_runtime_status_suspended(&client->dev))
1033 ov4689_power_off(&client->dev);
1034 pm_runtime_set_suspended(&client->dev);
1035 }
1036
1037 static const struct of_device_id ov4689_of_match[] = {
1038 { .compatible = "ovti,ov4689" },
1039 {},
1040 };
1041 MODULE_DEVICE_TABLE(of, ov4689_of_match);
1042
1043 static struct i2c_driver ov4689_i2c_driver = {
1044 .driver = {
1045 .name = "ov4689",
1046 .pm = &ov4689_pm_ops,
1047 .of_match_table = ov4689_of_match,
1048 },
1049 .probe = ov4689_probe,
1050 .remove = ov4689_remove,
1051 };
1052
1053 module_i2c_driver(ov4689_i2c_driver);
1054
1055 MODULE_DESCRIPTION("OmniVision ov4689 sensor driver");
1056 MODULE_LICENSE("GPL");
Kernel DRM miscellaneous fixes and cross-tree changes