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Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / media / i2c / tc358743.c
blobc50d4e85dfd144bd6a8aee8622d59dbd03a143b0
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * tc358743 - Toshiba HDMI to CSI-2 bridge
4 *
5 * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights
6 * reserved.
7 */
8
9 /*
10 * References (c = chapter, p = page):
11 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
12 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/slab.h>
18 #include <linux/i2c.h>
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/interrupt.h>
23 #include <linux/timer.h>
24 #include <linux/of_graph.h>
25 #include <linux/videodev2.h>
26 #include <linux/workqueue.h>
27 #include <linux/v4l2-dv-timings.h>
28 #include <linux/hdmi.h>
29 #include <media/cec.h>
30 #include <media/v4l2-dv-timings.h>
31 #include <media/v4l2-device.h>
32 #include <media/v4l2-ctrls.h>
33 #include <media/v4l2-event.h>
34 #include <media/v4l2-fwnode.h>
35 #include <media/i2c/tc358743.h>
36
37 #include "tc358743_regs.h"
38
39 static int debug;
40 module_param(debug, int, 0644);
41 MODULE_PARM_DESC(debug, "debug level (0-3)");
42
43 MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver");
44 MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>");
45 MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>");
46 MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>");
47 MODULE_LICENSE("GPL");
48
49 #define EDID_NUM_BLOCKS_MAX 8
50 #define EDID_BLOCK_SIZE 128
51
52 #define I2C_MAX_XFER_SIZE (EDID_BLOCK_SIZE + 2)
53
54 #define POLL_INTERVAL_CEC_MS 10
55 #define POLL_INTERVAL_MS 1000
56
57 static const struct v4l2_dv_timings_cap tc358743_timings_cap = {
58 .type = V4L2_DV_BT_656_1120,
59 /* keep this initialization for compatibility with GCC < 4.4.6 */
60 .reserved = { 0 },
61 /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
62 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 13000000, 165000000,
63 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
64 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
65 V4L2_DV_BT_CAP_PROGRESSIVE |
66 V4L2_DV_BT_CAP_REDUCED_BLANKING |
67 V4L2_DV_BT_CAP_CUSTOM)
68 };
69
70 struct tc358743_state {
71 struct tc358743_platform_data pdata;
72 struct v4l2_mbus_config_mipi_csi2 bus;
73 struct v4l2_subdev sd;
74 struct media_pad pad;
75 struct v4l2_ctrl_handler hdl;
76 struct i2c_client *i2c_client;
77 /* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */
78 struct mutex confctl_mutex;
79
80 /* controls */
81 struct v4l2_ctrl *detect_tx_5v_ctrl;
82 struct v4l2_ctrl *audio_sampling_rate_ctrl;
83 struct v4l2_ctrl *audio_present_ctrl;
84
85 struct delayed_work delayed_work_enable_hotplug;
86
87 struct timer_list timer;
88 struct work_struct work_i2c_poll;
89
90 /* debugfs */
91 struct dentry *debugfs_dir;
92 struct v4l2_debugfs_if *infoframes;
93
94 /* edid */
95 u8 edid_blocks_written;
96
97 struct v4l2_dv_timings timings;
98 u32 mbus_fmt_code;
99 u8 csi_lanes_in_use;
100
101 struct gpio_desc *reset_gpio;
102
103 struct cec_adapter *cec_adap;
104 };
105
106 static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
107 bool cable_connected);
108 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
109
110 static inline struct tc358743_state *to_state(struct v4l2_subdev *sd)
111 {
112 return container_of(sd, struct tc358743_state, sd);
113 }
114
115 /* --------------- I2C --------------- */
116
117 static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
118 {
119 struct tc358743_state *state = to_state(sd);
120 struct i2c_client *client = state->i2c_client;
121 int err;
122 u8 buf[2] = { reg >> 8, reg & 0xff };
123 struct i2c_msg msgs[] = {
124 {
125 .addr = client->addr,
126 .flags = 0,
127 .len = 2,
128 .buf = buf,
129 },
130 {
131 .addr = client->addr,
132 .flags = I2C_M_RD,
133 .len = n,
134 .buf = values,
135 },
136 };
137
138 err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
139 if (err != ARRAY_SIZE(msgs)) {
140 v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed: %d\n",
141 __func__, reg, client->addr, err);
142 }
143 }
144
145 static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
146 {
147 struct tc358743_state *state = to_state(sd);
148 struct i2c_client *client = state->i2c_client;
149 int err, i;
150 struct i2c_msg msg;
151 u8 data[I2C_MAX_XFER_SIZE];
152
153 if ((2 + n) > I2C_MAX_XFER_SIZE) {
154 n = I2C_MAX_XFER_SIZE - 2;
155 v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n",
156 reg, 2 + n);
157 }
158
159 msg.addr = client->addr;
160 msg.buf = data;
161 msg.len = 2 + n;
162 msg.flags = 0;
163
164 data[0] = reg >> 8;
165 data[1] = reg & 0xff;
166
167 for (i = 0; i < n; i++)
168 data[2 + i] = values[i];
169
170 err = i2c_transfer(client->adapter, &msg, 1);
171 if (err != 1) {
172 v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed: %d\n",
173 __func__, reg, client->addr, err);
174 return;
175 }
176
177 if (debug < 3)
178 return;
179
180 switch (n) {
181 case 1:
182 v4l2_info(sd, "I2C write 0x%04x = 0x%02x",
183 reg, data[2]);
184 break;
185 case 2:
186 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x",
187 reg, data[3], data[2]);
188 break;
189 case 4:
190 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x",
191 reg, data[5], data[4], data[3], data[2]);
192 break;
193 default:
194 v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
195 n, reg);
196 }
197 }
198
199 static noinline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n)
200 {
201 __le32 val = 0;
202
203 i2c_rd(sd, reg, (u8 __force *)&val, n);
204
205 return le32_to_cpu(val);
206 }
207
208 static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n)
209 {
210 __le32 raw = cpu_to_le32(val);
211
212 i2c_wr(sd, reg, (u8 __force *)&raw, n);
213 }
214
215 static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
216 {
217 return i2c_rdreg(sd, reg, 1);
218 }
219
220 static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
221 {
222 i2c_wrreg(sd, reg, val, 1);
223 }
224
225 static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg,
226 u8 mask, u8 val)
227 {
228 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1);
229 }
230
231 static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg)
232 {
233 return i2c_rdreg(sd, reg, 2);
234 }
235
236 static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
237 {
238 i2c_wrreg(sd, reg, val, 2);
239 }
240
241 static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val)
242 {
243 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 2) & mask) | val, 2);
244 }
245
246 static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg)
247 {
248 return i2c_rdreg(sd, reg, 4);
249 }
250
251 static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val)
252 {
253 i2c_wrreg(sd, reg, val, 4);
254 }
255
256 /* --------------- STATUS --------------- */
257
258 static inline bool is_hdmi(struct v4l2_subdev *sd)
259 {
260 return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI;
261 }
262
263 static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
264 {
265 return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V;
266 }
267
268 static inline bool no_signal(struct v4l2_subdev *sd)
269 {
270 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS);
271 }
272
273 static inline bool no_sync(struct v4l2_subdev *sd)
274 {
275 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC);
276 }
277
278 static inline bool audio_present(struct v4l2_subdev *sd)
279 {
280 return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE;
281 }
282
283 static int get_audio_sampling_rate(struct v4l2_subdev *sd)
284 {
285 static const int code_to_rate[] = {
286 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
287 88200, 768000, 96000, 705600, 176400, 0, 192000, 0
288 };
289
290 /* Register FS_SET is not cleared when the cable is disconnected */
291 if (no_signal(sd))
292 return 0;
293
294 return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS];
295 }
296
297 /* --------------- TIMINGS --------------- */
298
299 static inline unsigned fps(const struct v4l2_bt_timings *t)
300 {
301 if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
302 return 0;
303
304 return DIV_ROUND_CLOSEST((unsigned)t->pixelclock,
305 V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
306 }
307
308 static int tc358743_get_detected_timings(struct v4l2_subdev *sd,
309 struct v4l2_dv_timings *timings)
310 {
311 struct v4l2_bt_timings *bt = &timings->bt;
312 unsigned width, height, frame_width, frame_height, frame_interval, fps;
313
314 memset(timings, 0, sizeof(struct v4l2_dv_timings));
315
316 if (no_signal(sd)) {
317 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
318 return -ENOLINK;
319 }
320 if (no_sync(sd)) {
321 v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__);
322 return -ENOLCK;
323 }
324
325 timings->type = V4L2_DV_BT_656_1120;
326 bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ?
327 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
328
329 width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) +
330 i2c_rd8(sd, DE_WIDTH_H_LO);
331 height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) +
332 i2c_rd8(sd, DE_WIDTH_V_LO);
333 frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) +
334 i2c_rd8(sd, H_SIZE_LO);
335 frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) +
336 i2c_rd8(sd, V_SIZE_LO)) / 2;
337 /* frame interval in milliseconds * 10
338 * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */
339 frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) +
340 i2c_rd8(sd, FV_CNT_LO);
341 fps = (frame_interval > 0) ?
342 DIV_ROUND_CLOSEST(10000, frame_interval) : 0;
343
344 bt->width = width;
345 bt->height = height;
346 bt->vsync = frame_height - height;
347 bt->hsync = frame_width - width;
348 bt->pixelclock = frame_width * frame_height * fps;
349 if (bt->interlaced == V4L2_DV_INTERLACED) {
350 bt->height *= 2;
351 bt->il_vsync = bt->vsync + 1;
352 bt->pixelclock /= 2;
353 }
354
355 return 0;
356 }
357
358 /* --------------- HOTPLUG / HDCP / EDID --------------- */
359
360 static void tc358743_delayed_work_enable_hotplug(struct work_struct *work)
361 {
362 struct delayed_work *dwork = to_delayed_work(work);
363 struct tc358743_state *state = container_of(dwork,
364 struct tc358743_state, delayed_work_enable_hotplug);
365 struct v4l2_subdev *sd = &state->sd;
366
367 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
368
369 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0);
370 }
371
372 static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
373 {
374 v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ?
375 "enable" : "disable");
376
377 if (enable) {
378 i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, KEY_RD_CMD);
379
380 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 0);
381
382 i2c_wr8_and_or(sd, HDCP_REG1, 0xff,
383 MASK_AUTH_UNAUTH_SEL_16_FRAMES |
384 MASK_AUTH_UNAUTH_AUTO);
385
386 i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET,
387 SET_AUTO_P3_RESET_FRAMES(0x0f));
388 } else {
389 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION,
390 MASK_MANUAL_AUTHENTICATION);
391 }
392 }
393
394 static void tc358743_disable_edid(struct v4l2_subdev *sd)
395 {
396 struct tc358743_state *state = to_state(sd);
397
398 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
399
400 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
401
402 /* DDC access to EDID is also disabled when hotplug is disabled. See
403 * register DDC_CTL */
404 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0);
405 }
406
407 static void tc358743_enable_edid(struct v4l2_subdev *sd)
408 {
409 struct tc358743_state *state = to_state(sd);
410
411 if (state->edid_blocks_written == 0) {
412 v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__);
413 tc358743_s_ctrl_detect_tx_5v(sd);
414 return;
415 }
416
417 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
418
419 /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when
420 * hotplug is enabled. See register DDC_CTL */
421 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
422
423 tc358743_enable_interrupts(sd, true);
424 tc358743_s_ctrl_detect_tx_5v(sd);
425 }
426
427 static void tc358743_erase_bksv(struct v4l2_subdev *sd)
428 {
429 int i;
430
431 for (i = 0; i < 5; i++)
432 i2c_wr8(sd, BKSV + i, 0);
433 }
434
435 /* --------------- AVI infoframe --------------- */
436
437 static ssize_t
438 tc358743_debugfs_if_read(u32 type, void *priv, struct file *filp,
439 char __user *ubuf, size_t count, loff_t *ppos)
440 {
441 u8 buf[V4L2_DEBUGFS_IF_MAX_LEN] = {};
442 struct v4l2_subdev *sd = priv;
443 int len;
444
445 if (!is_hdmi(sd))
446 return 0;
447
448 if (type != V4L2_DEBUGFS_IF_AVI)
449 return 0;
450
451 i2c_rd(sd, PK_AVI_0HEAD, buf, PK_AVI_16BYTE - PK_AVI_0HEAD + 1);
452 len = buf[2] + 4;
453 if (len > V4L2_DEBUGFS_IF_MAX_LEN)
454 len = -ENOENT;
455 if (len > 0)
456 len = simple_read_from_buffer(ubuf, count, ppos, buf, len);
457 return len < 0 ? 0 : len;
458 }
459
460 static void print_avi_infoframe(struct v4l2_subdev *sd)
461 {
462 struct i2c_client *client = v4l2_get_subdevdata(sd);
463 struct device *dev = &client->dev;
464 union hdmi_infoframe frame;
465 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)] = {};
466
467 if (!is_hdmi(sd)) {
468 v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n");
469 return;
470 }
471
472 i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI));
473
474 if (hdmi_infoframe_unpack(&frame, buffer, sizeof(buffer)) < 0) {
475 v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__);
476 return;
477 }
478
479 hdmi_infoframe_log(KERN_INFO, dev, &frame);
480 }
481
482 /* --------------- CTRLS --------------- */
483
484 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
485 {
486 struct tc358743_state *state = to_state(sd);
487
488 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
489 tx_5v_power_present(sd));
490 }
491
492 static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
493 {
494 struct tc358743_state *state = to_state(sd);
495
496 return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl,
497 get_audio_sampling_rate(sd));
498 }
499
500 static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd)
501 {
502 struct tc358743_state *state = to_state(sd);
503
504 return v4l2_ctrl_s_ctrl(state->audio_present_ctrl,
505 audio_present(sd));
506 }
507
508 static int tc358743_update_controls(struct v4l2_subdev *sd)
509 {
510 int ret = 0;
511
512 ret |= tc358743_s_ctrl_detect_tx_5v(sd);
513 ret |= tc358743_s_ctrl_audio_sampling_rate(sd);
514 ret |= tc358743_s_ctrl_audio_present(sd);
515
516 return ret;
517 }
518
519 /* --------------- INIT --------------- */
520
521 static void tc358743_reset_phy(struct v4l2_subdev *sd)
522 {
523 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
524
525 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0);
526 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL);
527 }
528
529 static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask)
530 {
531 u16 sysctl = i2c_rd16(sd, SYSCTL);
532
533 i2c_wr16(sd, SYSCTL, sysctl | mask);
534 i2c_wr16(sd, SYSCTL, sysctl & ~mask);
535 }
536
537 static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable)
538 {
539 i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP,
540 enable ? MASK_SLEEP : 0);
541 }
542
543 static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
544 {
545 struct tc358743_state *state = to_state(sd);
546
547 v4l2_dbg(3, debug, sd, "%s: %sable\n",
548 __func__, enable ? "en" : "dis");
549
550 if (enable) {
551 /* It is critical for CSI receiver to see lane transition
552 * LP11->HS. Set to non-continuous mode to enable clock lane
553 * LP11 state. */
554 i2c_wr32(sd, TXOPTIONCNTRL, 0);
555 /* Set to continuous mode to trigger LP11->HS transition */
556 i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE);
557 /* Unmute video */
558 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE);
559 } else {
560 /* Mute video so that all data lanes go to LSP11 state.
561 * No data is output to CSI Tx block. */
562 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE);
563 }
564
565 mutex_lock(&state->confctl_mutex);
566 i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN),
567 enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0);
568 mutex_unlock(&state->confctl_mutex);
569 }
570
571 static void tc358743_set_pll(struct v4l2_subdev *sd)
572 {
573 struct tc358743_state *state = to_state(sd);
574 struct tc358743_platform_data *pdata = &state->pdata;
575 u16 pllctl0 = i2c_rd16(sd, PLLCTL0);
576 u16 pllctl1 = i2c_rd16(sd, PLLCTL1);
577 u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) |
578 SET_PLL_FBD(pdata->pll_fbd);
579 u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
580
581 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
582
583 /* Only rewrite when needed (new value or disabled), since rewriting
584 * triggers another format change event. */
585 if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) {
586 u16 pll_frs;
587
588 if (hsck > 500000000)
589 pll_frs = 0x0;
590 else if (hsck > 250000000)
591 pll_frs = 0x1;
592 else if (hsck > 125000000)
593 pll_frs = 0x2;
594 else
595 pll_frs = 0x3;
596
597 v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__);
598 tc358743_sleep_mode(sd, true);
599 i2c_wr16(sd, PLLCTL0, pllctl0_new);
600 i2c_wr16_and_or(sd, PLLCTL1,
601 ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN),
602 (SET_PLL_FRS(pll_frs) | MASK_RESETB |
603 MASK_PLL_EN));
604 udelay(10); /* REF_02, Sheet "Source HDMI" */
605 i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN);
606 tc358743_sleep_mode(sd, false);
607 }
608 }
609
610 static void tc358743_set_ref_clk(struct v4l2_subdev *sd)
611 {
612 struct tc358743_state *state = to_state(sd);
613 struct tc358743_platform_data *pdata = &state->pdata;
614 u32 sys_freq;
615 u32 lockdet_ref;
616 u32 cec_freq;
617 u16 fh_min;
618 u16 fh_max;
619
620 BUG_ON(!(pdata->refclk_hz == 26000000 ||
621 pdata->refclk_hz == 27000000 ||
622 pdata->refclk_hz == 42000000));
623
624 sys_freq = pdata->refclk_hz / 10000;
625 i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff);
626 i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8);
627
628 i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND,
629 (pdata->refclk_hz == 42000000) ?
630 MASK_PHY_SYSCLK_IND : 0x0);
631
632 fh_min = pdata->refclk_hz / 100000;
633 i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff);
634 i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8);
635
636 fh_max = (fh_min * 66) / 10;
637 i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff);
638 i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8);
639
640 lockdet_ref = pdata->refclk_hz / 100;
641 i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff);
642 i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8);
643 i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16);
644
645 i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD,
646 (pdata->refclk_hz == 27000000) ?
647 MASK_NCO_F0_MOD_27MHZ : 0x0);
648
649 /*
650 * Trial and error suggests that the default register value
651 * of 656 is for a 42 MHz reference clock. Use that to derive
652 * a new value based on the actual reference clock.
653 */
654 cec_freq = (656 * sys_freq) / 4200;
655 i2c_wr16(sd, CECHCLK, cec_freq);
656 i2c_wr16(sd, CECLCLK, cec_freq);
657 }
658
659 static void tc358743_set_csi_color_space(struct v4l2_subdev *sd)
660 {
661 struct tc358743_state *state = to_state(sd);
662
663 switch (state->mbus_fmt_code) {
664 case MEDIA_BUS_FMT_UYVY8_1X16:
665 v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__);
666 i2c_wr8_and_or(sd, VOUT_SET2,
667 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
668 MASK_SEL422 | MASK_VOUT_422FIL_100);
669 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
670 MASK_VOUT_COLOR_601_YCBCR_LIMITED);
671 mutex_lock(&state->confctl_mutex);
672 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT,
673 MASK_YCBCRFMT_422_8_BIT);
674 mutex_unlock(&state->confctl_mutex);
675 break;
676 case MEDIA_BUS_FMT_RGB888_1X24:
677 v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__);
678 i2c_wr8_and_or(sd, VOUT_SET2,
679 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
680 0x00);
681 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
682 MASK_VOUT_COLOR_RGB_FULL);
683 mutex_lock(&state->confctl_mutex);
684 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0);
685 mutex_unlock(&state->confctl_mutex);
686 break;
687 default:
688 v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n",
689 __func__, state->mbus_fmt_code);
690 }
691 }
692
693 static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd)
694 {
695 struct tc358743_state *state = to_state(sd);
696 struct v4l2_bt_timings *bt = &state->timings.bt;
697 struct tc358743_platform_data *pdata = &state->pdata;
698 u32 bits_pr_pixel =
699 (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24;
700 u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel;
701 u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
702
703 return DIV_ROUND_UP(bps, bps_pr_lane);
704 }
705
706 static void tc358743_set_csi(struct v4l2_subdev *sd)
707 {
708 struct tc358743_state *state = to_state(sd);
709 struct tc358743_platform_data *pdata = &state->pdata;
710 unsigned lanes = tc358743_num_csi_lanes_needed(sd);
711
712 v4l2_dbg(3, debug, sd, "%s:\n", __func__);
713
714 state->csi_lanes_in_use = lanes;
715
716 tc358743_reset(sd, MASK_CTXRST);
717
718 if (lanes < 1)
719 i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE);
720 if (lanes < 1)
721 i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE);
722 if (lanes < 2)
723 i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE);
724 if (lanes < 3)
725 i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE);
726 if (lanes < 4)
727 i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE);
728
729 i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt);
730 i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt);
731 i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt);
732 i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt);
733 i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt);
734 i2c_wr32(sd, TWAKEUP, pdata->twakeup);
735 i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt);
736 i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt);
737 i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt);
738
739 i2c_wr32(sd, HSTXVREGEN,
740 ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
741 ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
742 ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
743 ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
744 ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));
745
746 i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags &
747 V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK) ? 0 : MASK_CONTCLKMODE);
748 i2c_wr32(sd, STARTCNTRL, MASK_START);
749 i2c_wr32(sd, CSI_START, MASK_STRT);
750
751 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
752 MASK_ADDRESS_CSI_CONTROL |
753 MASK_CSI_MODE |
754 MASK_TXHSMD |
755 ((lanes == 4) ? MASK_NOL_4 :
756 (lanes == 3) ? MASK_NOL_3 :
757 (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1));
758
759 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
760 MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK |
761 MASK_WCER | MASK_INER);
762
763 i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR |
764 MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK);
765
766 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
767 MASK_ADDRESS_CSI_INT_ENA | MASK_INTER);
768 }
769
770 static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd)
771 {
772 struct tc358743_state *state = to_state(sd);
773 struct tc358743_platform_data *pdata = &state->pdata;
774
775 /* Default settings from REF_02, sheet "Source HDMI"
776 * and custom settings as platform data */
777 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0);
778 i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) |
779 SET_FREQ_RANGE_MODE_CYCLES(1));
780 i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn,
781 (pdata->hdmi_phy_auto_reset_tmds_detected ?
782 MASK_PHY_AUTO_RST2 : 0) |
783 (pdata->hdmi_phy_auto_reset_tmds_in_range ?
784 MASK_PHY_AUTO_RST3 : 0) |
785 (pdata->hdmi_phy_auto_reset_tmds_valid ?
786 MASK_PHY_AUTO_RST4 : 0));
787 i2c_wr8(sd, PHY_BIAS, 0x40);
788 i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a));
789 i2c_wr8(sd, AVM_CTL, 45);
790 i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V,
791 pdata->hdmi_detection_delay << 4);
792 i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST),
793 (pdata->hdmi_phy_auto_reset_hsync_out_of_range ?
794 MASK_H_PI_RST : 0) |
795 (pdata->hdmi_phy_auto_reset_vsync_out_of_range ?
796 MASK_V_PI_RST : 0));
797 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY);
798 }
799
800 static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd)
801 {
802 struct tc358743_state *state = to_state(sd);
803
804 /* Default settings from REF_02, sheet "Source HDMI" */
805 i2c_wr8(sd, FORCE_MUTE, 0x00);
806 i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 |
807 MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 |
808 MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0);
809 i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9);
810 i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2);
811 i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500));
812 i2c_wr8(sd, FS_MUTE, 0x00);
813 i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE);
814 i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE);
815 i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM);
816 i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM);
817 i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S);
818 i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100));
819
820 mutex_lock(&state->confctl_mutex);
821 i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 |
822 MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX);
823 mutex_unlock(&state->confctl_mutex);
824 }
825
826 static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd)
827 {
828 /* Default settings from REF_02, sheet "Source HDMI" */
829 i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE |
830 MASK_ACP_INT_MODE | MASK_VS_INT_MODE |
831 MASK_SPD_INT_MODE | MASK_MS_INT_MODE |
832 MASK_AUD_INT_MODE | MASK_AVI_INT_MODE);
833 i2c_wr8(sd, NO_PKT_LIMIT, 0x2c);
834 i2c_wr8(sd, NO_PKT_CLR, 0x53);
835 i2c_wr8(sd, ERR_PK_LIMIT, 0x01);
836 i2c_wr8(sd, NO_PKT_LIMIT2, 0x30);
837 i2c_wr8(sd, NO_GDB_LIMIT, 0x10);
838 }
839
840 static void tc358743_initial_setup(struct v4l2_subdev *sd)
841 {
842 struct tc358743_state *state = to_state(sd);
843 struct tc358743_platform_data *pdata = &state->pdata;
844
845 /*
846 * IR is not supported by this driver.
847 * CEC is only enabled if needed.
848 */
849 i2c_wr16_and_or(sd, SYSCTL, ~(MASK_IRRST | MASK_CECRST),
850 (MASK_IRRST | MASK_CECRST));
851
852 tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST);
853 #ifdef CONFIG_VIDEO_TC358743_CEC
854 tc358743_reset(sd, MASK_CECRST);
855 #endif
856 tc358743_sleep_mode(sd, false);
857
858 i2c_wr16(sd, FIFOCTL, pdata->fifo_level);
859
860 tc358743_set_ref_clk(sd);
861
862 i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE,
863 pdata->ddc5v_delay & MASK_DDC5V_MODE);
864 i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC);
865
866 tc358743_set_hdmi_phy(sd);
867 tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp);
868 tc358743_set_hdmi_audio(sd);
869 tc358743_set_hdmi_info_frame_mode(sd);
870
871 /* All CE and IT formats are detected as RGB full range in DVI mode */
872 i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0);
873
874 i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE,
875 MASK_VOUTCOLORMODE_AUTO);
876 i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT);
877 }
878
879 /* --------------- CEC --------------- */
880
881 #ifdef CONFIG_VIDEO_TC358743_CEC
882 static int tc358743_cec_adap_enable(struct cec_adapter *adap, bool enable)
883 {
884 struct tc358743_state *state = adap->priv;
885 struct v4l2_subdev *sd = &state->sd;
886
887 i2c_wr32(sd, CECIMSK, enable ? MASK_CECTIM | MASK_CECRIM : 0);
888 i2c_wr32(sd, CECICLR, MASK_CECTICLR | MASK_CECRICLR);
889 i2c_wr32(sd, CECEN, enable);
890 if (enable)
891 i2c_wr32(sd, CECREN, MASK_CECREN);
892 return 0;
893 }
894
895 static int tc358743_cec_adap_monitor_all_enable(struct cec_adapter *adap,
896 bool enable)
897 {
898 struct tc358743_state *state = adap->priv;
899 struct v4l2_subdev *sd = &state->sd;
900 u32 reg;
901
902 reg = i2c_rd32(sd, CECRCTL1);
903 if (enable)
904 reg |= MASK_CECOTH;
905 else
906 reg &= ~MASK_CECOTH;
907 i2c_wr32(sd, CECRCTL1, reg);
908 return 0;
909 }
910
911 static int tc358743_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
912 {
913 struct tc358743_state *state = adap->priv;
914 struct v4l2_subdev *sd = &state->sd;
915 unsigned int la = 0;
916
917 if (log_addr != CEC_LOG_ADDR_INVALID) {
918 la = i2c_rd32(sd, CECADD);
919 la |= 1 << log_addr;
920 }
921 i2c_wr32(sd, CECADD, la);
922 return 0;
923 }
924
925 static int tc358743_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
926 u32 signal_free_time, struct cec_msg *msg)
927 {
928 struct tc358743_state *state = adap->priv;
929 struct v4l2_subdev *sd = &state->sd;
930 unsigned int i;
931
932 i2c_wr32(sd, CECTCTL,
933 (cec_msg_is_broadcast(msg) ? MASK_CECBRD : 0) |
934 (signal_free_time - 1));
935 for (i = 0; i < msg->len; i++)
936 i2c_wr32(sd, CECTBUF1 + i * 4,
937 msg->msg[i] | ((i == msg->len - 1) ? MASK_CECTEOM : 0));
938 i2c_wr32(sd, CECTEN, MASK_CECTEN);
939 return 0;
940 }
941
942 static const struct cec_adap_ops tc358743_cec_adap_ops = {
943 .adap_enable = tc358743_cec_adap_enable,
944 .adap_log_addr = tc358743_cec_adap_log_addr,
945 .adap_transmit = tc358743_cec_adap_transmit,
946 .adap_monitor_all_enable = tc358743_cec_adap_monitor_all_enable,
947 };
948
949 static void tc358743_cec_handler(struct v4l2_subdev *sd, u16 intstatus,
950 bool *handled)
951 {
952 struct tc358743_state *state = to_state(sd);
953 unsigned int cec_rxint, cec_txint;
954 unsigned int clr = 0;
955
956 cec_rxint = i2c_rd32(sd, CECRSTAT);
957 cec_txint = i2c_rd32(sd, CECTSTAT);
958
959 if (intstatus & MASK_CEC_RINT)
960 clr |= MASK_CECRICLR;
961 if (intstatus & MASK_CEC_TINT)
962 clr |= MASK_CECTICLR;
963 i2c_wr32(sd, CECICLR, clr);
964
965 if ((intstatus & MASK_CEC_TINT) && cec_txint) {
966 if (cec_txint & MASK_CECTIEND)
967 cec_transmit_attempt_done(state->cec_adap,
968 CEC_TX_STATUS_OK);
969 else if (cec_txint & MASK_CECTIAL)
970 cec_transmit_attempt_done(state->cec_adap,
971 CEC_TX_STATUS_ARB_LOST);
972 else if (cec_txint & MASK_CECTIACK)
973 cec_transmit_attempt_done(state->cec_adap,
974 CEC_TX_STATUS_NACK);
975 else if (cec_txint & MASK_CECTIUR) {
976 /*
977 * Not sure when this bit is set. Treat
978 * it as an error for now.
979 */
980 cec_transmit_attempt_done(state->cec_adap,
981 CEC_TX_STATUS_ERROR);
982 }
983 if (handled)
984 *handled = true;
985 }
986 if ((intstatus & MASK_CEC_RINT) &&
987 (cec_rxint & MASK_CECRIEND)) {
988 struct cec_msg msg = {};
989 unsigned int i;
990 unsigned int v;
991
992 v = i2c_rd32(sd, CECRCTR);
993 msg.len = v & 0x1f;
994 if (msg.len > CEC_MAX_MSG_SIZE)
995 msg.len = CEC_MAX_MSG_SIZE;
996 for (i = 0; i < msg.len; i++) {
997 v = i2c_rd32(sd, CECRBUF1 + i * 4);
998 msg.msg[i] = v & 0xff;
999 }
1000 cec_received_msg(state->cec_adap, &msg);
1001 if (handled)
1002 *handled = true;
1003 }
1004 i2c_wr16(sd, INTSTATUS,
1005 intstatus & (MASK_CEC_RINT | MASK_CEC_TINT));
1006 }
1007
1008 #endif
1009
1010 /* --------------- IRQ --------------- */
1011
1012 static void tc358743_format_change(struct v4l2_subdev *sd)
1013 {
1014 struct tc358743_state *state = to_state(sd);
1015 struct v4l2_dv_timings timings;
1016 const struct v4l2_event tc358743_ev_fmt = {
1017 .type = V4L2_EVENT_SOURCE_CHANGE,
1018 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
1019 };
1020
1021 if (tc358743_get_detected_timings(sd, &timings)) {
1022 enable_stream(sd, false);
1023
1024 v4l2_dbg(1, debug, sd, "%s: No signal\n",
1025 __func__);
1026 } else {
1027 if (!v4l2_match_dv_timings(&state->timings, &timings, 0, false))
1028 enable_stream(sd, false);
1029
1030 if (debug)
1031 v4l2_print_dv_timings(sd->name,
1032 "tc358743_format_change: New format: ",
1033 &timings, false);
1034 }
1035
1036 if (sd->devnode)
1037 v4l2_subdev_notify_event(sd, &tc358743_ev_fmt);
1038 }
1039
1040 static void tc358743_init_interrupts(struct v4l2_subdev *sd)
1041 {
1042 u16 i;
1043
1044 /* clear interrupt status registers */
1045 for (i = SYS_INT; i <= KEY_INT; i++)
1046 i2c_wr8(sd, i, 0xff);
1047
1048 i2c_wr16(sd, INTSTATUS, 0xffff);
1049 }
1050
1051 static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
1052 bool cable_connected)
1053 {
1054 v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__,
1055 cable_connected);
1056
1057 if (cable_connected) {
1058 i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET |
1059 MASK_M_HDMI_DET) & 0xff);
1060 i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG);
1061 i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK |
1062 MASK_M_AF_UNLOCK) & 0xff);
1063 i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END);
1064 i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG);
1065 } else {
1066 i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff);
1067 i2c_wr8(sd, CLK_INTM, 0xff);
1068 i2c_wr8(sd, CBIT_INTM, 0xff);
1069 i2c_wr8(sd, AUDIO_INTM, 0xff);
1070 i2c_wr8(sd, MISC_INTM, 0xff);
1071 }
1072 }
1073
1074 static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd,
1075 bool *handled)
1076 {
1077 u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM);
1078 u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask;
1079
1080 i2c_wr8(sd, AUDIO_INT, audio_int);
1081
1082 v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int);
1083
1084 tc358743_s_ctrl_audio_sampling_rate(sd);
1085 tc358743_s_ctrl_audio_present(sd);
1086 }
1087
1088 static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled)
1089 {
1090 v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR));
1091
1092 i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER);
1093 }
1094
1095 static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd,
1096 bool *handled)
1097 {
1098 u8 misc_int_mask = i2c_rd8(sd, MISC_INTM);
1099 u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask;
1100
1101 i2c_wr8(sd, MISC_INT, misc_int);
1102
1103 v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int);
1104
1105 if (misc_int & MASK_I_SYNC_CHG) {
1106 /* Reset the HDMI PHY to try to trigger proper lock on the
1107 * incoming video format. Erase BKSV to prevent that old keys
1108 * are used when a new source is connected. */
1109 if (no_sync(sd) || no_signal(sd)) {
1110 tc358743_reset_phy(sd);
1111 tc358743_erase_bksv(sd);
1112 }
1113
1114 tc358743_format_change(sd);
1115
1116 misc_int &= ~MASK_I_SYNC_CHG;
1117 if (handled)
1118 *handled = true;
1119 }
1120
1121 if (misc_int) {
1122 v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n",
1123 __func__, misc_int);
1124 }
1125 }
1126
1127 static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd,
1128 bool *handled)
1129 {
1130 u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM);
1131 u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask;
1132
1133 i2c_wr8(sd, CBIT_INT, cbit_int);
1134
1135 v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int);
1136
1137 if (cbit_int & MASK_I_CBIT_FS) {
1138
1139 v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n",
1140 __func__);
1141 tc358743_s_ctrl_audio_sampling_rate(sd);
1142
1143 cbit_int &= ~MASK_I_CBIT_FS;
1144 if (handled)
1145 *handled = true;
1146 }
1147
1148 if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) {
1149
1150 v4l2_dbg(1, debug, sd, "%s: Audio present changed\n",
1151 __func__);
1152 tc358743_s_ctrl_audio_present(sd);
1153
1154 cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK);
1155 if (handled)
1156 *handled = true;
1157 }
1158
1159 if (cbit_int) {
1160 v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n",
1161 __func__, cbit_int);
1162 }
1163 }
1164
1165 static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled)
1166 {
1167 u8 clk_int_mask = i2c_rd8(sd, CLK_INTM);
1168 u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask;
1169
1170 /* Bit 7 and bit 6 are set even when they are masked */
1171 i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG);
1172
1173 v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int);
1174
1175 if (clk_int & (MASK_I_IN_DE_CHG)) {
1176
1177 v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n",
1178 __func__);
1179
1180 /* If the source switch to a new resolution with the same pixel
1181 * frequency as the existing (e.g. 1080p25 -> 720p50), the
1182 * I_SYNC_CHG interrupt is not always triggered, while the
1183 * I_IN_DE_CHG interrupt seems to work fine. Format change
1184 * notifications are only sent when the signal is stable to
1185 * reduce the number of notifications. */
1186 if (!no_signal(sd) && !no_sync(sd))
1187 tc358743_format_change(sd);
1188
1189 clk_int &= ~(MASK_I_IN_DE_CHG);
1190 if (handled)
1191 *handled = true;
1192 }
1193
1194 if (clk_int) {
1195 v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n",
1196 __func__, clk_int);
1197 }
1198 }
1199
1200 static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled)
1201 {
1202 struct tc358743_state *state = to_state(sd);
1203 u8 sys_int_mask = i2c_rd8(sd, SYS_INTM);
1204 u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask;
1205
1206 i2c_wr8(sd, SYS_INT, sys_int);
1207
1208 v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int);
1209
1210 if (sys_int & MASK_I_DDC) {
1211 bool tx_5v = tx_5v_power_present(sd);
1212
1213 v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n",
1214 __func__, tx_5v ? "yes" : "no");
1215
1216 if (tx_5v) {
1217 tc358743_enable_edid(sd);
1218 } else {
1219 tc358743_enable_interrupts(sd, false);
1220 tc358743_disable_edid(sd);
1221 memset(&state->timings, 0, sizeof(state->timings));
1222 tc358743_erase_bksv(sd);
1223 tc358743_update_controls(sd);
1224 }
1225
1226 sys_int &= ~MASK_I_DDC;
1227 if (handled)
1228 *handled = true;
1229 }
1230
1231 if (sys_int & MASK_I_DVI) {
1232 v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n",
1233 __func__);
1234
1235 /* Reset the HDMI PHY to try to trigger proper lock on the
1236 * incoming video format. Erase BKSV to prevent that old keys
1237 * are used when a new source is connected. */
1238 if (no_sync(sd) || no_signal(sd)) {
1239 tc358743_reset_phy(sd);
1240 tc358743_erase_bksv(sd);
1241 }
1242
1243 sys_int &= ~MASK_I_DVI;
1244 if (handled)
1245 *handled = true;
1246 }
1247
1248 if (sys_int & MASK_I_HDMI) {
1249 v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n",
1250 __func__);
1251
1252 /* Register is reset in DVI mode (REF_01, c. 6.6.41) */
1253 i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON);
1254
1255 sys_int &= ~MASK_I_HDMI;
1256 if (handled)
1257 *handled = true;
1258 }
1259
1260 if (sys_int) {
1261 v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n",
1262 __func__, sys_int);
1263 }
1264 }
1265
1266 /* --------------- CORE OPS --------------- */
1267
1268 static int tc358743_log_status(struct v4l2_subdev *sd)
1269 {
1270 struct tc358743_state *state = to_state(sd);
1271 struct v4l2_dv_timings timings;
1272 uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS);
1273 uint16_t sysctl = i2c_rd16(sd, SYSCTL);
1274 u8 vi_status3 = i2c_rd8(sd, VI_STATUS3);
1275 const int deep_color_mode[4] = { 8, 10, 12, 16 };
1276 static const char * const input_color_space[] = {
1277 "RGB", "YCbCr 601", "opRGB", "YCbCr 709", "NA (4)",
1278 "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601",
1279 "NA(10)", "NA(11)", "NA(12)", "opYCC 601"};
1280
1281 v4l2_info(sd, "-----Chip status-----\n");
1282 v4l2_info(sd, "Chip ID: 0x%02x\n",
1283 (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8);
1284 v4l2_info(sd, "Chip revision: 0x%02x\n",
1285 i2c_rd16(sd, CHIPID) & MASK_REVID);
1286 v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n",
1287 !!(sysctl & MASK_IRRST),
1288 !!(sysctl & MASK_CECRST),
1289 !!(sysctl & MASK_CTXRST),
1290 !!(sysctl & MASK_HDMIRST));
1291 v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off");
1292 v4l2_info(sd, "Cable detected (+5V power): %s\n",
1293 hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no");
1294 v4l2_info(sd, "DDC lines enabled: %s\n",
1295 (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ?
1296 "yes" : "no");
1297 v4l2_info(sd, "Hotplug enabled: %s\n",
1298 (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ?
1299 "yes" : "no");
1300 v4l2_info(sd, "CEC enabled: %s\n",
1301 (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no");
1302 v4l2_info(sd, "-----Signal status-----\n");
1303 v4l2_info(sd, "TMDS signal detected: %s\n",
1304 hdmi_sys_status & MASK_S_TMDS ? "yes" : "no");
1305 v4l2_info(sd, "Stable sync signal: %s\n",
1306 hdmi_sys_status & MASK_S_SYNC ? "yes" : "no");
1307 v4l2_info(sd, "PHY PLL locked: %s\n",
1308 hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no");
1309 v4l2_info(sd, "PHY DE detected: %s\n",
1310 hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no");
1311
1312 if (tc358743_get_detected_timings(sd, &timings)) {
1313 v4l2_info(sd, "No video detected\n");
1314 } else {
1315 v4l2_print_dv_timings(sd->name, "Detected format: ", &timings,
1316 true);
1317 }
1318 v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings,
1319 true);
1320
1321 v4l2_info(sd, "-----CSI-TX status-----\n");
1322 v4l2_info(sd, "Lanes needed: %d\n",
1323 tc358743_num_csi_lanes_needed(sd));
1324 v4l2_info(sd, "Lanes in use: %d\n",
1325 state->csi_lanes_in_use);
1326 v4l2_info(sd, "Waiting for particular sync signal: %s\n",
1327 (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ?
1328 "yes" : "no");
1329 v4l2_info(sd, "Transmit mode: %s\n",
1330 (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ?
1331 "yes" : "no");
1332 v4l2_info(sd, "Receive mode: %s\n",
1333 (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ?
1334 "yes" : "no");
1335 v4l2_info(sd, "Stopped: %s\n",
1336 (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ?
1337 "yes" : "no");
1338 v4l2_info(sd, "Color space: %s\n",
1339 state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ?
1340 "YCbCr 422 16-bit" :
1341 state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ?
1342 "RGB 888 24-bit" : "Unsupported");
1343
1344 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
1345 v4l2_info(sd, "HDCP encrypted content: %s\n",
1346 hdmi_sys_status & MASK_S_HDCP ? "yes" : "no");
1347 v4l2_info(sd, "Input color space: %s %s range\n",
1348 input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1],
1349 (vi_status3 & MASK_LIMITED) ? "limited" : "full");
1350 if (!is_hdmi(sd))
1351 return 0;
1352 v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" :
1353 "off");
1354 v4l2_info(sd, "Deep color mode: %d-bits per channel\n",
1355 deep_color_mode[(i2c_rd8(sd, VI_STATUS1) &
1356 MASK_S_DEEPCOLOR) >> 2]);
1357 print_avi_infoframe(sd);
1358
1359 return 0;
1360 }
1361
1362 #ifdef CONFIG_VIDEO_ADV_DEBUG
1363 static void tc358743_print_register_map(struct v4l2_subdev *sd)
1364 {
1365 v4l2_info(sd, "0x0000-0x00FF: Global Control Register\n");
1366 v4l2_info(sd, "0x0100-0x01FF: CSI2-TX PHY Register\n");
1367 v4l2_info(sd, "0x0200-0x03FF: CSI2-TX PPI Register\n");
1368 v4l2_info(sd, "0x0400-0x05FF: Reserved\n");
1369 v4l2_info(sd, "0x0600-0x06FF: CEC Register\n");
1370 v4l2_info(sd, "0x0700-0x84FF: Reserved\n");
1371 v4l2_info(sd, "0x8500-0x85FF: HDMIRX System Control Register\n");
1372 v4l2_info(sd, "0x8600-0x86FF: HDMIRX Audio Control Register\n");
1373 v4l2_info(sd, "0x8700-0x87FF: HDMIRX InfoFrame packet data Register\n");
1374 v4l2_info(sd, "0x8800-0x88FF: HDMIRX HDCP Port Register\n");
1375 v4l2_info(sd, "0x8900-0x89FF: HDMIRX Video Output Port & 3D Register\n");
1376 v4l2_info(sd, "0x8A00-0x8BFF: Reserved\n");
1377 v4l2_info(sd, "0x8C00-0x8FFF: HDMIRX EDID-RAM (1024bytes)\n");
1378 v4l2_info(sd, "0x9000-0x90FF: HDMIRX GBD Extraction Control\n");
1379 v4l2_info(sd, "0x9100-0x92FF: HDMIRX GBD RAM read\n");
1380 v4l2_info(sd, "0x9300- : Reserved\n");
1381 }
1382
1383 static int tc358743_get_reg_size(u16 address)
1384 {
1385 /* REF_01 p. 66-72 */
1386 if (address <= 0x00ff)
1387 return 2;
1388 else if ((address >= 0x0100) && (address <= 0x06FF))
1389 return 4;
1390 else if ((address >= 0x0700) && (address <= 0x84ff))
1391 return 2;
1392 else
1393 return 1;
1394 }
1395
1396 static int tc358743_g_register(struct v4l2_subdev *sd,
1397 struct v4l2_dbg_register *reg)
1398 {
1399 if (reg->reg > 0xffff) {
1400 tc358743_print_register_map(sd);
1401 return -EINVAL;
1402 }
1403
1404 reg->size = tc358743_get_reg_size(reg->reg);
1405
1406 reg->val = i2c_rdreg(sd, reg->reg, reg->size);
1407
1408 return 0;
1409 }
1410
1411 static int tc358743_s_register(struct v4l2_subdev *sd,
1412 const struct v4l2_dbg_register *reg)
1413 {
1414 if (reg->reg > 0xffff) {
1415 tc358743_print_register_map(sd);
1416 return -EINVAL;
1417 }
1418
1419 /* It should not be possible for the user to enable HDCP with a simple
1420 * v4l2-dbg command.
1421 *
1422 * DO NOT REMOVE THIS unless all other issues with HDCP have been
1423 * resolved.
1424 */
1425 if (reg->reg == HDCP_MODE ||
1426 reg->reg == HDCP_REG1 ||
1427 reg->reg == HDCP_REG2 ||
1428 reg->reg == HDCP_REG3 ||
1429 reg->reg == BCAPS)
1430 return 0;
1431
1432 i2c_wrreg(sd, (u16)reg->reg, reg->val,
1433 tc358743_get_reg_size(reg->reg));
1434
1435 return 0;
1436 }
1437 #endif
1438
1439 static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1440 {
1441 u16 intstatus = i2c_rd16(sd, INTSTATUS);
1442
1443 v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus);
1444
1445 if (intstatus & MASK_HDMI_INT) {
1446 u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0);
1447 u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1);
1448
1449 if (hdmi_int0 & MASK_I_MISC)
1450 tc358743_hdmi_misc_int_handler(sd, handled);
1451 if (hdmi_int1 & MASK_I_CBIT)
1452 tc358743_hdmi_cbit_int_handler(sd, handled);
1453 if (hdmi_int1 & MASK_I_CLK)
1454 tc358743_hdmi_clk_int_handler(sd, handled);
1455 if (hdmi_int1 & MASK_I_SYS)
1456 tc358743_hdmi_sys_int_handler(sd, handled);
1457 if (hdmi_int1 & MASK_I_AUD)
1458 tc358743_hdmi_audio_int_handler(sd, handled);
1459
1460 i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT);
1461 intstatus &= ~MASK_HDMI_INT;
1462 }
1463
1464 #ifdef CONFIG_VIDEO_TC358743_CEC
1465 if (intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)) {
1466 tc358743_cec_handler(sd, intstatus, handled);
1467 i2c_wr16(sd, INTSTATUS,
1468 intstatus & (MASK_CEC_RINT | MASK_CEC_TINT));
1469 intstatus &= ~(MASK_CEC_RINT | MASK_CEC_TINT);
1470 }
1471 #endif
1472
1473 if (intstatus & MASK_CSI_INT) {
1474 u32 csi_int = i2c_rd32(sd, CSI_INT);
1475
1476 if (csi_int & MASK_INTER)
1477 tc358743_csi_err_int_handler(sd, handled);
1478
1479 i2c_wr16(sd, INTSTATUS, MASK_CSI_INT);
1480 }
1481
1482 intstatus = i2c_rd16(sd, INTSTATUS);
1483 if (intstatus) {
1484 v4l2_dbg(1, debug, sd,
1485 "%s: Unhandled IntStatus interrupts: 0x%02x\n",
1486 __func__, intstatus);
1487 }
1488
1489 return 0;
1490 }
1491
1492 static irqreturn_t tc358743_irq_handler(int irq, void *dev_id)
1493 {
1494 struct tc358743_state *state = dev_id;
1495 bool handled = false;
1496
1497 tc358743_isr(&state->sd, 0, &handled);
1498
1499 return handled ? IRQ_HANDLED : IRQ_NONE;
1500 }
1501
1502 static void tc358743_irq_poll_timer(struct timer_list *t)
1503 {
1504 struct tc358743_state *state = from_timer(state, t, timer);
1505 unsigned int msecs;
1506
1507 schedule_work(&state->work_i2c_poll);
1508 /*
1509 * If CEC is present, then we need to poll more frequently,
1510 * otherwise we will miss CEC messages.
1511 */
1512 msecs = state->cec_adap ? POLL_INTERVAL_CEC_MS : POLL_INTERVAL_MS;
1513 mod_timer(&state->timer, jiffies + msecs_to_jiffies(msecs));
1514 }
1515
1516 static void tc358743_work_i2c_poll(struct work_struct *work)
1517 {
1518 struct tc358743_state *state = container_of(work,
1519 struct tc358743_state, work_i2c_poll);
1520 bool handled;
1521
1522 tc358743_isr(&state->sd, 0, &handled);
1523 }
1524
1525 static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1526 struct v4l2_event_subscription *sub)
1527 {
1528 switch (sub->type) {
1529 case V4L2_EVENT_SOURCE_CHANGE:
1530 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
1531 case V4L2_EVENT_CTRL:
1532 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
1533 default:
1534 return -EINVAL;
1535 }
1536 }
1537
1538 /* --------------- VIDEO OPS --------------- */
1539
1540 static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status)
1541 {
1542 *status = 0;
1543 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1544 *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0;
1545
1546 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1547
1548 return 0;
1549 }
1550
1551 static int tc358743_s_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
1552 struct v4l2_dv_timings *timings)
1553 {
1554 struct tc358743_state *state = to_state(sd);
1555
1556 if (pad != 0)
1557 return -EINVAL;
1558
1559 if (!timings)
1560 return -EINVAL;
1561
1562 if (debug)
1563 v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ",
1564 timings, false);
1565
1566 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1567 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1568 return 0;
1569 }
1570
1571 if (!v4l2_valid_dv_timings(timings,
1572 &tc358743_timings_cap, NULL, NULL)) {
1573 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1574 return -ERANGE;
1575 }
1576
1577 state->timings = *timings;
1578
1579 enable_stream(sd, false);
1580 tc358743_set_pll(sd);
1581 tc358743_set_csi(sd);
1582
1583 return 0;
1584 }
1585
1586 static int tc358743_g_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
1587 struct v4l2_dv_timings *timings)
1588 {
1589 struct tc358743_state *state = to_state(sd);
1590
1591 if (pad != 0)
1592 return -EINVAL;
1593
1594 *timings = state->timings;
1595
1596 return 0;
1597 }
1598
1599 static int tc358743_enum_dv_timings(struct v4l2_subdev *sd,
1600 struct v4l2_enum_dv_timings *timings)
1601 {
1602 if (timings->pad != 0)
1603 return -EINVAL;
1604
1605 return v4l2_enum_dv_timings_cap(timings,
1606 &tc358743_timings_cap, NULL, NULL);
1607 }
1608
1609 static int tc358743_query_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
1610 struct v4l2_dv_timings *timings)
1611 {
1612 int ret;
1613
1614 if (pad != 0)
1615 return -EINVAL;
1616
1617 ret = tc358743_get_detected_timings(sd, timings);
1618 if (ret)
1619 return ret;
1620
1621 if (debug)
1622 v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ",
1623 timings, false);
1624
1625 if (!v4l2_valid_dv_timings(timings,
1626 &tc358743_timings_cap, NULL, NULL)) {
1627 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1628 return -ERANGE;
1629 }
1630
1631 return 0;
1632 }
1633
1634 static int tc358743_dv_timings_cap(struct v4l2_subdev *sd,
1635 struct v4l2_dv_timings_cap *cap)
1636 {
1637 if (cap->pad != 0)
1638 return -EINVAL;
1639
1640 *cap = tc358743_timings_cap;
1641
1642 return 0;
1643 }
1644
1645 static int tc358743_get_mbus_config(struct v4l2_subdev *sd,
1646 unsigned int pad,
1647 struct v4l2_mbus_config *cfg)
1648 {
1649 struct tc358743_state *state = to_state(sd);
1650
1651 cfg->type = V4L2_MBUS_CSI2_DPHY;
1652
1653 /* Support for non-continuous CSI-2 clock is missing in the driver */
1654 cfg->bus.mipi_csi2.flags = 0;
1655 cfg->bus.mipi_csi2.num_data_lanes = state->csi_lanes_in_use;
1656
1657 return 0;
1658 }
1659
1660 static int tc358743_s_stream(struct v4l2_subdev *sd, int enable)
1661 {
1662 enable_stream(sd, enable);
1663 if (!enable) {
1664 /* Put all lanes in LP-11 state (STOPSTATE) */
1665 tc358743_set_csi(sd);
1666 }
1667
1668 return 0;
1669 }
1670
1671 /* --------------- PAD OPS --------------- */
1672
1673 static int tc358743_enum_mbus_code(struct v4l2_subdev *sd,
1674 struct v4l2_subdev_state *sd_state,
1675 struct v4l2_subdev_mbus_code_enum *code)
1676 {
1677 switch (code->index) {
1678 case 0:
1679 code->code = MEDIA_BUS_FMT_RGB888_1X24;
1680 break;
1681 case 1:
1682 code->code = MEDIA_BUS_FMT_UYVY8_1X16;
1683 break;
1684 default:
1685 return -EINVAL;
1686 }
1687 return 0;
1688 }
1689
1690 static int tc358743_get_fmt(struct v4l2_subdev *sd,
1691 struct v4l2_subdev_state *sd_state,
1692 struct v4l2_subdev_format *format)
1693 {
1694 struct tc358743_state *state = to_state(sd);
1695 u8 vi_rep = i2c_rd8(sd, VI_REP);
1696
1697 if (format->pad != 0)
1698 return -EINVAL;
1699
1700 format->format.code = state->mbus_fmt_code;
1701 format->format.width = state->timings.bt.width;
1702 format->format.height = state->timings.bt.height;
1703 format->format.field = V4L2_FIELD_NONE;
1704
1705 switch (vi_rep & MASK_VOUT_COLOR_SEL) {
1706 case MASK_VOUT_COLOR_RGB_FULL:
1707 case MASK_VOUT_COLOR_RGB_LIMITED:
1708 format->format.colorspace = V4L2_COLORSPACE_SRGB;
1709 break;
1710 case MASK_VOUT_COLOR_601_YCBCR_LIMITED:
1711 case MASK_VOUT_COLOR_601_YCBCR_FULL:
1712 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
1713 break;
1714 case MASK_VOUT_COLOR_709_YCBCR_FULL:
1715 case MASK_VOUT_COLOR_709_YCBCR_LIMITED:
1716 format->format.colorspace = V4L2_COLORSPACE_REC709;
1717 break;
1718 default:
1719 format->format.colorspace = 0;
1720 break;
1721 }
1722
1723 return 0;
1724 }
1725
1726 static int tc358743_set_fmt(struct v4l2_subdev *sd,
1727 struct v4l2_subdev_state *sd_state,
1728 struct v4l2_subdev_format *format)
1729 {
1730 struct tc358743_state *state = to_state(sd);
1731
1732 u32 code = format->format.code; /* is overwritten by get_fmt */
1733 int ret = tc358743_get_fmt(sd, sd_state, format);
1734
1735 format->format.code = code;
1736
1737 if (ret)
1738 return ret;
1739
1740 switch (code) {
1741 case MEDIA_BUS_FMT_RGB888_1X24:
1742 case MEDIA_BUS_FMT_UYVY8_1X16:
1743 break;
1744 default:
1745 return -EINVAL;
1746 }
1747
1748 if (format->which == V4L2_SUBDEV_FORMAT_TRY)
1749 return 0;
1750
1751 state->mbus_fmt_code = format->format.code;
1752
1753 enable_stream(sd, false);
1754 tc358743_set_pll(sd);
1755 tc358743_set_csi(sd);
1756 tc358743_set_csi_color_space(sd);
1757
1758 return 0;
1759 }
1760
1761 static int tc358743_g_edid(struct v4l2_subdev *sd,
1762 struct v4l2_subdev_edid *edid)
1763 {
1764 struct tc358743_state *state = to_state(sd);
1765
1766 memset(edid->reserved, 0, sizeof(edid->reserved));
1767
1768 if (edid->pad != 0)
1769 return -EINVAL;
1770
1771 if (edid->start_block == 0 && edid->blocks == 0) {
1772 edid->blocks = state->edid_blocks_written;
1773 return 0;
1774 }
1775
1776 if (state->edid_blocks_written == 0)
1777 return -ENODATA;
1778
1779 if (edid->start_block >= state->edid_blocks_written ||
1780 edid->blocks == 0)
1781 return -EINVAL;
1782
1783 if (edid->start_block + edid->blocks > state->edid_blocks_written)
1784 edid->blocks = state->edid_blocks_written - edid->start_block;
1785
1786 i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid,
1787 edid->blocks * EDID_BLOCK_SIZE);
1788
1789 return 0;
1790 }
1791
1792 static int tc358743_s_edid(struct v4l2_subdev *sd,
1793 struct v4l2_subdev_edid *edid)
1794 {
1795 struct tc358743_state *state = to_state(sd);
1796 u16 edid_len = edid->blocks * EDID_BLOCK_SIZE;
1797 u16 pa;
1798 int err;
1799 int i;
1800
1801 v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n",
1802 __func__, edid->pad, edid->start_block, edid->blocks);
1803
1804 memset(edid->reserved, 0, sizeof(edid->reserved));
1805
1806 if (edid->pad != 0)
1807 return -EINVAL;
1808
1809 if (edid->start_block != 0)
1810 return -EINVAL;
1811
1812 if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
1813 edid->blocks = EDID_NUM_BLOCKS_MAX;
1814 return -E2BIG;
1815 }
1816 pa = cec_get_edid_phys_addr(edid->edid, edid->blocks * 128, NULL);
1817 err = v4l2_phys_addr_validate(pa, &pa, NULL);
1818 if (err)
1819 return err;
1820
1821 cec_phys_addr_invalidate(state->cec_adap);
1822
1823 tc358743_disable_edid(sd);
1824
1825 i2c_wr8(sd, EDID_LEN1, edid_len & 0xff);
1826 i2c_wr8(sd, EDID_LEN2, edid_len >> 8);
1827
1828 if (edid->blocks == 0) {
1829 state->edid_blocks_written = 0;
1830 return 0;
1831 }
1832
1833 for (i = 0; i < edid_len; i += EDID_BLOCK_SIZE)
1834 i2c_wr(sd, EDID_RAM + i, edid->edid + i, EDID_BLOCK_SIZE);
1835
1836 state->edid_blocks_written = edid->blocks;
1837
1838 cec_s_phys_addr(state->cec_adap, pa, false);
1839
1840 if (tx_5v_power_present(sd))
1841 tc358743_enable_edid(sd);
1842
1843 return 0;
1844 }
1845
1846 /* -------------------------------------------------------------------------- */
1847
1848 static const struct v4l2_subdev_core_ops tc358743_core_ops = {
1849 .log_status = tc358743_log_status,
1850 #ifdef CONFIG_VIDEO_ADV_DEBUG
1851 .g_register = tc358743_g_register,
1852 .s_register = tc358743_s_register,
1853 #endif
1854 .interrupt_service_routine = tc358743_isr,
1855 .subscribe_event = tc358743_subscribe_event,
1856 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1857 };
1858
1859 static const struct v4l2_subdev_video_ops tc358743_video_ops = {
1860 .g_input_status = tc358743_g_input_status,
1861 .s_stream = tc358743_s_stream,
1862 };
1863
1864 static const struct v4l2_subdev_pad_ops tc358743_pad_ops = {
1865 .enum_mbus_code = tc358743_enum_mbus_code,
1866 .set_fmt = tc358743_set_fmt,
1867 .get_fmt = tc358743_get_fmt,
1868 .get_edid = tc358743_g_edid,
1869 .set_edid = tc358743_s_edid,
1870 .s_dv_timings = tc358743_s_dv_timings,
1871 .g_dv_timings = tc358743_g_dv_timings,
1872 .query_dv_timings = tc358743_query_dv_timings,
1873 .enum_dv_timings = tc358743_enum_dv_timings,
1874 .dv_timings_cap = tc358743_dv_timings_cap,
1875 .get_mbus_config = tc358743_get_mbus_config,
1876 };
1877
1878 static const struct v4l2_subdev_ops tc358743_ops = {
1879 .core = &tc358743_core_ops,
1880 .video = &tc358743_video_ops,
1881 .pad = &tc358743_pad_ops,
1882 };
1883
1884 /* --------------- CUSTOM CTRLS --------------- */
1885
1886 static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = {
1887 .id = TC358743_CID_AUDIO_SAMPLING_RATE,
1888 .name = "Audio sampling rate",
1889 .type = V4L2_CTRL_TYPE_INTEGER,
1890 .min = 0,
1891 .max = 768000,
1892 .step = 1,
1893 .def = 0,
1894 .flags = V4L2_CTRL_FLAG_READ_ONLY,
1895 };
1896
1897 static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = {
1898 .id = TC358743_CID_AUDIO_PRESENT,
1899 .name = "Audio present",
1900 .type = V4L2_CTRL_TYPE_BOOLEAN,
1901 .min = 0,
1902 .max = 1,
1903 .step = 1,
1904 .def = 0,
1905 .flags = V4L2_CTRL_FLAG_READ_ONLY,
1906 };
1907
1908 /* --------------- PROBE / REMOVE --------------- */
1909
1910 #ifdef CONFIG_OF
1911 static void tc358743_gpio_reset(struct tc358743_state *state)
1912 {
1913 usleep_range(5000, 10000);
1914 gpiod_set_value(state->reset_gpio, 1);
1915 usleep_range(1000, 2000);
1916 gpiod_set_value(state->reset_gpio, 0);
1917 msleep(20);
1918 }
1919
1920 static int tc358743_probe_of(struct tc358743_state *state)
1921 {
1922 struct device *dev = &state->i2c_client->dev;
1923 struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 };
1924 struct device_node *ep;
1925 struct clk *refclk;
1926 u32 bps_pr_lane;
1927 int ret;
1928
1929 refclk = devm_clk_get(dev, "refclk");
1930 if (IS_ERR(refclk))
1931 return dev_err_probe(dev, PTR_ERR(refclk),
1932 "failed to get refclk\n");
1933
1934 ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
1935 if (!ep) {
1936 dev_err(dev, "missing endpoint node\n");
1937 return -EINVAL;
1938 }
1939
1940 ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(ep), &endpoint);
1941 if (ret) {
1942 dev_err(dev, "failed to parse endpoint\n");
1943 goto put_node;
1944 }
1945
1946 if (endpoint.bus_type != V4L2_MBUS_CSI2_DPHY ||
1947 endpoint.bus.mipi_csi2.num_data_lanes == 0 ||
1948 endpoint.nr_of_link_frequencies == 0) {
1949 dev_err(dev, "missing CSI-2 properties in endpoint\n");
1950 ret = -EINVAL;
1951 goto free_endpoint;
1952 }
1953
1954 if (endpoint.bus.mipi_csi2.num_data_lanes > 4) {
1955 dev_err(dev, "invalid number of lanes\n");
1956 ret = -EINVAL;
1957 goto free_endpoint;
1958 }
1959
1960 state->bus = endpoint.bus.mipi_csi2;
1961
1962 ret = clk_prepare_enable(refclk);
1963 if (ret) {
1964 dev_err(dev, "Failed! to enable clock\n");
1965 goto free_endpoint;
1966 }
1967
1968 state->pdata.refclk_hz = clk_get_rate(refclk);
1969 state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
1970 state->pdata.enable_hdcp = false;
1971 /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
1972 state->pdata.fifo_level = 16;
1973 /*
1974 * The PLL input clock is obtained by dividing refclk by pll_prd.
1975 * It must be between 6 MHz and 40 MHz, lower frequency is better.
1976 */
1977 switch (state->pdata.refclk_hz) {
1978 case 26000000:
1979 case 27000000:
1980 case 42000000:
1981 state->pdata.pll_prd = state->pdata.refclk_hz / 6000000;
1982 break;
1983 default:
1984 dev_err(dev, "unsupported refclk rate: %u Hz\n",
1985 state->pdata.refclk_hz);
1986 goto disable_clk;
1987 }
1988
1989 /*
1990 * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
1991 * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
1992 */
1993 bps_pr_lane = 2 * endpoint.link_frequencies[0];
1994 if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
1995 dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane);
1996 ret = -EINVAL;
1997 goto disable_clk;
1998 }
1999
2000 /* The CSI speed per lane is refclk / pll_prd * pll_fbd */
2001 state->pdata.pll_fbd = bps_pr_lane /
2002 state->pdata.refclk_hz * state->pdata.pll_prd;
2003
2004 /*
2005 * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz
2006 * link frequency). In principle it should be possible to calculate
2007 * them based on link frequency and resolution.
2008 */
2009 if (bps_pr_lane != 594000000U)
2010 dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane);
2011 state->pdata.lineinitcnt = 0xe80;
2012 state->pdata.lptxtimecnt = 0x003;
2013 /* tclk-preparecnt: 3, tclk-zerocnt: 20 */
2014 state->pdata.tclk_headercnt = 0x1403;
2015 state->pdata.tclk_trailcnt = 0x00;
2016 /* ths-preparecnt: 3, ths-zerocnt: 1 */
2017 state->pdata.ths_headercnt = 0x0103;
2018 state->pdata.twakeup = 0x4882;
2019 state->pdata.tclk_postcnt = 0x008;
2020 state->pdata.ths_trailcnt = 0x2;
2021 state->pdata.hstxvregcnt = 0;
2022
2023 state->reset_gpio = devm_gpiod_get_optional(dev, "reset",
2024 GPIOD_OUT_LOW);
2025 if (IS_ERR(state->reset_gpio)) {
2026 dev_err(dev, "failed to get reset gpio\n");
2027 ret = PTR_ERR(state->reset_gpio);
2028 goto disable_clk;
2029 }
2030
2031 if (state->reset_gpio)
2032 tc358743_gpio_reset(state);
2033
2034 ret = 0;
2035 goto free_endpoint;
2036
2037 disable_clk:
2038 clk_disable_unprepare(refclk);
2039 free_endpoint:
2040 v4l2_fwnode_endpoint_free(&endpoint);
2041 put_node:
2042 of_node_put(ep);
2043 return ret;
2044 }
2045 #else
2046 static inline int tc358743_probe_of(struct tc358743_state *state)
2047 {
2048 return -ENODEV;
2049 }
2050 #endif
2051
2052 static int tc358743_probe(struct i2c_client *client)
2053 {
2054 static struct v4l2_dv_timings default_timing =
2055 V4L2_DV_BT_CEA_640X480P59_94;
2056 struct tc358743_state *state;
2057 struct tc358743_platform_data *pdata = client->dev.platform_data;
2058 struct v4l2_subdev *sd;
2059 u16 irq_mask = MASK_HDMI_MSK | MASK_CSI_MSK;
2060 int err;
2061
2062 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2063 return -EIO;
2064 v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n",
2065 client->addr << 1, client->adapter->name);
2066
2067 state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state),
2068 GFP_KERNEL);
2069 if (!state)
2070 return -ENOMEM;
2071
2072 state->i2c_client = client;
2073
2074 /* platform data */
2075 if (pdata) {
2076 state->pdata = *pdata;
2077 state->bus.flags = 0;
2078 } else {
2079 err = tc358743_probe_of(state);
2080 if (err == -ENODEV)
2081 v4l_err(client, "No platform data!\n");
2082 if (err)
2083 return err;
2084 }
2085
2086 sd = &state->sd;
2087 v4l2_i2c_subdev_init(sd, client, &tc358743_ops);
2088 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
2089
2090 /* i2c access */
2091 if ((i2c_rd16(sd, CHIPID) & MASK_CHIPID) != 0) {
2092 v4l2_info(sd, "not a TC358743 on address 0x%x\n",
2093 client->addr << 1);
2094 return -ENODEV;
2095 }
2096
2097 /* control handlers */
2098 v4l2_ctrl_handler_init(&state->hdl, 3);
2099
2100 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL,
2101 V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
2102
2103 /* custom controls */
2104 state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl,
2105 &tc358743_ctrl_audio_sampling_rate, NULL);
2106
2107 state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl,
2108 &tc358743_ctrl_audio_present, NULL);
2109
2110 sd->ctrl_handler = &state->hdl;
2111 if (state->hdl.error) {
2112 err = state->hdl.error;
2113 goto err_hdl;
2114 }
2115
2116 if (tc358743_update_controls(sd)) {
2117 err = -ENODEV;
2118 goto err_hdl;
2119 }
2120
2121 state->pad.flags = MEDIA_PAD_FL_SOURCE;
2122 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
2123 err = media_entity_pads_init(&sd->entity, 1, &state->pad);
2124 if (err < 0)
2125 goto err_hdl;
2126
2127 state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24;
2128
2129 sd->dev = &client->dev;
2130
2131 mutex_init(&state->confctl_mutex);
2132
2133 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2134 tc358743_delayed_work_enable_hotplug);
2135
2136 #ifdef CONFIG_VIDEO_TC358743_CEC
2137 state->cec_adap = cec_allocate_adapter(&tc358743_cec_adap_ops,
2138 state, dev_name(&client->dev),
2139 CEC_CAP_DEFAULTS | CEC_CAP_MONITOR_ALL, CEC_MAX_LOG_ADDRS);
2140 if (IS_ERR(state->cec_adap)) {
2141 err = PTR_ERR(state->cec_adap);
2142 goto err_hdl;
2143 }
2144 irq_mask |= MASK_CEC_RMSK | MASK_CEC_TMSK;
2145 #endif
2146
2147 tc358743_initial_setup(sd);
2148
2149 tc358743_s_dv_timings(sd, 0, &default_timing);
2150
2151 tc358743_set_csi_color_space(sd);
2152
2153 tc358743_init_interrupts(sd);
2154
2155 if (state->i2c_client->irq) {
2156 err = devm_request_threaded_irq(&client->dev,
2157 state->i2c_client->irq,
2158 NULL, tc358743_irq_handler,
2159 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
2160 "tc358743", state);
2161 if (err)
2162 goto err_work_queues;
2163 } else {
2164 INIT_WORK(&state->work_i2c_poll,
2165 tc358743_work_i2c_poll);
2166 timer_setup(&state->timer, tc358743_irq_poll_timer, 0);
2167 state->timer.expires = jiffies +
2168 msecs_to_jiffies(POLL_INTERVAL_MS);
2169 add_timer(&state->timer);
2170 }
2171
2172 err = cec_register_adapter(state->cec_adap, &client->dev);
2173 if (err < 0) {
2174 pr_err("%s: failed to register the cec device\n", __func__);
2175 cec_delete_adapter(state->cec_adap);
2176 state->cec_adap = NULL;
2177 goto err_work_queues;
2178 }
2179
2180 tc358743_enable_interrupts(sd, tx_5v_power_present(sd));
2181 i2c_wr16(sd, INTMASK, ~irq_mask);
2182
2183 err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
2184 if (err)
2185 goto err_work_queues;
2186
2187 err = v4l2_async_register_subdev(sd);
2188 if (err < 0)
2189 goto err_work_queues;
2190
2191 state->debugfs_dir = debugfs_create_dir(sd->name, v4l2_debugfs_root());
2192 state->infoframes = v4l2_debugfs_if_alloc(state->debugfs_dir,
2193 V4L2_DEBUGFS_IF_AVI, sd,
2194 tc358743_debugfs_if_read);
2195
2196 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2197 client->addr << 1, client->adapter->name);
2198
2199 return 0;
2200
2201 err_work_queues:
2202 cec_unregister_adapter(state->cec_adap);
2203 if (!state->i2c_client->irq) {
2204 del_timer(&state->timer);
2205 flush_work(&state->work_i2c_poll);
2206 }
2207 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2208 mutex_destroy(&state->confctl_mutex);
2209 err_hdl:
2210 media_entity_cleanup(&sd->entity);
2211 v4l2_ctrl_handler_free(&state->hdl);
2212 return err;
2213 }
2214
2215 static void tc358743_remove(struct i2c_client *client)
2216 {
2217 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2218 struct tc358743_state *state = to_state(sd);
2219
2220 if (!state->i2c_client->irq) {
2221 del_timer_sync(&state->timer);
2222 flush_work(&state->work_i2c_poll);
2223 }
2224 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2225 v4l2_debugfs_if_free(state->infoframes);
2226 debugfs_remove_recursive(state->debugfs_dir);
2227 cec_unregister_adapter(state->cec_adap);
2228 v4l2_async_unregister_subdev(sd);
2229 v4l2_device_unregister_subdev(sd);
2230 mutex_destroy(&state->confctl_mutex);
2231 media_entity_cleanup(&sd->entity);
2232 v4l2_ctrl_handler_free(&state->hdl);
2233 }
2234
2235 static const struct i2c_device_id tc358743_id[] = {
2236 { "tc358743" },
2237 {}
2238 };
2239
2240 MODULE_DEVICE_TABLE(i2c, tc358743_id);
2241
2242 #if IS_ENABLED(CONFIG_OF)
2243 static const struct of_device_id tc358743_of_match[] = {
2244 { .compatible = "toshiba,tc358743" },
2245 {},
2246 };
2247 MODULE_DEVICE_TABLE(of, tc358743_of_match);
2248 #endif
2249
2250 static struct i2c_driver tc358743_driver = {
2251 .driver = {
2252 .name = "tc358743",
2253 .of_match_table = of_match_ptr(tc358743_of_match),
2254 },
2255 .probe = tc358743_probe,
2256 .remove = tc358743_remove,
2257 .id_table = tc358743_id,
2258 };
2259
2260 module_i2c_driver(tc358743_driver);
Kernel DRM miscellaneous fixes and cross-tree changes