drivers/media/i2c/tvp7002.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
   3  * Digitizer with Horizontal PLL registers
   4  *
   5  * Copyright (C) 2009 Texas Instruments Inc
   6  * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
   7  *
   8  * This code is partially based upon the TVP5150 driver
   9  * written by Mauro Carvalho Chehab <mchehab@kernel.org>,
  10  * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com>
  11  * and the TVP7002 driver in the TI LSP 2.10.00.14. Revisions by
  12  * Muralidharan Karicheri and Snehaprabha Narnakaje (TI).
  13  */
  14 #include <linux/delay.h>
  15 #include <linux/i2c.h>
  16 #include <linux/slab.h>
  17 #include <linux/videodev2.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_graph.h>
  21 #include <linux/v4l2-dv-timings.h>
  22 #include <media/i2c/tvp7002.h>
  23 #include <media/v4l2-async.h>
  24 #include <media/v4l2-device.h>
  25 #include <media/v4l2-common.h>
  26 #include <media/v4l2-ctrls.h>
  27 #include <media/v4l2-fwnode.h>
  28
  29 #include "tvp7002_reg.h"
  30
  31 MODULE_DESCRIPTION("TI TVP7002 Video and Graphics Digitizer driver");
  32 MODULE_AUTHOR("Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>");
  33 MODULE_LICENSE("GPL");
  34
  35 /* I2C retry attempts */
  36 #define I2C_RETRY_COUNT         (5)
  37
  38 /* End of registers */
  39 #define TVP7002_EOR             0x5c
  40
  41 /* Read write definition for registers */
  42 #define TVP7002_READ            0
  43 #define TVP7002_WRITE           1
  44 #define TVP7002_RESERVED        2
  45
  46 /* Interlaced vs progressive mask and shift */
  47 #define TVP7002_IP_SHIFT        5
  48 #define TVP7002_INPR_MASK       (0x01 << TVP7002_IP_SHIFT)
  49
  50 /* Shift for CPL and LPF registers */
  51 #define TVP7002_CL_SHIFT        8
  52 #define TVP7002_CL_MASK         0x0f
  53
  54 /* Debug functions */
  55 static bool debug;
  56 module_param(debug, bool, 0644);
  57 MODULE_PARM_DESC(debug, "Debug level (0-2)");
  58
  59 /* Structure for register values */
  60 struct i2c_reg_value {
  61         u8 reg;
  62         u8 value;
  63         u8 type;
  64 };
  65
  66 /*
  67  * Register default values (according to tvp7002 datasheet)
  68  * In the case of read-only registers, the value (0xff) is
  69  * never written. R/W functionality is controlled by the
  70  * writable bit in the register struct definition.
  71  */
  72 static const struct i2c_reg_value tvp7002_init_default[] = {
  73         { TVP7002_CHIP_REV, 0xff, TVP7002_READ },
  74         { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE },
  75         { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE },
  76         { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE },
  77         { TVP7002_HPLL_PHASE_SEL, 0x80, TVP7002_WRITE },
  78         { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  79         { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  80         { TVP7002_HSYNC_OUT_W, 0x60, TVP7002_WRITE },
  81         { TVP7002_B_FINE_GAIN, 0x00, TVP7002_WRITE },
  82         { TVP7002_G_FINE_GAIN, 0x00, TVP7002_WRITE },
  83         { TVP7002_R_FINE_GAIN, 0x00, TVP7002_WRITE },
  84         { TVP7002_B_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
  85         { TVP7002_G_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
  86         { TVP7002_R_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
  87         { TVP7002_SYNC_CTL_1, 0x20, TVP7002_WRITE },
  88         { TVP7002_HPLL_AND_CLAMP_CTL, 0x2e, TVP7002_WRITE },
  89         { TVP7002_SYNC_ON_G_THRS, 0x5d, TVP7002_WRITE },
  90         { TVP7002_SYNC_SEPARATOR_THRS, 0x47, TVP7002_WRITE },
  91         { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE },
  92         { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  93         { TVP7002_SYNC_DETECT_STAT, 0xff, TVP7002_READ },
  94         { TVP7002_OUT_FORMATTER, 0x47, TVP7002_WRITE },
  95         { TVP7002_MISC_CTL_1, 0x01, TVP7002_WRITE },
  96         { TVP7002_MISC_CTL_2, 0x00, TVP7002_WRITE },
  97         { TVP7002_MISC_CTL_3, 0x01, TVP7002_WRITE },
  98         { TVP7002_IN_MUX_SEL_1, 0x00, TVP7002_WRITE },
  99         { TVP7002_IN_MUX_SEL_2, 0x67, TVP7002_WRITE },
 100         { TVP7002_B_AND_G_COARSE_GAIN, 0x77, TVP7002_WRITE },
 101         { TVP7002_R_COARSE_GAIN, 0x07, TVP7002_WRITE },
 102         { TVP7002_FINE_OFF_LSBS, 0x00, TVP7002_WRITE },
 103         { TVP7002_B_COARSE_OFF, 0x10, TVP7002_WRITE },
 104         { TVP7002_G_COARSE_OFF, 0x10, TVP7002_WRITE },
 105         { TVP7002_R_COARSE_OFF, 0x10, TVP7002_WRITE },
 106         { TVP7002_HSOUT_OUT_START, 0x08, TVP7002_WRITE },
 107         { TVP7002_MISC_CTL_4, 0x00, TVP7002_WRITE },
 108         { TVP7002_B_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
 109         { TVP7002_G_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
 110         { TVP7002_R_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
 111         { TVP7002_AUTO_LVL_CTL_ENABLE, 0x80, TVP7002_WRITE },
 112         { TVP7002_DGTL_ALC_OUT_MSBS, 0xff, TVP7002_READ },
 113         { TVP7002_AUTO_LVL_CTL_FILTER, 0x53, TVP7002_WRITE },
 114         { 0x29, 0x08, TVP7002_RESERVED },
 115         { TVP7002_FINE_CLAMP_CTL, 0x07, TVP7002_WRITE },
 116         /* PWR_CTL is controlled only by the probe and reset functions */
 117         { TVP7002_PWR_CTL, 0x00, TVP7002_RESERVED },
 118         { TVP7002_ADC_SETUP, 0x50, TVP7002_WRITE },
 119         { TVP7002_COARSE_CLAMP_CTL, 0x00, TVP7002_WRITE },
 120         { TVP7002_SOG_CLAMP, 0x80, TVP7002_WRITE },
 121         { TVP7002_RGB_COARSE_CLAMP_CTL, 0x8c, TVP7002_WRITE },
 122         { TVP7002_SOG_COARSE_CLAMP_CTL, 0x04, TVP7002_WRITE },
 123         { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
 124         { 0x32, 0x18, TVP7002_RESERVED },
 125         { 0x33, 0x60, TVP7002_RESERVED },
 126         { TVP7002_MVIS_STRIPPER_W, 0xff, TVP7002_RESERVED },
 127         { TVP7002_VSYNC_ALGN, 0x10, TVP7002_WRITE },
 128         { TVP7002_SYNC_BYPASS, 0x00, TVP7002_WRITE },
 129         { TVP7002_L_FRAME_STAT_LSBS, 0xff, TVP7002_READ },
 130         { TVP7002_L_FRAME_STAT_MSBS, 0xff, TVP7002_READ },
 131         { TVP7002_CLK_L_STAT_LSBS, 0xff, TVP7002_READ },
 132         { TVP7002_CLK_L_STAT_MSBS, 0xff, TVP7002_READ },
 133         { TVP7002_HSYNC_W, 0xff, TVP7002_READ },
 134         { TVP7002_VSYNC_W, 0xff, TVP7002_READ },
 135         { TVP7002_L_LENGTH_TOL, 0x03, TVP7002_WRITE },
 136         { 0x3e, 0x60, TVP7002_RESERVED },
 137         { TVP7002_VIDEO_BWTH_CTL, 0x01, TVP7002_WRITE },
 138         { TVP7002_AVID_START_PIXEL_LSBS, 0x01, TVP7002_WRITE },
 139         { TVP7002_AVID_START_PIXEL_MSBS, 0x2c, TVP7002_WRITE },
 140         { TVP7002_AVID_STOP_PIXEL_LSBS, 0x06, TVP7002_WRITE },
 141         { TVP7002_AVID_STOP_PIXEL_MSBS, 0x2c, TVP7002_WRITE },
 142         { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
 143         { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
 144         { TVP7002_VBLK_F_0_DURATION, 0x1e, TVP7002_WRITE },
 145         { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
 146         { TVP7002_FBIT_F_0_START_L_OFF, 0x00, TVP7002_WRITE },
 147         { TVP7002_FBIT_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
 148         { TVP7002_YUV_Y_G_COEF_LSBS, 0xe3, TVP7002_WRITE },
 149         { TVP7002_YUV_Y_G_COEF_MSBS, 0x16, TVP7002_WRITE },
 150         { TVP7002_YUV_Y_B_COEF_LSBS, 0x4f, TVP7002_WRITE },
 151         { TVP7002_YUV_Y_B_COEF_MSBS, 0x02, TVP7002_WRITE },
 152         { TVP7002_YUV_Y_R_COEF_LSBS, 0xce, TVP7002_WRITE },
 153         { TVP7002_YUV_Y_R_COEF_MSBS, 0x06, TVP7002_WRITE },
 154         { TVP7002_YUV_U_G_COEF_LSBS, 0xab, TVP7002_WRITE },
 155         { TVP7002_YUV_U_G_COEF_MSBS, 0xf3, TVP7002_WRITE },
 156         { TVP7002_YUV_U_B_COEF_LSBS, 0x00, TVP7002_WRITE },
 157         { TVP7002_YUV_U_B_COEF_MSBS, 0x10, TVP7002_WRITE },
 158         { TVP7002_YUV_U_R_COEF_LSBS, 0x55, TVP7002_WRITE },
 159         { TVP7002_YUV_U_R_COEF_MSBS, 0xfc, TVP7002_WRITE },
 160         { TVP7002_YUV_V_G_COEF_LSBS, 0x78, TVP7002_WRITE },
 161         { TVP7002_YUV_V_G_COEF_MSBS, 0xf1, TVP7002_WRITE },
 162         { TVP7002_YUV_V_B_COEF_LSBS, 0x88, TVP7002_WRITE },
 163         { TVP7002_YUV_V_B_COEF_MSBS, 0xfe, TVP7002_WRITE },
 164         { TVP7002_YUV_V_R_COEF_LSBS, 0x00, TVP7002_WRITE },
 165         { TVP7002_YUV_V_R_COEF_MSBS, 0x10, TVP7002_WRITE },
 166         /* This signals end of register values */
 167         { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 168 };
 169
 170 /* Register parameters for 480P */
 171 static const struct i2c_reg_value tvp7002_parms_480P[] = {
 172         { TVP7002_HPLL_FDBK_DIV_MSBS, 0x35, TVP7002_WRITE },
 173         { TVP7002_HPLL_FDBK_DIV_LSBS, 0xa0, TVP7002_WRITE },
 174         { TVP7002_HPLL_CRTL, 0x02, TVP7002_WRITE },
 175         { TVP7002_AVID_START_PIXEL_LSBS, 0x91, TVP7002_WRITE },
 176         { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE },
 177         { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0B, TVP7002_WRITE },
 178         { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE },
 179         { TVP7002_VBLK_F_0_START_L_OFF, 0x03, TVP7002_WRITE },
 180         { TVP7002_VBLK_F_1_START_L_OFF, 0x01, TVP7002_WRITE },
 181         { TVP7002_VBLK_F_0_DURATION, 0x13, TVP7002_WRITE },
 182         { TVP7002_VBLK_F_1_DURATION, 0x13, TVP7002_WRITE },
 183         { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE },
 184         { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE },
 185         { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE },
 186         { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE },
 187         { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE },
 188         { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 189 };
 190
 191 /* Register parameters for 576P */
 192 static const struct i2c_reg_value tvp7002_parms_576P[] = {
 193         { TVP7002_HPLL_FDBK_DIV_MSBS, 0x36, TVP7002_WRITE },
 194         { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE },
 195         { TVP7002_HPLL_CRTL, 0x18, TVP7002_WRITE },
 196         { TVP7002_AVID_START_PIXEL_LSBS, 0x9B, TVP7002_WRITE },
 197         { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE },
 198         { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0F, TVP7002_WRITE },
 199         { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE },
 200         { TVP7002_VBLK_F_0_START_L_OFF, 0x00, TVP7002_WRITE },
 201         { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
 202         { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
 203         { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
 204         { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE },
 205         { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE },
 206         { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE },
 207         { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE },
 208         { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE },
 209         { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 210 };
 211
 212 /* Register parameters for 1080I60 */
 213 static const struct i2c_reg_value tvp7002_parms_1080I60[] = {
 214         { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
 215         { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
 216         { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
 217         { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
 218         { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
 219         { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
 220         { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
 221         { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
 222         { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
 223         { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
 224         { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
 225         { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
 226         { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
 227         { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
 228         { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
 229         { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
 230         { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 231 };
 232
 233 /* Register parameters for 1080P60 */
 234 static const struct i2c_reg_value tvp7002_parms_1080P60[] = {
 235         { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
 236         { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
 237         { TVP7002_HPLL_CRTL, 0xE0, TVP7002_WRITE },
 238         { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
 239         { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
 240         { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
 241         { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
 242         { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
 243         { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
 244         { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
 245         { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
 246         { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
 247         { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
 248         { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
 249         { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
 250         { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
 251         { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 252 };
 253
 254 /* Register parameters for 1080I50 */
 255 static const struct i2c_reg_value tvp7002_parms_1080I50[] = {
 256         { TVP7002_HPLL_FDBK_DIV_MSBS, 0xa5, TVP7002_WRITE },
 257         { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE },
 258         { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
 259         { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
 260         { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
 261         { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
 262         { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
 263         { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
 264         { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
 265         { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
 266         { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
 267         { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
 268         { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
 269         { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
 270         { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
 271         { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
 272         { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 273 };
 274
 275 /* Register parameters for 720P60 */
 276 static const struct i2c_reg_value tvp7002_parms_720P60[] = {
 277         { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE },
 278         { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE },
 279         { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE },
 280         { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
 281         { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
 282         { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE },
 283         { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE },
 284         { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
 285         { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
 286         { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
 287         { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
 288         { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
 289         { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
 290         { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
 291         { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE },
 292         { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
 293         { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 294 };
 295
 296 /* Register parameters for 720P50 */
 297 static const struct i2c_reg_value tvp7002_parms_720P50[] = {
 298         { TVP7002_HPLL_FDBK_DIV_MSBS, 0x7b, TVP7002_WRITE },
 299         { TVP7002_HPLL_FDBK_DIV_LSBS, 0xc0, TVP7002_WRITE },
 300         { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
 301         { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
 302         { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
 303         { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE },
 304         { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE },
 305         { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
 306         { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
 307         { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
 308         { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
 309         { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
 310         { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
 311         { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
 312         { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
 313         { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
 314         { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 315 };
 316
 317 /* Timings definition for handling device operation */
 318 struct tvp7002_timings_definition {
 319         struct v4l2_dv_timings timings;
 320         const struct i2c_reg_value *p_settings;
 321         enum v4l2_colorspace color_space;
 322         enum v4l2_field scanmode;
 323         u16 progressive;
 324         u16 lines_per_frame;
 325         u16 cpl_min;
 326         u16 cpl_max;
 327 };
 328
 329 /* Struct list for digital video timings */
 330 static const struct tvp7002_timings_definition tvp7002_timings[] = {
 331         {
 332                 V4L2_DV_BT_CEA_1280X720P60,
 333                 tvp7002_parms_720P60,
 334                 V4L2_COLORSPACE_REC709,
 335                 V4L2_FIELD_NONE,
 336                 1,
 337                 0x2EE,
 338                 135,
 339                 153
 340         },
 341         {
 342                 V4L2_DV_BT_CEA_1920X1080I60,
 343                 tvp7002_parms_1080I60,
 344                 V4L2_COLORSPACE_REC709,
 345                 V4L2_FIELD_INTERLACED,
 346                 0,
 347                 0x465,
 348                 181,
 349                 205
 350         },
 351         {
 352                 V4L2_DV_BT_CEA_1920X1080I50,
 353                 tvp7002_parms_1080I50,
 354                 V4L2_COLORSPACE_REC709,
 355                 V4L2_FIELD_INTERLACED,
 356                 0,
 357                 0x465,
 358                 217,
 359                 245
 360         },
 361         {
 362                 V4L2_DV_BT_CEA_1280X720P50,
 363                 tvp7002_parms_720P50,
 364                 V4L2_COLORSPACE_REC709,
 365                 V4L2_FIELD_NONE,
 366                 1,
 367                 0x2EE,
 368                 163,
 369                 183
 370         },
 371         {
 372                 V4L2_DV_BT_CEA_1920X1080P60,
 373                 tvp7002_parms_1080P60,
 374                 V4L2_COLORSPACE_REC709,
 375                 V4L2_FIELD_NONE,
 376                 1,
 377                 0x465,
 378                 90,
 379                 102
 380         },
 381         {
 382                 V4L2_DV_BT_CEA_720X480P59_94,
 383                 tvp7002_parms_480P,
 384                 V4L2_COLORSPACE_SMPTE170M,
 385                 V4L2_FIELD_NONE,
 386                 1,
 387                 0x20D,
 388                 0xffff,
 389                 0xffff
 390         },
 391         {
 392                 V4L2_DV_BT_CEA_720X576P50,
 393                 tvp7002_parms_576P,
 394                 V4L2_COLORSPACE_SMPTE170M,
 395                 V4L2_FIELD_NONE,
 396                 1,
 397                 0x271,
 398                 0xffff,
 399                 0xffff
 400         }
 401 };
 402
 403 #define NUM_TIMINGS ARRAY_SIZE(tvp7002_timings)
 404
 405 /* Device definition */
 406 struct tvp7002 {
 407         struct v4l2_subdev sd;
 408         struct v4l2_ctrl_handler hdl;
 409         const struct tvp7002_config *pdata;
 410
 411         int ver;
 412         int streaming;
 413
 414         const struct tvp7002_timings_definition *current_timings;
 415         struct media_pad pad;
 416 };
 417
 418 /*
 419  * to_tvp7002 - Obtain device handler TVP7002
 420  * @sd: ptr to v4l2_subdev struct
 421  *
 422  * Returns device handler tvp7002.
 423  */
 424 static inline struct tvp7002 *to_tvp7002(struct v4l2_subdev *sd)
 425 {
 426         return container_of(sd, struct tvp7002, sd);
 427 }
 428
 429 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
 430 {
 431         return &container_of(ctrl->handler, struct tvp7002, hdl)->sd;
 432 }
 433
 434 /*
 435  * tvp7002_read - Read a value from a register in an TVP7002
 436  * @sd: ptr to v4l2_subdev struct
 437  * @addr: TVP7002 register address
 438  * @dst: pointer to 8-bit destination
 439  *
 440  * Returns value read if successful, or non-zero (-1) otherwise.
 441  */
 442 static int tvp7002_read(struct v4l2_subdev *sd, u8 addr, u8 *dst)
 443 {
 444         struct i2c_client *c = v4l2_get_subdevdata(sd);
 445         int retry;
 446         int error;
 447
 448         for (retry = 0; retry < I2C_RETRY_COUNT; retry++) {
 449                 error = i2c_smbus_read_byte_data(c, addr);
 450
 451                 if (error >= 0) {
 452                         *dst = (u8)error;
 453                         return 0;
 454                 }
 455
 456                 msleep_interruptible(10);
 457         }
 458         v4l2_err(sd, "TVP7002 read error %d\n", error);
 459         return error;
 460 }
 461
 462 /*
 463  * tvp7002_read_err() - Read a register value with error code
 464  * @sd: pointer to standard V4L2 sub-device structure
 465  * @reg: destination register
 466  * @val: value to be read
 467  * @err: pointer to error value
 468  *
 469  * Read a value in a register and save error value in pointer.
 470  * Also update the register table if successful
 471  */
 472 static inline void tvp7002_read_err(struct v4l2_subdev *sd, u8 reg,
 473                                                         u8 *dst, int *err)
 474 {
 475         if (!*err)
 476                 *err = tvp7002_read(sd, reg, dst);
 477 }
 478
 479 /*
 480  * tvp7002_write() - Write a value to a register in TVP7002
 481  * @sd: ptr to v4l2_subdev struct
 482  * @addr: TVP7002 register address
 483  * @value: value to be written to the register
 484  *
 485  * Write a value to a register in an TVP7002 decoder device.
 486  * Returns zero if successful, or non-zero otherwise.
 487  */
 488 static int tvp7002_write(struct v4l2_subdev *sd, u8 addr, u8 value)
 489 {
 490         struct i2c_client *c;
 491         int retry;
 492         int error;
 493
 494         c = v4l2_get_subdevdata(sd);
 495
 496         for (retry = 0; retry < I2C_RETRY_COUNT; retry++) {
 497                 error = i2c_smbus_write_byte_data(c, addr, value);
 498
 499                 if (error >= 0)
 500                         return 0;
 501
 502                 v4l2_warn(sd, "Write: retry ... %d\n", retry);
 503                 msleep_interruptible(10);
 504         }
 505         v4l2_err(sd, "TVP7002 write error %d\n", error);
 506         return error;
 507 }
 508
 509 /*
 510  * tvp7002_write_err() - Write a register value with error code
 511  * @sd: pointer to standard V4L2 sub-device structure
 512  * @reg: destination register
 513  * @val: value to be written
 514  * @err: pointer to error value
 515  *
 516  * Write a value in a register and save error value in pointer.
 517  * Also update the register table if successful
 518  */
 519 static inline void tvp7002_write_err(struct v4l2_subdev *sd, u8 reg,
 520                                                         u8 val, int *err)
 521 {
 522         if (!*err)
 523                 *err = tvp7002_write(sd, reg, val);
 524 }
 525
 526 /*
 527  * tvp7002_write_inittab() - Write initialization values
 528  * @sd: ptr to v4l2_subdev struct
 529  * @regs: ptr to i2c_reg_value struct
 530  *
 531  * Write initialization values.
 532  * Returns zero or -EINVAL if read operation fails.
 533  */
 534 static int tvp7002_write_inittab(struct v4l2_subdev *sd,
 535                                         const struct i2c_reg_value *regs)
 536 {
 537         int error = 0;
 538
 539         /* Initialize the first (defined) registers */
 540         while (TVP7002_EOR != regs->reg) {
 541                 if (TVP7002_WRITE == regs->type)
 542                         tvp7002_write_err(sd, regs->reg, regs->value, &error);
 543                 regs++;
 544         }
 545
 546         return error;
 547 }
 548
 549 static int tvp7002_s_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
 550                                 struct v4l2_dv_timings *dv_timings)
 551 {
 552         struct tvp7002 *device = to_tvp7002(sd);
 553         const struct v4l2_bt_timings *bt = &dv_timings->bt;
 554         int i;
 555
 556         if (pad != 0)
 557                 return -EINVAL;
 558
 559         if (dv_timings->type != V4L2_DV_BT_656_1120)
 560                 return -EINVAL;
 561         for (i = 0; i < NUM_TIMINGS; i++) {
 562                 const struct v4l2_bt_timings *t = &tvp7002_timings[i].timings.bt;
 563
 564                 if (!memcmp(bt, t, &bt->standards - &bt->width)) {
 565                         device->current_timings = &tvp7002_timings[i];
 566                         return tvp7002_write_inittab(sd, tvp7002_timings[i].p_settings);
 567                 }
 568         }
 569         return -EINVAL;
 570 }
 571
 572 static int tvp7002_g_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
 573                                 struct v4l2_dv_timings *dv_timings)
 574 {
 575         struct tvp7002 *device = to_tvp7002(sd);
 576
 577         if (pad != 0)
 578                 return -EINVAL;
 579
 580         *dv_timings = device->current_timings->timings;
 581         return 0;
 582 }
 583
 584 /*
 585  * tvp7002_s_ctrl() - Set a control
 586  * @ctrl: ptr to v4l2_ctrl struct
 587  *
 588  * Set a control in TVP7002 decoder device.
 589  * Returns zero when successful or -EINVAL if register access fails.
 590  */
 591 static int tvp7002_s_ctrl(struct v4l2_ctrl *ctrl)
 592 {
 593         struct v4l2_subdev *sd = to_sd(ctrl);
 594         int error = 0;
 595
 596         switch (ctrl->id) {
 597         case V4L2_CID_GAIN:
 598                 tvp7002_write_err(sd, TVP7002_R_FINE_GAIN, ctrl->val, &error);
 599                 tvp7002_write_err(sd, TVP7002_G_FINE_GAIN, ctrl->val, &error);
 600                 tvp7002_write_err(sd, TVP7002_B_FINE_GAIN, ctrl->val, &error);
 601                 return error;
 602         }
 603         return -EINVAL;
 604 }
 605
 606 /*
 607  * tvp7002_query_dv() - query DV timings
 608  * @sd: pointer to standard V4L2 sub-device structure
 609  * @index: index into the tvp7002_timings array
 610  *
 611  * Returns the current DV timings detected by TVP7002. If no active input is
 612  * detected, returns -EINVAL
 613  */
 614 static int tvp7002_query_dv(struct v4l2_subdev *sd, int *index)
 615 {
 616         const struct tvp7002_timings_definition *timings = tvp7002_timings;
 617         u8 progressive;
 618         u32 lpfr;
 619         u32 cpln;
 620         int error = 0;
 621         u8 lpf_lsb;
 622         u8 lpf_msb;
 623         u8 cpl_lsb;
 624         u8 cpl_msb;
 625
 626         /* Return invalid index if no active input is detected */
 627         *index = NUM_TIMINGS;
 628
 629         /* Read standards from device registers */
 630         tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_LSBS, &lpf_lsb, &error);
 631         tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_MSBS, &lpf_msb, &error);
 632
 633         if (error < 0)
 634                 return error;
 635
 636         tvp7002_read_err(sd, TVP7002_CLK_L_STAT_LSBS, &cpl_lsb, &error);
 637         tvp7002_read_err(sd, TVP7002_CLK_L_STAT_MSBS, &cpl_msb, &error);
 638
 639         if (error < 0)
 640                 return error;
 641
 642         /* Get lines per frame, clocks per line and interlaced/progresive */
 643         lpfr = lpf_lsb | ((TVP7002_CL_MASK & lpf_msb) << TVP7002_CL_SHIFT);
 644         cpln = cpl_lsb | ((TVP7002_CL_MASK & cpl_msb) << TVP7002_CL_SHIFT);
 645         progressive = (lpf_msb & TVP7002_INPR_MASK) >> TVP7002_IP_SHIFT;
 646
 647         /* Do checking of video modes */
 648         for (*index = 0; *index < NUM_TIMINGS; (*index)++, timings++)
 649                 if (lpfr == timings->lines_per_frame &&
 650                         progressive == timings->progressive) {
 651                         if (timings->cpl_min == 0xffff)
 652                                 break;
 653                         if (cpln >= timings->cpl_min && cpln <= timings->cpl_max)
 654                                 break;
 655                 }
 656
 657         if (*index == NUM_TIMINGS) {
 658                 v4l2_dbg(1, debug, sd, "detection failed: lpf = %x, cpl = %x\n",
 659                                                                 lpfr, cpln);
 660                 return -ENOLINK;
 661         }
 662
 663         /* Update lines per frame and clocks per line info */
 664         v4l2_dbg(1, debug, sd, "detected timings: %d\n", *index);
 665         return 0;
 666 }
 667
 668 static int tvp7002_query_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
 669                                     struct v4l2_dv_timings *timings)
 670 {
 671         int index;
 672         int err;
 673
 674         if (pad != 0)
 675                 return -EINVAL;
 676
 677         err = tvp7002_query_dv(sd, &index);
 678         if (err)
 679                 return err;
 680         *timings = tvp7002_timings[index].timings;
 681         return 0;
 682 }
 683
 684 #ifdef CONFIG_VIDEO_ADV_DEBUG
 685 /*
 686  * tvp7002_g_register() - Get the value of a register
 687  * @sd: ptr to v4l2_subdev struct
 688  * @reg: ptr to v4l2_dbg_register struct
 689  *
 690  * Get the value of a TVP7002 decoder device register.
 691  * Returns zero when successful, -EINVAL if register read fails or
 692  * access to I2C client fails.
 693  */
 694 static int tvp7002_g_register(struct v4l2_subdev *sd,
 695                                                 struct v4l2_dbg_register *reg)
 696 {
 697         u8 val;
 698         int ret;
 699
 700         ret = tvp7002_read(sd, reg->reg & 0xff, &val);
 701         if (ret < 0)
 702                 return ret;
 703         reg->val = val;
 704         reg->size = 1;
 705         return 0;
 706 }
 707
 708 /*
 709  * tvp7002_s_register() - set a control
 710  * @sd: ptr to v4l2_subdev struct
 711  * @reg: ptr to v4l2_dbg_register struct
 712  *
 713  * Get the value of a TVP7002 decoder device register.
 714  * Returns zero when successful, -EINVAL if register read fails.
 715  */
 716 static int tvp7002_s_register(struct v4l2_subdev *sd,
 717                                                 const struct v4l2_dbg_register *reg)
 718 {
 719         return tvp7002_write(sd, reg->reg & 0xff, reg->val & 0xff);
 720 }
 721 #endif
 722
 723 /*
 724  * tvp7002_s_stream() - V4L2 decoder i/f handler for s_stream
 725  * @sd: pointer to standard V4L2 sub-device structure
 726  * @enable: streaming enable or disable
 727  *
 728  * Sets streaming to enable or disable, if possible.
 729  */
 730 static int tvp7002_s_stream(struct v4l2_subdev *sd, int enable)
 731 {
 732         struct tvp7002 *device = to_tvp7002(sd);
 733         int error;
 734
 735         if (device->streaming == enable)
 736                 return 0;
 737
 738         /* low impedance: on, high impedance: off */
 739         error = tvp7002_write(sd, TVP7002_MISC_CTL_2, enable ? 0x00 : 0x03);
 740         if (error) {
 741                 v4l2_dbg(1, debug, sd, "Fail to set streaming\n");
 742                 return error;
 743         }
 744
 745         device->streaming = enable;
 746         return 0;
 747 }
 748
 749 /*
 750  * tvp7002_log_status() - Print information about register settings
 751  * @sd: ptr to v4l2_subdev struct
 752  *
 753  * Log register values of a TVP7002 decoder device.
 754  * Returns zero or -EINVAL if read operation fails.
 755  */
 756 static int tvp7002_log_status(struct v4l2_subdev *sd)
 757 {
 758         struct tvp7002 *device = to_tvp7002(sd);
 759         const struct v4l2_bt_timings *bt;
 760         int detected;
 761
 762         /* Find my current timings */
 763         tvp7002_query_dv(sd, &detected);
 764
 765         bt = &device->current_timings->timings.bt;
 766         v4l2_info(sd, "Selected DV Timings: %ux%u\n", bt->width, bt->height);
 767         if (detected == NUM_TIMINGS) {
 768                 v4l2_info(sd, "Detected DV Timings: None\n");
 769         } else {
 770                 bt = &tvp7002_timings[detected].timings.bt;
 771                 v4l2_info(sd, "Detected DV Timings: %ux%u\n",
 772                                 bt->width, bt->height);
 773         }
 774         v4l2_info(sd, "Streaming enabled: %s\n",
 775                                         device->streaming ? "yes" : "no");
 776
 777         /* Print the current value of the gain control */
 778         v4l2_ctrl_handler_log_status(&device->hdl, sd->name);
 779
 780         return 0;
 781 }
 782
 783 static int tvp7002_enum_dv_timings(struct v4l2_subdev *sd,
 784                 struct v4l2_enum_dv_timings *timings)
 785 {
 786         if (timings->pad != 0)
 787                 return -EINVAL;
 788
 789         /* Check requested format index is within range */
 790         if (timings->index >= NUM_TIMINGS)
 791                 return -EINVAL;
 792
 793         timings->timings = tvp7002_timings[timings->index].timings;
 794         return 0;
 795 }
 796
 797 static const struct v4l2_ctrl_ops tvp7002_ctrl_ops = {
 798         .s_ctrl = tvp7002_s_ctrl,
 799 };
 800
 801 /*
 802  * tvp7002_enum_mbus_code() - Enum supported digital video format on pad
 803  * @sd: pointer to standard V4L2 sub-device structure
 804  * @sd_state: V4L2 subdev state
 805  * @code: pointer to subdev enum mbus code struct
 806  *
 807  * Enumerate supported digital video formats for pad.
 808  */
 809 static int
 810 tvp7002_enum_mbus_code(struct v4l2_subdev *sd,
 811                        struct v4l2_subdev_state *sd_state,
 812                        struct v4l2_subdev_mbus_code_enum *code)
 813 {
 814         /* Check requested format index is within range */
 815         if (code->index != 0)
 816                 return -EINVAL;
 817
 818         code->code = MEDIA_BUS_FMT_YUYV10_1X20;
 819
 820         return 0;
 821 }
 822
 823 /*
 824  * tvp7002_get_pad_format() - get video format on pad
 825  * @sd: pointer to standard V4L2 sub-device structure
 826  * @sd_state: V4L2 subdev state
 827  * @fmt: pointer to subdev format struct
 828  *
 829  * get video format for pad.
 830  */
 831 static int
 832 tvp7002_get_pad_format(struct v4l2_subdev *sd,
 833                        struct v4l2_subdev_state *sd_state,
 834                        struct v4l2_subdev_format *fmt)
 835 {
 836         struct tvp7002 *tvp7002 = to_tvp7002(sd);
 837
 838         fmt->format.code = MEDIA_BUS_FMT_YUYV10_1X20;
 839         fmt->format.width = tvp7002->current_timings->timings.bt.width;
 840         fmt->format.height = tvp7002->current_timings->timings.bt.height;
 841         fmt->format.field = tvp7002->current_timings->scanmode;
 842         fmt->format.colorspace = tvp7002->current_timings->color_space;
 843
 844         return 0;
 845 }
 846
 847 /*
 848  * tvp7002_set_pad_format() - set video format on pad
 849  * @sd: pointer to standard V4L2 sub-device structure
 850  * @sd_state: V4L2 subdev state
 851  * @fmt: pointer to subdev format struct
 852  *
 853  * set video format for pad.
 854  */
 855 static int
 856 tvp7002_set_pad_format(struct v4l2_subdev *sd,
 857                        struct v4l2_subdev_state *sd_state,
 858                        struct v4l2_subdev_format *fmt)
 859 {
 860         return tvp7002_get_pad_format(sd, sd_state, fmt);
 861 }
 862
 863 /* V4L2 core operation handlers */
 864 static const struct v4l2_subdev_core_ops tvp7002_core_ops = {
 865         .log_status = tvp7002_log_status,
 866 #ifdef CONFIG_VIDEO_ADV_DEBUG
 867         .g_register = tvp7002_g_register,
 868         .s_register = tvp7002_s_register,
 869 #endif
 870 };
 871
 872 /* Specific video subsystem operation handlers */
 873 static const struct v4l2_subdev_video_ops tvp7002_video_ops = {
 874         .s_stream = tvp7002_s_stream,
 875 };
 876
 877 /* media pad related operation handlers */
 878 static const struct v4l2_subdev_pad_ops tvp7002_pad_ops = {
 879         .enum_mbus_code = tvp7002_enum_mbus_code,
 880         .get_fmt = tvp7002_get_pad_format,
 881         .set_fmt = tvp7002_set_pad_format,
 882         .g_dv_timings = tvp7002_g_dv_timings,
 883         .s_dv_timings = tvp7002_s_dv_timings,
 884         .query_dv_timings = tvp7002_query_dv_timings,
 885         .enum_dv_timings = tvp7002_enum_dv_timings,
 886 };
 887
 888 /* V4L2 top level operation handlers */
 889 static const struct v4l2_subdev_ops tvp7002_ops = {
 890         .core = &tvp7002_core_ops,
 891         .video = &tvp7002_video_ops,
 892         .pad = &tvp7002_pad_ops,
 893 };
 894
 895 static struct tvp7002_config *
 896 tvp7002_get_pdata(struct i2c_client *client)
 897 {
 898         struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
 899         struct tvp7002_config *pdata = NULL;
 900         struct device_node *endpoint;
 901         unsigned int flags;
 902
 903         if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
 904                 return client->dev.platform_data;
 905
 906         endpoint = of_graph_get_endpoint_by_regs(client->dev.of_node, 0, -1);
 907         if (!endpoint)
 908                 return NULL;
 909
 910         if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), &bus_cfg))
 911                 goto done;
 912
 913         pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
 914         if (!pdata)
 915                 goto done;
 916
 917         flags = bus_cfg.bus.parallel.flags;
 918
 919         if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
 920                 pdata->hs_polarity = 1;
 921
 922         if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
 923                 pdata->vs_polarity = 1;
 924
 925         if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
 926                 pdata->clk_polarity = 1;
 927
 928         if (flags & V4L2_MBUS_FIELD_EVEN_HIGH)
 929                 pdata->fid_polarity = 1;
 930
 931         if (flags & V4L2_MBUS_VIDEO_SOG_ACTIVE_HIGH)
 932                 pdata->sog_polarity = 1;
 933
 934 done:
 935         of_node_put(endpoint);
 936         return pdata;
 937 }
 938
 939 /*
 940  * tvp7002_probe - Probe a TVP7002 device
 941  * @c: ptr to i2c_client struct
 942  * @id: ptr to i2c_device_id struct
 943  *
 944  * Initialize the TVP7002 device
 945  * Returns zero when successful, -EINVAL if register read fails or
 946  * -EIO if i2c access is not available.
 947  */
 948 static int tvp7002_probe(struct i2c_client *c)
 949 {
 950         struct tvp7002_config *pdata = tvp7002_get_pdata(c);
 951         struct v4l2_subdev *sd;
 952         struct tvp7002 *device;
 953         struct v4l2_dv_timings timings;
 954         int polarity_a;
 955         int polarity_b;
 956         u8 revision;
 957         int error;
 958
 959         if (pdata == NULL) {
 960                 dev_err(&c->dev, "No platform data\n");
 961                 return -EINVAL;
 962         }
 963
 964         /* Check if the adapter supports the needed features */
 965         if (!i2c_check_functionality(c->adapter,
 966                 I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
 967                 return -EIO;
 968
 969         device = devm_kzalloc(&c->dev, sizeof(struct tvp7002), GFP_KERNEL);
 970
 971         if (!device)
 972                 return -ENOMEM;
 973
 974         sd = &device->sd;
 975         device->pdata = pdata;
 976         device->current_timings = tvp7002_timings;
 977
 978         /* Tell v4l2 the device is ready */
 979         v4l2_i2c_subdev_init(sd, c, &tvp7002_ops);
 980         v4l_info(c, "tvp7002 found @ 0x%02x (%s)\n",
 981                                         c->addr, c->adapter->name);
 982
 983         error = tvp7002_read(sd, TVP7002_CHIP_REV, &revision);
 984         if (error < 0)
 985                 return error;
 986
 987         /* Get revision number */
 988         v4l2_info(sd, "Rev. %02x detected.\n", revision);
 989         if (revision != 0x02)
 990                 v4l2_info(sd, "Unknown revision detected.\n");
 991
 992         /* Initializes TVP7002 to its default values */
 993         error = tvp7002_write_inittab(sd, tvp7002_init_default);
 994
 995         if (error < 0)
 996                 return error;
 997
 998         /* Set polarity information after registers have been set */
 999         polarity_a = 0x20 | device->pdata->hs_polarity << 5
1000                         | device->pdata->vs_polarity << 2;
1001         error = tvp7002_write(sd, TVP7002_SYNC_CTL_1, polarity_a);
1002         if (error < 0)
1003                 return error;
1004
1005         polarity_b = 0x01  | device->pdata->fid_polarity << 2
1006                         | device->pdata->sog_polarity << 1
1007                         | device->pdata->clk_polarity;
1008         error = tvp7002_write(sd, TVP7002_MISC_CTL_3, polarity_b);
1009         if (error < 0)
1010                 return error;
1011
1012         /* Set registers according to default video mode */
1013         timings = device->current_timings->timings;
1014         error = tvp7002_s_dv_timings(sd, 0, &timings);
1015
1016 #if defined(CONFIG_MEDIA_CONTROLLER)
1017         device->pad.flags = MEDIA_PAD_FL_SOURCE;
1018         device->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1019         device->sd.entity.function = MEDIA_ENT_F_ATV_DECODER;
1020
1021         error = media_entity_pads_init(&device->sd.entity, 1, &device->pad);
1022         if (error < 0)
1023                 return error;
1024 #endif
1025
1026         v4l2_ctrl_handler_init(&device->hdl, 1);
1027         v4l2_ctrl_new_std(&device->hdl, &tvp7002_ctrl_ops,
1028                         V4L2_CID_GAIN, 0, 255, 1, 0);
1029         sd->ctrl_handler = &device->hdl;
1030         if (device->hdl.error) {
1031                 error = device->hdl.error;
1032                 goto error;
1033         }
1034         v4l2_ctrl_handler_setup(&device->hdl);
1035
1036         error = v4l2_async_register_subdev(&device->sd);
1037         if (error)
1038                 goto error;
1039
1040         return 0;
1041
1042 error:
1043         v4l2_ctrl_handler_free(&device->hdl);
1044 #if defined(CONFIG_MEDIA_CONTROLLER)
1045         media_entity_cleanup(&device->sd.entity);
1046 #endif
1047         return error;
1048 }
1049
1050 /*
1051  * tvp7002_remove - Remove TVP7002 device support
1052  * @c: ptr to i2c_client struct
1053  *
1054  * Reset the TVP7002 device
1055  * Returns zero.
1056  */
1057 static void tvp7002_remove(struct i2c_client *c)
1058 {
1059         struct v4l2_subdev *sd = i2c_get_clientdata(c);
1060         struct tvp7002 *device = to_tvp7002(sd);
1061
1062         v4l2_dbg(1, debug, sd, "Removing tvp7002 adapter"
1063                                 "on address 0x%x\n", c->addr);
1064         v4l2_async_unregister_subdev(&device->sd);
1065 #if defined(CONFIG_MEDIA_CONTROLLER)
1066         media_entity_cleanup(&device->sd.entity);
1067 #endif
1068         v4l2_ctrl_handler_free(&device->hdl);
1069 }
1070
1071 /* I2C Device ID table */
1072 static const struct i2c_device_id tvp7002_id[] = {
1073         { "tvp7002" },
1074         { }
1075 };
1076 MODULE_DEVICE_TABLE(i2c, tvp7002_id);
1077
1078 #if IS_ENABLED(CONFIG_OF)
1079 static const struct of_device_id tvp7002_of_match[] = {
1080         { .compatible = "ti,tvp7002", },
1081         { /* sentinel */ },
1082 };
1083 MODULE_DEVICE_TABLE(of, tvp7002_of_match);
1084 #endif
1085
1086 /* I2C driver data */
1087 static struct i2c_driver tvp7002_driver = {
1088         .driver = {
1089                 .of_match_table = of_match_ptr(tvp7002_of_match),
1090                 .name = TVP7002_MODULE_NAME,
1091         },
1092         .probe = tvp7002_probe,
1093         .remove = tvp7002_remove,
1094         .id_table = tvp7002_id,
1095 };
1096
1097 module_i2c_driver(tvp7002_driver);