drivers/media/pci/intel/ipu6/ipu6-isys.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /* Copyright (C) 2013--2024 Intel Corporation */
   3
   4 #ifndef IPU6_ISYS_H
   5 #define IPU6_ISYS_H
   6
   7 #include <linux/irqreturn.h>
   8 #include <linux/list.h>
   9 #include <linux/mutex.h>
  10 #include <linux/pm_qos.h>
  11 #include <linux/spinlock_types.h>
  12 #include <linux/types.h>
  13
  14 #include <media/media-device.h>
  15 #include <media/v4l2-async.h>
  16 #include <media/v4l2-device.h>
  17
  18 #include "ipu6.h"
  19 #include "ipu6-fw-isys.h"
  20 #include "ipu6-isys-csi2.h"
  21 #include "ipu6-isys-video.h"
  22
  23 struct ipu6_bus_device;
  24
  25 #define IPU6_ISYS_ENTITY_PREFIX         "Intel IPU6"
  26 /* FW support max 16 streams */
  27 #define IPU6_ISYS_MAX_STREAMS           16
  28 #define ISYS_UNISPART_IRQS      (IPU6_ISYS_UNISPART_IRQ_SW |    \
  29                                  IPU6_ISYS_UNISPART_IRQ_CSI0 |  \
  30                                  IPU6_ISYS_UNISPART_IRQ_CSI1)
  31
  32 #define IPU6_ISYS_2600_MEM_LINE_ALIGN   64
  33
  34 /*
  35  * Current message queue configuration. These must be big enough
  36  * so that they never gets full. Queues are located in system memory
  37  */
  38 #define IPU6_ISYS_SIZE_RECV_QUEUE 40
  39 #define IPU6_ISYS_SIZE_SEND_QUEUE 40
  40 #define IPU6_ISYS_SIZE_PROXY_RECV_QUEUE 5
  41 #define IPU6_ISYS_SIZE_PROXY_SEND_QUEUE 5
  42 #define IPU6_ISYS_NUM_RECV_QUEUE 1
  43
  44 #define IPU6_ISYS_MIN_WIDTH             2U
  45 #define IPU6_ISYS_MIN_HEIGHT            2U
  46 #define IPU6_ISYS_MAX_WIDTH             4672U
  47 #define IPU6_ISYS_MAX_HEIGHT            3416U
  48
  49 /* the threshold granularity is 2KB on IPU6 */
  50 #define IPU6_SRAM_GRANULARITY_SHIFT     11
  51 #define IPU6_SRAM_GRANULARITY_SIZE      2048
  52 /* the threshold granularity is 1KB on IPU6SE */
  53 #define IPU6SE_SRAM_GRANULARITY_SHIFT   10
  54 #define IPU6SE_SRAM_GRANULARITY_SIZE    1024
  55 /* IS pixel buffer is 256KB, MaxSRAMSize is 200KB on IPU6 */
  56 #define IPU6_MAX_SRAM_SIZE                      (200 << 10)
  57 /* IS pixel buffer is 128KB, MaxSRAMSize is 96KB on IPU6SE */
  58 #define IPU6SE_MAX_SRAM_SIZE                    (96 << 10)
  59
  60 #define IPU6EP_LTR_VALUE                        200
  61 #define IPU6EP_MIN_MEMOPEN_TH                   0x4
  62 #define IPU6EP_MTL_LTR_VALUE                    1023
  63 #define IPU6EP_MTL_MIN_MEMOPEN_TH               0xc
  64
  65 struct ltr_did {
  66         union {
  67                 u32 value;
  68                 struct {
  69                         u8 val0;
  70                         u8 val1;
  71                         u8 val2;
  72                         u8 val3;
  73                 } bits;
  74         } lut_ltr;
  75         union {
  76                 u32 value;
  77                 struct {
  78                         u8 th0;
  79                         u8 th1;
  80                         u8 th2;
  81                         u8 th3;
  82                 } bits;
  83         } lut_fill_time;
  84 };
  85
  86 struct isys_iwake_watermark {
  87         bool iwake_enabled;
  88         bool force_iwake_disable;
  89         u32 iwake_threshold;
  90         u64 isys_pixelbuffer_datarate;
  91         struct ltr_did ltrdid;
  92         struct mutex mutex; /* protect whole struct */
  93         struct ipu6_isys *isys;
  94         struct list_head video_list;
  95 };
  96
  97 struct ipu6_isys_csi2_config {
  98         u32 nlanes;
  99         u32 port;
 100 };
 101
 102 struct sensor_async_sd {
 103         struct v4l2_async_connection asc;
 104         struct ipu6_isys_csi2_config csi2;
 105 };
 106
 107 /*
 108  * struct ipu6_isys
 109  *
 110  * @media_dev: Media device
 111  * @v4l2_dev: V4L2 device
 112  * @adev: ISYS bus device
 113  * @power: Is ISYS powered on or not?
 114  * @isr_bits: Which bits does the ISR handle?
 115  * @power_lock: Serialise access to power (power state in general)
 116  * @csi2_rx_ctrl_cached: cached shared value between all CSI2 receivers
 117  * @streams_lock: serialise access to streams
 118  * @streams: streams per firmware stream ID
 119  * @fwcom: fw communication layer private pointer
 120  *         or optional external library private pointer
 121  * @line_align: line alignment in memory
 122  * @phy_termcal_val: the termination calibration value, only used for DWC PHY
 123  * @need_reset: Isys requires d0i0->i3 transition
 124  * @ref_count: total number of callers fw open
 125  * @mutex: serialise access isys video open/release related operations
 126  * @stream_mutex: serialise stream start and stop, queueing requests
 127  * @pdata: platform data pointer
 128  * @csi2: CSI-2 receivers
 129  */
 130 struct ipu6_isys {
 131         struct media_device media_dev;
 132         struct v4l2_device v4l2_dev;
 133         struct ipu6_bus_device *adev;
 134
 135         int power;
 136         spinlock_t power_lock;
 137         u32 isr_csi2_bits;
 138         u32 csi2_rx_ctrl_cached;
 139         spinlock_t streams_lock;
 140         struct ipu6_isys_stream streams[IPU6_ISYS_MAX_STREAMS];
 141         int streams_ref_count[IPU6_ISYS_MAX_STREAMS];
 142         void *fwcom;
 143         unsigned int line_align;
 144         u32 phy_termcal_val;
 145         bool need_reset;
 146         bool icache_prefetch;
 147         bool csi2_cse_ipc_not_supported;
 148         unsigned int ref_count;
 149         unsigned int stream_opened;
 150         unsigned int sensor_type;
 151
 152         struct mutex mutex;
 153         struct mutex stream_mutex;
 154
 155         struct ipu6_isys_pdata *pdata;
 156
 157         int (*phy_set_power)(struct ipu6_isys *isys,
 158                              struct ipu6_isys_csi2_config *cfg,
 159                              const struct ipu6_isys_csi2_timing *timing,
 160                              bool on);
 161
 162         struct ipu6_isys_csi2 *csi2;
 163
 164         struct pm_qos_request pm_qos;
 165         spinlock_t listlock;    /* Protect framebuflist */
 166         struct list_head framebuflist;
 167         struct list_head framebuflist_fw;
 168         struct v4l2_async_notifier notifier;
 169         struct isys_iwake_watermark iwake_watermark;
 170 };
 171
 172 struct isys_fw_msgs {
 173         union {
 174                 u64 dummy;
 175                 struct ipu6_fw_isys_frame_buff_set_abi frame;
 176                 struct ipu6_fw_isys_stream_cfg_data_abi stream;
 177         } fw_msg;
 178         struct list_head head;
 179         dma_addr_t dma_addr;
 180 };
 181
 182 struct isys_fw_msgs *ipu6_get_fw_msg_buf(struct ipu6_isys_stream *stream);
 183 void ipu6_put_fw_msg_buf(struct ipu6_isys *isys, uintptr_t data);
 184 void ipu6_cleanup_fw_msg_bufs(struct ipu6_isys *isys);
 185
 186 extern const struct v4l2_ioctl_ops ipu6_isys_ioctl_ops;
 187
 188 void isys_setup_hw(struct ipu6_isys *isys);
 189 irqreturn_t isys_isr(struct ipu6_bus_device *adev);
 190 void update_watermark_setting(struct ipu6_isys *isys);
 191
 192 int ipu6_isys_mcd_phy_set_power(struct ipu6_isys *isys,
 193                                 struct ipu6_isys_csi2_config *cfg,
 194                                 const struct ipu6_isys_csi2_timing *timing,
 195                                 bool on);
 196
 197 int ipu6_isys_dwc_phy_set_power(struct ipu6_isys *isys,
 198                                 struct ipu6_isys_csi2_config *cfg,
 199                                 const struct ipu6_isys_csi2_timing *timing,
 200                                 bool on);
 201
 202 int ipu6_isys_jsl_phy_set_power(struct ipu6_isys *isys,
 203                                 struct ipu6_isys_csi2_config *cfg,
 204                                 const struct ipu6_isys_csi2_timing *timing,
 205                                 bool on);
 206 #endif /* IPU6_ISYS_H */