?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / media / pci / tw686x / tw686x-video.c
blob785dd797d921b515ead7b500edd01a4ac0618e6d
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar
4 *
5 * Based on original driver by Krzysztof Ha?asa:
6 * Copyright (C) 2015 Industrial Research Institute for Automation
7 * and Measurements PIAP
8 */
9
10 #include <linux/init.h>
11 #include <linux/delay.h>
12 #include <linux/list.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <media/v4l2-common.h>
17 #include <media/v4l2-event.h>
18 #include <media/videobuf2-dma-contig.h>
19 #include <media/videobuf2-dma-sg.h>
20 #include <media/videobuf2-vmalloc.h>
21 #include "tw686x.h"
22 #include "tw686x-regs.h"
23
24 #define TW686X_INPUTS_PER_CH 4
25 #define TW686X_VIDEO_WIDTH 720
26 #define TW686X_VIDEO_HEIGHT(id) ((id & V4L2_STD_525_60) ? 480 : 576)
27 #define TW686X_MAX_FPS(id) ((id & V4L2_STD_525_60) ? 30 : 25)
28
29 #define TW686X_MAX_SG_ENTRY_SIZE 4096
30 #define TW686X_MAX_SG_DESC_COUNT 256 /* PAL 720x576 needs 203 4-KB pages */
31 #define TW686X_SG_TABLE_SIZE (TW686X_MAX_SG_DESC_COUNT * sizeof(struct tw686x_sg_desc))
32
33 static const struct tw686x_format formats[] = {
34 {
35 .fourcc = V4L2_PIX_FMT_UYVY,
36 .mode = 0,
37 .depth = 16,
38 }, {
39 .fourcc = V4L2_PIX_FMT_RGB565,
40 .mode = 5,
41 .depth = 16,
42 }, {
43 .fourcc = V4L2_PIX_FMT_YUYV,
44 .mode = 6,
45 .depth = 16,
46 }
47 };
48
49 static void tw686x_buf_done(struct tw686x_video_channel *vc,
50 unsigned int pb)
51 {
52 struct tw686x_dma_desc *desc = &vc->dma_descs[pb];
53 struct tw686x_dev *dev = vc->dev;
54 struct vb2_v4l2_buffer *vb;
55 struct vb2_buffer *vb2_buf;
56
57 if (vc->curr_bufs[pb]) {
58 vb = &vc->curr_bufs[pb]->vb;
59
60 vb->field = dev->dma_ops->field;
61 vb->sequence = vc->sequence++;
62 vb2_buf = &vb->vb2_buf;
63
64 if (dev->dma_mode == TW686X_DMA_MODE_MEMCPY)
65 memcpy(vb2_plane_vaddr(vb2_buf, 0), desc->virt,
66 desc->size);
67 vb2_buf->timestamp = ktime_get_ns();
68 vb2_buffer_done(vb2_buf, VB2_BUF_STATE_DONE);
69 }
70
71 vc->pb = !pb;
72 }
73
74 /*
75 * We can call this even when alloc_dma failed for the given channel
76 */
77 static void tw686x_memcpy_dma_free(struct tw686x_video_channel *vc,
78 unsigned int pb)
79 {
80 struct tw686x_dma_desc *desc = &vc->dma_descs[pb];
81 struct tw686x_dev *dev = vc->dev;
82 struct pci_dev *pci_dev;
83 unsigned long flags;
84
85 /* Check device presence. Shouldn't really happen! */
86 spin_lock_irqsave(&dev->lock, flags);
87 pci_dev = dev->pci_dev;
88 spin_unlock_irqrestore(&dev->lock, flags);
89 if (!pci_dev) {
90 WARN(1, "trying to deallocate on missing device\n");
91 return;
92 }
93
94 if (desc->virt) {
95 dma_free_coherent(&dev->pci_dev->dev, desc->size, desc->virt,
96 desc->phys);
97 desc->virt = NULL;
98 }
99 }
100
101 static int tw686x_memcpy_dma_alloc(struct tw686x_video_channel *vc,
102 unsigned int pb)
103 {
104 struct tw686x_dev *dev = vc->dev;
105 u32 reg = pb ? VDMA_B_ADDR[vc->ch] : VDMA_P_ADDR[vc->ch];
106 unsigned int len;
107 void *virt;
108
109 WARN(vc->dma_descs[pb].virt,
110 "Allocating buffer but previous still here\n");
111
112 len = (vc->width * vc->height * vc->format->depth) >> 3;
113 virt = dma_alloc_coherent(&dev->pci_dev->dev, len,
114 &vc->dma_descs[pb].phys, GFP_KERNEL);
115 if (!virt) {
116 v4l2_err(&dev->v4l2_dev,
117 "dma%d: unable to allocate %s-buffer\n",
118 vc->ch, pb ? "B" : "P");
119 return -ENOMEM;
120 }
121 vc->dma_descs[pb].size = len;
122 vc->dma_descs[pb].virt = virt;
123 reg_write(dev, reg, vc->dma_descs[pb].phys);
124
125 return 0;
126 }
127
128 static void tw686x_memcpy_buf_refill(struct tw686x_video_channel *vc,
129 unsigned int pb)
130 {
131 struct tw686x_v4l2_buf *buf;
132
133 while (!list_empty(&vc->vidq_queued)) {
134
135 buf = list_first_entry(&vc->vidq_queued,
136 struct tw686x_v4l2_buf, list);
137 list_del(&buf->list);
138
139 vc->curr_bufs[pb] = buf;
140 return;
141 }
142 vc->curr_bufs[pb] = NULL;
143 }
144
145 static const struct tw686x_dma_ops memcpy_dma_ops = {
146 .alloc = tw686x_memcpy_dma_alloc,
147 .free = tw686x_memcpy_dma_free,
148 .buf_refill = tw686x_memcpy_buf_refill,
149 .mem_ops = &vb2_vmalloc_memops,
150 .hw_dma_mode = TW686X_FRAME_MODE,
151 .field = V4L2_FIELD_INTERLACED,
152 };
153
154 static void tw686x_contig_buf_refill(struct tw686x_video_channel *vc,
155 unsigned int pb)
156 {
157 struct tw686x_v4l2_buf *buf;
158
159 while (!list_empty(&vc->vidq_queued)) {
160 u32 reg = pb ? VDMA_B_ADDR[vc->ch] : VDMA_P_ADDR[vc->ch];
161 dma_addr_t phys;
162
163 buf = list_first_entry(&vc->vidq_queued,
164 struct tw686x_v4l2_buf, list);
165 list_del(&buf->list);
166
167 phys = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
168 reg_write(vc->dev, reg, phys);
169
170 buf->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
171 vc->curr_bufs[pb] = buf;
172 return;
173 }
174 vc->curr_bufs[pb] = NULL;
175 }
176
177 static const struct tw686x_dma_ops contig_dma_ops = {
178 .buf_refill = tw686x_contig_buf_refill,
179 .mem_ops = &vb2_dma_contig_memops,
180 .hw_dma_mode = TW686X_FRAME_MODE,
181 .field = V4L2_FIELD_INTERLACED,
182 };
183
184 static int tw686x_sg_desc_fill(struct tw686x_sg_desc *descs,
185 struct tw686x_v4l2_buf *buf,
186 unsigned int buf_len)
187 {
188 struct sg_table *vbuf = vb2_dma_sg_plane_desc(&buf->vb.vb2_buf, 0);
189 unsigned int len, entry_len;
190 struct scatterlist *sg;
191 int i, count;
192
193 /* Clear the scatter-gather table */
194 memset(descs, 0, TW686X_SG_TABLE_SIZE);
195
196 count = 0;
197 for_each_sg(vbuf->sgl, sg, vbuf->nents, i) {
198 dma_addr_t phys = sg_dma_address(sg);
199 len = sg_dma_len(sg);
200
201 while (len && buf_len) {
202
203 if (count == TW686X_MAX_SG_DESC_COUNT)
204 return -ENOMEM;
205
206 entry_len = min_t(unsigned int, len,
207 TW686X_MAX_SG_ENTRY_SIZE);
208 entry_len = min_t(unsigned int, entry_len, buf_len);
209 descs[count].phys = cpu_to_le32(phys);
210 descs[count++].flags_length =
211 cpu_to_le32(BIT(30) | entry_len);
212 phys += entry_len;
213 len -= entry_len;
214 buf_len -= entry_len;
215 }
216
217 if (!buf_len)
218 return 0;
219 }
220
221 return -ENOMEM;
222 }
223
224 static void tw686x_sg_buf_refill(struct tw686x_video_channel *vc,
225 unsigned int pb)
226 {
227 struct tw686x_dev *dev = vc->dev;
228 struct tw686x_v4l2_buf *buf;
229
230 while (!list_empty(&vc->vidq_queued)) {
231 unsigned int buf_len;
232
233 buf = list_first_entry(&vc->vidq_queued,
234 struct tw686x_v4l2_buf, list);
235 list_del(&buf->list);
236
237 buf_len = (vc->width * vc->height * vc->format->depth) >> 3;
238 if (tw686x_sg_desc_fill(vc->sg_descs[pb], buf, buf_len)) {
239 v4l2_err(&dev->v4l2_dev,
240 "dma%d: unable to fill %s-buffer\n",
241 vc->ch, pb ? "B" : "P");
242 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
243 continue;
244 }
245
246 buf->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
247 vc->curr_bufs[pb] = buf;
248 return;
249 }
250
251 vc->curr_bufs[pb] = NULL;
252 }
253
254 static void tw686x_sg_dma_free(struct tw686x_video_channel *vc,
255 unsigned int pb)
256 {
257 struct tw686x_dma_desc *desc = &vc->dma_descs[pb];
258 struct tw686x_dev *dev = vc->dev;
259
260 if (desc->size) {
261 dma_free_coherent(&dev->pci_dev->dev, desc->size, desc->virt,
262 desc->phys);
263 desc->virt = NULL;
264 }
265
266 vc->sg_descs[pb] = NULL;
267 }
268
269 static int tw686x_sg_dma_alloc(struct tw686x_video_channel *vc,
270 unsigned int pb)
271 {
272 struct tw686x_dma_desc *desc = &vc->dma_descs[pb];
273 struct tw686x_dev *dev = vc->dev;
274 u32 reg = pb ? DMA_PAGE_TABLE1_ADDR[vc->ch] :
275 DMA_PAGE_TABLE0_ADDR[vc->ch];
276 void *virt;
277
278 if (desc->size) {
279 virt = dma_alloc_coherent(&dev->pci_dev->dev, desc->size,
280 &desc->phys, GFP_KERNEL);
281 if (!virt) {
282 v4l2_err(&dev->v4l2_dev,
283 "dma%d: unable to allocate %s-buffer\n",
284 vc->ch, pb ? "B" : "P");
285 return -ENOMEM;
286 }
287 desc->virt = virt;
288 reg_write(dev, reg, desc->phys);
289 } else {
290 virt = dev->video_channels[0].dma_descs[pb].virt +
291 vc->ch * TW686X_SG_TABLE_SIZE;
292 }
293
294 vc->sg_descs[pb] = virt;
295 return 0;
296 }
297
298 static int tw686x_sg_setup(struct tw686x_dev *dev)
299 {
300 unsigned int sg_table_size, pb, ch, channels;
301
302 if (is_second_gen(dev)) {
303 /*
304 * TW6865/TW6869: each channel needs a pair of
305 * P-B descriptor tables.
306 */
307 channels = max_channels(dev);
308 sg_table_size = TW686X_SG_TABLE_SIZE;
309 } else {
310 /*
311 * TW6864/TW6868: we need to allocate a pair of
312 * P-B descriptor tables, common for all channels.
313 * Each table will be bigger than 4 KB.
314 */
315 channels = 1;
316 sg_table_size = max_channels(dev) * TW686X_SG_TABLE_SIZE;
317 }
318
319 for (ch = 0; ch < channels; ch++) {
320 struct tw686x_video_channel *vc = &dev->video_channels[ch];
321
322 for (pb = 0; pb < 2; pb++)
323 vc->dma_descs[pb].size = sg_table_size;
324 }
325
326 return 0;
327 }
328
329 static const struct tw686x_dma_ops sg_dma_ops = {
330 .setup = tw686x_sg_setup,
331 .alloc = tw686x_sg_dma_alloc,
332 .free = tw686x_sg_dma_free,
333 .buf_refill = tw686x_sg_buf_refill,
334 .mem_ops = &vb2_dma_sg_memops,
335 .hw_dma_mode = TW686X_SG_MODE,
336 .field = V4L2_FIELD_SEQ_TB,
337 };
338
339 static const unsigned int fps_map[15] = {
340 /*
341 * bit 31 enables selecting the field control register
342 * bits 0-29 are a bitmask with fields that will be output.
343 * For NTSC (and PAL-M, PAL-60), all 30 bits are used.
344 * For other PAL standards, only the first 25 bits are used.
345 */
346 0x00000000, /* output all fields */
347 0x80000006, /* 2 fps (60Hz), 2 fps (50Hz) */
348 0x80018006, /* 4 fps (60Hz), 4 fps (50Hz) */
349 0x80618006, /* 6 fps (60Hz), 6 fps (50Hz) */
350 0x81818186, /* 8 fps (60Hz), 8 fps (50Hz) */
351 0x86186186, /* 10 fps (60Hz), 8 fps (50Hz) */
352 0x86619866, /* 12 fps (60Hz), 10 fps (50Hz) */
353 0x86666666, /* 14 fps (60Hz), 12 fps (50Hz) */
354 0x9999999e, /* 16 fps (60Hz), 14 fps (50Hz) */
355 0x99e6799e, /* 18 fps (60Hz), 16 fps (50Hz) */
356 0x9e79e79e, /* 20 fps (60Hz), 16 fps (50Hz) */
357 0x9e7e7e7e, /* 22 fps (60Hz), 18 fps (50Hz) */
358 0x9fe7f9fe, /* 24 fps (60Hz), 20 fps (50Hz) */
359 0x9ffe7ffe, /* 26 fps (60Hz), 22 fps (50Hz) */
360 0x9ffffffe, /* 28 fps (60Hz), 24 fps (50Hz) */
361 };
362
363 static unsigned int tw686x_real_fps(unsigned int index, unsigned int max_fps)
364 {
365 unsigned long mask;
366
367 if (!index || index >= ARRAY_SIZE(fps_map))
368 return max_fps;
369
370 mask = GENMASK(max_fps - 1, 0);
371 return hweight_long(fps_map[index] & mask);
372 }
373
374 static unsigned int tw686x_fps_idx(unsigned int fps, unsigned int max_fps)
375 {
376 unsigned int idx, real_fps;
377 int delta;
378
379 /* First guess */
380 idx = (12 + 15 * fps) / max_fps;
381
382 /* Minimal possible framerate is 2 frames per second */
383 if (!idx)
384 return 1;
385
386 /* Check if the difference is bigger than abs(1) and adjust */
387 real_fps = tw686x_real_fps(idx, max_fps);
388 delta = real_fps - fps;
389 if (delta < -1)
390 idx++;
391 else if (delta > 1)
392 idx--;
393
394 /* Max framerate */
395 if (idx >= 15)
396 return 0;
397
398 return idx;
399 }
400
401 static void tw686x_set_framerate(struct tw686x_video_channel *vc,
402 unsigned int fps)
403 {
404 unsigned int i;
405
406 i = tw686x_fps_idx(fps, TW686X_MAX_FPS(vc->video_standard));
407 reg_write(vc->dev, VIDEO_FIELD_CTRL[vc->ch], fps_map[i]);
408 vc->fps = tw686x_real_fps(i, TW686X_MAX_FPS(vc->video_standard));
409 }
410
411 static const struct tw686x_format *format_by_fourcc(unsigned int fourcc)
412 {
413 unsigned int cnt;
414
415 for (cnt = 0; cnt < ARRAY_SIZE(formats); cnt++)
416 if (formats[cnt].fourcc == fourcc)
417 return &formats[cnt];
418 return NULL;
419 }
420
421 static int tw686x_queue_setup(struct vb2_queue *vq,
422 unsigned int *nbuffers, unsigned int *nplanes,
423 unsigned int sizes[], struct device *alloc_devs[])
424 {
425 struct tw686x_video_channel *vc = vb2_get_drv_priv(vq);
426 unsigned int q_num_bufs = vb2_get_num_buffers(vq);
427 unsigned int szimage =
428 (vc->width * vc->height * vc->format->depth) >> 3;
429
430 /*
431 * Let's request at least three buffers: two for the
432 * DMA engine and one for userspace.
433 */
434 if (q_num_bufs + *nbuffers < 3)
435 *nbuffers = 3 - q_num_bufs;
436
437 if (*nplanes) {
438 if (*nplanes != 1 || sizes[0] < szimage)
439 return -EINVAL;
440 return 0;
441 }
442
443 sizes[0] = szimage;
444 *nplanes = 1;
445 return 0;
446 }
447
448 static void tw686x_buf_queue(struct vb2_buffer *vb)
449 {
450 struct tw686x_video_channel *vc = vb2_get_drv_priv(vb->vb2_queue);
451 struct tw686x_dev *dev = vc->dev;
452 struct pci_dev *pci_dev;
453 unsigned long flags;
454 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
455 struct tw686x_v4l2_buf *buf =
456 container_of(vbuf, struct tw686x_v4l2_buf, vb);
457
458 /* Check device presence */
459 spin_lock_irqsave(&dev->lock, flags);
460 pci_dev = dev->pci_dev;
461 spin_unlock_irqrestore(&dev->lock, flags);
462 if (!pci_dev) {
463 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
464 return;
465 }
466
467 spin_lock_irqsave(&vc->qlock, flags);
468 list_add_tail(&buf->list, &vc->vidq_queued);
469 spin_unlock_irqrestore(&vc->qlock, flags);
470 }
471
472 static void tw686x_clear_queue(struct tw686x_video_channel *vc,
473 enum vb2_buffer_state state)
474 {
475 unsigned int pb;
476
477 while (!list_empty(&vc->vidq_queued)) {
478 struct tw686x_v4l2_buf *buf;
479
480 buf = list_first_entry(&vc->vidq_queued,
481 struct tw686x_v4l2_buf, list);
482 list_del(&buf->list);
483 vb2_buffer_done(&buf->vb.vb2_buf, state);
484 }
485
486 for (pb = 0; pb < 2; pb++) {
487 if (vc->curr_bufs[pb])
488 vb2_buffer_done(&vc->curr_bufs[pb]->vb.vb2_buf, state);
489 vc->curr_bufs[pb] = NULL;
490 }
491 }
492
493 static int tw686x_start_streaming(struct vb2_queue *vq, unsigned int count)
494 {
495 struct tw686x_video_channel *vc = vb2_get_drv_priv(vq);
496 struct tw686x_dev *dev = vc->dev;
497 struct pci_dev *pci_dev;
498 unsigned long flags;
499 int pb, err;
500
501 /* Check device presence */
502 spin_lock_irqsave(&dev->lock, flags);
503 pci_dev = dev->pci_dev;
504 spin_unlock_irqrestore(&dev->lock, flags);
505 if (!pci_dev) {
506 err = -ENODEV;
507 goto err_clear_queue;
508 }
509
510 spin_lock_irqsave(&vc->qlock, flags);
511
512 /* Sanity check */
513 if (dev->dma_mode == TW686X_DMA_MODE_MEMCPY &&
514 (!vc->dma_descs[0].virt || !vc->dma_descs[1].virt)) {
515 spin_unlock_irqrestore(&vc->qlock, flags);
516 v4l2_err(&dev->v4l2_dev,
517 "video%d: refusing to start without DMA buffers\n",
518 vc->num);
519 err = -ENOMEM;
520 goto err_clear_queue;
521 }
522
523 for (pb = 0; pb < 2; pb++)
524 dev->dma_ops->buf_refill(vc, pb);
525 spin_unlock_irqrestore(&vc->qlock, flags);
526
527 vc->sequence = 0;
528 vc->pb = 0;
529
530 spin_lock_irqsave(&dev->lock, flags);
531 tw686x_enable_channel(dev, vc->ch);
532 spin_unlock_irqrestore(&dev->lock, flags);
533
534 mod_timer(&dev->dma_delay_timer, jiffies + msecs_to_jiffies(100));
535
536 return 0;
537
538 err_clear_queue:
539 spin_lock_irqsave(&vc->qlock, flags);
540 tw686x_clear_queue(vc, VB2_BUF_STATE_QUEUED);
541 spin_unlock_irqrestore(&vc->qlock, flags);
542 return err;
543 }
544
545 static void tw686x_stop_streaming(struct vb2_queue *vq)
546 {
547 struct tw686x_video_channel *vc = vb2_get_drv_priv(vq);
548 struct tw686x_dev *dev = vc->dev;
549 struct pci_dev *pci_dev;
550 unsigned long flags;
551
552 /* Check device presence */
553 spin_lock_irqsave(&dev->lock, flags);
554 pci_dev = dev->pci_dev;
555 spin_unlock_irqrestore(&dev->lock, flags);
556 if (pci_dev)
557 tw686x_disable_channel(dev, vc->ch);
558
559 spin_lock_irqsave(&vc->qlock, flags);
560 tw686x_clear_queue(vc, VB2_BUF_STATE_ERROR);
561 spin_unlock_irqrestore(&vc->qlock, flags);
562 }
563
564 static int tw686x_buf_prepare(struct vb2_buffer *vb)
565 {
566 struct tw686x_video_channel *vc = vb2_get_drv_priv(vb->vb2_queue);
567 unsigned int size =
568 (vc->width * vc->height * vc->format->depth) >> 3;
569
570 if (vb2_plane_size(vb, 0) < size)
571 return -EINVAL;
572 vb2_set_plane_payload(vb, 0, size);
573 return 0;
574 }
575
576 static const struct vb2_ops tw686x_video_qops = {
577 .queue_setup = tw686x_queue_setup,
578 .buf_queue = tw686x_buf_queue,
579 .buf_prepare = tw686x_buf_prepare,
580 .start_streaming = tw686x_start_streaming,
581 .stop_streaming = tw686x_stop_streaming,
582 };
583
584 static int tw686x_s_ctrl(struct v4l2_ctrl *ctrl)
585 {
586 struct tw686x_video_channel *vc;
587 struct tw686x_dev *dev;
588 unsigned int ch;
589
590 vc = container_of(ctrl->handler, struct tw686x_video_channel,
591 ctrl_handler);
592 dev = vc->dev;
593 ch = vc->ch;
594
595 switch (ctrl->id) {
596 case V4L2_CID_BRIGHTNESS:
597 reg_write(dev, BRIGHT[ch], ctrl->val & 0xff);
598 return 0;
599
600 case V4L2_CID_CONTRAST:
601 reg_write(dev, CONTRAST[ch], ctrl->val);
602 return 0;
603
604 case V4L2_CID_SATURATION:
605 reg_write(dev, SAT_U[ch], ctrl->val);
606 reg_write(dev, SAT_V[ch], ctrl->val);
607 return 0;
608
609 case V4L2_CID_HUE:
610 reg_write(dev, HUE[ch], ctrl->val & 0xff);
611 return 0;
612 }
613
614 return -EINVAL;
615 }
616
617 static const struct v4l2_ctrl_ops ctrl_ops = {
618 .s_ctrl = tw686x_s_ctrl,
619 };
620
621 static int tw686x_g_fmt_vid_cap(struct file *file, void *priv,
622 struct v4l2_format *f)
623 {
624 struct tw686x_video_channel *vc = video_drvdata(file);
625 struct tw686x_dev *dev = vc->dev;
626
627 f->fmt.pix.width = vc->width;
628 f->fmt.pix.height = vc->height;
629 f->fmt.pix.field = dev->dma_ops->field;
630 f->fmt.pix.pixelformat = vc->format->fourcc;
631 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
632 f->fmt.pix.bytesperline = (f->fmt.pix.width * vc->format->depth) / 8;
633 f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
634 return 0;
635 }
636
637 static int tw686x_try_fmt_vid_cap(struct file *file, void *priv,
638 struct v4l2_format *f)
639 {
640 struct tw686x_video_channel *vc = video_drvdata(file);
641 struct tw686x_dev *dev = vc->dev;
642 unsigned int video_height = TW686X_VIDEO_HEIGHT(vc->video_standard);
643 const struct tw686x_format *format;
644
645 format = format_by_fourcc(f->fmt.pix.pixelformat);
646 if (!format) {
647 format = &formats[0];
648 f->fmt.pix.pixelformat = format->fourcc;
649 }
650
651 if (f->fmt.pix.width <= TW686X_VIDEO_WIDTH / 2)
652 f->fmt.pix.width = TW686X_VIDEO_WIDTH / 2;
653 else
654 f->fmt.pix.width = TW686X_VIDEO_WIDTH;
655
656 if (f->fmt.pix.height <= video_height / 2)
657 f->fmt.pix.height = video_height / 2;
658 else
659 f->fmt.pix.height = video_height;
660
661 f->fmt.pix.bytesperline = (f->fmt.pix.width * format->depth) / 8;
662 f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
663 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
664 f->fmt.pix.field = dev->dma_ops->field;
665
666 return 0;
667 }
668
669 static int tw686x_set_format(struct tw686x_video_channel *vc,
670 unsigned int pixelformat, unsigned int width,
671 unsigned int height, bool realloc)
672 {
673 struct tw686x_dev *dev = vc->dev;
674 u32 val, dma_width, dma_height, dma_line_width;
675 int err, pb;
676
677 vc->format = format_by_fourcc(pixelformat);
678 vc->width = width;
679 vc->height = height;
680
681 /* We need new DMA buffers if the framesize has changed */
682 if (dev->dma_ops->alloc && realloc) {
683 for (pb = 0; pb < 2; pb++)
684 dev->dma_ops->free(vc, pb);
685
686 for (pb = 0; pb < 2; pb++) {
687 err = dev->dma_ops->alloc(vc, pb);
688 if (err) {
689 if (pb > 0)
690 dev->dma_ops->free(vc, 0);
691 return err;
692 }
693 }
694 }
695
696 val = reg_read(vc->dev, VDMA_CHANNEL_CONFIG[vc->ch]);
697
698 if (vc->width <= TW686X_VIDEO_WIDTH / 2)
699 val |= BIT(23);
700 else
701 val &= ~BIT(23);
702
703 if (vc->height <= TW686X_VIDEO_HEIGHT(vc->video_standard) / 2)
704 val |= BIT(24);
705 else
706 val &= ~BIT(24);
707
708 val &= ~0x7ffff;
709
710 /* Program the DMA scatter-gather */
711 if (dev->dma_mode == TW686X_DMA_MODE_SG) {
712 u32 start_idx, end_idx;
713
714 start_idx = is_second_gen(dev) ?
715 0 : vc->ch * TW686X_MAX_SG_DESC_COUNT;
716 end_idx = start_idx + TW686X_MAX_SG_DESC_COUNT - 1;
717
718 val |= (end_idx << 10) | start_idx;
719 }
720
721 val &= ~(0x7 << 20);
722 val |= vc->format->mode << 20;
723 reg_write(vc->dev, VDMA_CHANNEL_CONFIG[vc->ch], val);
724
725 /* Program the DMA frame size */
726 dma_width = (vc->width * 2) & 0x7ff;
727 dma_height = vc->height / 2;
728 dma_line_width = (vc->width * 2) & 0x7ff;
729 val = (dma_height << 22) | (dma_line_width << 11) | dma_width;
730 reg_write(vc->dev, VDMA_WHP[vc->ch], val);
731 return 0;
732 }
733
734 static int tw686x_s_fmt_vid_cap(struct file *file, void *priv,
735 struct v4l2_format *f)
736 {
737 struct tw686x_video_channel *vc = video_drvdata(file);
738 unsigned long area;
739 bool realloc;
740 int err;
741
742 if (vb2_is_busy(&vc->vidq))
743 return -EBUSY;
744
745 area = vc->width * vc->height;
746 err = tw686x_try_fmt_vid_cap(file, priv, f);
747 if (err)
748 return err;
749
750 realloc = area != (f->fmt.pix.width * f->fmt.pix.height);
751 return tw686x_set_format(vc, f->fmt.pix.pixelformat,
752 f->fmt.pix.width, f->fmt.pix.height,
753 realloc);
754 }
755
756 static int tw686x_querycap(struct file *file, void *priv,
757 struct v4l2_capability *cap)
758 {
759 struct tw686x_video_channel *vc = video_drvdata(file);
760 struct tw686x_dev *dev = vc->dev;
761
762 strscpy(cap->driver, "tw686x", sizeof(cap->driver));
763 strscpy(cap->card, dev->name, sizeof(cap->card));
764 return 0;
765 }
766
767 static int tw686x_set_standard(struct tw686x_video_channel *vc, v4l2_std_id id)
768 {
769 u32 val;
770
771 if (id & V4L2_STD_NTSC)
772 val = 0;
773 else if (id & V4L2_STD_PAL)
774 val = 1;
775 else if (id & V4L2_STD_SECAM)
776 val = 2;
777 else if (id & V4L2_STD_NTSC_443)
778 val = 3;
779 else if (id & V4L2_STD_PAL_M)
780 val = 4;
781 else if (id & V4L2_STD_PAL_Nc)
782 val = 5;
783 else if (id & V4L2_STD_PAL_60)
784 val = 6;
785 else
786 return -EINVAL;
787
788 vc->video_standard = id;
789 reg_write(vc->dev, SDT[vc->ch], val);
790
791 val = reg_read(vc->dev, VIDEO_CONTROL1);
792 if (id & V4L2_STD_525_60)
793 val &= ~(1 << (SYS_MODE_DMA_SHIFT + vc->ch));
794 else
795 val |= (1 << (SYS_MODE_DMA_SHIFT + vc->ch));
796 reg_write(vc->dev, VIDEO_CONTROL1, val);
797
798 return 0;
799 }
800
801 static int tw686x_s_std(struct file *file, void *priv, v4l2_std_id id)
802 {
803 struct tw686x_video_channel *vc = video_drvdata(file);
804 struct v4l2_format f;
805 int ret;
806
807 if (vc->video_standard == id)
808 return 0;
809
810 if (vb2_is_busy(&vc->vidq))
811 return -EBUSY;
812
813 ret = tw686x_set_standard(vc, id);
814 if (ret)
815 return ret;
816 /*
817 * Adjust format after V4L2_STD_525_60/V4L2_STD_625_50 change,
818 * calling g_fmt and s_fmt will sanitize the height
819 * according to the standard.
820 */
821 tw686x_g_fmt_vid_cap(file, priv, &f);
822 tw686x_s_fmt_vid_cap(file, priv, &f);
823
824 /*
825 * Frame decimation depends on the chosen standard,
826 * so reset it to the current value.
827 */
828 tw686x_set_framerate(vc, vc->fps);
829 return 0;
830 }
831
832 static int tw686x_querystd(struct file *file, void *priv, v4l2_std_id *std)
833 {
834 struct tw686x_video_channel *vc = video_drvdata(file);
835 struct tw686x_dev *dev = vc->dev;
836 unsigned int old_std, detected_std = 0;
837 unsigned long end;
838
839 if (vb2_is_streaming(&vc->vidq))
840 return -EBUSY;
841
842 /* Enable and start standard detection */
843 old_std = reg_read(dev, SDT[vc->ch]);
844 reg_write(dev, SDT[vc->ch], 0x7);
845 reg_write(dev, SDT_EN[vc->ch], 0xff);
846
847 end = jiffies + msecs_to_jiffies(500);
848 while (time_is_after_jiffies(end)) {
849
850 detected_std = reg_read(dev, SDT[vc->ch]);
851 if (!(detected_std & BIT(7)))
852 break;
853 msleep(100);
854 }
855 reg_write(dev, SDT[vc->ch], old_std);
856
857 /* Exit if still busy */
858 if (detected_std & BIT(7))
859 return 0;
860
861 detected_std = (detected_std >> 4) & 0x7;
862 switch (detected_std) {
863 case TW686X_STD_NTSC_M:
864 *std &= V4L2_STD_NTSC;
865 break;
866 case TW686X_STD_NTSC_443:
867 *std &= V4L2_STD_NTSC_443;
868 break;
869 case TW686X_STD_PAL_M:
870 *std &= V4L2_STD_PAL_M;
871 break;
872 case TW686X_STD_PAL_60:
873 *std &= V4L2_STD_PAL_60;
874 break;
875 case TW686X_STD_PAL:
876 *std &= V4L2_STD_PAL;
877 break;
878 case TW686X_STD_PAL_CN:
879 *std &= V4L2_STD_PAL_Nc;
880 break;
881 case TW686X_STD_SECAM:
882 *std &= V4L2_STD_SECAM;
883 break;
884 default:
885 *std = 0;
886 }
887 return 0;
888 }
889
890 static int tw686x_g_std(struct file *file, void *priv, v4l2_std_id *id)
891 {
892 struct tw686x_video_channel *vc = video_drvdata(file);
893
894 *id = vc->video_standard;
895 return 0;
896 }
897
898 static int tw686x_enum_framesizes(struct file *file, void *priv,
899 struct v4l2_frmsizeenum *fsize)
900 {
901 struct tw686x_video_channel *vc = video_drvdata(file);
902
903 if (fsize->index)
904 return -EINVAL;
905 fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
906 fsize->stepwise.max_width = TW686X_VIDEO_WIDTH;
907 fsize->stepwise.min_width = fsize->stepwise.max_width / 2;
908 fsize->stepwise.step_width = fsize->stepwise.min_width;
909 fsize->stepwise.max_height = TW686X_VIDEO_HEIGHT(vc->video_standard);
910 fsize->stepwise.min_height = fsize->stepwise.max_height / 2;
911 fsize->stepwise.step_height = fsize->stepwise.min_height;
912 return 0;
913 }
914
915 static int tw686x_enum_frameintervals(struct file *file, void *priv,
916 struct v4l2_frmivalenum *ival)
917 {
918 struct tw686x_video_channel *vc = video_drvdata(file);
919 int max_fps = TW686X_MAX_FPS(vc->video_standard);
920 int max_rates = DIV_ROUND_UP(max_fps, 2);
921
922 if (ival->index >= max_rates)
923 return -EINVAL;
924
925 ival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
926 ival->discrete.numerator = 1;
927 if (ival->index < (max_rates - 1))
928 ival->discrete.denominator = (ival->index + 1) * 2;
929 else
930 ival->discrete.denominator = max_fps;
931 return 0;
932 }
933
934 static int tw686x_g_parm(struct file *file, void *priv,
935 struct v4l2_streamparm *sp)
936 {
937 struct tw686x_video_channel *vc = video_drvdata(file);
938 struct v4l2_captureparm *cp = &sp->parm.capture;
939
940 if (sp->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
941 return -EINVAL;
942 sp->parm.capture.readbuffers = 3;
943
944 cp->capability = V4L2_CAP_TIMEPERFRAME;
945 cp->timeperframe.numerator = 1;
946 cp->timeperframe.denominator = vc->fps;
947 return 0;
948 }
949
950 static int tw686x_s_parm(struct file *file, void *priv,
951 struct v4l2_streamparm *sp)
952 {
953 struct tw686x_video_channel *vc = video_drvdata(file);
954 struct v4l2_captureparm *cp = &sp->parm.capture;
955 unsigned int denominator = cp->timeperframe.denominator;
956 unsigned int numerator = cp->timeperframe.numerator;
957 unsigned int fps;
958
959 if (vb2_is_busy(&vc->vidq))
960 return -EBUSY;
961
962 fps = (!numerator || !denominator) ? 0 : denominator / numerator;
963 if (vc->fps != fps)
964 tw686x_set_framerate(vc, fps);
965 return tw686x_g_parm(file, priv, sp);
966 }
967
968 static int tw686x_enum_fmt_vid_cap(struct file *file, void *priv,
969 struct v4l2_fmtdesc *f)
970 {
971 if (f->index >= ARRAY_SIZE(formats))
972 return -EINVAL;
973 f->pixelformat = formats[f->index].fourcc;
974 return 0;
975 }
976
977 static void tw686x_set_input(struct tw686x_video_channel *vc, unsigned int i)
978 {
979 u32 val;
980
981 vc->input = i;
982
983 val = reg_read(vc->dev, VDMA_CHANNEL_CONFIG[vc->ch]);
984 val &= ~(0x3 << 30);
985 val |= i << 30;
986 reg_write(vc->dev, VDMA_CHANNEL_CONFIG[vc->ch], val);
987 }
988
989 static int tw686x_s_input(struct file *file, void *priv, unsigned int i)
990 {
991 struct tw686x_video_channel *vc = video_drvdata(file);
992
993 if (i >= TW686X_INPUTS_PER_CH)
994 return -EINVAL;
995 if (i == vc->input)
996 return 0;
997 /*
998 * Not sure we are able to support on the fly input change
999 */
1000 if (vb2_is_busy(&vc->vidq))
1001 return -EBUSY;
1002
1003 tw686x_set_input(vc, i);
1004 return 0;
1005 }
1006
1007 static int tw686x_g_input(struct file *file, void *priv, unsigned int *i)
1008 {
1009 struct tw686x_video_channel *vc = video_drvdata(file);
1010
1011 *i = vc->input;
1012 return 0;
1013 }
1014
1015 static int tw686x_enum_input(struct file *file, void *priv,
1016 struct v4l2_input *i)
1017 {
1018 struct tw686x_video_channel *vc = video_drvdata(file);
1019 unsigned int vidstat;
1020
1021 if (i->index >= TW686X_INPUTS_PER_CH)
1022 return -EINVAL;
1023
1024 snprintf(i->name, sizeof(i->name), "Composite%d", i->index);
1025 i->type = V4L2_INPUT_TYPE_CAMERA;
1026 i->std = vc->device->tvnorms;
1027 i->capabilities = V4L2_IN_CAP_STD;
1028
1029 vidstat = reg_read(vc->dev, VIDSTAT[vc->ch]);
1030 i->status = 0;
1031 if (vidstat & TW686X_VIDSTAT_VDLOSS)
1032 i->status |= V4L2_IN_ST_NO_SIGNAL;
1033 if (!(vidstat & TW686X_VIDSTAT_HLOCK))
1034 i->status |= V4L2_IN_ST_NO_H_LOCK;
1035
1036 return 0;
1037 }
1038
1039 static const struct v4l2_file_operations tw686x_video_fops = {
1040 .owner = THIS_MODULE,
1041 .open = v4l2_fh_open,
1042 .unlocked_ioctl = video_ioctl2,
1043 .release = vb2_fop_release,
1044 .poll = vb2_fop_poll,
1045 .read = vb2_fop_read,
1046 .mmap = vb2_fop_mmap,
1047 };
1048
1049 static const struct v4l2_ioctl_ops tw686x_video_ioctl_ops = {
1050 .vidioc_querycap = tw686x_querycap,
1051 .vidioc_g_fmt_vid_cap = tw686x_g_fmt_vid_cap,
1052 .vidioc_s_fmt_vid_cap = tw686x_s_fmt_vid_cap,
1053 .vidioc_enum_fmt_vid_cap = tw686x_enum_fmt_vid_cap,
1054 .vidioc_try_fmt_vid_cap = tw686x_try_fmt_vid_cap,
1055
1056 .vidioc_querystd = tw686x_querystd,
1057 .vidioc_g_std = tw686x_g_std,
1058 .vidioc_s_std = tw686x_s_std,
1059
1060 .vidioc_g_parm = tw686x_g_parm,
1061 .vidioc_s_parm = tw686x_s_parm,
1062 .vidioc_enum_framesizes = tw686x_enum_framesizes,
1063 .vidioc_enum_frameintervals = tw686x_enum_frameintervals,
1064
1065 .vidioc_enum_input = tw686x_enum_input,
1066 .vidioc_g_input = tw686x_g_input,
1067 .vidioc_s_input = tw686x_s_input,
1068
1069 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1070 .vidioc_querybuf = vb2_ioctl_querybuf,
1071 .vidioc_qbuf = vb2_ioctl_qbuf,
1072 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1073 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1074 .vidioc_streamon = vb2_ioctl_streamon,
1075 .vidioc_streamoff = vb2_ioctl_streamoff,
1076 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1077
1078 .vidioc_log_status = v4l2_ctrl_log_status,
1079 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1080 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1081 };
1082
1083 void tw686x_video_irq(struct tw686x_dev *dev, unsigned long requests,
1084 unsigned int pb_status, unsigned int fifo_status,
1085 unsigned int *reset_ch)
1086 {
1087 struct tw686x_video_channel *vc;
1088 unsigned long flags;
1089 unsigned int ch, pb;
1090
1091 for_each_set_bit(ch, &requests, max_channels(dev)) {
1092 vc = &dev->video_channels[ch];
1093
1094 /*
1095 * This can either be a blue frame (with signal-lost bit set)
1096 * or a good frame (with signal-lost bit clear). If we have just
1097 * got signal, then this channel needs resetting.
1098 */
1099 if (vc->no_signal && !(fifo_status & BIT(ch))) {
1100 v4l2_printk(KERN_DEBUG, &dev->v4l2_dev,
1101 "video%d: signal recovered\n", vc->num);
1102 vc->no_signal = false;
1103 *reset_ch |= BIT(ch);
1104 vc->pb = 0;
1105 continue;
1106 }
1107 vc->no_signal = !!(fifo_status & BIT(ch));
1108
1109 /* Check FIFO errors only if there's signal */
1110 if (!vc->no_signal) {
1111 u32 fifo_ov, fifo_bad;
1112
1113 fifo_ov = (fifo_status >> 24) & BIT(ch);
1114 fifo_bad = (fifo_status >> 16) & BIT(ch);
1115 if (fifo_ov || fifo_bad) {
1116 /* Mark this channel for reset */
1117 v4l2_printk(KERN_DEBUG, &dev->v4l2_dev,
1118 "video%d: FIFO error\n", vc->num);
1119 *reset_ch |= BIT(ch);
1120 vc->pb = 0;
1121 continue;
1122 }
1123 }
1124
1125 pb = !!(pb_status & BIT(ch));
1126 if (vc->pb != pb) {
1127 /* Mark this channel for reset */
1128 v4l2_printk(KERN_DEBUG, &dev->v4l2_dev,
1129 "video%d: unexpected p-b buffer!\n",
1130 vc->num);
1131 *reset_ch |= BIT(ch);
1132 vc->pb = 0;
1133 continue;
1134 }
1135
1136 spin_lock_irqsave(&vc->qlock, flags);
1137 tw686x_buf_done(vc, pb);
1138 dev->dma_ops->buf_refill(vc, pb);
1139 spin_unlock_irqrestore(&vc->qlock, flags);
1140 }
1141 }
1142
1143 void tw686x_video_free(struct tw686x_dev *dev)
1144 {
1145 unsigned int ch, pb;
1146
1147 for (ch = 0; ch < max_channels(dev); ch++) {
1148 struct tw686x_video_channel *vc = &dev->video_channels[ch];
1149
1150 video_unregister_device(vc->device);
1151
1152 if (dev->dma_ops->free)
1153 for (pb = 0; pb < 2; pb++)
1154 dev->dma_ops->free(vc, pb);
1155 }
1156 }
1157
1158 int tw686x_video_init(struct tw686x_dev *dev)
1159 {
1160 unsigned int ch, val;
1161 int err;
1162
1163 if (dev->dma_mode == TW686X_DMA_MODE_MEMCPY)
1164 dev->dma_ops = &memcpy_dma_ops;
1165 else if (dev->dma_mode == TW686X_DMA_MODE_CONTIG)
1166 dev->dma_ops = &contig_dma_ops;
1167 else if (dev->dma_mode == TW686X_DMA_MODE_SG)
1168 dev->dma_ops = &sg_dma_ops;
1169 else
1170 return -EINVAL;
1171
1172 err = v4l2_device_register(&dev->pci_dev->dev, &dev->v4l2_dev);
1173 if (err)
1174 return err;
1175
1176 if (dev->dma_ops->setup) {
1177 err = dev->dma_ops->setup(dev);
1178 if (err)
1179 return err;
1180 }
1181
1182 /* Initialize vc->dev and vc->ch for the error path */
1183 for (ch = 0; ch < max_channels(dev); ch++) {
1184 struct tw686x_video_channel *vc = &dev->video_channels[ch];
1185
1186 vc->dev = dev;
1187 vc->ch = ch;
1188 }
1189
1190 for (ch = 0; ch < max_channels(dev); ch++) {
1191 struct tw686x_video_channel *vc = &dev->video_channels[ch];
1192 struct video_device *vdev;
1193
1194 mutex_init(&vc->vb_mutex);
1195 spin_lock_init(&vc->qlock);
1196 INIT_LIST_HEAD(&vc->vidq_queued);
1197
1198 /* default settings */
1199 err = tw686x_set_standard(vc, V4L2_STD_NTSC);
1200 if (err)
1201 goto error;
1202
1203 err = tw686x_set_format(vc, formats[0].fourcc,
1204 TW686X_VIDEO_WIDTH,
1205 TW686X_VIDEO_HEIGHT(vc->video_standard),
1206 true);
1207 if (err)
1208 goto error;
1209
1210 tw686x_set_input(vc, 0);
1211 tw686x_set_framerate(vc, 30);
1212 reg_write(dev, VDELAY_LO[ch], 0x14);
1213 reg_write(dev, HACTIVE_LO[ch], 0xd0);
1214 reg_write(dev, VIDEO_SIZE[ch], 0);
1215
1216 vc->vidq.io_modes = VB2_READ | VB2_MMAP | VB2_DMABUF;
1217 vc->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1218 vc->vidq.drv_priv = vc;
1219 vc->vidq.buf_struct_size = sizeof(struct tw686x_v4l2_buf);
1220 vc->vidq.ops = &tw686x_video_qops;
1221 vc->vidq.mem_ops = dev->dma_ops->mem_ops;
1222 vc->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1223 vc->vidq.min_queued_buffers = 2;
1224 vc->vidq.lock = &vc->vb_mutex;
1225 vc->vidq.gfp_flags = dev->dma_mode != TW686X_DMA_MODE_MEMCPY ?
1226 GFP_DMA32 : 0;
1227 vc->vidq.dev = &dev->pci_dev->dev;
1228
1229 err = vb2_queue_init(&vc->vidq);
1230 if (err) {
1231 v4l2_err(&dev->v4l2_dev,
1232 "dma%d: cannot init vb2 queue\n", ch);
1233 goto error;
1234 }
1235
1236 err = v4l2_ctrl_handler_init(&vc->ctrl_handler, 4);
1237 if (err) {
1238 v4l2_err(&dev->v4l2_dev,
1239 "dma%d: cannot init ctrl handler\n", ch);
1240 goto error;
1241 }
1242 v4l2_ctrl_new_std(&vc->ctrl_handler, &ctrl_ops,
1243 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
1244 v4l2_ctrl_new_std(&vc->ctrl_handler, &ctrl_ops,
1245 V4L2_CID_CONTRAST, 0, 255, 1, 100);
1246 v4l2_ctrl_new_std(&vc->ctrl_handler, &ctrl_ops,
1247 V4L2_CID_SATURATION, 0, 255, 1, 128);
1248 v4l2_ctrl_new_std(&vc->ctrl_handler, &ctrl_ops,
1249 V4L2_CID_HUE, -128, 127, 1, 0);
1250 err = vc->ctrl_handler.error;
1251 if (err)
1252 goto error;
1253
1254 err = v4l2_ctrl_handler_setup(&vc->ctrl_handler);
1255 if (err)
1256 goto error;
1257
1258 vdev = video_device_alloc();
1259 if (!vdev) {
1260 v4l2_err(&dev->v4l2_dev,
1261 "dma%d: unable to allocate device\n", ch);
1262 err = -ENOMEM;
1263 goto error;
1264 }
1265
1266 snprintf(vdev->name, sizeof(vdev->name), "%s video", dev->name);
1267 vdev->fops = &tw686x_video_fops;
1268 vdev->ioctl_ops = &tw686x_video_ioctl_ops;
1269 vdev->release = video_device_release;
1270 vdev->v4l2_dev = &dev->v4l2_dev;
1271 vdev->queue = &vc->vidq;
1272 vdev->tvnorms = V4L2_STD_525_60 | V4L2_STD_625_50;
1273 vdev->minor = -1;
1274 vdev->lock = &vc->vb_mutex;
1275 vdev->ctrl_handler = &vc->ctrl_handler;
1276 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE |
1277 V4L2_CAP_STREAMING | V4L2_CAP_READWRITE;
1278 vc->device = vdev;
1279 video_set_drvdata(vdev, vc);
1280
1281 err = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
1282 if (err < 0) {
1283 video_device_release(vdev);
1284 goto error;
1285 }
1286 vc->num = vdev->num;
1287 }
1288
1289 val = TW686X_DEF_PHASE_REF;
1290 for (ch = 0; ch < max_channels(dev); ch++)
1291 val |= dev->dma_ops->hw_dma_mode << (16 + ch * 2);
1292 reg_write(dev, PHASE_REF, val);
1293
1294 reg_write(dev, MISC2[0], 0xe7);
1295 reg_write(dev, VCTRL1[0], 0xcc);
1296 reg_write(dev, LOOP[0], 0xa5);
1297 if (max_channels(dev) > 4) {
1298 reg_write(dev, VCTRL1[1], 0xcc);
1299 reg_write(dev, LOOP[1], 0xa5);
1300 reg_write(dev, MISC2[1], 0xe7);
1301 }
1302 return 0;
1303
1304 error:
1305 tw686x_video_free(dev);
1306 return err;
1307 }
Kernel DRM miscellaneous fixes and cross-tree changes