drivers/media/platform/nuvoton/npcm-regs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Register definition header for NPCM video driver
   4  *
   5  * Copyright (C) 2022 Nuvoton Technologies
   6  */
   7
   8 #ifndef _NPCM_REGS_H
   9 #define _NPCM_REGS_H
  10
  11 /* VCD Registers */
  12 #define VCD_DIFF_TBL                    0x0000
  13 #define VCD_FBA_ADR                     0x8000
  14 #define VCD_FBB_ADR                     0x8004
  15
  16 #define VCD_FB_LP                       0x8008
  17 #define  VCD_FBA_LP                     GENMASK(15, 0)
  18 #define  VCD_FBB_LP                     GENMASK(31, 16)
  19
  20 #define VCD_CAP_RES                     0x800c
  21 #define  VCD_CAP_RES_VERT_RES           GENMASK(10, 0)
  22 #define  VCD_CAP_RES_HOR_RES            GENMASK(26, 16)
  23
  24 #define VCD_MODE                        0x8014
  25 #define  VCD_MODE_VCDE                  BIT(0)
  26 #define  VCD_MODE_CM565                 BIT(1)
  27 #define  VCD_MODE_IDBC                  BIT(3)
  28 #define  VCD_MODE_KVM_BW_SET            BIT(16)
  29
  30 #define VCD_CMD                         0x8018
  31 #define  VCD_CMD_GO                     BIT(0)
  32 #define  VCD_CMD_RST                    BIT(1)
  33 #define  VCD_CMD_OPERATION              GENMASK(6, 4)
  34 #define   VCD_CMD_OPERATION_CAPTURE     0
  35 #define   VCD_CMD_OPERATION_COMPARE     2
  36
  37 #define VCD_STAT                        0x801c
  38 #define  VCD_STAT_DONE                  BIT(0)
  39 #define  VCD_STAT_IFOT                  BIT(2)
  40 #define  VCD_STAT_IFOR                  BIT(3)
  41 #define  VCD_STAT_VHT_CHG               BIT(5)
  42 #define  VCD_STAT_HAC_CHG               BIT(8)
  43 #define  VCD_STAT_BUSY                  BIT(30)
  44 #define VCD_STAT_CLEAR                  0x3fff
  45
  46 #define VCD_INTE                        0x8020
  47 #define  VCD_INTE_DONE_IE               BIT(0)
  48 #define  VCD_INTE_IFOT_IE               BIT(2)
  49 #define  VCD_INTE_IFOR_IE               BIT(3)
  50 #define  VCD_INTE_VHT_IE                BIT(5)
  51 #define  VCD_INTE_HAC_IE                BIT(8)
  52
  53 #define VCD_RCHG                        0x8028
  54 #define  VCD_RCHG_IG_CHG0               GENMASK(2, 0)
  55 #define  VCD_RCHG_TIM_PRSCL             GENMASK(12, 9)
  56
  57 #define VCD_VER_HI_TIM                  0x8044
  58 #define  VCD_VER_HI_TIME                GENMASK(23, 0)
  59
  60 #define VCD_VER_HI_LST                  0x8048
  61 #define  VCD_VER_HI_LAST                GENMASK(23, 0)
  62
  63 #define VCD_HOR_AC_TIM                  0x804c
  64 #define  VCD_HOR_AC_TIME                GENMASK(13, 0)
  65
  66 #define VCD_HOR_AC_LST                  0x8050
  67 #define  VCD_HOR_AC_LAST                GENMASK(13, 0)
  68
  69 #define VCD_FIFO                        0x805c
  70 #define  VCD_FIFO_TH                    0x100350ff
  71
  72 #define VCD_FB_SIZE                     0x500000 /* support up to 1920 x 1200 */
  73 #define VCD_KVM_BW_PCLK                 120000000UL
  74 #define VCD_TIMEOUT_US                  300000
  75
  76 /* ECE Registers */
  77 #define ECE_DDA_CTRL                    0x0000
  78 #define  ECE_DDA_CTRL_ECEEN             BIT(0)
  79 #define  ECE_DDA_CTRL_INTEN             BIT(8)
  80
  81 #define ECE_DDA_STS                     0x0004
  82 #define  ECE_DDA_STS_CDREADY            BIT(8)
  83 #define  ECE_DDA_STS_ACDRDY             BIT(10)
  84
  85 #define ECE_FBR_BA                      0x0008
  86 #define ECE_ED_BA                       0x000c
  87 #define ECE_RECT_XY                     0x0010
  88
  89 #define ECE_RECT_DIMEN                  0x0014
  90 #define  ECE_RECT_DIMEN_WR              GENMASK(10, 0)
  91 #define  ECE_RECT_DIMEN_WLTR            GENMASK(14, 11)
  92 #define  ECE_RECT_DIMEN_HR              GENMASK(26, 16)
  93 #define  ECE_RECT_DIMEN_HLTR            GENMASK(30, 27)
  94
  95 #define ECE_RESOL                       0x001c
  96 #define  ECE_RESOL_FB_LP_512            0
  97 #define  ECE_RESOL_FB_LP_1024           1
  98 #define  ECE_RESOL_FB_LP_2048           2
  99 #define  ECE_RESOL_FB_LP_2560           3
 100 #define  ECE_RESOL_FB_LP_4096           4
 101
 102 #define ECE_HEX_CTRL                    0x0040
 103 #define  ECE_HEX_CTRL_ENCDIS            BIT(0)
 104 #define  ECE_HEX_CTRL_ENC_GAP           GENMASK(12, 8)
 105
 106 #define ECE_HEX_RECT_OFFSET             0x0048
 107 #define  ECE_HEX_RECT_OFFSET_MASK       GENMASK(22, 0)
 108
 109 #define ECE_TILE_W                      16
 110 #define ECE_TILE_H                      16
 111 #define ECE_POLL_TIMEOUT_US             300000
 112
 113 /* GCR Registers */
 114 #define INTCR                           0x3c
 115 #define  INTCR_GFXIFDIS                 GENMASK(9, 8)
 116 #define  INTCR_DEHS                     BIT(27)
 117
 118 #define INTCR2                          0x60
 119 #define  INTCR2_GIRST2                  BIT(2)
 120 #define  INTCR2_GIHCRST                 BIT(5)
 121 #define  INTCR2_GIVCRST                 BIT(6)
 122
 123 /* GFXI Register */
 124 #define DISPST                          0x00
 125 #define  DISPST_HSCROFF                 BIT(1)
 126 #define  DISPST_MGAMODE                 BIT(7)
 127
 128 #define HVCNTL                          0x10
 129 #define  HVCNTL_MASK                    GENMASK(7, 0)
 130
 131 #define HVCNTH                          0x14
 132 #define  HVCNTH_MASK                    GENMASK(2, 0)
 133
 134 #define VVCNTL                          0x20
 135 #define  VVCNTL_MASK                    GENMASK(7, 0)
 136
 137 #define VVCNTH                          0x24
 138 #define  VVCNTH_MASK                    GENMASK(2, 0)
 139
 140 #define GPLLINDIV                       0x40
 141 #define  GPLLINDIV_MASK                 GENMASK(5, 0)
 142 #define  GPLLINDIV_GPLLFBDV8            BIT(7)
 143
 144 #define GPLLFBDIV                       0x44
 145 #define  GPLLFBDIV_MASK                 GENMASK(7, 0)
 146
 147 #define GPLLST                          0x48
 148 #define  GPLLST_PLLOTDIV1               GENMASK(2, 0)
 149 #define  GPLLST_PLLOTDIV2               GENMASK(5, 3)
 150 #define  GPLLST_GPLLFBDV109             GENMASK(7, 6)
 151
 152 #endif /* _NPCM_REGS_H */