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Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / media / platform / nuvoton / npcm-video.c
blob4f5d75645b2bb94669d976f9bfe7a9870f92c481
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for Video Capture/Differentiation Engine (VCD) and Encoding
4 * Compression Engine (ECE) present on Nuvoton NPCM SoCs.
5 *
6 * Copyright (C) 2022 Nuvoton Technologies
7 */
8
9 #include <linux/atomic.h>
10 #include <linux/bitfield.h>
11 #include <linux/bitmap.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/interrupt.h>
17 #include <linux/jiffies.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/module.h>
20 #include <linux/mutex.h>
21 #include <linux/of.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_platform.h>
24 #include <linux/of_reserved_mem.h>
25 #include <linux/platform_device.h>
26 #include <linux/regmap.h>
27 #include <linux/reset.h>
28 #include <linux/sched.h>
29 #include <linux/string.h>
30 #include <linux/v4l2-controls.h>
31 #include <linux/videodev2.h>
32 #include <media/v4l2-ctrls.h>
33 #include <media/v4l2-dev.h>
34 #include <media/v4l2-device.h>
35 #include <media/v4l2-dv-timings.h>
36 #include <media/v4l2-event.h>
37 #include <media/v4l2-ioctl.h>
38 #include <media/videobuf2-dma-contig.h>
39 #include <uapi/linux/npcm-video.h>
40 #include "npcm-regs.h"
41
42 #define DEVICE_NAME "npcm-video"
43 #define MAX_WIDTH 1920
44 #define MAX_HEIGHT 1200
45 #define MIN_WIDTH 320
46 #define MIN_HEIGHT 240
47 #define MIN_LP 512
48 #define MAX_LP 4096
49 #define RECT_W 16
50 #define RECT_H 16
51 #define BITMAP_SIZE 32
52
53 struct npcm_video_addr {
54 size_t size;
55 dma_addr_t dma;
56 void *virt;
57 };
58
59 struct npcm_video_buffer {
60 struct vb2_v4l2_buffer vb;
61 struct list_head link;
62 };
63
64 #define to_npcm_video_buffer(x) \
65 container_of((x), struct npcm_video_buffer, vb)
66
67 /*
68 * VIDEO_STREAMING: a flag indicating if the video has started streaming
69 * VIDEO_CAPTURING: a flag indicating if the VCD is capturing a frame
70 * VIDEO_RES_CHANGING: a flag indicating if the resolution is changing
71 * VIDEO_STOPPED: a flag indicating if the video has stopped streaming
72 */
73 enum {
74 VIDEO_STREAMING,
75 VIDEO_CAPTURING,
76 VIDEO_RES_CHANGING,
77 VIDEO_STOPPED,
78 };
79
80 struct rect_list {
81 struct v4l2_clip clip;
82 struct list_head list;
83 };
84
85 struct rect_list_info {
86 struct rect_list *list;
87 struct rect_list *first;
88 struct list_head *head;
89 unsigned int index;
90 unsigned int tile_perline;
91 unsigned int tile_perrow;
92 unsigned int offset_perline;
93 unsigned int tile_size;
94 unsigned int tile_cnt;
95 };
96
97 struct npcm_ece {
98 struct regmap *regmap;
99 atomic_t clients;
100 struct reset_control *reset;
101 bool enable;
102 };
103
104 struct npcm_video {
105 struct regmap *gcr_regmap;
106 struct regmap *gfx_regmap;
107 struct regmap *vcd_regmap;
108
109 struct device *dev;
110 struct v4l2_ctrl_handler ctrl_handler;
111 struct v4l2_ctrl *rect_cnt_ctrl;
112 struct v4l2_device v4l2_dev;
113 struct v4l2_pix_format pix_fmt;
114 struct v4l2_bt_timings active_timings;
115 struct v4l2_bt_timings detected_timings;
116 unsigned int v4l2_input_status;
117 struct vb2_queue queue;
118 struct video_device vdev;
119 struct mutex video_lock; /* v4l2 and videobuf2 lock */
120
121 struct list_head buffers;
122 struct mutex buffer_lock; /* buffer list lock */
123 unsigned long flags;
124 unsigned int sequence;
125
126 struct npcm_video_addr src;
127 struct reset_control *reset;
128 struct npcm_ece ece;
129
130 unsigned int bytesperline;
131 unsigned int bytesperpixel;
132 unsigned int rect_cnt;
133 struct list_head list[VIDEO_MAX_FRAME];
134 unsigned int rect[VIDEO_MAX_FRAME];
135 unsigned int ctrl_cmd;
136 unsigned int op_cmd;
137 };
138
139 #define to_npcm_video(x) container_of((x), struct npcm_video, v4l2_dev)
140
141 struct npcm_fmt {
142 unsigned int fourcc;
143 unsigned int bpp; /* bytes per pixel */
144 };
145
146 static const struct npcm_fmt npcm_fmt_list[] = {
147 {
148 .fourcc = V4L2_PIX_FMT_RGB565,
149 .bpp = 2,
150 },
151 {
152 .fourcc = V4L2_PIX_FMT_HEXTILE,
153 .bpp = 2,
154 },
155 };
156
157 #define NUM_FORMATS ARRAY_SIZE(npcm_fmt_list)
158
159 static const struct v4l2_dv_timings_cap npcm_video_timings_cap = {
160 .type = V4L2_DV_BT_656_1120,
161 .bt = {
162 .min_width = MIN_WIDTH,
163 .max_width = MAX_WIDTH,
164 .min_height = MIN_HEIGHT,
165 .max_height = MAX_HEIGHT,
166 .min_pixelclock = 6574080, /* 640 x 480 x 24Hz */
167 .max_pixelclock = 138240000, /* 1920 x 1200 x 60Hz */
168 .standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
169 V4L2_DV_BT_STD_CVT | V4L2_DV_BT_STD_GTF,
170 .capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
171 V4L2_DV_BT_CAP_REDUCED_BLANKING |
172 V4L2_DV_BT_CAP_CUSTOM,
173 },
174 };
175
176 static DECLARE_BITMAP(bitmap, BITMAP_SIZE);
177
178 static const struct npcm_fmt *npcm_video_find_format(struct v4l2_format *f)
179 {
180 const struct npcm_fmt *fmt;
181 unsigned int k;
182
183 for (k = 0; k < NUM_FORMATS; k++) {
184 fmt = &npcm_fmt_list[k];
185 if (fmt->fourcc == f->fmt.pix.pixelformat)
186 break;
187 }
188
189 if (k == NUM_FORMATS)
190 return NULL;
191
192 return &npcm_fmt_list[k];
193 }
194
195 static void npcm_video_ece_prepend_rect_header(void *addr, u16 x, u16 y, u16 w, u16 h)
196 {
197 __be16 x_pos = cpu_to_be16(x);
198 __be16 y_pos = cpu_to_be16(y);
199 __be16 width = cpu_to_be16(w);
200 __be16 height = cpu_to_be16(h);
201 __be32 encoding = cpu_to_be32(5); /* Hextile encoding */
202
203 memcpy(addr, &x_pos, 2);
204 memcpy(addr + 2, &y_pos, 2);
205 memcpy(addr + 4, &width, 2);
206 memcpy(addr + 6, &height, 2);
207 memcpy(addr + 8, &encoding, 4);
208 }
209
210 static unsigned int npcm_video_ece_get_ed_size(struct npcm_video *video,
211 unsigned int offset, void *addr)
212 {
213 struct regmap *ece = video->ece.regmap;
214 unsigned int size, gap, val;
215 int ret;
216
217 ret = regmap_read_poll_timeout(ece, ECE_DDA_STS, val,
218 (val & ECE_DDA_STS_CDREADY), 0,
219 ECE_POLL_TIMEOUT_US);
220
221 if (ret) {
222 dev_warn(video->dev, "Wait for ECE_DDA_STS_CDREADY timeout\n");
223 return 0;
224 }
225
226 size = readl((void __iomem *)addr + offset);
227 regmap_read(ece, ECE_HEX_CTRL, &val);
228 gap = FIELD_GET(ECE_HEX_CTRL_ENC_GAP, val);
229
230 dev_dbg(video->dev, "offset = %u, ed_size = %u, gap = %u\n", offset,
231 size, gap);
232
233 return size + gap;
234 }
235
236 static void npcm_video_ece_enc_rect(struct npcm_video *video,
237 unsigned int r_off_x, unsigned int r_off_y,
238 unsigned int r_w, unsigned int r_h)
239 {
240 struct regmap *ece = video->ece.regmap;
241 unsigned int rect_offset = (r_off_y * video->bytesperline) + (r_off_x * 2);
242 unsigned int w_size = ECE_TILE_W, h_size = ECE_TILE_H;
243 unsigned int temp, w_tile, h_tile;
244
245 regmap_update_bits(ece, ECE_DDA_CTRL, ECE_DDA_CTRL_ECEEN, 0);
246 regmap_update_bits(ece, ECE_DDA_CTRL, ECE_DDA_CTRL_ECEEN, ECE_DDA_CTRL_ECEEN);
247 regmap_write(ece, ECE_DDA_STS, ECE_DDA_STS_CDREADY | ECE_DDA_STS_ACDRDY);
248 regmap_write(ece, ECE_RECT_XY, rect_offset);
249
250 w_tile = r_w / ECE_TILE_W;
251 h_tile = r_h / ECE_TILE_H;
252
253 if (r_w % ECE_TILE_W) {
254 w_tile += 1;
255 w_size = r_w % ECE_TILE_W;
256 }
257 if (r_h % ECE_TILE_H || !h_tile) {
258 h_tile += 1;
259 h_size = r_h % ECE_TILE_H;
260 }
261
262 temp = FIELD_PREP(ECE_RECT_DIMEN_WLTR, w_size - 1) |
263 FIELD_PREP(ECE_RECT_DIMEN_HLTR, h_size - 1) |
264 FIELD_PREP(ECE_RECT_DIMEN_WR, w_tile - 1) |
265 FIELD_PREP(ECE_RECT_DIMEN_HR, h_tile - 1);
266
267 regmap_write(ece, ECE_RECT_DIMEN, temp);
268 }
269
270 static unsigned int npcm_video_ece_read_rect_offset(struct npcm_video *video)
271 {
272 struct regmap *ece = video->ece.regmap;
273 unsigned int offset;
274
275 regmap_read(ece, ECE_HEX_RECT_OFFSET, &offset);
276 return FIELD_GET(ECE_HEX_RECT_OFFSET_MASK, offset);
277 }
278
279 /*
280 * Set the line pitch (in bytes) for the frame buffers.
281 * Can be on of those values: 512, 1024, 2048, 2560 or 4096 bytes.
282 */
283 static void npcm_video_ece_set_lp(struct npcm_video *video, unsigned int pitch)
284 {
285 struct regmap *ece = video->ece.regmap;
286 unsigned int lp;
287
288 switch (pitch) {
289 case 512:
290 lp = ECE_RESOL_FB_LP_512;
291 break;
292 case 1024:
293 lp = ECE_RESOL_FB_LP_1024;
294 break;
295 case 2048:
296 lp = ECE_RESOL_FB_LP_2048;
297 break;
298 case 2560:
299 lp = ECE_RESOL_FB_LP_2560;
300 break;
301 case 4096:
302 lp = ECE_RESOL_FB_LP_4096;
303 break;
304 default:
305 return;
306 }
307
308 regmap_write(ece, ECE_RESOL, lp);
309 }
310
311 static inline void npcm_video_ece_set_fb_addr(struct npcm_video *video,
312 unsigned int buffer)
313 {
314 struct regmap *ece = video->ece.regmap;
315
316 regmap_write(ece, ECE_FBR_BA, buffer);
317 }
318
319 static inline void npcm_video_ece_set_enc_dba(struct npcm_video *video,
320 unsigned int addr)
321 {
322 struct regmap *ece = video->ece.regmap;
323
324 regmap_write(ece, ECE_ED_BA, addr);
325 }
326
327 static inline void npcm_video_ece_clear_rect_offset(struct npcm_video *video)
328 {
329 struct regmap *ece = video->ece.regmap;
330
331 regmap_write(ece, ECE_HEX_RECT_OFFSET, 0);
332 }
333
334 static void npcm_video_ece_ctrl_reset(struct npcm_video *video)
335 {
336 struct regmap *ece = video->ece.regmap;
337
338 regmap_update_bits(ece, ECE_DDA_CTRL, ECE_DDA_CTRL_ECEEN, 0);
339 regmap_update_bits(ece, ECE_HEX_CTRL, ECE_HEX_CTRL_ENCDIS, ECE_HEX_CTRL_ENCDIS);
340 regmap_update_bits(ece, ECE_DDA_CTRL, ECE_DDA_CTRL_ECEEN, ECE_DDA_CTRL_ECEEN);
341 regmap_update_bits(ece, ECE_HEX_CTRL, ECE_HEX_CTRL_ENCDIS, 0);
342
343 npcm_video_ece_clear_rect_offset(video);
344 }
345
346 static void npcm_video_ece_ip_reset(struct npcm_video *video)
347 {
348 /*
349 * After resetting a module and clearing the reset bit, it should wait
350 * at least 10 us before accessing the module.
351 */
352 reset_control_assert(video->ece.reset);
353 usleep_range(10, 20);
354 reset_control_deassert(video->ece.reset);
355 usleep_range(10, 20);
356 }
357
358 static void npcm_video_ece_stop(struct npcm_video *video)
359 {
360 struct regmap *ece = video->ece.regmap;
361
362 regmap_update_bits(ece, ECE_DDA_CTRL, ECE_DDA_CTRL_ECEEN, 0);
363 regmap_update_bits(ece, ECE_DDA_CTRL, ECE_DDA_CTRL_INTEN, 0);
364 regmap_update_bits(ece, ECE_HEX_CTRL, ECE_HEX_CTRL_ENCDIS, ECE_HEX_CTRL_ENCDIS);
365 npcm_video_ece_clear_rect_offset(video);
366 }
367
368 static bool npcm_video_alloc_fb(struct npcm_video *video,
369 struct npcm_video_addr *addr)
370 {
371 addr->virt = dma_alloc_coherent(video->dev, VCD_FB_SIZE, &addr->dma,
372 GFP_KERNEL);
373 if (!addr->virt)
374 return false;
375
376 addr->size = VCD_FB_SIZE;
377 return true;
378 }
379
380 static void npcm_video_free_fb(struct npcm_video *video,
381 struct npcm_video_addr *addr)
382 {
383 dma_free_coherent(video->dev, addr->size, addr->virt, addr->dma);
384 addr->size = 0;
385 addr->dma = 0ULL;
386 addr->virt = NULL;
387 }
388
389 static void npcm_video_free_diff_table(struct npcm_video *video)
390 {
391 struct list_head *head, *pos, *nx;
392 struct rect_list *tmp;
393 unsigned int i;
394
395 for (i = 0; i < vb2_get_num_buffers(&video->queue); i++) {
396 head = &video->list[i];
397 list_for_each_safe(pos, nx, head) {
398 tmp = list_entry(pos, struct rect_list, list);
399 list_del(&tmp->list);
400 kfree(tmp);
401 }
402 }
403 }
404
405 static unsigned int npcm_video_add_rect(struct npcm_video *video,
406 unsigned int index,
407 unsigned int x, unsigned int y,
408 unsigned int w, unsigned int h)
409 {
410 struct list_head *head = &video->list[index];
411 struct rect_list *list = NULL;
412 struct v4l2_rect *r;
413
414 list = kzalloc(sizeof(*list), GFP_KERNEL);
415 if (!list)
416 return 0;
417
418 r = &list->clip.c;
419 r->left = x;
420 r->top = y;
421 r->width = w;
422 r->height = h;
423
424 list_add_tail(&list->list, head);
425 return 1;
426 }
427
428 static void npcm_video_merge_rect(struct npcm_video *video,
429 struct rect_list_info *info)
430 {
431 struct list_head *head = info->head;
432 struct rect_list *list = info->list, *first = info->first;
433 struct v4l2_rect *r = &list->clip.c, *f = &first->clip.c;
434
435 if (!first) {
436 first = list;
437 info->first = first;
438 list_add_tail(&list->list, head);
439 video->rect_cnt++;
440 } else {
441 if ((r->left == (f->left + f->width)) && r->top == f->top) {
442 f->width += r->width;
443 kfree(list);
444 } else if ((r->top == (f->top + f->height)) &&
445 (r->left == f->left)) {
446 f->height += r->height;
447 kfree(list);
448 } else if (((r->top > f->top) &&
449 (r->top < (f->top + f->height))) &&
450 ((r->left > f->left) &&
451 (r->left < (f->left + f->width)))) {
452 kfree(list);
453 } else {
454 list_add_tail(&list->list, head);
455 video->rect_cnt++;
456 info->first = list;
457 }
458 }
459 }
460
461 static struct rect_list *npcm_video_new_rect(struct npcm_video *video,
462 unsigned int offset,
463 unsigned int index)
464 {
465 struct v4l2_bt_timings *act = &video->active_timings;
466 struct rect_list *list = NULL;
467 struct v4l2_rect *r;
468
469 list = kzalloc(sizeof(*list), GFP_KERNEL);
470 if (!list)
471 return NULL;
472
473 r = &list->clip.c;
474
475 r->left = (offset << 4);
476 r->top = (index >> 2);
477 r->width = RECT_W;
478 r->height = RECT_H;
479 if ((r->left + RECT_W) > act->width)
480 r->width = act->width - r->left;
481 if ((r->top + RECT_H) > act->height)
482 r->height = act->height - r->top;
483
484 return list;
485 }
486
487 static int npcm_video_find_rect(struct npcm_video *video,
488 struct rect_list_info *info,
489 unsigned int offset)
490 {
491 if (offset < info->tile_perline) {
492 info->list = npcm_video_new_rect(video, offset, info->index);
493 if (!info->list) {
494 dev_err(video->dev, "Failed to allocate rect_list\n");
495 return -ENOMEM;
496 }
497
498 npcm_video_merge_rect(video, info);
499 }
500 return 0;
501 }
502
503 static int npcm_video_build_table(struct npcm_video *video,
504 struct rect_list_info *info)
505 {
506 struct regmap *vcd = video->vcd_regmap;
507 unsigned int j, bit, value;
508 int ret;
509
510 for (j = 0; j < info->offset_perline; j += 4) {
511 regmap_read(vcd, VCD_DIFF_TBL + (j + info->index), &value);
512
513 bitmap_from_arr32(bitmap, &value, BITMAP_SIZE);
514
515 for_each_set_bit(bit, bitmap, BITMAP_SIZE) {
516 ret = npcm_video_find_rect(video, info, bit + (j << 3));
517 if (ret)
518 return ret;
519 }
520 }
521 info->index += 64;
522 return info->tile_perline;
523 }
524
525 static void npcm_video_get_rect_list(struct npcm_video *video, unsigned int index)
526 {
527 struct v4l2_bt_timings *act = &video->active_timings;
528 struct rect_list_info info;
529 unsigned int tile_cnt = 0, mod;
530 int ret = 0;
531
532 memset(&info, 0, sizeof(struct rect_list_info));
533 info.head = &video->list[index];
534
535 info.tile_perline = act->width >> 4;
536 mod = act->width % RECT_W;
537 if (mod != 0)
538 info.tile_perline += 1;
539
540 info.tile_perrow = act->height >> 4;
541 mod = act->height % RECT_H;
542 if (mod != 0)
543 info.tile_perrow += 1;
544
545 info.tile_size = info.tile_perrow * info.tile_perline;
546
547 info.offset_perline = info.tile_perline >> 5;
548 mod = info.tile_perline % 32;
549 if (mod != 0)
550 info.offset_perline += 1;
551
552 info.offset_perline *= 4;
553
554 do {
555 ret = npcm_video_build_table(video, &info);
556 if (ret < 0)
557 return;
558
559 tile_cnt += ret;
560 } while (tile_cnt < info.tile_size);
561 }
562
563 static unsigned int npcm_video_is_mga(struct npcm_video *video)
564 {
565 struct regmap *gfxi = video->gfx_regmap;
566 unsigned int dispst;
567
568 regmap_read(gfxi, DISPST, &dispst);
569 return ((dispst & DISPST_MGAMODE) == DISPST_MGAMODE);
570 }
571
572 static unsigned int npcm_video_hres(struct npcm_video *video)
573 {
574 struct regmap *gfxi = video->gfx_regmap;
575 unsigned int hvcnth, hvcntl, apb_hor_res;
576
577 regmap_read(gfxi, HVCNTH, &hvcnth);
578 regmap_read(gfxi, HVCNTL, &hvcntl);
579 apb_hor_res = (((hvcnth & HVCNTH_MASK) << 8) + (hvcntl & HVCNTL_MASK) + 1);
580
581 return apb_hor_res;
582 }
583
584 static unsigned int npcm_video_vres(struct npcm_video *video)
585 {
586 struct regmap *gfxi = video->gfx_regmap;
587 unsigned int vvcnth, vvcntl, apb_ver_res;
588
589 regmap_read(gfxi, VVCNTH, &vvcnth);
590 regmap_read(gfxi, VVCNTL, &vvcntl);
591
592 apb_ver_res = (((vvcnth & VVCNTH_MASK) << 8) + (vvcntl & VVCNTL_MASK));
593
594 return apb_ver_res;
595 }
596
597 static int npcm_video_capres(struct npcm_video *video, unsigned int hor_res,
598 unsigned int vert_res)
599 {
600 struct regmap *vcd = video->vcd_regmap;
601 unsigned int res, cap_res;
602
603 if (hor_res > MAX_WIDTH || vert_res > MAX_HEIGHT)
604 return -EINVAL;
605
606 res = FIELD_PREP(VCD_CAP_RES_VERT_RES, vert_res) |
607 FIELD_PREP(VCD_CAP_RES_HOR_RES, hor_res);
608
609 regmap_write(vcd, VCD_CAP_RES, res);
610 regmap_read(vcd, VCD_CAP_RES, &cap_res);
611
612 if (cap_res != res)
613 return -EINVAL;
614
615 return 0;
616 }
617
618 static void npcm_video_vcd_ip_reset(struct npcm_video *video)
619 {
620 /*
621 * After resetting a module and clearing the reset bit, it should wait
622 * at least 10 us before accessing the module.
623 */
624 reset_control_assert(video->reset);
625 usleep_range(10, 20);
626 reset_control_deassert(video->reset);
627 usleep_range(10, 20);
628 }
629
630 static void npcm_video_vcd_state_machine_reset(struct npcm_video *video)
631 {
632 struct regmap *vcd = video->vcd_regmap;
633
634 regmap_update_bits(vcd, VCD_MODE, VCD_MODE_VCDE, 0);
635 regmap_update_bits(vcd, VCD_MODE, VCD_MODE_IDBC, 0);
636 regmap_update_bits(vcd, VCD_CMD, VCD_CMD_RST, VCD_CMD_RST);
637
638 /*
639 * VCD_CMD_RST will reset VCD internal state machines and clear FIFOs,
640 * it should wait at least 800 us for the reset operations completed.
641 */
642 usleep_range(800, 1000);
643
644 regmap_write(vcd, VCD_STAT, VCD_STAT_CLEAR);
645 regmap_update_bits(vcd, VCD_MODE, VCD_MODE_VCDE, VCD_MODE_VCDE);
646 regmap_update_bits(vcd, VCD_MODE, VCD_MODE_IDBC, VCD_MODE_IDBC);
647 }
648
649 static void npcm_video_gfx_reset(struct npcm_video *video)
650 {
651 struct regmap *gcr = video->gcr_regmap;
652
653 regmap_update_bits(gcr, INTCR2, INTCR2_GIRST2, INTCR2_GIRST2);
654 npcm_video_vcd_state_machine_reset(video);
655 regmap_update_bits(gcr, INTCR2, INTCR2_GIRST2, 0);
656 }
657
658 static void npcm_video_kvm_bw(struct npcm_video *video, bool set_bw)
659 {
660 struct regmap *vcd = video->vcd_regmap;
661
662 if (set_bw || !npcm_video_is_mga(video))
663 regmap_update_bits(vcd, VCD_MODE, VCD_MODE_KVM_BW_SET,
664 VCD_MODE_KVM_BW_SET);
665 else
666 regmap_update_bits(vcd, VCD_MODE, VCD_MODE_KVM_BW_SET, 0);
667 }
668
669 static unsigned int npcm_video_pclk(struct npcm_video *video)
670 {
671 struct regmap *gfxi = video->gfx_regmap;
672 unsigned int tmp, pllfbdiv, pllinotdiv, gpllfbdiv;
673 unsigned int gpllfbdv109, gpllfbdv8, gpllindiv;
674 unsigned int gpllst_pllotdiv1, gpllst_pllotdiv2;
675
676 regmap_read(gfxi, GPLLST, &tmp);
677 gpllfbdv109 = FIELD_GET(GPLLST_GPLLFBDV109, tmp);
678 gpllst_pllotdiv1 = FIELD_GET(GPLLST_PLLOTDIV1, tmp);
679 gpllst_pllotdiv2 = FIELD_GET(GPLLST_PLLOTDIV2, tmp);
680
681 regmap_read(gfxi, GPLLINDIV, &tmp);
682 gpllfbdv8 = FIELD_GET(GPLLINDIV_GPLLFBDV8, tmp);
683 gpllindiv = FIELD_GET(GPLLINDIV_MASK, tmp);
684
685 regmap_read(gfxi, GPLLFBDIV, &tmp);
686 gpllfbdiv = FIELD_GET(GPLLFBDIV_MASK, tmp);
687
688 pllfbdiv = (512 * gpllfbdv109 + 256 * gpllfbdv8 + gpllfbdiv);
689 pllinotdiv = (gpllindiv * gpllst_pllotdiv1 * gpllst_pllotdiv2);
690 if (pllfbdiv == 0 || pllinotdiv == 0)
691 return 0;
692
693 return ((pllfbdiv * 25000) / pllinotdiv) * 1000;
694 }
695
696 static unsigned int npcm_video_get_bpp(struct npcm_video *video)
697 {
698 const struct npcm_fmt *fmt;
699 unsigned int k;
700
701 for (k = 0; k < NUM_FORMATS; k++) {
702 fmt = &npcm_fmt_list[k];
703 if (fmt->fourcc == video->pix_fmt.pixelformat)
704 break;
705 }
706
707 return fmt->bpp;
708 }
709
710 /*
711 * Pitch must be a power of 2, >= linebytes,
712 * at least 512, and no more than 4096.
713 */
714 static void npcm_video_set_linepitch(struct npcm_video *video,
715 unsigned int linebytes)
716 {
717 struct regmap *vcd = video->vcd_regmap;
718 unsigned int pitch = MIN_LP;
719
720 while ((pitch < linebytes) && (pitch < MAX_LP))
721 pitch *= 2;
722
723 regmap_write(vcd, VCD_FB_LP, FIELD_PREP(VCD_FBA_LP, pitch) |
724 FIELD_PREP(VCD_FBB_LP, pitch));
725 }
726
727 static unsigned int npcm_video_get_linepitch(struct npcm_video *video)
728 {
729 struct regmap *vcd = video->vcd_regmap;
730 unsigned int linepitch;
731
732 regmap_read(vcd, VCD_FB_LP, &linepitch);
733 return FIELD_GET(VCD_FBA_LP, linepitch);
734 }
735
736 static void npcm_video_command(struct npcm_video *video, unsigned int value)
737 {
738 struct regmap *vcd = video->vcd_regmap;
739 unsigned int cmd;
740
741 regmap_write(vcd, VCD_STAT, VCD_STAT_CLEAR);
742 regmap_read(vcd, VCD_CMD, &cmd);
743 cmd |= FIELD_PREP(VCD_CMD_OPERATION, value);
744
745 regmap_write(vcd, VCD_CMD, cmd);
746 regmap_update_bits(vcd, VCD_CMD, VCD_CMD_GO, VCD_CMD_GO);
747 video->op_cmd = value;
748 }
749
750 static void npcm_video_init_reg(struct npcm_video *video)
751 {
752 struct regmap *gcr = video->gcr_regmap, *vcd = video->vcd_regmap;
753
754 /* Selects Data Enable */
755 regmap_update_bits(gcr, INTCR, INTCR_DEHS, 0);
756
757 /* Enable display of KVM GFX and access to memory */
758 regmap_update_bits(gcr, INTCR, INTCR_GFXIFDIS, 0);
759
760 /* Active Vertical/Horizontal Counters Reset */
761 regmap_update_bits(gcr, INTCR2, INTCR2_GIHCRST | INTCR2_GIVCRST,
762 INTCR2_GIHCRST | INTCR2_GIVCRST);
763
764 /* Reset video modules */
765 npcm_video_vcd_ip_reset(video);
766 npcm_video_gfx_reset(video);
767
768 /* Set the FIFO thresholds */
769 regmap_write(vcd, VCD_FIFO, VCD_FIFO_TH);
770
771 /* Set RCHG timer */
772 regmap_write(vcd, VCD_RCHG, FIELD_PREP(VCD_RCHG_TIM_PRSCL, 0xf) |
773 FIELD_PREP(VCD_RCHG_IG_CHG0, 0x3));
774
775 /* Set video mode */
776 regmap_write(vcd, VCD_MODE, VCD_MODE_VCDE | VCD_MODE_CM565 |
777 VCD_MODE_IDBC | VCD_MODE_KVM_BW_SET);
778 }
779
780 static int npcm_video_start_frame(struct npcm_video *video)
781 {
782 struct npcm_video_buffer *buf;
783 struct regmap *vcd = video->vcd_regmap;
784 unsigned int val;
785 int ret;
786
787 if (video->v4l2_input_status) {
788 dev_dbg(video->dev, "No video signal; skip capture frame\n");
789 return 0;
790 }
791
792 ret = regmap_read_poll_timeout(vcd, VCD_STAT, val, !(val & VCD_STAT_BUSY),
793 1000, VCD_TIMEOUT_US);
794 if (ret) {
795 dev_err(video->dev, "Wait for VCD_STAT_BUSY timeout\n");
796 return -EBUSY;
797 }
798
799 mutex_lock(&video->buffer_lock);
800 buf = list_first_entry_or_null(&video->buffers,
801 struct npcm_video_buffer, link);
802 if (!buf) {
803 mutex_unlock(&video->buffer_lock);
804 dev_dbg(video->dev, "No empty buffers; skip capture frame\n");
805 return 0;
806 }
807
808 set_bit(VIDEO_CAPTURING, &video->flags);
809 mutex_unlock(&video->buffer_lock);
810
811 npcm_video_vcd_state_machine_reset(video);
812
813 regmap_read(vcd, VCD_HOR_AC_TIM, &val);
814 regmap_update_bits(vcd, VCD_HOR_AC_LST, VCD_HOR_AC_LAST,
815 FIELD_GET(VCD_HOR_AC_TIME, val));
816
817 regmap_read(vcd, VCD_VER_HI_TIM, &val);
818 regmap_update_bits(vcd, VCD_VER_HI_LST, VCD_VER_HI_LAST,
819 FIELD_GET(VCD_VER_HI_TIME, val));
820
821 regmap_update_bits(vcd, VCD_INTE, VCD_INTE_DONE_IE | VCD_INTE_IFOT_IE |
822 VCD_INTE_IFOR_IE | VCD_INTE_HAC_IE | VCD_INTE_VHT_IE,
823 VCD_INTE_DONE_IE | VCD_INTE_IFOT_IE | VCD_INTE_IFOR_IE |
824 VCD_INTE_HAC_IE | VCD_INTE_VHT_IE);
825
826 npcm_video_command(video, video->ctrl_cmd);
827
828 return 0;
829 }
830
831 static void npcm_video_bufs_done(struct npcm_video *video,
832 enum vb2_buffer_state state)
833 {
834 struct npcm_video_buffer *buf;
835
836 mutex_lock(&video->buffer_lock);
837 list_for_each_entry(buf, &video->buffers, link)
838 vb2_buffer_done(&buf->vb.vb2_buf, state);
839
840 INIT_LIST_HEAD(&video->buffers);
841 mutex_unlock(&video->buffer_lock);
842 }
843
844 static void npcm_video_get_diff_rect(struct npcm_video *video, unsigned int index)
845 {
846 unsigned int width = video->active_timings.width;
847 unsigned int height = video->active_timings.height;
848
849 if (video->op_cmd != VCD_CMD_OPERATION_CAPTURE) {
850 video->rect_cnt = 0;
851 npcm_video_get_rect_list(video, index);
852 video->rect[index] = video->rect_cnt;
853 } else {
854 video->rect[index] = npcm_video_add_rect(video, index, 0, 0,
855 width, height);
856 }
857 }
858
859 static void npcm_video_detect_resolution(struct npcm_video *video)
860 {
861 struct v4l2_bt_timings *act = &video->active_timings;
862 struct v4l2_bt_timings *det = &video->detected_timings;
863 struct regmap *gfxi = video->gfx_regmap;
864 unsigned int dispst;
865
866 video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL;
867 det->width = npcm_video_hres(video);
868 det->height = npcm_video_vres(video);
869
870 if (act->width != det->width || act->height != det->height) {
871 dev_dbg(video->dev, "Resolution changed\n");
872
873 if (npcm_video_hres(video) > 0 && npcm_video_vres(video) > 0) {
874 if (test_bit(VIDEO_STREAMING, &video->flags)) {
875 /*
876 * Wait for resolution is available,
877 * and it is also captured by host.
878 */
879 do {
880 mdelay(100);
881 regmap_read(gfxi, DISPST, &dispst);
882 } while (npcm_video_vres(video) < 100 ||
883 npcm_video_pclk(video) == 0 ||
884 (dispst & DISPST_HSCROFF));
885 }
886
887 det->width = npcm_video_hres(video);
888 det->height = npcm_video_vres(video);
889 det->pixelclock = npcm_video_pclk(video);
890 }
891
892 clear_bit(VIDEO_RES_CHANGING, &video->flags);
893 }
894
895 if (det->width && det->height)
896 video->v4l2_input_status = 0;
897
898 dev_dbg(video->dev, "Got resolution[%dx%d] -> [%dx%d], status %d\n",
899 act->width, act->height, det->width, det->height,
900 video->v4l2_input_status);
901 }
902
903 static int npcm_video_set_resolution(struct npcm_video *video,
904 struct v4l2_bt_timings *timing)
905 {
906 struct regmap *vcd = video->vcd_regmap;
907 unsigned int mode;
908
909 if (npcm_video_capres(video, timing->width, timing->height)) {
910 dev_err(video->dev, "Failed to set VCD_CAP_RES\n");
911 return -EINVAL;
912 }
913
914 video->active_timings = *timing;
915 video->bytesperpixel = npcm_video_get_bpp(video);
916 npcm_video_set_linepitch(video, timing->width * video->bytesperpixel);
917 video->bytesperline = npcm_video_get_linepitch(video);
918 video->pix_fmt.width = timing->width ? timing->width : MIN_WIDTH;
919 video->pix_fmt.height = timing->height ? timing->height : MIN_HEIGHT;
920 video->pix_fmt.sizeimage = video->pix_fmt.width * video->pix_fmt.height *
921 video->bytesperpixel;
922 video->pix_fmt.bytesperline = video->bytesperline;
923
924 npcm_video_kvm_bw(video, timing->pixelclock > VCD_KVM_BW_PCLK);
925 npcm_video_gfx_reset(video);
926 regmap_read(vcd, VCD_MODE, &mode);
927
928 dev_dbg(video->dev, "VCD mode = 0x%x, %s mode\n", mode,
929 npcm_video_is_mga(video) ? "Hi Res" : "VGA");
930
931 dev_dbg(video->dev,
932 "Digital mode: %d x %d x %d, pixelclock %lld, bytesperline %d\n",
933 timing->width, timing->height, video->bytesperpixel,
934 timing->pixelclock, video->bytesperline);
935
936 return 0;
937 }
938
939 static void npcm_video_start(struct npcm_video *video)
940 {
941 npcm_video_init_reg(video);
942
943 if (!npcm_video_alloc_fb(video, &video->src)) {
944 dev_err(video->dev, "Failed to allocate VCD frame buffer\n");
945 return;
946 }
947
948 npcm_video_detect_resolution(video);
949 if (npcm_video_set_resolution(video, &video->detected_timings)) {
950 dev_err(video->dev, "Failed to set resolution\n");
951 return;
952 }
953
954 /* Set frame buffer physical address */
955 regmap_write(video->vcd_regmap, VCD_FBA_ADR, video->src.dma);
956 regmap_write(video->vcd_regmap, VCD_FBB_ADR, video->src.dma);
957
958 if (video->ece.enable && atomic_inc_return(&video->ece.clients) == 1) {
959 npcm_video_ece_ip_reset(video);
960 npcm_video_ece_ctrl_reset(video);
961 npcm_video_ece_set_fb_addr(video, video->src.dma);
962 npcm_video_ece_set_lp(video, video->bytesperline);
963
964 dev_dbg(video->dev, "ECE open: client %d\n",
965 atomic_read(&video->ece.clients));
966 }
967 }
968
969 static void npcm_video_stop(struct npcm_video *video)
970 {
971 struct regmap *vcd = video->vcd_regmap;
972
973 set_bit(VIDEO_STOPPED, &video->flags);
974
975 regmap_write(vcd, VCD_INTE, 0);
976 regmap_write(vcd, VCD_MODE, 0);
977 regmap_write(vcd, VCD_RCHG, 0);
978 regmap_write(vcd, VCD_STAT, VCD_STAT_CLEAR);
979
980 if (video->src.size)
981 npcm_video_free_fb(video, &video->src);
982
983 npcm_video_free_diff_table(video);
984 video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL;
985 video->flags = 0;
986 video->ctrl_cmd = VCD_CMD_OPERATION_CAPTURE;
987
988 if (video->ece.enable && atomic_dec_return(&video->ece.clients) == 0) {
989 npcm_video_ece_stop(video);
990 dev_dbg(video->dev, "ECE close: client %d\n",
991 atomic_read(&video->ece.clients));
992 }
993 }
994
995 static unsigned int npcm_video_raw(struct npcm_video *video, int index, void *addr)
996 {
997 unsigned int width = video->active_timings.width;
998 unsigned int height = video->active_timings.height;
999 unsigned int i, len, offset, bytes = 0;
1000
1001 video->rect[index] = npcm_video_add_rect(video, index, 0, 0, width, height);
1002
1003 for (i = 0; i < height; i++) {
1004 len = width * video->bytesperpixel;
1005 offset = i * video->bytesperline;
1006
1007 memcpy(addr + bytes, video->src.virt + offset, len);
1008 bytes += len;
1009 }
1010
1011 return bytes;
1012 }
1013
1014 static unsigned int npcm_video_hextile(struct npcm_video *video, unsigned int index,
1015 unsigned int dma_addr, void *vaddr)
1016 {
1017 struct rect_list *rect_list;
1018 struct v4l2_rect *rect;
1019 unsigned int offset, len, bytes = 0;
1020
1021 npcm_video_ece_ctrl_reset(video);
1022 npcm_video_ece_clear_rect_offset(video);
1023 npcm_video_ece_set_fb_addr(video, video->src.dma);
1024
1025 /* Set base address of encoded data to video buffer */
1026 npcm_video_ece_set_enc_dba(video, dma_addr);
1027
1028 npcm_video_ece_set_lp(video, video->bytesperline);
1029 npcm_video_get_diff_rect(video, index);
1030
1031 list_for_each_entry(rect_list, &video->list[index], list) {
1032 rect = &rect_list->clip.c;
1033 offset = npcm_video_ece_read_rect_offset(video);
1034 npcm_video_ece_enc_rect(video, rect->left, rect->top,
1035 rect->width, rect->height);
1036
1037 len = npcm_video_ece_get_ed_size(video, offset, vaddr);
1038 npcm_video_ece_prepend_rect_header(vaddr + offset,
1039 rect->left, rect->top,
1040 rect->width, rect->height);
1041 bytes += len;
1042 }
1043
1044 return bytes;
1045 }
1046
1047 static irqreturn_t npcm_video_irq(int irq, void *arg)
1048 {
1049 struct npcm_video *video = arg;
1050 struct regmap *vcd = video->vcd_regmap;
1051 struct npcm_video_buffer *buf;
1052 unsigned int index, size, status, fmt;
1053 dma_addr_t dma_addr;
1054 void *addr;
1055 static const struct v4l2_event ev = {
1056 .type = V4L2_EVENT_SOURCE_CHANGE,
1057 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
1058 };
1059
1060 regmap_read(vcd, VCD_STAT, &status);
1061 dev_dbg(video->dev, "VCD irq status 0x%x\n", status);
1062
1063 regmap_write(vcd, VCD_STAT, VCD_STAT_CLEAR);
1064
1065 if (test_bit(VIDEO_STOPPED, &video->flags) ||
1066 !test_bit(VIDEO_STREAMING, &video->flags))
1067 return IRQ_NONE;
1068
1069 if (status & VCD_STAT_DONE) {
1070 regmap_write(vcd, VCD_INTE, 0);
1071 mutex_lock(&video->buffer_lock);
1072 clear_bit(VIDEO_CAPTURING, &video->flags);
1073 buf = list_first_entry_or_null(&video->buffers,
1074 struct npcm_video_buffer, link);
1075 if (!buf) {
1076 mutex_unlock(&video->buffer_lock);
1077 return IRQ_NONE;
1078 }
1079
1080 addr = vb2_plane_vaddr(&buf->vb.vb2_buf, 0);
1081 index = buf->vb.vb2_buf.index;
1082 fmt = video->pix_fmt.pixelformat;
1083
1084 switch (fmt) {
1085 case V4L2_PIX_FMT_RGB565:
1086 size = npcm_video_raw(video, index, addr);
1087 break;
1088 case V4L2_PIX_FMT_HEXTILE:
1089 dma_addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
1090 size = npcm_video_hextile(video, index, dma_addr, addr);
1091 break;
1092 default:
1093 mutex_unlock(&video->buffer_lock);
1094 return IRQ_NONE;
1095 }
1096
1097 vb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);
1098 buf->vb.vb2_buf.timestamp = ktime_get_ns();
1099 buf->vb.sequence = video->sequence++;
1100 buf->vb.field = V4L2_FIELD_NONE;
1101
1102 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
1103 list_del(&buf->link);
1104 mutex_unlock(&video->buffer_lock);
1105
1106 if (npcm_video_start_frame(video))
1107 dev_err(video->dev, "Failed to capture next frame\n");
1108 }
1109
1110 /* Resolution changed */
1111 if (status & VCD_STAT_VHT_CHG || status & VCD_STAT_HAC_CHG) {
1112 if (!test_bit(VIDEO_RES_CHANGING, &video->flags)) {
1113 set_bit(VIDEO_RES_CHANGING, &video->flags);
1114
1115 vb2_queue_error(&video->queue);
1116 v4l2_event_queue(&video->vdev, &ev);
1117 }
1118 }
1119
1120 if (status & VCD_STAT_IFOR || status & VCD_STAT_IFOT) {
1121 dev_warn(video->dev, "VCD FIFO overrun or over thresholds\n");
1122 if (npcm_video_start_frame(video))
1123 dev_err(video->dev, "Failed to recover from FIFO overrun\n");
1124 }
1125
1126 return IRQ_HANDLED;
1127 }
1128
1129 static int npcm_video_querycap(struct file *file, void *fh,
1130 struct v4l2_capability *cap)
1131 {
1132 strscpy(cap->driver, DEVICE_NAME, sizeof(cap->driver));
1133 strscpy(cap->card, "NPCM Video Engine", sizeof(cap->card));
1134
1135 return 0;
1136 }
1137
1138 static int npcm_video_enum_format(struct file *file, void *fh,
1139 struct v4l2_fmtdesc *f)
1140 {
1141 struct npcm_video *video = video_drvdata(file);
1142 const struct npcm_fmt *fmt;
1143
1144 if (f->index >= NUM_FORMATS)
1145 return -EINVAL;
1146
1147 fmt = &npcm_fmt_list[f->index];
1148 if (fmt->fourcc == V4L2_PIX_FMT_HEXTILE && !video->ece.enable)
1149 return -EINVAL;
1150
1151 f->pixelformat = fmt->fourcc;
1152 return 0;
1153 }
1154
1155 static int npcm_video_try_format(struct file *file, void *fh,
1156 struct v4l2_format *f)
1157 {
1158 struct npcm_video *video = video_drvdata(file);
1159 const struct npcm_fmt *fmt;
1160
1161 fmt = npcm_video_find_format(f);
1162
1163 /* If format not found or HEXTILE not supported, use RGB565 as default */
1164 if (!fmt || (fmt->fourcc == V4L2_PIX_FMT_HEXTILE && !video->ece.enable))
1165 f->fmt.pix.pixelformat = npcm_fmt_list[0].fourcc;
1166
1167 f->fmt.pix.field = V4L2_FIELD_NONE;
1168 f->fmt.pix.colorspace = V4L2_COLORSPACE_SRGB;
1169 f->fmt.pix.quantization = V4L2_QUANTIZATION_FULL_RANGE;
1170 f->fmt.pix.width = video->pix_fmt.width;
1171 f->fmt.pix.height = video->pix_fmt.height;
1172 f->fmt.pix.bytesperline = video->bytesperline;
1173 f->fmt.pix.sizeimage = video->pix_fmt.sizeimage;
1174
1175 return 0;
1176 }
1177
1178 static int npcm_video_get_format(struct file *file, void *fh,
1179 struct v4l2_format *f)
1180 {
1181 struct npcm_video *video = video_drvdata(file);
1182
1183 f->fmt.pix = video->pix_fmt;
1184 return 0;
1185 }
1186
1187 static int npcm_video_set_format(struct file *file, void *fh,
1188 struct v4l2_format *f)
1189 {
1190 struct npcm_video *video = video_drvdata(file);
1191 int ret;
1192
1193 ret = npcm_video_try_format(file, fh, f);
1194 if (ret)
1195 return ret;
1196
1197 if (vb2_is_busy(&video->queue)) {
1198 dev_err(video->dev, "%s device busy\n", __func__);
1199 return -EBUSY;
1200 }
1201
1202 video->pix_fmt.pixelformat = f->fmt.pix.pixelformat;
1203 return 0;
1204 }
1205
1206 static int npcm_video_enum_input(struct file *file, void *fh,
1207 struct v4l2_input *inp)
1208 {
1209 struct npcm_video *video = video_drvdata(file);
1210
1211 if (inp->index)
1212 return -EINVAL;
1213
1214 strscpy(inp->name, "Host VGA capture", sizeof(inp->name));
1215 inp->type = V4L2_INPUT_TYPE_CAMERA;
1216 inp->capabilities = V4L2_IN_CAP_DV_TIMINGS;
1217 inp->status = video->v4l2_input_status;
1218
1219 return 0;
1220 }
1221
1222 static int npcm_video_get_input(struct file *file, void *fh, unsigned int *i)
1223 {
1224 *i = 0;
1225
1226 return 0;
1227 }
1228
1229 static int npcm_video_set_input(struct file *file, void *fh, unsigned int i)
1230 {
1231 if (i)
1232 return -EINVAL;
1233
1234 return 0;
1235 }
1236
1237 static int npcm_video_set_dv_timings(struct file *file, void *fh,
1238 struct v4l2_dv_timings *timings)
1239 {
1240 struct npcm_video *video = video_drvdata(file);
1241 int rc;
1242
1243 if (timings->bt.width == video->active_timings.width &&
1244 timings->bt.height == video->active_timings.height)
1245 return 0;
1246
1247 if (vb2_is_busy(&video->queue)) {
1248 dev_err(video->dev, "%s device busy\n", __func__);
1249 return -EBUSY;
1250 }
1251
1252 rc = npcm_video_set_resolution(video, &timings->bt);
1253 if (rc)
1254 return rc;
1255
1256 timings->type = V4L2_DV_BT_656_1120;
1257
1258 return 0;
1259 }
1260
1261 static int npcm_video_get_dv_timings(struct file *file, void *fh,
1262 struct v4l2_dv_timings *timings)
1263 {
1264 struct npcm_video *video = video_drvdata(file);
1265
1266 timings->type = V4L2_DV_BT_656_1120;
1267 timings->bt = video->active_timings;
1268
1269 return 0;
1270 }
1271
1272 static int npcm_video_query_dv_timings(struct file *file, void *fh,
1273 struct v4l2_dv_timings *timings)
1274 {
1275 struct npcm_video *video = video_drvdata(file);
1276
1277 npcm_video_detect_resolution(video);
1278 timings->type = V4L2_DV_BT_656_1120;
1279 timings->bt = video->detected_timings;
1280
1281 return video->v4l2_input_status ? -ENOLINK : 0;
1282 }
1283
1284 static int npcm_video_enum_dv_timings(struct file *file, void *fh,
1285 struct v4l2_enum_dv_timings *timings)
1286 {
1287 return v4l2_enum_dv_timings_cap(timings, &npcm_video_timings_cap,
1288 NULL, NULL);
1289 }
1290
1291 static int npcm_video_dv_timings_cap(struct file *file, void *fh,
1292 struct v4l2_dv_timings_cap *cap)
1293 {
1294 *cap = npcm_video_timings_cap;
1295
1296 return 0;
1297 }
1298
1299 static int npcm_video_sub_event(struct v4l2_fh *fh,
1300 const struct v4l2_event_subscription *sub)
1301 {
1302 switch (sub->type) {
1303 case V4L2_EVENT_SOURCE_CHANGE:
1304 return v4l2_src_change_event_subscribe(fh, sub);
1305 }
1306
1307 return v4l2_ctrl_subscribe_event(fh, sub);
1308 }
1309
1310 static const struct v4l2_ioctl_ops npcm_video_ioctls = {
1311 .vidioc_querycap = npcm_video_querycap,
1312
1313 .vidioc_enum_fmt_vid_cap = npcm_video_enum_format,
1314 .vidioc_g_fmt_vid_cap = npcm_video_get_format,
1315 .vidioc_s_fmt_vid_cap = npcm_video_set_format,
1316 .vidioc_try_fmt_vid_cap = npcm_video_try_format,
1317
1318 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1319 .vidioc_querybuf = vb2_ioctl_querybuf,
1320 .vidioc_qbuf = vb2_ioctl_qbuf,
1321 .vidioc_expbuf = vb2_ioctl_expbuf,
1322 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1323 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1324 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1325 .vidioc_streamon = vb2_ioctl_streamon,
1326 .vidioc_streamoff = vb2_ioctl_streamoff,
1327
1328 .vidioc_enum_input = npcm_video_enum_input,
1329 .vidioc_g_input = npcm_video_get_input,
1330 .vidioc_s_input = npcm_video_set_input,
1331
1332 .vidioc_s_dv_timings = npcm_video_set_dv_timings,
1333 .vidioc_g_dv_timings = npcm_video_get_dv_timings,
1334 .vidioc_query_dv_timings = npcm_video_query_dv_timings,
1335 .vidioc_enum_dv_timings = npcm_video_enum_dv_timings,
1336 .vidioc_dv_timings_cap = npcm_video_dv_timings_cap,
1337
1338 .vidioc_subscribe_event = npcm_video_sub_event,
1339 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1340 };
1341
1342 static int npcm_video_set_ctrl(struct v4l2_ctrl *ctrl)
1343 {
1344 struct npcm_video *video = container_of(ctrl->handler, struct npcm_video,
1345 ctrl_handler);
1346
1347 switch (ctrl->id) {
1348 case V4L2_CID_NPCM_CAPTURE_MODE:
1349 if (ctrl->val == V4L2_NPCM_CAPTURE_MODE_COMPLETE)
1350 video->ctrl_cmd = VCD_CMD_OPERATION_CAPTURE;
1351 else if (ctrl->val == V4L2_NPCM_CAPTURE_MODE_DIFF)
1352 video->ctrl_cmd = VCD_CMD_OPERATION_COMPARE;
1353 break;
1354 default:
1355 return -EINVAL;
1356 }
1357
1358 return 0;
1359 }
1360
1361 static const struct v4l2_ctrl_ops npcm_video_ctrl_ops = {
1362 .s_ctrl = npcm_video_set_ctrl,
1363 };
1364
1365 static const char * const npcm_ctrl_capture_mode_menu[] = {
1366 "COMPLETE",
1367 "DIFF",
1368 NULL,
1369 };
1370
1371 static const struct v4l2_ctrl_config npcm_ctrl_capture_mode = {
1372 .ops = &npcm_video_ctrl_ops,
1373 .id = V4L2_CID_NPCM_CAPTURE_MODE,
1374 .name = "NPCM Video Capture Mode",
1375 .type = V4L2_CTRL_TYPE_MENU,
1376 .min = 0,
1377 .max = V4L2_NPCM_CAPTURE_MODE_DIFF,
1378 .def = 0,
1379 .qmenu = npcm_ctrl_capture_mode_menu,
1380 };
1381
1382 /*
1383 * This control value is set when a buffer is dequeued by userspace, i.e. in
1384 * npcm_video_buf_finish function.
1385 */
1386 static const struct v4l2_ctrl_config npcm_ctrl_rect_count = {
1387 .id = V4L2_CID_NPCM_RECT_COUNT,
1388 .name = "NPCM Hextile Rectangle Count",
1389 .type = V4L2_CTRL_TYPE_INTEGER,
1390 .min = 0,
1391 .max = (MAX_WIDTH / RECT_W) * (MAX_HEIGHT / RECT_H),
1392 .step = 1,
1393 .def = 0,
1394 };
1395
1396 static int npcm_video_open(struct file *file)
1397 {
1398 struct npcm_video *video = video_drvdata(file);
1399 int rc;
1400
1401 mutex_lock(&video->video_lock);
1402 rc = v4l2_fh_open(file);
1403 if (rc) {
1404 mutex_unlock(&video->video_lock);
1405 return rc;
1406 }
1407
1408 if (v4l2_fh_is_singular_file(file))
1409 npcm_video_start(video);
1410
1411 mutex_unlock(&video->video_lock);
1412 return 0;
1413 }
1414
1415 static int npcm_video_release(struct file *file)
1416 {
1417 struct npcm_video *video = video_drvdata(file);
1418 int rc;
1419
1420 mutex_lock(&video->video_lock);
1421 if (v4l2_fh_is_singular_file(file))
1422 npcm_video_stop(video);
1423
1424 rc = _vb2_fop_release(file, NULL);
1425
1426 mutex_unlock(&video->video_lock);
1427 return rc;
1428 }
1429
1430 static const struct v4l2_file_operations npcm_video_v4l2_fops = {
1431 .owner = THIS_MODULE,
1432 .read = vb2_fop_read,
1433 .poll = vb2_fop_poll,
1434 .unlocked_ioctl = video_ioctl2,
1435 .mmap = vb2_fop_mmap,
1436 .open = npcm_video_open,
1437 .release = npcm_video_release,
1438 };
1439
1440 static int npcm_video_queue_setup(struct vb2_queue *q, unsigned int *num_buffers,
1441 unsigned int *num_planes, unsigned int sizes[],
1442 struct device *alloc_devs[])
1443 {
1444 struct npcm_video *video = vb2_get_drv_priv(q);
1445 unsigned int i;
1446
1447 if (*num_planes) {
1448 if (sizes[0] < video->pix_fmt.sizeimage)
1449 return -EINVAL;
1450
1451 return 0;
1452 }
1453
1454 *num_planes = 1;
1455 sizes[0] = video->pix_fmt.sizeimage;
1456
1457 for (i = 0; i < VIDEO_MAX_FRAME; i++)
1458 INIT_LIST_HEAD(&video->list[i]);
1459
1460 return 0;
1461 }
1462
1463 static int npcm_video_buf_prepare(struct vb2_buffer *vb)
1464 {
1465 struct npcm_video *video = vb2_get_drv_priv(vb->vb2_queue);
1466
1467 if (vb2_plane_size(vb, 0) < video->pix_fmt.sizeimage)
1468 return -EINVAL;
1469
1470 return 0;
1471 }
1472
1473 static int npcm_video_start_streaming(struct vb2_queue *q, unsigned int count)
1474 {
1475 struct npcm_video *video = vb2_get_drv_priv(q);
1476 int rc;
1477
1478 video->sequence = 0;
1479 rc = npcm_video_start_frame(video);
1480 if (rc) {
1481 npcm_video_bufs_done(video, VB2_BUF_STATE_QUEUED);
1482 return rc;
1483 }
1484
1485 set_bit(VIDEO_STREAMING, &video->flags);
1486 return 0;
1487 }
1488
1489 static void npcm_video_stop_streaming(struct vb2_queue *q)
1490 {
1491 struct npcm_video *video = vb2_get_drv_priv(q);
1492 struct regmap *vcd = video->vcd_regmap;
1493
1494 clear_bit(VIDEO_STREAMING, &video->flags);
1495 regmap_write(vcd, VCD_INTE, 0);
1496 regmap_write(vcd, VCD_STAT, VCD_STAT_CLEAR);
1497 npcm_video_gfx_reset(video);
1498 npcm_video_bufs_done(video, VB2_BUF_STATE_ERROR);
1499 video->ctrl_cmd = VCD_CMD_OPERATION_CAPTURE;
1500 v4l2_ctrl_s_ctrl(video->rect_cnt_ctrl, 0);
1501 }
1502
1503 static void npcm_video_buf_queue(struct vb2_buffer *vb)
1504 {
1505 struct npcm_video *video = vb2_get_drv_priv(vb->vb2_queue);
1506 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1507 struct npcm_video_buffer *nvb = to_npcm_video_buffer(vbuf);
1508 bool empty;
1509
1510 mutex_lock(&video->buffer_lock);
1511 empty = list_empty(&video->buffers);
1512 list_add_tail(&nvb->link, &video->buffers);
1513 mutex_unlock(&video->buffer_lock);
1514
1515 if (test_bit(VIDEO_STREAMING, &video->flags) &&
1516 !test_bit(VIDEO_CAPTURING, &video->flags) && empty) {
1517 if (npcm_video_start_frame(video))
1518 dev_err(video->dev, "Failed to capture next frame\n");
1519 }
1520 }
1521
1522 static void npcm_video_buf_finish(struct vb2_buffer *vb)
1523 {
1524 struct npcm_video *video = vb2_get_drv_priv(vb->vb2_queue);
1525 struct list_head *head, *pos, *nx;
1526 struct rect_list *tmp;
1527
1528 /*
1529 * This callback is called when the buffer is dequeued, so update
1530 * V4L2_CID_NPCM_RECT_COUNT control value with the number of rectangles
1531 * in this buffer and free associated rect_list.
1532 */
1533 if (test_bit(VIDEO_STREAMING, &video->flags)) {
1534 v4l2_ctrl_s_ctrl(video->rect_cnt_ctrl, video->rect[vb->index]);
1535
1536 head = &video->list[vb->index];
1537 list_for_each_safe(pos, nx, head) {
1538 tmp = list_entry(pos, struct rect_list, list);
1539 list_del(&tmp->list);
1540 kfree(tmp);
1541 }
1542 }
1543 }
1544
1545 static const struct regmap_config npcm_video_regmap_cfg = {
1546 .reg_bits = 32,
1547 .reg_stride = 4,
1548 .val_bits = 32,
1549 .max_register = VCD_FIFO,
1550 };
1551
1552 static const struct regmap_config npcm_video_ece_regmap_cfg = {
1553 .reg_bits = 32,
1554 .reg_stride = 4,
1555 .val_bits = 32,
1556 .max_register = ECE_HEX_RECT_OFFSET,
1557 };
1558
1559 static const struct vb2_ops npcm_video_vb2_ops = {
1560 .queue_setup = npcm_video_queue_setup,
1561 .buf_prepare = npcm_video_buf_prepare,
1562 .buf_finish = npcm_video_buf_finish,
1563 .start_streaming = npcm_video_start_streaming,
1564 .stop_streaming = npcm_video_stop_streaming,
1565 .buf_queue = npcm_video_buf_queue,
1566 };
1567
1568 static int npcm_video_setup_video(struct npcm_video *video)
1569 {
1570 struct v4l2_device *v4l2_dev = &video->v4l2_dev;
1571 struct video_device *vdev = &video->vdev;
1572 struct vb2_queue *vbq = &video->queue;
1573 int rc;
1574
1575 if (video->ece.enable)
1576 video->pix_fmt.pixelformat = V4L2_PIX_FMT_HEXTILE;
1577 else
1578 video->pix_fmt.pixelformat = V4L2_PIX_FMT_RGB565;
1579
1580 video->pix_fmt.field = V4L2_FIELD_NONE;
1581 video->pix_fmt.colorspace = V4L2_COLORSPACE_SRGB;
1582 video->pix_fmt.quantization = V4L2_QUANTIZATION_FULL_RANGE;
1583 video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL;
1584
1585 rc = v4l2_device_register(video->dev, v4l2_dev);
1586 if (rc) {
1587 dev_err(video->dev, "Failed to register v4l2 device\n");
1588 return rc;
1589 }
1590
1591 v4l2_ctrl_handler_init(&video->ctrl_handler, 2);
1592 v4l2_ctrl_new_custom(&video->ctrl_handler, &npcm_ctrl_capture_mode, NULL);
1593 video->rect_cnt_ctrl = v4l2_ctrl_new_custom(&video->ctrl_handler,
1594 &npcm_ctrl_rect_count, NULL);
1595 if (video->ctrl_handler.error) {
1596 dev_err(video->dev, "Failed to init controls: %d\n",
1597 video->ctrl_handler.error);
1598
1599 rc = video->ctrl_handler.error;
1600 goto rel_ctrl_handler;
1601 }
1602 v4l2_dev->ctrl_handler = &video->ctrl_handler;
1603
1604 vbq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1605 vbq->io_modes = VB2_MMAP | VB2_DMABUF;
1606 vbq->dev = v4l2_dev->dev;
1607 vbq->lock = &video->video_lock;
1608 vbq->ops = &npcm_video_vb2_ops;
1609 vbq->mem_ops = &vb2_dma_contig_memops;
1610 vbq->drv_priv = video;
1611 vbq->buf_struct_size = sizeof(struct npcm_video_buffer);
1612 vbq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1613 vbq->min_queued_buffers = 3;
1614
1615 rc = vb2_queue_init(vbq);
1616 if (rc) {
1617 dev_err(video->dev, "Failed to init vb2 queue\n");
1618 goto rel_ctrl_handler;
1619 }
1620 vdev->queue = vbq;
1621 vdev->fops = &npcm_video_v4l2_fops;
1622 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1623 vdev->v4l2_dev = v4l2_dev;
1624 strscpy(vdev->name, DEVICE_NAME, sizeof(vdev->name));
1625 vdev->vfl_type = VFL_TYPE_VIDEO;
1626 vdev->vfl_dir = VFL_DIR_RX;
1627 vdev->release = video_device_release_empty;
1628 vdev->ioctl_ops = &npcm_video_ioctls;
1629 vdev->lock = &video->video_lock;
1630
1631 video_set_drvdata(vdev, video);
1632 rc = video_register_device(vdev, VFL_TYPE_VIDEO, 0);
1633 if (rc) {
1634 dev_err(video->dev, "Failed to register video device\n");
1635 goto rel_vb_queue;
1636 }
1637
1638 return 0;
1639
1640 rel_vb_queue:
1641 vb2_queue_release(vbq);
1642 rel_ctrl_handler:
1643 v4l2_ctrl_handler_free(&video->ctrl_handler);
1644 v4l2_device_unregister(v4l2_dev);
1645
1646 return rc;
1647 }
1648
1649 static int npcm_video_ece_init(struct npcm_video *video)
1650 {
1651 struct device *dev = video->dev;
1652 struct device_node *ece_node;
1653 struct platform_device *ece_pdev;
1654 void __iomem *regs;
1655
1656 ece_node = of_parse_phandle(video->dev->of_node, "nuvoton,ece", 0);
1657 if (!ece_node) {
1658 dev_err(dev, "Failed to get ECE phandle in DTS\n");
1659 return -ENODEV;
1660 }
1661
1662 video->ece.enable = of_device_is_available(ece_node);
1663
1664 if (video->ece.enable) {
1665 dev_info(dev, "Support HEXTILE pixel format\n");
1666
1667 ece_pdev = of_find_device_by_node(ece_node);
1668 if (IS_ERR(ece_pdev)) {
1669 dev_err(dev, "Failed to find ECE device\n");
1670 return PTR_ERR(ece_pdev);
1671 }
1672 of_node_put(ece_node);
1673
1674 regs = devm_platform_ioremap_resource(ece_pdev, 0);
1675 if (IS_ERR(regs)) {
1676 dev_err(dev, "Failed to parse ECE reg in DTS\n");
1677 return PTR_ERR(regs);
1678 }
1679
1680 video->ece.regmap = devm_regmap_init_mmio(dev, regs,
1681 &npcm_video_ece_regmap_cfg);
1682 if (IS_ERR(video->ece.regmap)) {
1683 dev_err(dev, "Failed to initialize ECE regmap\n");
1684 return PTR_ERR(video->ece.regmap);
1685 }
1686
1687 video->ece.reset = devm_reset_control_get(&ece_pdev->dev, NULL);
1688 if (IS_ERR(video->ece.reset)) {
1689 dev_err(dev, "Failed to get ECE reset control in DTS\n");
1690 return PTR_ERR(video->ece.reset);
1691 }
1692 }
1693
1694 return 0;
1695 }
1696
1697 static int npcm_video_init(struct npcm_video *video)
1698 {
1699 struct device *dev = video->dev;
1700 int irq, rc;
1701
1702 irq = irq_of_parse_and_map(dev->of_node, 0);
1703 if (!irq) {
1704 dev_err(dev, "Failed to find VCD IRQ\n");
1705 return -ENODEV;
1706 }
1707
1708 rc = devm_request_threaded_irq(dev, irq, NULL, npcm_video_irq,
1709 IRQF_ONESHOT, DEVICE_NAME, video);
1710 if (rc < 0) {
1711 dev_err(dev, "Failed to request IRQ %d\n", irq);
1712 return rc;
1713 }
1714
1715 of_reserved_mem_device_init(dev);
1716 rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
1717 if (rc) {
1718 dev_err(dev, "Failed to set DMA mask\n");
1719 of_reserved_mem_device_release(dev);
1720 }
1721
1722 rc = npcm_video_ece_init(video);
1723 if (rc) {
1724 dev_err(dev, "Failed to initialize ECE\n");
1725 return rc;
1726 }
1727
1728 return 0;
1729 }
1730
1731 static int npcm_video_probe(struct platform_device *pdev)
1732 {
1733 struct npcm_video *video = kzalloc(sizeof(*video), GFP_KERNEL);
1734 int rc;
1735 void __iomem *regs;
1736
1737 if (!video)
1738 return -ENOMEM;
1739
1740 video->dev = &pdev->dev;
1741 mutex_init(&video->video_lock);
1742 mutex_init(&video->buffer_lock);
1743 INIT_LIST_HEAD(&video->buffers);
1744
1745 regs = devm_platform_ioremap_resource(pdev, 0);
1746 if (IS_ERR(regs)) {
1747 dev_err(&pdev->dev, "Failed to parse VCD reg in DTS\n");
1748 return PTR_ERR(regs);
1749 }
1750
1751 video->vcd_regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1752 &npcm_video_regmap_cfg);
1753 if (IS_ERR(video->vcd_regmap)) {
1754 dev_err(&pdev->dev, "Failed to initialize VCD regmap\n");
1755 return PTR_ERR(video->vcd_regmap);
1756 }
1757
1758 video->reset = devm_reset_control_get(&pdev->dev, NULL);
1759 if (IS_ERR(video->reset)) {
1760 dev_err(&pdev->dev, "Failed to get VCD reset control in DTS\n");
1761 return PTR_ERR(video->reset);
1762 }
1763
1764 video->gcr_regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1765 "nuvoton,sysgcr");
1766 if (IS_ERR(video->gcr_regmap))
1767 return PTR_ERR(video->gcr_regmap);
1768
1769 video->gfx_regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1770 "nuvoton,sysgfxi");
1771 if (IS_ERR(video->gfx_regmap))
1772 return PTR_ERR(video->gfx_regmap);
1773
1774 rc = npcm_video_init(video);
1775 if (rc)
1776 return rc;
1777
1778 rc = npcm_video_setup_video(video);
1779 if (rc)
1780 return rc;
1781
1782 dev_info(video->dev, "NPCM video driver probed\n");
1783 return 0;
1784 }
1785
1786 static void npcm_video_remove(struct platform_device *pdev)
1787 {
1788 struct device *dev = &pdev->dev;
1789 struct v4l2_device *v4l2_dev = dev_get_drvdata(dev);
1790 struct npcm_video *video = to_npcm_video(v4l2_dev);
1791
1792 video_unregister_device(&video->vdev);
1793 vb2_queue_release(&video->queue);
1794 v4l2_ctrl_handler_free(&video->ctrl_handler);
1795 v4l2_device_unregister(v4l2_dev);
1796 if (video->ece.enable)
1797 npcm_video_ece_stop(video);
1798 of_reserved_mem_device_release(dev);
1799 }
1800
1801 static const struct of_device_id npcm_video_match[] = {
1802 { .compatible = "nuvoton,npcm750-vcd" },
1803 { .compatible = "nuvoton,npcm845-vcd" },
1804 {},
1805 };
1806
1807 MODULE_DEVICE_TABLE(of, npcm_video_match);
1808
1809 static struct platform_driver npcm_video_driver = {
1810 .driver = {
1811 .name = DEVICE_NAME,
1812 .of_match_table = npcm_video_match,
1813 },
1814 .probe = npcm_video_probe,
1815 .remove = npcm_video_remove,
1816 };
1817
1818 module_platform_driver(npcm_video_driver);
1819
1820 MODULE_AUTHOR("Joseph Liu <kwliu@nuvoton.com>");
1821 MODULE_AUTHOR("Marvin Lin <kflin@nuvoton.com>");
1822 MODULE_DESCRIPTION("Driver for Nuvoton NPCM Video Capture/Encode Engine");
1823 MODULE_LICENSE("GPL v2");
Kernel DRM miscellaneous fixes and cross-tree changes