drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * camss-csiphy-3ph-1-0.c
   4  *
   5  * Qualcomm MSM Camera Subsystem - CSIPHY Module 3phase v1.0
   6  *
   7  * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
   8  * Copyright (C) 2016-2018 Linaro Ltd.
   9  */
  10
  11 #include "camss.h"
  12 #include "camss-csiphy.h"
  13
  14 #include <linux/delay.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17
  18 #define CSIPHY_3PH_LNn_CFG1(n)                  (0x000 + 0x100 * (n))
  19 #define CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG     (BIT(7) | BIT(6))
  20 #define CSIPHY_3PH_LNn_CFG2(n)                  (0x004 + 0x100 * (n))
  21 #define CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT       BIT(3)
  22 #define CSIPHY_3PH_LNn_CFG3(n)                  (0x008 + 0x100 * (n))
  23 #define CSIPHY_3PH_LNn_CFG4(n)                  (0x00c + 0x100 * (n))
  24 #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS       0xa4
  25 #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS_660   0xa5
  26 #define CSIPHY_3PH_LNn_CFG5(n)                  (0x010 + 0x100 * (n))
  27 #define CSIPHY_3PH_LNn_CFG5_T_HS_DTERM          0x02
  28 #define CSIPHY_3PH_LNn_CFG5_HS_REC_EQ_FQ_INT    0x50
  29 #define CSIPHY_3PH_LNn_TEST_IMP(n)              (0x01c + 0x100 * (n))
  30 #define CSIPHY_3PH_LNn_TEST_IMP_HS_TERM_IMP     0xa
  31 #define CSIPHY_3PH_LNn_MISC1(n)                 (0x028 + 0x100 * (n))
  32 #define CSIPHY_3PH_LNn_MISC1_IS_CLKLANE         BIT(2)
  33 #define CSIPHY_3PH_LNn_CFG6(n)                  (0x02c + 0x100 * (n))
  34 #define CSIPHY_3PH_LNn_CFG6_SWI_FORCE_INIT_EXIT BIT(0)
  35 #define CSIPHY_3PH_LNn_CFG7(n)                  (0x030 + 0x100 * (n))
  36 #define CSIPHY_3PH_LNn_CFG7_SWI_T_INIT          0x2
  37 #define CSIPHY_3PH_LNn_CFG8(n)                  (0x034 + 0x100 * (n))
  38 #define CSIPHY_3PH_LNn_CFG8_SWI_SKIP_WAKEUP     BIT(0)
  39 #define CSIPHY_3PH_LNn_CFG8_SKEW_FILTER_ENABLE  BIT(1)
  40 #define CSIPHY_3PH_LNn_CFG9(n)                  (0x038 + 0x100 * (n))
  41 #define CSIPHY_3PH_LNn_CFG9_SWI_T_WAKEUP        0x1
  42 #define CSIPHY_3PH_LNn_CSI_LANE_CTRL15(n)       (0x03c + 0x100 * (n))
  43 #define CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL   0xb8
  44
  45 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(n)      (0x800 + 0x4 * (n))
  46 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE      BIT(7)
  47 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B  BIT(0)
  48 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID     BIT(1)
  49 #define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(n)    (0x8b0 + 0x4 * (n))
  50
  51 #define CSIPHY_DEFAULT_PARAMS            0
  52 #define CSIPHY_LANE_ENABLE               1
  53 #define CSIPHY_SETTLE_CNT_LOWER_BYTE     2
  54 #define CSIPHY_SETTLE_CNT_HIGHER_BYTE    3
  55 #define CSIPHY_DNP_PARAMS                4
  56 #define CSIPHY_2PH_REGS                  5
  57 #define CSIPHY_3PH_REGS                  6
  58
  59 struct csiphy_reg_t {
  60         s32 reg_addr;
  61         s32 reg_data;
  62         s32 delay;
  63         u32 csiphy_param_type;
  64 };
  65
  66 /* GEN2 1.0 2PH */
  67 static const struct
  68 csiphy_reg_t lane_regs_sdm845[5][14] = {
  69         {
  70                 {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
  71                 {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
  72                 {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
  73                 {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
  74                 {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
  75                 {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
  76                 {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
  77                 {0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
  78                 {0x0008, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
  79                 {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
  80                 {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
  81                 {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
  82                 {0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
  83                 {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
  84         },
  85         {
  86                 {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
  87                 {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
  88                 {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
  89                 {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
  90                 {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
  91                 {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
  92                 {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
  93                 {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
  94                 {0x0708, 0x14, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
  95                 {0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
  96                 {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
  97                 {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
  98                 {0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
  99                 {0x0764, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
 100         },
 101         {
 102                 {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
 103                 {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 104                 {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
 105                 {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
 106                 {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
 107                 {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 108                 {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
 109                 {0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
 110                 {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
 111                 {0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 112                 {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
 113                 {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
 114                 {0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 115                 {0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
 116         },
 117         {
 118                 {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
 119                 {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 120                 {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
 121                 {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
 122                 {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
 123                 {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 124                 {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
 125                 {0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
 126                 {0x0408, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
 127                 {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 128                 {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
 129                 {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
 130                 {0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 131                 {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
 132         },
 133         {
 134                 {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
 135                 {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 136                 {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
 137                 {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
 138                 {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
 139                 {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 140                 {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
 141                 {0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
 142                 {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
 143                 {0x060C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 144                 {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
 145                 {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
 146                 {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 147                 {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
 148         },
 149 };
 150
 151 /* GEN2 1.1 2PH */
 152 static const struct
 153 csiphy_reg_t lane_regs_sc8280xp[5][14] = {
 154         {
 155                 {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
 156                 {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 157                 {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
 158                 {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
 159                 {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
 160                 {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 161                 {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
 162                 {0x0000, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS},
 163                 {0x0008, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
 164                 {0x000C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 165                 {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
 166                 {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
 167                 {0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 168                 {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
 169         },
 170         {
 171                 {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
 172                 {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 173                 {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
 174                 {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
 175                 {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
 176                 {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
 177                 {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
 178                 {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
 179                 {0x0708, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
 180                 {0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
 181                 {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
 182                 {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
 183                 {0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 184                 {0x0764, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
 185         },
 186         {
 187                 {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
 188                 {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 189                 {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
 190                 {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
 191                 {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
 192                 {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 193                 {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
 194                 {0x0200, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS},
 195                 {0x0208, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
 196                 {0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 197                 {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
 198                 {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
 199                 {0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 200                 {0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
 201         },
 202         {
 203                 {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
 204                 {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 205                 {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
 206                 {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
 207                 {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
 208                 {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 209                 {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
 210                 {0x0400, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS},
 211                 {0x0408, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
 212                 {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 213                 {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
 214                 {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
 215                 {0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 216                 {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
 217         },
 218         {
 219                 {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
 220                 {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 221                 {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
 222                 {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
 223                 {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
 224                 {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 225                 {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
 226                 {0x0600, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS},
 227                 {0x0608, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
 228                 {0x060C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 229                 {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
 230                 {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
 231                 {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 232                 {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
 233         },
 234 };
 235
 236 /* GEN2 1.2.1 2PH */
 237 static const struct
 238 csiphy_reg_t lane_regs_sm8250[5][20] = {
 239         {
 240                 {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 241                 {0x0900, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
 242                 {0x0908, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
 243                 {0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 244                 {0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
 245                 {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
 246                 {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 247                 {0x0034, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
 248                 {0x0010, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
 249                 {0x001C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
 250                 {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
 251                 {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
 252                 {0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
 253                 {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 254                 {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
 255                 {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
 256                 {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 257                 {0x0024, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 258                 {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
 259                 {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 260         },
 261         {
 262                 {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 263                 {0x0C80, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
 264                 {0x0C88, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
 265                 {0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 266                 {0x0C84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
 267                 {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
 268                 {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 269                 {0x0734, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
 270                 {0x0710, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
 271                 {0x071C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
 272                 {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
 273                 {0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
 274                 {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
 275                 {0x070c, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
 276                 {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
 277                 {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
 278                 {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
 279                 {0x0724, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 280                 {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
 281                 {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 282         },
 283         {
 284                 {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 285                 {0x0A00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
 286                 {0x0A08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
 287                 {0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 288                 {0x0A04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
 289                 {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
 290                 {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 291                 {0x0234, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
 292                 {0x0210, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
 293                 {0x021C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
 294                 {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
 295                 {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
 296                 {0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
 297                 {0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 298                 {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
 299                 {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
 300                 {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 301                 {0x0224, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 302                 {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
 303                 {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 304         },
 305         {
 306                 {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 307                 {0x0B00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
 308                 {0x0B08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
 309                 {0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 310                 {0x0B04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
 311                 {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
 312                 {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 313                 {0x0434, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
 314                 {0x0410, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
 315                 {0x041C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
 316                 {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
 317                 {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
 318                 {0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
 319                 {0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 320                 {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
 321                 {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
 322                 {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 323                 {0x0424, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 324                 {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
 325                 {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 326         },
 327         {
 328                 {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 329                 {0x0C00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
 330                 {0x0C08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
 331                 {0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 332                 {0x0C04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
 333                 {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
 334                 {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 335                 {0x0634, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
 336                 {0x0610, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
 337                 {0x061C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
 338                 {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
 339                 {0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
 340                 {0x0600, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
 341                 {0x060c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 342                 {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
 343                 {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
 344                 {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 345                 {0x0624, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 346                 {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
 347                 {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 348         },
 349 };
 350
 351 static void csiphy_hw_version_read(struct csiphy_device *csiphy,
 352                                    struct device *dev)
 353 {
 354         u32 hw_version;
 355
 356         writel(CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID,
 357                csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6));
 358
 359         hw_version = readl_relaxed(csiphy->base +
 360                                    CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(12));
 361         hw_version |= readl_relaxed(csiphy->base +
 362                                    CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(13)) << 8;
 363         hw_version |= readl_relaxed(csiphy->base +
 364                                    CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(14)) << 16;
 365         hw_version |= readl_relaxed(csiphy->base +
 366                                    CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(15)) << 24;
 367
 368         dev_dbg(dev, "CSIPHY 3PH HW Version = 0x%08x\n", hw_version);
 369 }
 370
 371 /*
 372  * csiphy_reset - Perform software reset on CSIPHY module
 373  * @csiphy: CSIPHY device
 374  */
 375 static void csiphy_reset(struct csiphy_device *csiphy)
 376 {
 377         writel_relaxed(0x1, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0));
 378         usleep_range(5000, 8000);
 379         writel_relaxed(0x0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0));
 380 }
 381
 382 static irqreturn_t csiphy_isr(int irq, void *dev)
 383 {
 384         struct csiphy_device *csiphy = dev;
 385         int i;
 386
 387         for (i = 0; i < 11; i++) {
 388                 int c = i + 22;
 389                 u8 val = readl_relaxed(csiphy->base +
 390                                        CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(i));
 391
 392                 writel_relaxed(val, csiphy->base +
 393                                     CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(c));
 394         }
 395
 396         writel_relaxed(0x1, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(10));
 397         writel_relaxed(0x0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(10));
 398
 399         for (i = 22; i < 33; i++)
 400                 writel_relaxed(0x0, csiphy->base +
 401                                     CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(i));
 402
 403         return IRQ_HANDLED;
 404 }
 405
 406 /*
 407  * csiphy_settle_cnt_calc - Calculate settle count value
 408  *
 409  * Helper function to calculate settle count value. This is
 410  * based on the CSI2 T_hs_settle parameter which in turn
 411  * is calculated based on the CSI2 transmitter link frequency.
 412  *
 413  * Return settle count value or 0 if the CSI2 link frequency
 414  * is not available
 415  */
 416 static u8 csiphy_settle_cnt_calc(s64 link_freq, u32 timer_clk_rate)
 417 {
 418         u32 ui; /* ps */
 419         u32 timer_period; /* ps */
 420         u32 t_hs_prepare_max; /* ps */
 421         u32 t_hs_settle; /* ps */
 422         u8 settle_cnt;
 423
 424         if (link_freq <= 0)
 425                 return 0;
 426
 427         ui = div_u64(1000000000000LL, link_freq);
 428         ui /= 2;
 429         t_hs_prepare_max = 85000 + 6 * ui;
 430         t_hs_settle = t_hs_prepare_max;
 431
 432         timer_period = div_u64(1000000000000LL, timer_clk_rate);
 433         settle_cnt = t_hs_settle / timer_period - 6;
 434
 435         return settle_cnt;
 436 }
 437
 438 static void csiphy_gen1_config_lanes(struct csiphy_device *csiphy,
 439                                      struct csiphy_config *cfg,
 440                                      u8 settle_cnt)
 441 {
 442         struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
 443         int i, l = 0;
 444         u8 val;
 445
 446         for (i = 0; i <= c->num_data; i++) {
 447                 if (i == c->num_data)
 448                         l = 7;
 449                 else
 450                         l = c->data[i].pos * 2;
 451
 452                 val = CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG;
 453                 val |= 0x17;
 454                 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l));
 455
 456                 val = CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT;
 457                 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG2(l));
 458
 459                 val = settle_cnt;
 460                 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG3(l));
 461
 462                 val = CSIPHY_3PH_LNn_CFG5_T_HS_DTERM |
 463                         CSIPHY_3PH_LNn_CFG5_HS_REC_EQ_FQ_INT;
 464                 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG5(l));
 465
 466                 val = CSIPHY_3PH_LNn_CFG6_SWI_FORCE_INIT_EXIT;
 467                 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG6(l));
 468
 469                 val = CSIPHY_3PH_LNn_CFG7_SWI_T_INIT;
 470                 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG7(l));
 471
 472                 val = CSIPHY_3PH_LNn_CFG8_SWI_SKIP_WAKEUP |
 473                         CSIPHY_3PH_LNn_CFG8_SKEW_FILTER_ENABLE;
 474                 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG8(l));
 475
 476                 val = CSIPHY_3PH_LNn_CFG9_SWI_T_WAKEUP;
 477                 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG9(l));
 478
 479                 val = CSIPHY_3PH_LNn_TEST_IMP_HS_TERM_IMP;
 480                 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_TEST_IMP(l));
 481
 482                 val = CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL;
 483                 writel_relaxed(val, csiphy->base +
 484                                     CSIPHY_3PH_LNn_CSI_LANE_CTRL15(l));
 485         }
 486
 487         val = CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG;
 488         writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l));
 489
 490         if (csiphy->camss->res->version == CAMSS_660)
 491                 val = CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS_660;
 492         else
 493                 val = CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS;
 494         writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG4(l));
 495
 496         val = CSIPHY_3PH_LNn_MISC1_IS_CLKLANE;
 497         writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_MISC1(l));
 498 }
 499
 500 static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy,
 501                                      u8 settle_cnt)
 502 {
 503         const struct csiphy_reg_t *r;
 504         int i, l, array_size;
 505         u32 val;
 506
 507         switch (csiphy->camss->res->version) {
 508         case CAMSS_845:
 509                 r = &lane_regs_sdm845[0][0];
 510                 array_size = ARRAY_SIZE(lane_regs_sdm845[0]);
 511                 break;
 512         case CAMSS_8250:
 513                 r = &lane_regs_sm8250[0][0];
 514                 array_size = ARRAY_SIZE(lane_regs_sm8250[0]);
 515                 break;
 516         case CAMSS_8280XP:
 517                 r = &lane_regs_sc8280xp[0][0];
 518                 array_size = ARRAY_SIZE(lane_regs_sc8280xp[0]);
 519                 break;
 520         default:
 521                 WARN(1, "unknown cspi version\n");
 522                 return;
 523         }
 524
 525         for (l = 0; l < 5; l++) {
 526                 for (i = 0; i < array_size; i++, r++) {
 527                         switch (r->csiphy_param_type) {
 528                         case CSIPHY_SETTLE_CNT_LOWER_BYTE:
 529                                 val = settle_cnt & 0xff;
 530                                 break;
 531                         case CSIPHY_DNP_PARAMS:
 532                                 continue;
 533                         default:
 534                                 val = r->reg_data;
 535                                 break;
 536                         }
 537                         writel_relaxed(val, csiphy->base + r->reg_addr);
 538                 }
 539         }
 540 }
 541
 542 static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg)
 543 {
 544         u8 lane_mask;
 545         int i;
 546
 547         lane_mask = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
 548
 549         for (i = 0; i < lane_cfg->num_data; i++)
 550                 lane_mask |= 1 << lane_cfg->data[i].pos;
 551
 552         return lane_mask;
 553 }
 554
 555 static bool csiphy_is_gen2(u32 version)
 556 {
 557         bool ret = false;
 558
 559         switch (version) {
 560         case CAMSS_845:
 561         case CAMSS_8250:
 562         case CAMSS_8280XP:
 563                 ret = true;
 564                 break;
 565         }
 566
 567         return ret;
 568 }
 569
 570 static void csiphy_lanes_enable(struct csiphy_device *csiphy,
 571                                 struct csiphy_config *cfg,
 572                                 s64 link_freq, u8 lane_mask)
 573 {
 574         struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
 575         u8 settle_cnt;
 576         u8 val;
 577         int i;
 578
 579         settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
 580
 581         val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
 582         for (i = 0; i < c->num_data; i++)
 583                 val |= BIT(c->data[i].pos * 2);
 584
 585         writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5));
 586
 587         val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B;
 588         writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6));
 589
 590         val = 0x02;
 591         writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(7));
 592
 593         val = 0x00;
 594         writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0));
 595
 596         if (csiphy_is_gen2(csiphy->camss->res->version))
 597                 csiphy_gen2_config_lanes(csiphy, settle_cnt);
 598         else
 599                 csiphy_gen1_config_lanes(csiphy, cfg, settle_cnt);
 600
 601         /* IRQ_MASK registers - disable all interrupts */
 602         for (i = 11; i < 22; i++)
 603                 writel_relaxed(0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(i));
 604 }
 605
 606 static void csiphy_lanes_disable(struct csiphy_device *csiphy,
 607                                  struct csiphy_config *cfg)
 608 {
 609         writel_relaxed(0, csiphy->base +
 610                           CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5));
 611
 612         writel_relaxed(0, csiphy->base +
 613                           CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6));
 614 }
 615
 616 const struct csiphy_hw_ops csiphy_ops_3ph_1_0 = {
 617         .get_lane_mask = csiphy_get_lane_mask,
 618         .hw_version_read = csiphy_hw_version_read,
 619         .reset = csiphy_reset,
 620         .lanes_enable = csiphy_lanes_enable,
 621         .lanes_disable = csiphy_lanes_disable,
 622         .isr = csiphy_isr,
 623 };