drivers/mmc/host/sdhci-acpi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Secure Digital Host Controller Interface ACPI driver.
   4  *
   5  * Copyright (c) 2012, Intel Corporation.
   6  */
   7
   8 #include <linux/bitfield.h>
   9 #include <linux/init.h>
  10 #include <linux/export.h>
  11 #include <linux/module.h>
  12 #include <linux/device.h>
  13 #include <linux/pinctrl/pinconf-generic.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/ioport.h>
  16 #include <linux/io.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/compiler.h>
  19 #include <linux/stddef.h>
  20 #include <linux/bitops.h>
  21 #include <linux/types.h>
  22 #include <linux/err.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/acpi.h>
  25 #include <linux/pm.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/delay.h>
  28 #include <linux/dmi.h>
  29
  30 #include <linux/mmc/host.h>
  31 #include <linux/mmc/pm.h>
  32 #include <linux/mmc/slot-gpio.h>
  33
  34 #ifdef CONFIG_X86
  35 #include <linux/platform_data/x86/soc.h>
  36 #include <asm/iosf_mbi.h>
  37 #endif
  38
  39 #include "sdhci.h"
  40
  41 enum {
  42         SDHCI_ACPI_SD_CD                = BIT(0),
  43         SDHCI_ACPI_RUNTIME_PM           = BIT(1),
  44         SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL = BIT(2),
  45 };
  46
  47 struct sdhci_acpi_chip {
  48         const struct    sdhci_ops *ops;
  49         unsigned int    quirks;
  50         unsigned int    quirks2;
  51         unsigned long   caps;
  52         unsigned int    caps2;
  53         mmc_pm_flag_t   pm_caps;
  54 };
  55
  56 struct sdhci_acpi_slot {
  57         const struct    sdhci_acpi_chip *chip;
  58         unsigned int    quirks;
  59         unsigned int    quirks2;
  60         unsigned long   caps;
  61         unsigned int    caps2;
  62         mmc_pm_flag_t   pm_caps;
  63         unsigned int    flags;
  64         size_t          priv_size;
  65         int (*probe_slot)(struct platform_device *, struct acpi_device *);
  66         int (*remove_slot)(struct platform_device *);
  67         int (*free_slot)(struct platform_device *pdev);
  68         int (*setup_host)(struct platform_device *pdev);
  69 };
  70
  71 struct sdhci_acpi_host {
  72         struct sdhci_host               *host;
  73         const struct sdhci_acpi_slot    *slot;
  74         struct platform_device          *pdev;
  75         bool                            use_runtime_pm;
  76         bool                            is_intel;
  77         bool                            reset_signal_volt_on_suspend;
  78         unsigned long                   private[] ____cacheline_aligned;
  79 };
  80
  81 enum {
  82         DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP                  = BIT(0),
  83         DMI_QUIRK_SD_NO_WRITE_PROTECT                           = BIT(1),
  84         DMI_QUIRK_SD_CD_ACTIVE_HIGH                             = BIT(2),
  85         DMI_QUIRK_SD_CD_ENABLE_PULL_UP                          = BIT(3),
  86 };
  87
  88 static inline void *sdhci_acpi_priv(struct sdhci_acpi_host *c)
  89 {
  90         return (void *)c->private;
  91 }
  92
  93 static inline bool sdhci_acpi_flag(struct sdhci_acpi_host *c, unsigned int flag)
  94 {
  95         return c->slot && (c->slot->flags & flag);
  96 }
  97
  98 #define INTEL_DSM_HS_CAPS_SDR25         BIT(0)
  99 #define INTEL_DSM_HS_CAPS_DDR50         BIT(1)
 100 #define INTEL_DSM_HS_CAPS_SDR50         BIT(2)
 101 #define INTEL_DSM_HS_CAPS_SDR104        BIT(3)
 102
 103 enum {
 104         INTEL_DSM_FNS           =  0,
 105         INTEL_DSM_V18_SWITCH    =  3,
 106         INTEL_DSM_V33_SWITCH    =  4,
 107         INTEL_DSM_HS_CAPS       =  8,
 108 };
 109
 110 struct intel_host {
 111         u32     dsm_fns;
 112         u32     hs_caps;
 113 };
 114
 115 static const guid_t intel_dsm_guid =
 116         GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
 117                   0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
 118
 119 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
 120                        unsigned int fn, u32 *result)
 121 {
 122         union acpi_object *obj;
 123         int err = 0;
 124
 125         obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
 126         if (!obj)
 127                 return -EOPNOTSUPP;
 128
 129         if (obj->type == ACPI_TYPE_INTEGER) {
 130                 *result = obj->integer.value;
 131         } else if (obj->type == ACPI_TYPE_BUFFER && obj->buffer.length > 0) {
 132                 size_t len = min_t(size_t, obj->buffer.length, 4);
 133
 134                 *result = 0;
 135                 memcpy(result, obj->buffer.pointer, len);
 136         } else {
 137                 dev_err(dev, "%s DSM fn %u obj->type %d obj->buffer.length %d\n",
 138                         __func__, fn, obj->type, obj->buffer.length);
 139                 err = -EINVAL;
 140         }
 141
 142         ACPI_FREE(obj);
 143
 144         return err;
 145 }
 146
 147 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
 148                      unsigned int fn, u32 *result)
 149 {
 150         if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
 151                 return -EOPNOTSUPP;
 152
 153         return __intel_dsm(intel_host, dev, fn, result);
 154 }
 155
 156 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
 157                            struct mmc_host *mmc)
 158 {
 159         int err;
 160
 161         intel_host->hs_caps = ~0;
 162
 163         err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
 164         if (err) {
 165                 pr_debug("%s: DSM not supported, error %d\n",
 166                          mmc_hostname(mmc), err);
 167                 return;
 168         }
 169
 170         pr_debug("%s: DSM function mask %#x\n",
 171                  mmc_hostname(mmc), intel_host->dsm_fns);
 172
 173         intel_dsm(intel_host, dev, INTEL_DSM_HS_CAPS, &intel_host->hs_caps);
 174 }
 175
 176 static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
 177                                              struct mmc_ios *ios)
 178 {
 179         struct device *dev = mmc_dev(mmc);
 180         struct sdhci_acpi_host *c = dev_get_drvdata(dev);
 181         struct intel_host *intel_host = sdhci_acpi_priv(c);
 182         unsigned int fn;
 183         u32 result = 0;
 184         int err;
 185
 186         err = sdhci_start_signal_voltage_switch(mmc, ios);
 187         if (err)
 188                 return err;
 189
 190         switch (ios->signal_voltage) {
 191         case MMC_SIGNAL_VOLTAGE_330:
 192                 fn = INTEL_DSM_V33_SWITCH;
 193                 break;
 194         case MMC_SIGNAL_VOLTAGE_180:
 195                 fn = INTEL_DSM_V18_SWITCH;
 196                 break;
 197         default:
 198                 return 0;
 199         }
 200
 201         err = intel_dsm(intel_host, dev, fn, &result);
 202         pr_debug("%s: %s DSM fn %u error %d result %u\n",
 203                  mmc_hostname(mmc), __func__, fn, err, result);
 204
 205         return 0;
 206 }
 207
 208 static void sdhci_acpi_int_hw_reset(struct sdhci_host *host)
 209 {
 210         u8 reg;
 211
 212         reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
 213         reg |= 0x10;
 214         sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
 215         /* For eMMC, minimum is 1us but give it 9us for good measure */
 216         udelay(9);
 217         reg &= ~0x10;
 218         sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
 219         /* For eMMC, minimum is 200us but give it 300us for good measure */
 220         usleep_range(300, 1000);
 221 }
 222
 223 static const struct sdhci_ops sdhci_acpi_ops_dflt = {
 224         .set_clock = sdhci_set_clock,
 225         .set_bus_width = sdhci_set_bus_width,
 226         .reset = sdhci_reset,
 227         .set_uhs_signaling = sdhci_set_uhs_signaling,
 228 };
 229
 230 static const struct sdhci_ops sdhci_acpi_ops_int = {
 231         .set_clock = sdhci_set_clock,
 232         .set_bus_width = sdhci_set_bus_width,
 233         .reset = sdhci_reset,
 234         .set_uhs_signaling = sdhci_set_uhs_signaling,
 235         .hw_reset   = sdhci_acpi_int_hw_reset,
 236 };
 237
 238 static const struct sdhci_acpi_chip sdhci_acpi_chip_int = {
 239         .ops = &sdhci_acpi_ops_int,
 240 };
 241
 242 #ifdef CONFIG_X86
 243
 244 #define BYT_IOSF_SCCEP                  0x63
 245 #define BYT_IOSF_OCP_NETCTRL0           0x1078
 246 #define BYT_IOSF_OCP_TIMEOUT_BASE       GENMASK(10, 8)
 247
 248 static void sdhci_acpi_byt_setting(struct device *dev)
 249 {
 250         u32 val = 0;
 251
 252         if (!soc_intel_is_byt())
 253                 return;
 254
 255         if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
 256                           &val)) {
 257                 dev_err(dev, "%s read error\n", __func__);
 258                 return;
 259         }
 260
 261         if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
 262                 return;
 263
 264         val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;
 265
 266         if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
 267                            val)) {
 268                 dev_err(dev, "%s write error\n", __func__);
 269                 return;
 270         }
 271
 272         dev_dbg(dev, "%s completed\n", __func__);
 273 }
 274
 275 static bool sdhci_acpi_byt_defer(struct device *dev)
 276 {
 277         if (!soc_intel_is_byt())
 278                 return false;
 279
 280         if (!iosf_mbi_available())
 281                 return true;
 282
 283         sdhci_acpi_byt_setting(dev);
 284
 285         return false;
 286 }
 287
 288 #else
 289
 290 static inline void sdhci_acpi_byt_setting(struct device *dev)
 291 {
 292 }
 293
 294 static inline bool sdhci_acpi_byt_defer(struct device *dev)
 295 {
 296         return false;
 297 }
 298
 299 #endif
 300
 301 static int bxt_get_cd(struct mmc_host *mmc)
 302 {
 303         int gpio_cd = mmc_gpio_get_cd(mmc);
 304
 305         if (!gpio_cd)
 306                 return 0;
 307
 308         return sdhci_get_cd_nogpio(mmc);
 309 }
 310
 311 static int intel_probe_slot(struct platform_device *pdev, struct acpi_device *adev)
 312 {
 313         struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
 314         struct intel_host *intel_host = sdhci_acpi_priv(c);
 315         struct sdhci_host *host = c->host;
 316
 317         if (acpi_dev_hid_uid_match(adev, "80860F14", "1") &&
 318             sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 &&
 319             sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807)
 320                 host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
 321
 322         if (acpi_dev_hid_uid_match(adev, "80865ACA", NULL))
 323                 host->mmc_host_ops.get_cd = bxt_get_cd;
 324
 325         intel_dsm_init(intel_host, &pdev->dev, host->mmc);
 326
 327         host->mmc_host_ops.start_signal_voltage_switch =
 328                                         intel_start_signal_voltage_switch;
 329
 330         c->is_intel = true;
 331
 332         return 0;
 333 }
 334
 335 static int intel_setup_host(struct platform_device *pdev)
 336 {
 337         struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
 338         struct intel_host *intel_host = sdhci_acpi_priv(c);
 339
 340         if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR25))
 341                 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR25;
 342
 343         if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR50))
 344                 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR50;
 345
 346         if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_DDR50))
 347                 c->host->mmc->caps &= ~MMC_CAP_UHS_DDR50;
 348
 349         if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR104))
 350                 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR104;
 351
 352         return 0;
 353 }
 354
 355 static const struct sdhci_acpi_slot sdhci_acpi_slot_int_emmc = {
 356         .chip    = &sdhci_acpi_chip_int,
 357         .caps    = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
 358                    MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
 359                    MMC_CAP_CMD_DURING_TFR | MMC_CAP_WAIT_WHILE_BUSY,
 360         .flags   = SDHCI_ACPI_RUNTIME_PM,
 361         .quirks  = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
 362                    SDHCI_QUIRK_NO_LED,
 363         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 364                    SDHCI_QUIRK2_STOP_WITH_TC |
 365                    SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400,
 366         .probe_slot     = intel_probe_slot,
 367         .setup_host     = intel_setup_host,
 368         .priv_size      = sizeof(struct intel_host),
 369 };
 370
 371 static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = {
 372         .quirks  = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 373                    SDHCI_QUIRK_NO_LED |
 374                    SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 375         .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
 376         .caps    = MMC_CAP_NONREMOVABLE | MMC_CAP_POWER_OFF_CARD |
 377                    MMC_CAP_WAIT_WHILE_BUSY,
 378         .flags   = SDHCI_ACPI_RUNTIME_PM,
 379         .pm_caps = MMC_PM_KEEP_POWER,
 380         .probe_slot     = intel_probe_slot,
 381         .setup_host     = intel_setup_host,
 382         .priv_size      = sizeof(struct intel_host),
 383 };
 384
 385 static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sd = {
 386         .flags   = SDHCI_ACPI_SD_CD | SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL |
 387                    SDHCI_ACPI_RUNTIME_PM,
 388         .quirks  = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
 389                    SDHCI_QUIRK_NO_LED,
 390         .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
 391                    SDHCI_QUIRK2_STOP_WITH_TC,
 392         .caps    = MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_AGGRESSIVE_PM,
 393         .probe_slot     = intel_probe_slot,
 394         .setup_host     = intel_setup_host,
 395         .priv_size      = sizeof(struct intel_host),
 396 };
 397
 398 #define VENDOR_SPECIFIC_PWRCTL_CLEAR_REG        0x1a8
 399 #define VENDOR_SPECIFIC_PWRCTL_CTL_REG          0x1ac
 400 static irqreturn_t sdhci_acpi_qcom_handler(int irq, void *ptr)
 401 {
 402         struct sdhci_host *host = ptr;
 403
 404         sdhci_writel(host, 0x3, VENDOR_SPECIFIC_PWRCTL_CLEAR_REG);
 405         sdhci_writel(host, 0x1, VENDOR_SPECIFIC_PWRCTL_CTL_REG);
 406
 407         return IRQ_HANDLED;
 408 }
 409
 410 static int qcom_probe_slot(struct platform_device *pdev, struct acpi_device *adev)
 411 {
 412         struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
 413         struct sdhci_host *host = c->host;
 414         int *irq = sdhci_acpi_priv(c);
 415
 416         *irq = -EINVAL;
 417
 418         if (!acpi_dev_hid_uid_match(adev, "QCOM8051", NULL))
 419                 return 0;
 420
 421         *irq = platform_get_irq(pdev, 1);
 422         if (*irq < 0)
 423                 return 0;
 424
 425         return request_threaded_irq(*irq, NULL, sdhci_acpi_qcom_handler,
 426                                     IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
 427                                     "sdhci_qcom", host);
 428 }
 429
 430 static int qcom_free_slot(struct platform_device *pdev)
 431 {
 432         struct device *dev = &pdev->dev;
 433         struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
 434         struct sdhci_host *host = c->host;
 435         struct acpi_device *adev;
 436         int *irq = sdhci_acpi_priv(c);
 437
 438         adev = ACPI_COMPANION(dev);
 439         if (!adev)
 440                 return -ENODEV;
 441
 442         if (!acpi_dev_hid_uid_match(adev, "QCOM8051", NULL))
 443                 return 0;
 444
 445         if (*irq < 0)
 446                 return 0;
 447
 448         free_irq(*irq, host);
 449         return 0;
 450 }
 451
 452 static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd_3v = {
 453         .quirks  = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
 454         .quirks2 = SDHCI_QUIRK2_NO_1_8_V,
 455         .caps    = MMC_CAP_NONREMOVABLE,
 456         .priv_size      = sizeof(int),
 457         .probe_slot     = qcom_probe_slot,
 458         .free_slot      = qcom_free_slot,
 459 };
 460
 461 static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd = {
 462         .quirks  = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
 463         .caps    = MMC_CAP_NONREMOVABLE,
 464 };
 465
 466 struct amd_sdhci_host {
 467         bool    tuned_clock;
 468         bool    dll_enabled;
 469 };
 470
 471 /* AMD sdhci reset dll register. */
 472 #define SDHCI_AMD_RESET_DLL_REGISTER    0x908
 473
 474 static int amd_select_drive_strength(struct mmc_card *card,
 475                                      unsigned int max_dtr, int host_drv,
 476                                      int card_drv, int *host_driver_strength)
 477 {
 478         struct sdhci_host *host = mmc_priv(card->host);
 479         u16 preset, preset_driver_strength;
 480
 481         /*
 482          * This method is only called by mmc_select_hs200 so we only need to
 483          * read from the HS200 (SDR104) preset register.
 484          *
 485          * Firmware that has "invalid/default" presets return a driver strength
 486          * of A. This matches the previously hard coded value.
 487          */
 488         preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
 489         preset_driver_strength = FIELD_GET(SDHCI_PRESET_DRV_MASK, preset);
 490
 491         /*
 492          * We want the controller driver strength to match the card's driver
 493          * strength so they have similar rise/fall times.
 494          *
 495          * The controller driver strength set by this method is sticky for all
 496          * timings after this method is called. This unfortunately means that
 497          * while HS400 tuning is in progress we end up with mismatched driver
 498          * strengths between the controller and the card. HS400 tuning requires
 499          * switching from HS400->DDR52->HS->HS200->HS400. So the driver mismatch
 500          * happens while in DDR52 and HS modes. This has not been observed to
 501          * cause problems. Enabling presets would fix this issue.
 502          */
 503         *host_driver_strength = preset_driver_strength;
 504
 505         /*
 506          * The resulting card driver strength is only set when switching the
 507          * card's timing to HS200 or HS400. The card will use the default driver
 508          * strength (B) for any other mode.
 509          */
 510         return preset_driver_strength;
 511 }
 512
 513 static void sdhci_acpi_amd_hs400_dll(struct sdhci_host *host, bool enable)
 514 {
 515         struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
 516         struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
 517
 518         /* AMD Platform requires dll setting */
 519         sdhci_writel(host, 0x40003210, SDHCI_AMD_RESET_DLL_REGISTER);
 520         usleep_range(10, 20);
 521         if (enable)
 522                 sdhci_writel(host, 0x40033210, SDHCI_AMD_RESET_DLL_REGISTER);
 523
 524         amd_host->dll_enabled = enable;
 525 }
 526
 527 /*
 528  * The initialization sequence for HS400 is:
 529  *     HS->HS200->Perform Tuning->HS->HS400
 530  *
 531  * The re-tuning sequence is:
 532  *     HS400->DDR52->HS->HS200->Perform Tuning->HS->HS400
 533  *
 534  * The AMD eMMC Controller can only use the tuned clock while in HS200 and HS400
 535  * mode. If we switch to a different mode, we need to disable the tuned clock.
 536  * If we have previously performed tuning and switch back to HS200 or
 537  * HS400, we can re-enable the tuned clock.
 538  *
 539  */
 540 static void amd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 541 {
 542         struct sdhci_host *host = mmc_priv(mmc);
 543         struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
 544         struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
 545         unsigned int old_timing = host->timing;
 546         u16 val;
 547
 548         sdhci_set_ios(mmc, ios);
 549
 550         if (old_timing != host->timing && amd_host->tuned_clock) {
 551                 if (host->timing == MMC_TIMING_MMC_HS400 ||
 552                     host->timing == MMC_TIMING_MMC_HS200) {
 553                         val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 554                         val |= SDHCI_CTRL_TUNED_CLK;
 555                         sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
 556                 } else {
 557                         val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 558                         val &= ~SDHCI_CTRL_TUNED_CLK;
 559                         sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
 560                 }
 561
 562                 /* DLL is only required for HS400 */
 563                 if (host->timing == MMC_TIMING_MMC_HS400 &&
 564                     !amd_host->dll_enabled)
 565                         sdhci_acpi_amd_hs400_dll(host, true);
 566         }
 567 }
 568
 569 static int amd_sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
 570 {
 571         int err;
 572         struct sdhci_host *host = mmc_priv(mmc);
 573         struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
 574         struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
 575
 576         amd_host->tuned_clock = false;
 577
 578         err = sdhci_execute_tuning(mmc, opcode);
 579
 580         if (!err && !host->tuning_err)
 581                 amd_host->tuned_clock = true;
 582
 583         return err;
 584 }
 585
 586 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask)
 587 {
 588         struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
 589         struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
 590
 591         if (mask & SDHCI_RESET_ALL) {
 592                 amd_host->tuned_clock = false;
 593                 sdhci_acpi_amd_hs400_dll(host, false);
 594         }
 595
 596         sdhci_reset(host, mask);
 597 }
 598
 599 static const struct sdhci_ops sdhci_acpi_ops_amd = {
 600         .set_clock      = sdhci_set_clock,
 601         .set_bus_width  = sdhci_set_bus_width,
 602         .reset          = amd_sdhci_reset,
 603         .set_uhs_signaling = sdhci_set_uhs_signaling,
 604 };
 605
 606 static const struct sdhci_acpi_chip sdhci_acpi_chip_amd = {
 607         .ops = &sdhci_acpi_ops_amd,
 608 };
 609
 610 static int sdhci_acpi_emmc_amd_probe_slot(struct platform_device *pdev,
 611                                           struct acpi_device *adev)
 612 {
 613         struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
 614         struct sdhci_host *host   = c->host;
 615
 616         sdhci_read_caps(host);
 617         if (host->caps1 & SDHCI_SUPPORT_DDR50)
 618                 host->mmc->caps = MMC_CAP_1_8V_DDR;
 619
 620         if ((host->caps1 & SDHCI_SUPPORT_SDR104) &&
 621             (host->mmc->caps & MMC_CAP_1_8V_DDR))
 622                 host->mmc->caps2 = MMC_CAP2_HS400_1_8V;
 623
 624         /*
 625          * There are two types of presets out in the wild:
 626          * 1) Default/broken presets.
 627          *    These presets have two sets of problems:
 628          *    a) The clock divisor for SDR12, SDR25, and SDR50 is too small.
 629          *       This results in clock frequencies that are 2x higher than
 630          *       acceptable. i.e., SDR12 = 25 MHz, SDR25 = 50 MHz, SDR50 =
 631          *       100 MHz.x
 632          *    b) The HS200 and HS400 driver strengths don't match.
 633          *       By default, the SDR104 preset register has a driver strength of
 634          *       A, but the (internal) HS400 preset register has a driver
 635          *       strength of B. As part of initializing HS400, HS200 tuning
 636          *       needs to be performed. Having different driver strengths
 637          *       between tuning and operation is wrong. It results in different
 638          *       rise/fall times that lead to incorrect sampling.
 639          * 2) Firmware with properly initialized presets.
 640          *    These presets have proper clock divisors. i.e., SDR12 => 12MHz,
 641          *    SDR25 => 25 MHz, SDR50 => 50 MHz. Additionally the HS200 and
 642          *    HS400 preset driver strengths match.
 643          *
 644          *    Enabling presets for HS400 doesn't work for the following reasons:
 645          *    1) sdhci_set_ios has a hard coded list of timings that are used
 646          *       to determine if presets should be enabled.
 647          *    2) sdhci_get_preset_value is using a non-standard register to
 648          *       read out HS400 presets. The AMD controller doesn't support this
 649          *       non-standard register. In fact, it doesn't expose the HS400
 650          *       preset register anywhere in the SDHCI memory map. This results
 651          *       in reading a garbage value and using the wrong presets.
 652          *
 653          *       Since HS400 and HS200 presets must be identical, we could
 654          *       instead use the SDR104 preset register.
 655          *
 656          *    If the above issues are resolved we could remove this quirk for
 657          *    firmware that has valid presets (i.e., SDR12 <= 12 MHz).
 658          */
 659         host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
 660
 661         host->mmc_host_ops.select_drive_strength = amd_select_drive_strength;
 662         host->mmc_host_ops.set_ios = amd_set_ios;
 663         host->mmc_host_ops.execute_tuning = amd_sdhci_execute_tuning;
 664         return 0;
 665 }
 666
 667 static const struct sdhci_acpi_slot sdhci_acpi_slot_amd_emmc = {
 668         .chip           = &sdhci_acpi_chip_amd,
 669         .caps           = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
 670         .quirks         = SDHCI_QUIRK_32BIT_DMA_ADDR |
 671                           SDHCI_QUIRK_32BIT_DMA_SIZE |
 672                           SDHCI_QUIRK_32BIT_ADMA_SIZE,
 673         .quirks2        = SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
 674         .probe_slot     = sdhci_acpi_emmc_amd_probe_slot,
 675         .priv_size      = sizeof(struct amd_sdhci_host),
 676 };
 677
 678 struct sdhci_acpi_uid_slot {
 679         const char *hid;
 680         const char *uid;
 681         const struct sdhci_acpi_slot *slot;
 682 };
 683
 684 static const struct sdhci_acpi_uid_slot sdhci_acpi_uids[] = {
 685         { "80865ACA", NULL, &sdhci_acpi_slot_int_sd },
 686         { "80865ACC", NULL, &sdhci_acpi_slot_int_emmc },
 687         { "80865AD0", NULL, &sdhci_acpi_slot_int_sdio },
 688         { "80860F14" , "1" , &sdhci_acpi_slot_int_emmc },
 689         { "80860F14" , "2" , &sdhci_acpi_slot_int_sdio },
 690         { "80860F14" , "3" , &sdhci_acpi_slot_int_sd   },
 691         { "80860F16" , NULL, &sdhci_acpi_slot_int_sd   },
 692         { "INT33BB"  , "2" , &sdhci_acpi_slot_int_sdio },
 693         { "INT33BB"  , "3" , &sdhci_acpi_slot_int_sd },
 694         { "INT33C6"  , NULL, &sdhci_acpi_slot_int_sdio },
 695         { "INT3436"  , NULL, &sdhci_acpi_slot_int_sdio },
 696         { "INT344D"  , NULL, &sdhci_acpi_slot_int_sdio },
 697         { "PNP0FFF"  , "3" , &sdhci_acpi_slot_int_sd   },
 698         { "PNP0D40"  },
 699         { "QCOM8051", NULL, &sdhci_acpi_slot_qcom_sd_3v },
 700         { "QCOM8052", NULL, &sdhci_acpi_slot_qcom_sd },
 701         { "AMDI0040", NULL, &sdhci_acpi_slot_amd_emmc },
 702         { "AMDI0041", NULL, &sdhci_acpi_slot_amd_emmc },
 703         { },
 704 };
 705
 706 static const struct acpi_device_id sdhci_acpi_ids[] = {
 707         { "80865ACA" },
 708         { "80865ACC" },
 709         { "80865AD0" },
 710         { "80860F14" },
 711         { "80860F16" },
 712         { "INT33BB"  },
 713         { "INT33C6"  },
 714         { "INT3436"  },
 715         { "INT344D"  },
 716         { "PNP0D40"  },
 717         { "QCOM8051" },
 718         { "QCOM8052" },
 719         { "AMDI0040" },
 720         { "AMDI0041" },
 721         { },
 722 };
 723 MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);
 724
 725 /* Please keep this list sorted alphabetically */
 726 static const struct dmi_system_id sdhci_acpi_quirks[] = {
 727         {
 728                 /*
 729                  * The Acer Aspire Switch 10 (SW5-012) microSD slot always
 730                  * reports the card being write-protected even though microSD
 731                  * cards do not have a write-protect switch at all.
 732                  */
 733                 .matches = {
 734                         DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
 735                         DMI_MATCH(DMI_PRODUCT_NAME, "Aspire SW5-012"),
 736                 },
 737                 .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT,
 738         },
 739         {
 740                 /* Asus T100TA, needs pull-up for cd but DSDT GpioInt has NoPull set */
 741                 .matches = {
 742                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
 743                         DMI_MATCH(DMI_PRODUCT_NAME, "T100TA"),
 744                 },
 745                 .driver_data = (void *)DMI_QUIRK_SD_CD_ENABLE_PULL_UP,
 746         },
 747         {
 748                 /*
 749                  * The Lenovo Miix 320-10ICR has a bug in the _PS0 method of
 750                  * the SHC1 ACPI device, this bug causes it to reprogram the
 751                  * wrong LDO (DLDO3) to 1.8V if 1.8V modes are used and the
 752                  * card is (runtime) suspended + resumed. DLDO3 is used for
 753                  * the LCD and setting it to 1.8V causes the LCD to go black.
 754                  */
 755                 .matches = {
 756                         DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
 757                         DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),
 758                 },
 759                 .driver_data = (void *)DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP,
 760         },
 761         {
 762                 /*
 763                  * Lenovo Yoga Tablet 2 Pro 1380F/L (13" Android version) this
 764                  * has broken WP reporting and an inverted CD signal.
 765                  * Note this has more or less the same BIOS as the Lenovo Yoga
 766                  * Tablet 2 830F/L or 1050F/L (8" and 10" Android), but unlike
 767                  * the 830 / 1050 models which share the same mainboard this
 768                  * model has a different mainboard and the inverted CD and
 769                  * broken WP are unique to this board.
 770                  */
 771                 .matches = {
 772                         DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp."),
 773                         DMI_MATCH(DMI_PRODUCT_NAME, "VALLEYVIEW C0 PLATFORM"),
 774                         DMI_MATCH(DMI_BOARD_NAME, "BYT-T FFD8"),
 775                         /* Full match so as to NOT match the 830/1050 BIOS */
 776                         DMI_MATCH(DMI_BIOS_VERSION, "BLADE_21.X64.0005.R00.1504101516"),
 777                 },
 778                 .driver_data = (void *)(DMI_QUIRK_SD_NO_WRITE_PROTECT |
 779                                         DMI_QUIRK_SD_CD_ACTIVE_HIGH),
 780         },
 781         {
 782                 /*
 783                  * The Toshiba WT8-B's microSD slot always reports the card being
 784                  * write-protected.
 785                  */
 786                 .matches = {
 787                         DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 788                         DMI_MATCH(DMI_PRODUCT_NAME, "TOSHIBA ENCORE 2 WT8-B"),
 789                 },
 790                 .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT,
 791         },
 792         {
 793                 /*
 794                  * The Toshiba WT10-A's microSD slot always reports the card being
 795                  * write-protected.
 796                  */
 797                 .matches = {
 798                         DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 799                         DMI_MATCH(DMI_PRODUCT_NAME, "TOSHIBA WT10-A"),
 800                 },
 801                 .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT,
 802         },
 803         {} /* Terminating entry */
 804 };
 805
 806 static const struct sdhci_acpi_slot *sdhci_acpi_get_slot(struct acpi_device *adev)
 807 {
 808         const struct sdhci_acpi_uid_slot *u;
 809
 810         for (u = sdhci_acpi_uids; u->hid; u++) {
 811                 if (acpi_dev_hid_uid_match(adev, u->hid, u->uid))
 812                         return u->slot;
 813         }
 814         return NULL;
 815 }
 816
 817 static int sdhci_acpi_probe(struct platform_device *pdev)
 818 {
 819         struct device *dev = &pdev->dev;
 820         const struct sdhci_acpi_slot *slot;
 821         const struct dmi_system_id *id;
 822         struct acpi_device *device;
 823         struct sdhci_acpi_host *c;
 824         struct sdhci_host *host;
 825         struct resource *iomem;
 826         resource_size_t len;
 827         size_t priv_size;
 828         int quirks = 0;
 829         int err;
 830
 831         device = ACPI_COMPANION(dev);
 832         if (!device)
 833                 return -ENODEV;
 834
 835         id = dmi_first_match(sdhci_acpi_quirks);
 836         if (id)
 837                 quirks = (long)id->driver_data;
 838
 839         slot = sdhci_acpi_get_slot(device);
 840
 841         /* Power on the SDHCI controller and its children */
 842         acpi_device_fix_up_power_extended(device);
 843
 844         if (sdhci_acpi_byt_defer(dev))
 845                 return -EPROBE_DEFER;
 846
 847         iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 848         if (!iomem)
 849                 return -ENOMEM;
 850
 851         len = resource_size(iomem);
 852         if (len < 0x100)
 853                 dev_err(dev, "Invalid iomem size!\n");
 854
 855         if (!devm_request_mem_region(dev, iomem->start, len, dev_name(dev)))
 856                 return -ENOMEM;
 857
 858         priv_size = slot ? slot->priv_size : 0;
 859         host = sdhci_alloc_host(dev, sizeof(struct sdhci_acpi_host) + priv_size);
 860         if (IS_ERR(host))
 861                 return PTR_ERR(host);
 862
 863         c = sdhci_priv(host);
 864         c->host = host;
 865         c->slot = slot;
 866         c->pdev = pdev;
 867         c->use_runtime_pm = sdhci_acpi_flag(c, SDHCI_ACPI_RUNTIME_PM);
 868
 869         platform_set_drvdata(pdev, c);
 870
 871         host->hw_name   = "ACPI";
 872         host->ops       = &sdhci_acpi_ops_dflt;
 873         host->irq       = platform_get_irq(pdev, 0);
 874         if (host->irq < 0) {
 875                 err = host->irq;
 876                 goto err_free;
 877         }
 878
 879         host->ioaddr = devm_ioremap(dev, iomem->start,
 880                                             resource_size(iomem));
 881         if (host->ioaddr == NULL) {
 882                 err = -ENOMEM;
 883                 goto err_free;
 884         }
 885
 886         if (c->slot) {
 887                 if (c->slot->probe_slot) {
 888                         err = c->slot->probe_slot(pdev, device);
 889                         if (err)
 890                                 goto err_free;
 891                 }
 892                 if (c->slot->chip) {
 893                         host->ops            = c->slot->chip->ops;
 894                         host->quirks        |= c->slot->chip->quirks;
 895                         host->quirks2       |= c->slot->chip->quirks2;
 896                         host->mmc->caps     |= c->slot->chip->caps;
 897                         host->mmc->caps2    |= c->slot->chip->caps2;
 898                         host->mmc->pm_caps  |= c->slot->chip->pm_caps;
 899                 }
 900                 host->quirks        |= c->slot->quirks;
 901                 host->quirks2       |= c->slot->quirks2;
 902                 host->mmc->caps     |= c->slot->caps;
 903                 host->mmc->caps2    |= c->slot->caps2;
 904                 host->mmc->pm_caps  |= c->slot->pm_caps;
 905         }
 906
 907         host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
 908
 909         if (sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD)) {
 910                 bool v = sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL);
 911
 912                 if (quirks & DMI_QUIRK_SD_CD_ACTIVE_HIGH)
 913                         host->mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
 914
 915                 err = mmc_gpiod_request_cd(host->mmc, NULL, 0, v, 0);
 916                 if (err) {
 917                         if (err == -EPROBE_DEFER)
 918                                 goto err_free;
 919                         dev_warn(dev, "failed to setup card detect gpio\n");
 920                         c->use_runtime_pm = false;
 921                 } else if (quirks & DMI_QUIRK_SD_CD_ENABLE_PULL_UP) {
 922                         mmc_gpiod_set_cd_config(host->mmc,
 923                                                 PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 20000));
 924                 }
 925
 926                 if (quirks & DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP)
 927                         c->reset_signal_volt_on_suspend = true;
 928
 929                 if (quirks & DMI_QUIRK_SD_NO_WRITE_PROTECT)
 930                         host->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
 931         }
 932
 933         err = sdhci_setup_host(host);
 934         if (err)
 935                 goto err_free;
 936
 937         if (c->slot && c->slot->setup_host) {
 938                 err = c->slot->setup_host(pdev);
 939                 if (err)
 940                         goto err_cleanup;
 941         }
 942
 943         err = __sdhci_add_host(host);
 944         if (err)
 945                 goto err_cleanup;
 946
 947         if (c->use_runtime_pm) {
 948                 pm_runtime_set_active(dev);
 949                 pm_suspend_ignore_children(dev, 1);
 950                 pm_runtime_set_autosuspend_delay(dev, 50);
 951                 pm_runtime_use_autosuspend(dev);
 952                 pm_runtime_enable(dev);
 953         }
 954
 955         device_enable_async_suspend(dev);
 956
 957         return 0;
 958
 959 err_cleanup:
 960         sdhci_cleanup_host(c->host);
 961 err_free:
 962         if (c->slot && c->slot->free_slot)
 963                 c->slot->free_slot(pdev);
 964
 965         sdhci_free_host(c->host);
 966         return err;
 967 }
 968
 969 static void sdhci_acpi_remove(struct platform_device *pdev)
 970 {
 971         struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
 972         struct device *dev = &pdev->dev;
 973         int dead;
 974
 975         if (c->use_runtime_pm) {
 976                 pm_runtime_get_sync(dev);
 977                 pm_runtime_disable(dev);
 978                 pm_runtime_put_noidle(dev);
 979         }
 980
 981         if (c->slot && c->slot->remove_slot)
 982                 c->slot->remove_slot(pdev);
 983
 984         dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0);
 985         sdhci_remove_host(c->host, dead);
 986
 987         if (c->slot && c->slot->free_slot)
 988                 c->slot->free_slot(pdev);
 989
 990         sdhci_free_host(c->host);
 991 }
 992
 993 static void __maybe_unused sdhci_acpi_reset_signal_voltage_if_needed(
 994         struct device *dev)
 995 {
 996         struct sdhci_acpi_host *c = dev_get_drvdata(dev);
 997         struct sdhci_host *host = c->host;
 998
 999         if (c->is_intel && c->reset_signal_volt_on_suspend &&
1000             host->mmc->ios.signal_voltage != MMC_SIGNAL_VOLTAGE_330) {
1001                 struct intel_host *intel_host = sdhci_acpi_priv(c);
1002                 unsigned int fn = INTEL_DSM_V33_SWITCH;
1003                 u32 result = 0;
1004
1005                 intel_dsm(intel_host, dev, fn, &result);
1006         }
1007 }
1008
1009 #ifdef CONFIG_PM_SLEEP
1010
1011 static int sdhci_acpi_suspend(struct device *dev)
1012 {
1013         struct sdhci_acpi_host *c = dev_get_drvdata(dev);
1014         struct sdhci_host *host = c->host;
1015         int ret;
1016
1017         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1018                 mmc_retune_needed(host->mmc);
1019
1020         ret = sdhci_suspend_host(host);
1021         if (ret)
1022                 return ret;
1023
1024         sdhci_acpi_reset_signal_voltage_if_needed(dev);
1025         return 0;
1026 }
1027
1028 static int sdhci_acpi_resume(struct device *dev)
1029 {
1030         struct sdhci_acpi_host *c = dev_get_drvdata(dev);
1031
1032         sdhci_acpi_byt_setting(&c->pdev->dev);
1033
1034         return sdhci_resume_host(c->host);
1035 }
1036
1037 #endif
1038
1039 #ifdef CONFIG_PM
1040
1041 static int sdhci_acpi_runtime_suspend(struct device *dev)
1042 {
1043         struct sdhci_acpi_host *c = dev_get_drvdata(dev);
1044         struct sdhci_host *host = c->host;
1045         int ret;
1046
1047         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1048                 mmc_retune_needed(host->mmc);
1049
1050         ret = sdhci_runtime_suspend_host(host);
1051         if (ret)
1052                 return ret;
1053
1054         sdhci_acpi_reset_signal_voltage_if_needed(dev);
1055         return 0;
1056 }
1057
1058 static int sdhci_acpi_runtime_resume(struct device *dev)
1059 {
1060         struct sdhci_acpi_host *c = dev_get_drvdata(dev);
1061
1062         sdhci_acpi_byt_setting(&c->pdev->dev);
1063
1064         return sdhci_runtime_resume_host(c->host, 0);
1065 }
1066
1067 #endif
1068
1069 static const struct dev_pm_ops sdhci_acpi_pm_ops = {
1070         SET_SYSTEM_SLEEP_PM_OPS(sdhci_acpi_suspend, sdhci_acpi_resume)
1071         SET_RUNTIME_PM_OPS(sdhci_acpi_runtime_suspend,
1072                         sdhci_acpi_runtime_resume, NULL)
1073 };
1074
1075 static struct platform_driver sdhci_acpi_driver = {
1076         .driver = {
1077                 .name                   = "sdhci-acpi",
1078                 .probe_type             = PROBE_PREFER_ASYNCHRONOUS,
1079                 .acpi_match_table       = sdhci_acpi_ids,
1080                 .pm                     = &sdhci_acpi_pm_ops,
1081         },
1082         .probe  = sdhci_acpi_probe,
1083         .remove = sdhci_acpi_remove,
1084 };
1085
1086 module_platform_driver(sdhci_acpi_driver);
1087
1088 MODULE_DESCRIPTION("Secure Digital Host Controller Interface ACPI driver");
1089 MODULE_AUTHOR("Adrian Hunter");
1090 MODULE_LICENSE("GPL v2");