drivers/mmc/host/sdhci-uhs2.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Header file for Host Controller UHS2 related registers.
   4  *
   5  *  Copyright (C) 2014 Intel Corp, All Rights Reserved.
   6  */
   7 #ifndef __SDHCI_UHS2_H
   8 #define __SDHCI_UHS2_H
   9
  10 #include <linux/bits.h>
  11
  12 /* SDHCI Category C registers : UHS2 usage */
  13
  14 #define  SDHCI_UHS2_CM_TRAN_RESP                0x10
  15 #define  SDHCI_UHS2_SD_TRAN_RESP                0x18
  16 #define  SDHCI_UHS2_SD_TRAN_RESP_1              0x1C
  17
  18 /* SDHCI Category B registers : UHS2 only */
  19
  20 #define SDHCI_UHS2_BLOCK_SIZE                   0x80
  21 #define  SDHCI_UHS2_MAKE_BLKSZ(dma, blksz)      ((((dma) & 0x7) << 12) | ((blksz) & 0xFFF))
  22
  23 #define SDHCI_UHS2_BLOCK_COUNT                  0x84
  24
  25 #define SDHCI_UHS2_CMD_PACKET                   0x88
  26 #define  SDHCI_UHS2_CMD_PACK_MAX_LEN            20
  27
  28 #define SDHCI_UHS2_TRANS_MODE                   0x9C
  29 #define  SDHCI_UHS2_TRNS_DMA                    BIT(0)
  30 #define  SDHCI_UHS2_TRNS_BLK_CNT_EN             BIT(1)
  31 #define  SDHCI_UHS2_TRNS_DATA_TRNS_WRT          BIT(4)
  32 #define  SDHCI_UHS2_TRNS_BLK_BYTE_MODE          BIT(5)
  33 #define  SDHCI_UHS2_TRNS_RES_R5                 BIT(6)
  34 #define  SDHCI_UHS2_TRNS_RES_ERR_CHECK_EN       BIT(7)
  35 #define  SDHCI_UHS2_TRNS_RES_INT_DIS            BIT(8)
  36 #define  SDHCI_UHS2_TRNS_WAIT_EBSY              BIT(14)
  37 #define  SDHCI_UHS2_TRNS_2L_HD                  BIT(15)
  38
  39 #define SDHCI_UHS2_CMD                          0x9E
  40 #define  SDHCI_UHS2_CMD_SUB_CMD                 BIT(2)
  41 #define  SDHCI_UHS2_CMD_DATA                    BIT(5)
  42 #define  SDHCI_UHS2_CMD_TRNS_ABORT              BIT(6)
  43 #define  SDHCI_UHS2_CMD_CMD12                   BIT(7)
  44 #define  SDHCI_UHS2_CMD_DORMANT                 GENMASK(7, 6)
  45 #define  SDHCI_UHS2_CMD_PACK_LEN_MASK           GENMASK(12, 8)
  46
  47 #define SDHCI_UHS2_RESPONSE                     0xA0
  48 #define  SDHCI_UHS2_RESPONSE_MAX_LEN            20
  49
  50 #define SDHCI_UHS2_MSG_SELECT                   0xB4
  51 #define SDHCI_UHS2_MSG_SELECT_CURR              0x0
  52 #define SDHCI_UHS2_MSG_SELECT_ONE               0x1
  53 #define SDHCI_UHS2_MSG_SELECT_TWO               0x2
  54 #define SDHCI_UHS2_MSG_SELECT_THREE             0x3
  55
  56 #define SDHCI_UHS2_MSG                          0xB8
  57
  58 #define SDHCI_UHS2_DEV_INT_STATUS               0xBC
  59
  60 #define SDHCI_UHS2_DEV_SELECT                   0xBE
  61 #define SDHCI_UHS2_DEV_SEL_MASK                 GENMASK(3, 0)
  62 #define SDHCI_UHS2_DEV_SEL_INT_MSG_EN           BIT(7)
  63
  64 #define SDHCI_UHS2_DEV_INT_CODE                 0xBF
  65
  66 #define SDHCI_UHS2_SW_RESET                     0xC0
  67 #define SDHCI_UHS2_SW_RESET_FULL                BIT(0)
  68 #define SDHCI_UHS2_SW_RESET_SD                  BIT(1)
  69
  70 #define SDHCI_UHS2_TIMER_CTRL                   0xC2
  71 #define SDHCI_UHS2_TIMER_CTRL_DEADLOCK_MASK     GENMASK(7, 4)
  72
  73 #define SDHCI_UHS2_INT_STATUS                   0xC4
  74 #define SDHCI_UHS2_INT_STATUS_ENABLE            0xC8
  75 #define SDHCI_UHS2_INT_SIGNAL_ENABLE            0xCC
  76 #define SDHCI_UHS2_INT_HEADER_ERR               BIT(0)
  77 #define SDHCI_UHS2_INT_RES_ERR                  BIT(1)
  78 #define SDHCI_UHS2_INT_RETRY_EXP                BIT(2)
  79 #define SDHCI_UHS2_INT_CRC                      BIT(3)
  80 #define SDHCI_UHS2_INT_FRAME_ERR                BIT(4)
  81 #define SDHCI_UHS2_INT_TID_ERR                  BIT(5)
  82 #define SDHCI_UHS2_INT_UNRECOVER                BIT(7)
  83 #define SDHCI_UHS2_INT_EBUSY_ERR                BIT(8)
  84 #define SDHCI_UHS2_INT_ADMA_ERROR               BIT(15)
  85 #define SDHCI_UHS2_INT_CMD_TIMEOUT              BIT(16)
  86 #define SDHCI_UHS2_INT_DEADLOCK_TIMEOUT         BIT(17)
  87 #define SDHCI_UHS2_INT_VENDOR_ERR               BIT(27)
  88 #define SDHCI_UHS2_INT_ERROR_MASK              ( \
  89                 SDHCI_UHS2_INT_HEADER_ERR      | \
  90                 SDHCI_UHS2_INT_RES_ERR         | \
  91                 SDHCI_UHS2_INT_RETRY_EXP       | \
  92                 SDHCI_UHS2_INT_CRC             | \
  93                 SDHCI_UHS2_INT_FRAME_ERR       | \
  94                 SDHCI_UHS2_INT_TID_ERR         | \
  95                 SDHCI_UHS2_INT_UNRECOVER       | \
  96                 SDHCI_UHS2_INT_EBUSY_ERR       | \
  97                 SDHCI_UHS2_INT_ADMA_ERROR      | \
  98                 SDHCI_UHS2_INT_CMD_TIMEOUT     | \
  99                 SDHCI_UHS2_INT_DEADLOCK_TIMEOUT)
 100 #define SDHCI_UHS2_INT_CMD_ERR_MASK       ( \
 101                 SDHCI_UHS2_INT_HEADER_ERR | \
 102                 SDHCI_UHS2_INT_RES_ERR    | \
 103                 SDHCI_UHS2_INT_FRAME_ERR  | \
 104                 SDHCI_UHS2_INT_TID_ERR    | \
 105                 SDHCI_UHS2_INT_CMD_TIMEOUT)
 106 /* CRC Error occurs during a packet receiving */
 107 #define SDHCI_UHS2_INT_DATA_ERR_MASK           ( \
 108                 SDHCI_UHS2_INT_RETRY_EXP       | \
 109                 SDHCI_UHS2_INT_CRC             | \
 110                 SDHCI_UHS2_INT_UNRECOVER       | \
 111                 SDHCI_UHS2_INT_EBUSY_ERR       | \
 112                 SDHCI_UHS2_INT_ADMA_ERROR      | \
 113                 SDHCI_UHS2_INT_DEADLOCK_TIMEOUT)
 114
 115 #define SDHCI_UHS2_SETTINGS_PTR                 0xE0
 116 #define   SDHCI_UHS2_GEN_SETTINGS_POWER_LOW     BIT(0)
 117 #define   SDHCI_UHS2_GEN_SETTINGS_N_LANES_MASK  GENMASK(11, 8)
 118 #define   SDHCI_UHS2_FD_OR_2L_HD                0x0 /* 2 lanes */
 119 #define   SDHCI_UHS2_2D1U_FD                    0x2 /* 3 lanes, 2 down, 1 up, full duplex */
 120 #define   SDHCI_UHS2_1D2U_FD                    0x3 /* 3 lanes, 1 down, 2 up, full duplex */
 121 #define   SDHCI_UHS2_2D2U_FD                    0x4 /* 4 lanes, 2 down, 2 up, full duplex */
 122
 123 #define   SDHCI_UHS2_PHY_SET_SPEED_B            BIT(6)
 124 #define   SDHCI_UHS2_PHY_HIBERNATE_EN           BIT(12)
 125 #define   SDHCI_UHS2_PHY_N_LSS_SYN_MASK         GENMASK(19, 16)
 126 #define   SDHCI_UHS2_PHY_N_LSS_DIR_MASK         GENMASK(23, 20)
 127
 128 #define   SDHCI_UHS2_TRAN_N_FCU_MASK            GENMASK(15, 8)
 129 #define   SDHCI_UHS2_TRAN_RETRY_CNT_MASK        GENMASK(17, 16)
 130 #define   SDHCI_UHS2_TRAN_1_N_DAT_GAP_MASK      GENMASK(7, 0)
 131
 132 #define SDHCI_UHS2_CAPS_PTR                     0xE2
 133 #define   SDHCI_UHS2_CAPS_OFFSET                0
 134 #define   SDHCI_UHS2_CAPS_DAP_MASK              GENMASK(3, 0)
 135 #define   SDHCI_UHS2_CAPS_GAP_MASK              GENMASK(7, 4)
 136 #define   SDHCI_UHS2_CAPS_GAP(gap)              ((gap) * 360)
 137 #define   SDHCI_UHS2_CAPS_LANE_MASK             GENMASK(13, 8)
 138 #define   SDHCI_UHS2_CAPS_2L_HD_FD              1
 139 #define   SDHCI_UHS2_CAPS_2D1U_FD               2
 140 #define   SDHCI_UHS2_CAPS_1D2U_FD               4
 141 #define   SDHCI_UHS2_CAPS_2D2U_FD               8
 142 #define   SDHCI_UHS2_CAPS_ADDR_64               BIT(14)
 143 #define   SDHCI_UHS2_CAPS_BOOT                  BIT(15)
 144 #define   SDHCI_UHS2_CAPS_DEV_TYPE_MASK         GENMASK(17, 16)
 145 #define   SDHCI_UHS2_CAPS_DEV_TYPE_RMV          0
 146 #define   SDHCI_UHS2_CAPS_DEV_TYPE_EMB          1
 147 #define   SDHCI_UHS2_CAPS_DEV_TYPE_EMB_RMV      2
 148 #define   SDHCI_UHS2_CAPS_NUM_DEV_MASK          GENMASK(21, 18)
 149 #define   SDHCI_UHS2_CAPS_BUS_TOPO_MASK         GENMASK(23, 22)
 150 #define   SDHCI_UHS2_CAPS_BUS_TOPO_SHIFT        22
 151 #define   SDHCI_UHS2_CAPS_BUS_TOPO_P2P          0
 152 #define   SDHCI_UHS2_CAPS_BUS_TOPO_RING         1
 153 #define   SDHCI_UHS2_CAPS_BUS_TOPO_HUB          2
 154 #define   SDHCI_UHS2_CAPS_BUS_TOPO_HUB_RING     3
 155
 156 #define  SDHCI_UHS2_CAPS_PHY_OFFSET             4
 157 #define   SDHCI_UHS2_CAPS_PHY_REV_MASK          GENMASK(5, 0)
 158 #define   SDHCI_UHS2_CAPS_PHY_RANGE_MASK        GENMASK(7, 6)
 159 #define   SDHCI_UHS2_CAPS_PHY_RANGE_A           0
 160 #define   SDHCI_UHS2_CAPS_PHY_RANGE_B           1
 161 #define   SDHCI_UHS2_CAPS_PHY_N_LSS_SYN_MASK    GENMASK(19, 16)
 162 #define   SDHCI_UHS2_CAPS_PHY_N_LSS_DIR_MASK    GENMASK(23, 20)
 163 #define  SDHCI_UHS2_CAPS_TRAN_OFFSET            8
 164 #define   SDHCI_UHS2_CAPS_TRAN_LINK_REV_MASK    GENMASK(5, 0)
 165 #define   SDHCI_UHS2_CAPS_TRAN_N_FCU_MASK       GENMASK(15, 8)
 166 #define   SDHCI_UHS2_CAPS_TRAN_HOST_TYPE_MASK   GENMASK(18, 16)
 167 #define   SDHCI_UHS2_CAPS_TRAN_BLK_LEN_MASK     GENMASK(31, 20)
 168
 169 #define  SDHCI_UHS2_CAPS_TRAN_1_OFFSET          12
 170 #define  SDHCI_UHS2_CAPS_TRAN_1_N_DATA_GAP_MASK GENMASK(7, 0)
 171
 172 #define SDHCI_UHS2_EMBED_CTRL_PTR               0xE6
 173 #define SDHCI_UHS2_VENDOR_PTR                   0xE8
 174
 175 struct sdhci_host;
 176 struct mmc_command;
 177 struct mmc_request;
 178
 179 void sdhci_uhs2_dump_regs(struct sdhci_host *host);
 180 void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask);
 181 void sdhci_uhs2_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd);
 182 void sdhci_uhs2_set_timeout(struct sdhci_host *host, struct mmc_command *cmd);
 183 int sdhci_uhs2_add_host(struct sdhci_host *host);
 184 void sdhci_uhs2_remove_host(struct sdhci_host *host, int dead);
 185 void sdhci_uhs2_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set);
 186 u32 sdhci_uhs2_irq(struct sdhci_host *host, u32 intmask);
 187
 188 #endif /* __SDHCI_UHS2_H */