drivers/net/ethernet/chelsio/cxgb/elmer0.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*****************************************************************************
   3  *                                                                           *
   4  * File: elmer0.h                                                            *
   5  * $Revision: 1.6 $                                                          *
   6  * $Date: 2005/06/21 22:49:43 $                                              *
   7  * Description:                                                              *
   8  *  part of the Chelsio 10Gb Ethernet Driver.                                *
   9  *                                                                           *
  10  *                                                                           *
  11  * http://www.chelsio.com                                                    *
  12  *                                                                           *
  13  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
  14  * All rights reserved.                                                      *
  15  *                                                                           *
  16  * Maintainers: maintainers@chelsio.com                                      *
  17  *                                                                           *
  18  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
  19  *          Tina Yang               <tainay@chelsio.com>                     *
  20  *          Felix Marti             <felix@chelsio.com>                      *
  21  *          Scott Bardone           <sbardone@chelsio.com>                   *
  22  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
  23  *          Frank DiMambro          <frank@chelsio.com>                      *
  24  *                                                                           *
  25  * History:                                                                  *
  26  *                                                                           *
  27  ****************************************************************************/
  28
  29 #ifndef _CXGB_ELMER0_H_
  30 #define _CXGB_ELMER0_H_
  31
  32 /* ELMER0 flavors */
  33 enum {
  34         ELMER0_XC2S300E_6FT256_C,
  35         ELMER0_XC2S100E_6TQ144_C
  36 };
  37
  38 /* ELMER0 registers */
  39 #define A_ELMER0_VERSION        0x100000
  40 #define A_ELMER0_PHY_CFG        0x100004
  41 #define A_ELMER0_INT_ENABLE     0x100008
  42 #define A_ELMER0_INT_CAUSE      0x10000c
  43 #define A_ELMER0_GPI_CFG        0x100010
  44 #define A_ELMER0_GPI_STAT       0x100014
  45 #define A_ELMER0_GPO            0x100018
  46 #define A_ELMER0_PORT0_MI1_CFG  0x400000
  47
  48 #define S_MI1_MDI_ENABLE    0
  49 #define V_MI1_MDI_ENABLE(x) ((x) << S_MI1_MDI_ENABLE)
  50 #define F_MI1_MDI_ENABLE    V_MI1_MDI_ENABLE(1U)
  51
  52 #define S_MI1_MDI_INVERT    1
  53 #define V_MI1_MDI_INVERT(x) ((x) << S_MI1_MDI_INVERT)
  54 #define F_MI1_MDI_INVERT    V_MI1_MDI_INVERT(1U)
  55
  56 #define S_MI1_PREAMBLE_ENABLE    2
  57 #define V_MI1_PREAMBLE_ENABLE(x) ((x) << S_MI1_PREAMBLE_ENABLE)
  58 #define F_MI1_PREAMBLE_ENABLE    V_MI1_PREAMBLE_ENABLE(1U)
  59
  60 #define S_MI1_SOF    3
  61 #define M_MI1_SOF    0x3
  62 #define V_MI1_SOF(x) ((x) << S_MI1_SOF)
  63 #define G_MI1_SOF(x) (((x) >> S_MI1_SOF) & M_MI1_SOF)
  64
  65 #define S_MI1_CLK_DIV    5
  66 #define M_MI1_CLK_DIV    0xff
  67 #define V_MI1_CLK_DIV(x) ((x) << S_MI1_CLK_DIV)
  68 #define G_MI1_CLK_DIV(x) (((x) >> S_MI1_CLK_DIV) & M_MI1_CLK_DIV)
  69
  70 #define A_ELMER0_PORT0_MI1_ADDR 0x400004
  71
  72 #define S_MI1_REG_ADDR    0
  73 #define M_MI1_REG_ADDR    0x1f
  74 #define V_MI1_REG_ADDR(x) ((x) << S_MI1_REG_ADDR)
  75 #define G_MI1_REG_ADDR(x) (((x) >> S_MI1_REG_ADDR) & M_MI1_REG_ADDR)
  76
  77 #define S_MI1_PHY_ADDR    5
  78 #define M_MI1_PHY_ADDR    0x1f
  79 #define V_MI1_PHY_ADDR(x) ((x) << S_MI1_PHY_ADDR)
  80 #define G_MI1_PHY_ADDR(x) (((x) >> S_MI1_PHY_ADDR) & M_MI1_PHY_ADDR)
  81
  82 #define A_ELMER0_PORT0_MI1_DATA 0x400008
  83
  84 #define S_MI1_DATA    0
  85 #define M_MI1_DATA    0xffff
  86 #define V_MI1_DATA(x) ((x) << S_MI1_DATA)
  87 #define G_MI1_DATA(x) (((x) >> S_MI1_DATA) & M_MI1_DATA)
  88
  89 #define A_ELMER0_PORT0_MI1_OP 0x40000c
  90
  91 #define S_MI1_OP    0
  92 #define M_MI1_OP    0x3
  93 #define V_MI1_OP(x) ((x) << S_MI1_OP)
  94 #define G_MI1_OP(x) (((x) >> S_MI1_OP) & M_MI1_OP)
  95
  96 #define S_MI1_ADDR_AUTOINC    2
  97 #define V_MI1_ADDR_AUTOINC(x) ((x) << S_MI1_ADDR_AUTOINC)
  98 #define F_MI1_ADDR_AUTOINC    V_MI1_ADDR_AUTOINC(1U)
  99
 100 #define S_MI1_OP_BUSY    31
 101 #define V_MI1_OP_BUSY(x) ((x) << S_MI1_OP_BUSY)
 102 #define F_MI1_OP_BUSY    V_MI1_OP_BUSY(1U)
 103
 104 #define A_ELMER0_PORT1_MI1_CFG  0x500000
 105 #define A_ELMER0_PORT1_MI1_ADDR 0x500004
 106 #define A_ELMER0_PORT1_MI1_DATA 0x500008
 107 #define A_ELMER0_PORT1_MI1_OP   0x50000c
 108 #define A_ELMER0_PORT2_MI1_CFG  0x600000
 109 #define A_ELMER0_PORT2_MI1_ADDR 0x600004
 110 #define A_ELMER0_PORT2_MI1_DATA 0x600008
 111 #define A_ELMER0_PORT2_MI1_OP   0x60000c
 112 #define A_ELMER0_PORT3_MI1_CFG  0x700000
 113 #define A_ELMER0_PORT3_MI1_ADDR 0x700004
 114 #define A_ELMER0_PORT3_MI1_DATA 0x700008
 115 #define A_ELMER0_PORT3_MI1_OP   0x70000c
 116
 117 /* Simple bit definition for GPI and GP0 registers. */
 118 #define     ELMER0_GP_BIT0              0x0001
 119 #define     ELMER0_GP_BIT1              0x0002
 120 #define     ELMER0_GP_BIT2              0x0004
 121 #define     ELMER0_GP_BIT3              0x0008
 122 #define     ELMER0_GP_BIT4              0x0010
 123 #define     ELMER0_GP_BIT5              0x0020
 124 #define     ELMER0_GP_BIT6              0x0040
 125 #define     ELMER0_GP_BIT7              0x0080
 126 #define     ELMER0_GP_BIT8              0x0100
 127 #define     ELMER0_GP_BIT9              0x0200
 128 #define     ELMER0_GP_BIT10             0x0400
 129 #define     ELMER0_GP_BIT11             0x0800
 130 #define     ELMER0_GP_BIT12             0x1000
 131 #define     ELMER0_GP_BIT13             0x2000
 132 #define     ELMER0_GP_BIT14             0x4000
 133 #define     ELMER0_GP_BIT15             0x8000
 134 #define     ELMER0_GP_BIT16             0x10000
 135 #define     ELMER0_GP_BIT17             0x20000
 136 #define     ELMER0_GP_BIT18             0x40000
 137 #define     ELMER0_GP_BIT19             0x80000
 138
 139 #define MI1_OP_DIRECT_WRITE 1
 140 #define MI1_OP_DIRECT_READ  2
 141
 142 #define MI1_OP_INDIRECT_ADDRESS  0
 143 #define MI1_OP_INDIRECT_WRITE    1
 144 #define MI1_OP_INDIRECT_READ_INC 2
 145 #define MI1_OP_INDIRECT_READ     3
 146
 147 #endif /* _CXGB_ELMER0_H_ */