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Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / net / ethernet / intel / i40e / i40e_lan_hmc.c
blobbeaaf5c309d510a6b5a01fd1f220965850f9102e
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
3
4 #include "i40e_alloc.h"
5 #include "i40e_debug.h"
6 #include "i40e_lan_hmc.h"
7 #include "i40e_type.h"
8
9 /* lan specific interface functions */
10
11 /**
12 * i40e_align_l2obj_base - aligns base object pointer to 512 bytes
13 * @offset: base address offset needing alignment
14 *
15 * Aligns the layer 2 function private memory so it's 512-byte aligned.
16 **/
17 static u64 i40e_align_l2obj_base(u64 offset)
18 {
19 u64 aligned_offset = offset;
20
21 if ((offset % I40E_HMC_L2OBJ_BASE_ALIGNMENT) > 0)
22 aligned_offset += (I40E_HMC_L2OBJ_BASE_ALIGNMENT -
23 (offset % I40E_HMC_L2OBJ_BASE_ALIGNMENT));
24
25 return aligned_offset;
26 }
27
28 /**
29 * i40e_calculate_l2fpm_size - calculates layer 2 FPM memory size
30 * @txq_num: number of Tx queues needing backing context
31 * @rxq_num: number of Rx queues needing backing context
32 * @fcoe_cntx_num: amount of FCoE statefull contexts needing backing context
33 * @fcoe_filt_num: number of FCoE filters needing backing context
34 *
35 * Calculates the maximum amount of memory for the function required, based
36 * on the number of resources it must provide context for.
37 **/
38 static u64 i40e_calculate_l2fpm_size(u32 txq_num, u32 rxq_num,
39 u32 fcoe_cntx_num, u32 fcoe_filt_num)
40 {
41 u64 fpm_size = 0;
42
43 fpm_size = txq_num * I40E_HMC_OBJ_SIZE_TXQ;
44 fpm_size = i40e_align_l2obj_base(fpm_size);
45
46 fpm_size += (rxq_num * I40E_HMC_OBJ_SIZE_RXQ);
47 fpm_size = i40e_align_l2obj_base(fpm_size);
48
49 fpm_size += (fcoe_cntx_num * I40E_HMC_OBJ_SIZE_FCOE_CNTX);
50 fpm_size = i40e_align_l2obj_base(fpm_size);
51
52 fpm_size += (fcoe_filt_num * I40E_HMC_OBJ_SIZE_FCOE_FILT);
53 fpm_size = i40e_align_l2obj_base(fpm_size);
54
55 return fpm_size;
56 }
57
58 /**
59 * i40e_init_lan_hmc - initialize i40e_hmc_info struct
60 * @hw: pointer to the HW structure
61 * @txq_num: number of Tx queues needing backing context
62 * @rxq_num: number of Rx queues needing backing context
63 * @fcoe_cntx_num: amount of FCoE statefull contexts needing backing context
64 * @fcoe_filt_num: number of FCoE filters needing backing context
65 *
66 * This function will be called once per physical function initialization.
67 * It will fill out the i40e_hmc_obj_info structure for LAN objects based on
68 * the driver's provided input, as well as information from the HMC itself
69 * loaded from NVRAM.
70 *
71 * Assumptions:
72 * - HMC Resource Profile has been selected before calling this function.
73 **/
74 int i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
75 u32 rxq_num, u32 fcoe_cntx_num,
76 u32 fcoe_filt_num)
77 {
78 struct i40e_hmc_obj_info *obj, *full_obj;
79 int ret_code = 0;
80 u64 l2fpm_size;
81 u32 size_exp;
82
83 hw->hmc.signature = I40E_HMC_INFO_SIGNATURE;
84 hw->hmc.hmc_fn_id = hw->pf_id;
85
86 /* allocate memory for hmc_obj */
87 ret_code = i40e_allocate_virt_mem(hw, &hw->hmc.hmc_obj_virt_mem,
88 sizeof(struct i40e_hmc_obj_info) * I40E_HMC_LAN_MAX);
89 if (ret_code)
90 goto init_lan_hmc_out;
91 hw->hmc.hmc_obj = (struct i40e_hmc_obj_info *)
92 hw->hmc.hmc_obj_virt_mem.va;
93
94 /* The full object will be used to create the LAN HMC SD */
95 full_obj = &hw->hmc.hmc_obj[I40E_HMC_LAN_FULL];
96 full_obj->max_cnt = 0;
97 full_obj->cnt = 0;
98 full_obj->base = 0;
99 full_obj->size = 0;
100
101 /* Tx queue context information */
102 obj = &hw->hmc.hmc_obj[I40E_HMC_LAN_TX];
103 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX);
104 obj->cnt = txq_num;
105 obj->base = 0;
106 size_exp = rd32(hw, I40E_GLHMC_LANTXOBJSZ);
107 obj->size = BIT_ULL(size_exp);
108
109 /* validate values requested by driver don't exceed HMC capacity */
110 if (txq_num > obj->max_cnt) {
111 ret_code = -EINVAL;
112 hw_dbg(hw, "i40e_init_lan_hmc: Tx context: asks for 0x%x but max allowed is 0x%x, returns error %d\n",
113 txq_num, obj->max_cnt, ret_code);
114 goto init_lan_hmc_out;
115 }
116
117 /* aggregate values into the full LAN object for later */
118 full_obj->max_cnt += obj->max_cnt;
119 full_obj->cnt += obj->cnt;
120
121 /* Rx queue context information */
122 obj = &hw->hmc.hmc_obj[I40E_HMC_LAN_RX];
123 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX);
124 obj->cnt = rxq_num;
125 obj->base = hw->hmc.hmc_obj[I40E_HMC_LAN_TX].base +
126 (hw->hmc.hmc_obj[I40E_HMC_LAN_TX].cnt *
127 hw->hmc.hmc_obj[I40E_HMC_LAN_TX].size);
128 obj->base = i40e_align_l2obj_base(obj->base);
129 size_exp = rd32(hw, I40E_GLHMC_LANRXOBJSZ);
130 obj->size = BIT_ULL(size_exp);
131
132 /* validate values requested by driver don't exceed HMC capacity */
133 if (rxq_num > obj->max_cnt) {
134 ret_code = -EINVAL;
135 hw_dbg(hw, "i40e_init_lan_hmc: Rx context: asks for 0x%x but max allowed is 0x%x, returns error %d\n",
136 rxq_num, obj->max_cnt, ret_code);
137 goto init_lan_hmc_out;
138 }
139
140 /* aggregate values into the full LAN object for later */
141 full_obj->max_cnt += obj->max_cnt;
142 full_obj->cnt += obj->cnt;
143
144 /* FCoE context information */
145 obj = &hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX];
146 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEMAX);
147 obj->cnt = fcoe_cntx_num;
148 obj->base = hw->hmc.hmc_obj[I40E_HMC_LAN_RX].base +
149 (hw->hmc.hmc_obj[I40E_HMC_LAN_RX].cnt *
150 hw->hmc.hmc_obj[I40E_HMC_LAN_RX].size);
151 obj->base = i40e_align_l2obj_base(obj->base);
152 size_exp = rd32(hw, I40E_GLHMC_FCOEDDPOBJSZ);
153 obj->size = BIT_ULL(size_exp);
154
155 /* validate values requested by driver don't exceed HMC capacity */
156 if (fcoe_cntx_num > obj->max_cnt) {
157 ret_code = -EINVAL;
158 hw_dbg(hw, "i40e_init_lan_hmc: FCoE context: asks for 0x%x but max allowed is 0x%x, returns error %d\n",
159 fcoe_cntx_num, obj->max_cnt, ret_code);
160 goto init_lan_hmc_out;
161 }
162
163 /* aggregate values into the full LAN object for later */
164 full_obj->max_cnt += obj->max_cnt;
165 full_obj->cnt += obj->cnt;
166
167 /* FCoE filter information */
168 obj = &hw->hmc.hmc_obj[I40E_HMC_FCOE_FILT];
169 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEFMAX);
170 obj->cnt = fcoe_filt_num;
171 obj->base = hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX].base +
172 (hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX].cnt *
173 hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX].size);
174 obj->base = i40e_align_l2obj_base(obj->base);
175 size_exp = rd32(hw, I40E_GLHMC_FCOEFOBJSZ);
176 obj->size = BIT_ULL(size_exp);
177
178 /* validate values requested by driver don't exceed HMC capacity */
179 if (fcoe_filt_num > obj->max_cnt) {
180 ret_code = -EINVAL;
181 hw_dbg(hw, "i40e_init_lan_hmc: FCoE filter: asks for 0x%x but max allowed is 0x%x, returns error %d\n",
182 fcoe_filt_num, obj->max_cnt, ret_code);
183 goto init_lan_hmc_out;
184 }
185
186 /* aggregate values into the full LAN object for later */
187 full_obj->max_cnt += obj->max_cnt;
188 full_obj->cnt += obj->cnt;
189
190 hw->hmc.first_sd_index = 0;
191 hw->hmc.sd_table.ref_cnt = 0;
192 l2fpm_size = i40e_calculate_l2fpm_size(txq_num, rxq_num, fcoe_cntx_num,
193 fcoe_filt_num);
194 if (NULL == hw->hmc.sd_table.sd_entry) {
195 hw->hmc.sd_table.sd_cnt = (u32)
196 (l2fpm_size + I40E_HMC_DIRECT_BP_SIZE - 1) /
197 I40E_HMC_DIRECT_BP_SIZE;
198
199 /* allocate the sd_entry members in the sd_table */
200 ret_code = i40e_allocate_virt_mem(hw, &hw->hmc.sd_table.addr,
201 (sizeof(struct i40e_hmc_sd_entry) *
202 hw->hmc.sd_table.sd_cnt));
203 if (ret_code)
204 goto init_lan_hmc_out;
205 hw->hmc.sd_table.sd_entry =
206 (struct i40e_hmc_sd_entry *)hw->hmc.sd_table.addr.va;
207 }
208 /* store in the LAN full object for later */
209 full_obj->size = l2fpm_size;
210
211 init_lan_hmc_out:
212 return ret_code;
213 }
214
215 /**
216 * i40e_remove_pd_page - Remove a page from the page descriptor table
217 * @hw: pointer to the HW structure
218 * @hmc_info: pointer to the HMC configuration information structure
219 * @idx: segment descriptor index to find the relevant page descriptor
220 *
221 * This function:
222 * 1. Marks the entry in pd table (for paged address mode) invalid
223 * 2. write to register PMPDINV to invalidate the backing page in FV cache
224 * 3. Decrement the ref count for pd_entry
225 * assumptions:
226 * 1. caller can deallocate the memory used by pd after this function
227 * returns.
228 **/
229 static int i40e_remove_pd_page(struct i40e_hw *hw,
230 struct i40e_hmc_info *hmc_info,
231 u32 idx)
232 {
233 int ret_code = 0;
234
235 if (!i40e_prep_remove_pd_page(hmc_info, idx))
236 ret_code = i40e_remove_pd_page_new(hw, hmc_info, idx, true);
237
238 return ret_code;
239 }
240
241 /**
242 * i40e_remove_sd_bp - remove a backing page from a segment descriptor
243 * @hw: pointer to our HW structure
244 * @hmc_info: pointer to the HMC configuration information structure
245 * @idx: the page index
246 *
247 * This function:
248 * 1. Marks the entry in sd table (for direct address mode) invalid
249 * 2. write to register PMSDCMD, PMSDDATALOW(PMSDDATALOW.PMSDVALID set
250 * to 0) and PMSDDATAHIGH to invalidate the sd page
251 * 3. Decrement the ref count for the sd_entry
252 * assumptions:
253 * 1. caller can deallocate the memory used by backing storage after this
254 * function returns.
255 **/
256 static int i40e_remove_sd_bp(struct i40e_hw *hw,
257 struct i40e_hmc_info *hmc_info,
258 u32 idx)
259 {
260 int ret_code = 0;
261
262 if (!i40e_prep_remove_sd_bp(hmc_info, idx))
263 ret_code = i40e_remove_sd_bp_new(hw, hmc_info, idx, true);
264
265 return ret_code;
266 }
267
268 /**
269 * i40e_create_lan_hmc_object - allocate backing store for hmc objects
270 * @hw: pointer to the HW structure
271 * @info: pointer to i40e_hmc_create_obj_info struct
272 *
273 * This will allocate memory for PDs and backing pages and populate
274 * the sd and pd entries.
275 **/
276 static int i40e_create_lan_hmc_object(struct i40e_hw *hw,
277 struct i40e_hmc_lan_create_obj_info *info)
278 {
279 struct i40e_hmc_sd_entry *sd_entry;
280 u32 pd_idx1 = 0, pd_lmt1 = 0;
281 u32 pd_idx = 0, pd_lmt = 0;
282 bool pd_error = false;
283 u32 sd_idx, sd_lmt;
284 int ret_code = 0;
285 u64 sd_size;
286 u32 i, j;
287
288 if (NULL == info) {
289 ret_code = -EINVAL;
290 hw_dbg(hw, "i40e_create_lan_hmc_object: bad info ptr\n");
291 goto exit;
292 }
293 if (NULL == info->hmc_info) {
294 ret_code = -EINVAL;
295 hw_dbg(hw, "i40e_create_lan_hmc_object: bad hmc_info ptr\n");
296 goto exit;
297 }
298 if (I40E_HMC_INFO_SIGNATURE != info->hmc_info->signature) {
299 ret_code = -EINVAL;
300 hw_dbg(hw, "i40e_create_lan_hmc_object: bad signature\n");
301 goto exit;
302 }
303
304 if (info->start_idx >= info->hmc_info->hmc_obj[info->rsrc_type].cnt) {
305 ret_code = -EINVAL;
306 hw_dbg(hw, "i40e_create_lan_hmc_object: returns error %d\n",
307 ret_code);
308 goto exit;
309 }
310 if ((info->start_idx + info->count) >
311 info->hmc_info->hmc_obj[info->rsrc_type].cnt) {
312 ret_code = -EINVAL;
313 hw_dbg(hw, "i40e_create_lan_hmc_object: returns error %d\n",
314 ret_code);
315 goto exit;
316 }
317
318 /* find sd index and limit */
319 I40E_FIND_SD_INDEX_LIMIT(info->hmc_info, info->rsrc_type,
320 info->start_idx, info->count,
321 &sd_idx, &sd_lmt);
322 if (sd_idx >= info->hmc_info->sd_table.sd_cnt ||
323 sd_lmt > info->hmc_info->sd_table.sd_cnt) {
324 ret_code = -EINVAL;
325 goto exit;
326 }
327 /* find pd index */
328 I40E_FIND_PD_INDEX_LIMIT(info->hmc_info, info->rsrc_type,
329 info->start_idx, info->count, &pd_idx,
330 &pd_lmt);
331
332 /* This is to cover for cases where you may not want to have an SD with
333 * the full 2M memory but something smaller. By not filling out any
334 * size, the function will default the SD size to be 2M.
335 */
336 if (info->direct_mode_sz == 0)
337 sd_size = I40E_HMC_DIRECT_BP_SIZE;
338 else
339 sd_size = info->direct_mode_sz;
340
341 /* check if all the sds are valid. If not, allocate a page and
342 * initialize it.
343 */
344 for (j = sd_idx; j < sd_lmt; j++) {
345 /* update the sd table entry */
346 ret_code = i40e_add_sd_table_entry(hw, info->hmc_info, j,
347 info->entry_type,
348 sd_size);
349 if (ret_code)
350 goto exit_sd_error;
351 sd_entry = &info->hmc_info->sd_table.sd_entry[j];
352 if (I40E_SD_TYPE_PAGED == sd_entry->entry_type) {
353 /* check if all the pds in this sd are valid. If not,
354 * allocate a page and initialize it.
355 */
356
357 /* find pd_idx and pd_lmt in this sd */
358 pd_idx1 = max(pd_idx, (j * I40E_HMC_MAX_BP_COUNT));
359 pd_lmt1 = min(pd_lmt,
360 ((j + 1) * I40E_HMC_MAX_BP_COUNT));
361 for (i = pd_idx1; i < pd_lmt1; i++) {
362 /* update the pd table entry */
363 ret_code = i40e_add_pd_table_entry(hw,
364 info->hmc_info,
365 i, NULL);
366 if (ret_code) {
367 pd_error = true;
368 break;
369 }
370 }
371 if (pd_error) {
372 /* remove the backing pages from pd_idx1 to i */
373 while (i && (i > pd_idx1)) {
374 i40e_remove_pd_bp(hw, info->hmc_info,
375 (i - 1));
376 i--;
377 }
378 }
379 }
380 if (!sd_entry->valid) {
381 sd_entry->valid = true;
382 switch (sd_entry->entry_type) {
383 case I40E_SD_TYPE_PAGED:
384 I40E_SET_PF_SD_ENTRY(hw,
385 sd_entry->u.pd_table.pd_page_addr.pa,
386 j, sd_entry->entry_type);
387 break;
388 case I40E_SD_TYPE_DIRECT:
389 I40E_SET_PF_SD_ENTRY(hw, sd_entry->u.bp.addr.pa,
390 j, sd_entry->entry_type);
391 break;
392 default:
393 ret_code = -EINVAL;
394 goto exit;
395 }
396 }
397 }
398 goto exit;
399
400 exit_sd_error:
401 /* cleanup for sd entries from j to sd_idx */
402 while (j && (j > sd_idx)) {
403 sd_entry = &info->hmc_info->sd_table.sd_entry[j - 1];
404 switch (sd_entry->entry_type) {
405 case I40E_SD_TYPE_PAGED:
406 pd_idx1 = max(pd_idx,
407 ((j - 1) * I40E_HMC_MAX_BP_COUNT));
408 pd_lmt1 = min(pd_lmt, (j * I40E_HMC_MAX_BP_COUNT));
409 for (i = pd_idx1; i < pd_lmt1; i++)
410 i40e_remove_pd_bp(hw, info->hmc_info, i);
411 i40e_remove_pd_page(hw, info->hmc_info, (j - 1));
412 break;
413 case I40E_SD_TYPE_DIRECT:
414 i40e_remove_sd_bp(hw, info->hmc_info, (j - 1));
415 break;
416 default:
417 ret_code = -EINVAL;
418 break;
419 }
420 j--;
421 }
422 exit:
423 return ret_code;
424 }
425
426 /**
427 * i40e_configure_lan_hmc - prepare the HMC backing store
428 * @hw: pointer to the hw structure
429 * @model: the model for the layout of the SD/PD tables
430 *
431 * - This function will be called once per physical function initialization.
432 * - This function will be called after i40e_init_lan_hmc() and before
433 * any LAN/FCoE HMC objects can be created.
434 **/
435 int i40e_configure_lan_hmc(struct i40e_hw *hw,
436 enum i40e_hmc_model model)
437 {
438 struct i40e_hmc_lan_create_obj_info info;
439 u8 hmc_fn_id = hw->hmc.hmc_fn_id;
440 struct i40e_hmc_obj_info *obj;
441 int ret_code = 0;
442
443 /* Initialize part of the create object info struct */
444 info.hmc_info = &hw->hmc;
445 info.rsrc_type = I40E_HMC_LAN_FULL;
446 info.start_idx = 0;
447 info.direct_mode_sz = hw->hmc.hmc_obj[I40E_HMC_LAN_FULL].size;
448
449 /* Build the SD entry for the LAN objects */
450 switch (model) {
451 case I40E_HMC_MODEL_DIRECT_PREFERRED:
452 case I40E_HMC_MODEL_DIRECT_ONLY:
453 info.entry_type = I40E_SD_TYPE_DIRECT;
454 /* Make one big object, a single SD */
455 info.count = 1;
456 ret_code = i40e_create_lan_hmc_object(hw, &info);
457 if (ret_code && (model == I40E_HMC_MODEL_DIRECT_PREFERRED))
458 goto try_type_paged;
459 else if (ret_code)
460 goto configure_lan_hmc_out;
461 /* else clause falls through the break */
462 break;
463 case I40E_HMC_MODEL_PAGED_ONLY:
464 try_type_paged:
465 info.entry_type = I40E_SD_TYPE_PAGED;
466 /* Make one big object in the PD table */
467 info.count = 1;
468 ret_code = i40e_create_lan_hmc_object(hw, &info);
469 if (ret_code)
470 goto configure_lan_hmc_out;
471 break;
472 default:
473 /* unsupported type */
474 ret_code = -EINVAL;
475 hw_dbg(hw, "i40e_configure_lan_hmc: Unknown SD type: %d\n",
476 ret_code);
477 goto configure_lan_hmc_out;
478 }
479
480 /* Configure and program the FPM registers so objects can be created */
481
482 /* Tx contexts */
483 obj = &hw->hmc.hmc_obj[I40E_HMC_LAN_TX];
484 wr32(hw, I40E_GLHMC_LANTXBASE(hmc_fn_id),
485 (u32)((obj->base & I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK) / 512));
486 wr32(hw, I40E_GLHMC_LANTXCNT(hmc_fn_id), obj->cnt);
487
488 /* Rx contexts */
489 obj = &hw->hmc.hmc_obj[I40E_HMC_LAN_RX];
490 wr32(hw, I40E_GLHMC_LANRXBASE(hmc_fn_id),
491 (u32)((obj->base & I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK) / 512));
492 wr32(hw, I40E_GLHMC_LANRXCNT(hmc_fn_id), obj->cnt);
493
494 /* FCoE contexts */
495 obj = &hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX];
496 wr32(hw, I40E_GLHMC_FCOEDDPBASE(hmc_fn_id),
497 (u32)((obj->base & I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK) / 512));
498 wr32(hw, I40E_GLHMC_FCOEDDPCNT(hmc_fn_id), obj->cnt);
499
500 /* FCoE filters */
501 obj = &hw->hmc.hmc_obj[I40E_HMC_FCOE_FILT];
502 wr32(hw, I40E_GLHMC_FCOEFBASE(hmc_fn_id),
503 (u32)((obj->base & I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK) / 512));
504 wr32(hw, I40E_GLHMC_FCOEFCNT(hmc_fn_id), obj->cnt);
505
506 configure_lan_hmc_out:
507 return ret_code;
508 }
509
510 /**
511 * i40e_delete_lan_hmc_object - remove hmc objects
512 * @hw: pointer to the HW structure
513 * @info: pointer to i40e_hmc_delete_obj_info struct
514 *
515 * This will de-populate the SDs and PDs. It frees
516 * the memory for PDS and backing storage. After this function is returned,
517 * caller should deallocate memory allocated previously for
518 * book-keeping information about PDs and backing storage.
519 **/
520 static int i40e_delete_lan_hmc_object(struct i40e_hw *hw,
521 struct i40e_hmc_lan_delete_obj_info *info)
522 {
523 struct i40e_hmc_pd_table *pd_table;
524 u32 pd_idx, pd_lmt, rel_pd_idx;
525 u32 sd_idx, sd_lmt;
526 int ret_code = 0;
527 u32 i, j;
528
529 if (NULL == info) {
530 ret_code = -EINVAL;
531 hw_dbg(hw, "i40e_delete_hmc_object: bad info ptr\n");
532 goto exit;
533 }
534 if (NULL == info->hmc_info) {
535 ret_code = -EINVAL;
536 hw_dbg(hw, "i40e_delete_hmc_object: bad info->hmc_info ptr\n");
537 goto exit;
538 }
539 if (I40E_HMC_INFO_SIGNATURE != info->hmc_info->signature) {
540 ret_code = -EINVAL;
541 hw_dbg(hw, "i40e_delete_hmc_object: bad hmc_info->signature\n");
542 goto exit;
543 }
544
545 if (NULL == info->hmc_info->sd_table.sd_entry) {
546 ret_code = -EINVAL;
547 hw_dbg(hw, "i40e_delete_hmc_object: bad sd_entry\n");
548 goto exit;
549 }
550
551 if (NULL == info->hmc_info->hmc_obj) {
552 ret_code = -EINVAL;
553 hw_dbg(hw, "i40e_delete_hmc_object: bad hmc_info->hmc_obj\n");
554 goto exit;
555 }
556 if (info->start_idx >= info->hmc_info->hmc_obj[info->rsrc_type].cnt) {
557 ret_code = -EINVAL;
558 hw_dbg(hw, "i40e_delete_hmc_object: returns error %d\n",
559 ret_code);
560 goto exit;
561 }
562
563 if ((info->start_idx + info->count) >
564 info->hmc_info->hmc_obj[info->rsrc_type].cnt) {
565 ret_code = -EINVAL;
566 hw_dbg(hw, "i40e_delete_hmc_object: returns error %d\n",
567 ret_code);
568 goto exit;
569 }
570
571 I40E_FIND_PD_INDEX_LIMIT(info->hmc_info, info->rsrc_type,
572 info->start_idx, info->count, &pd_idx,
573 &pd_lmt);
574
575 for (j = pd_idx; j < pd_lmt; j++) {
576 sd_idx = j / I40E_HMC_PD_CNT_IN_SD;
577
578 if (I40E_SD_TYPE_PAGED !=
579 info->hmc_info->sd_table.sd_entry[sd_idx].entry_type)
580 continue;
581
582 rel_pd_idx = j % I40E_HMC_PD_CNT_IN_SD;
583
584 pd_table =
585 &info->hmc_info->sd_table.sd_entry[sd_idx].u.pd_table;
586 if (pd_table->pd_entry[rel_pd_idx].valid) {
587 ret_code = i40e_remove_pd_bp(hw, info->hmc_info, j);
588 if (ret_code)
589 goto exit;
590 }
591 }
592
593 /* find sd index and limit */
594 I40E_FIND_SD_INDEX_LIMIT(info->hmc_info, info->rsrc_type,
595 info->start_idx, info->count,
596 &sd_idx, &sd_lmt);
597 if (sd_idx >= info->hmc_info->sd_table.sd_cnt ||
598 sd_lmt > info->hmc_info->sd_table.sd_cnt) {
599 ret_code = -EINVAL;
600 goto exit;
601 }
602
603 for (i = sd_idx; i < sd_lmt; i++) {
604 if (!info->hmc_info->sd_table.sd_entry[i].valid)
605 continue;
606 switch (info->hmc_info->sd_table.sd_entry[i].entry_type) {
607 case I40E_SD_TYPE_DIRECT:
608 ret_code = i40e_remove_sd_bp(hw, info->hmc_info, i);
609 if (ret_code)
610 goto exit;
611 break;
612 case I40E_SD_TYPE_PAGED:
613 ret_code = i40e_remove_pd_page(hw, info->hmc_info, i);
614 if (ret_code)
615 goto exit;
616 break;
617 default:
618 break;
619 }
620 }
621 exit:
622 return ret_code;
623 }
624
625 /**
626 * i40e_shutdown_lan_hmc - Remove HMC backing store, free allocated memory
627 * @hw: pointer to the hw structure
628 *
629 * This must be called by drivers as they are shutting down and being
630 * removed from the OS.
631 **/
632 int i40e_shutdown_lan_hmc(struct i40e_hw *hw)
633 {
634 struct i40e_hmc_lan_delete_obj_info info;
635 int ret_code;
636
637 info.hmc_info = &hw->hmc;
638 info.rsrc_type = I40E_HMC_LAN_FULL;
639 info.start_idx = 0;
640 info.count = 1;
641
642 /* delete the object */
643 ret_code = i40e_delete_lan_hmc_object(hw, &info);
644
645 /* free the SD table entry for LAN */
646 i40e_free_virt_mem(hw, &hw->hmc.sd_table.addr);
647 hw->hmc.sd_table.sd_cnt = 0;
648 hw->hmc.sd_table.sd_entry = NULL;
649
650 /* free memory used for hmc_obj */
651 i40e_free_virt_mem(hw, &hw->hmc.hmc_obj_virt_mem);
652 hw->hmc.hmc_obj = NULL;
653
654 return ret_code;
655 }
656
657 #define I40E_HMC_STORE(_struct, _ele) \
658 offsetof(struct _struct, _ele), \
659 sizeof_field(struct _struct, _ele)
660
661 struct i40e_context_ele {
662 u16 offset;
663 u16 size_of;
664 u16 width;
665 u16 lsb;
666 };
667
668 /* LAN Tx Queue Context */
669 static struct i40e_context_ele i40e_hmc_txq_ce_info[] = {
670 /* Field Width LSB */
671 {I40E_HMC_STORE(i40e_hmc_obj_txq, head), 13, 0 },
672 {I40E_HMC_STORE(i40e_hmc_obj_txq, new_context), 1, 30 },
673 {I40E_HMC_STORE(i40e_hmc_obj_txq, base), 57, 32 },
674 {I40E_HMC_STORE(i40e_hmc_obj_txq, fc_ena), 1, 89 },
675 {I40E_HMC_STORE(i40e_hmc_obj_txq, timesync_ena), 1, 90 },
676 {I40E_HMC_STORE(i40e_hmc_obj_txq, fd_ena), 1, 91 },
677 {I40E_HMC_STORE(i40e_hmc_obj_txq, alt_vlan_ena), 1, 92 },
678 {I40E_HMC_STORE(i40e_hmc_obj_txq, cpuid), 8, 96 },
679 /* line 1 */
680 {I40E_HMC_STORE(i40e_hmc_obj_txq, thead_wb), 13, 0 + 128 },
681 {I40E_HMC_STORE(i40e_hmc_obj_txq, head_wb_ena), 1, 32 + 128 },
682 {I40E_HMC_STORE(i40e_hmc_obj_txq, qlen), 13, 33 + 128 },
683 {I40E_HMC_STORE(i40e_hmc_obj_txq, tphrdesc_ena), 1, 46 + 128 },
684 {I40E_HMC_STORE(i40e_hmc_obj_txq, tphrpacket_ena), 1, 47 + 128 },
685 {I40E_HMC_STORE(i40e_hmc_obj_txq, tphwdesc_ena), 1, 48 + 128 },
686 {I40E_HMC_STORE(i40e_hmc_obj_txq, head_wb_addr), 64, 64 + 128 },
687 /* line 7 */
688 {I40E_HMC_STORE(i40e_hmc_obj_txq, crc), 32, 0 + (7 * 128) },
689 {I40E_HMC_STORE(i40e_hmc_obj_txq, rdylist), 10, 84 + (7 * 128) },
690 {I40E_HMC_STORE(i40e_hmc_obj_txq, rdylist_act), 1, 94 + (7 * 128) },
691 { 0 }
692 };
693
694 /* LAN Rx Queue Context */
695 static struct i40e_context_ele i40e_hmc_rxq_ce_info[] = {
696 /* Field Width LSB */
697 { I40E_HMC_STORE(i40e_hmc_obj_rxq, head), 13, 0 },
698 { I40E_HMC_STORE(i40e_hmc_obj_rxq, cpuid), 8, 13 },
699 { I40E_HMC_STORE(i40e_hmc_obj_rxq, base), 57, 32 },
700 { I40E_HMC_STORE(i40e_hmc_obj_rxq, qlen), 13, 89 },
701 { I40E_HMC_STORE(i40e_hmc_obj_rxq, dbuff), 7, 102 },
702 { I40E_HMC_STORE(i40e_hmc_obj_rxq, hbuff), 5, 109 },
703 { I40E_HMC_STORE(i40e_hmc_obj_rxq, dtype), 2, 114 },
704 { I40E_HMC_STORE(i40e_hmc_obj_rxq, dsize), 1, 116 },
705 { I40E_HMC_STORE(i40e_hmc_obj_rxq, crcstrip), 1, 117 },
706 { I40E_HMC_STORE(i40e_hmc_obj_rxq, fc_ena), 1, 118 },
707 { I40E_HMC_STORE(i40e_hmc_obj_rxq, l2tsel), 1, 119 },
708 { I40E_HMC_STORE(i40e_hmc_obj_rxq, hsplit_0), 4, 120 },
709 { I40E_HMC_STORE(i40e_hmc_obj_rxq, hsplit_1), 2, 124 },
710 { I40E_HMC_STORE(i40e_hmc_obj_rxq, showiv), 1, 127 },
711 { I40E_HMC_STORE(i40e_hmc_obj_rxq, rxmax), 14, 174 },
712 { I40E_HMC_STORE(i40e_hmc_obj_rxq, tphrdesc_ena), 1, 193 },
713 { I40E_HMC_STORE(i40e_hmc_obj_rxq, tphwdesc_ena), 1, 194 },
714 { I40E_HMC_STORE(i40e_hmc_obj_rxq, tphdata_ena), 1, 195 },
715 { I40E_HMC_STORE(i40e_hmc_obj_rxq, tphhead_ena), 1, 196 },
716 { I40E_HMC_STORE(i40e_hmc_obj_rxq, lrxqthresh), 3, 198 },
717 { I40E_HMC_STORE(i40e_hmc_obj_rxq, prefena), 1, 201 },
718 { 0 }
719 };
720
721 /**
722 * i40e_write_byte - replace HMC context byte
723 * @hmc_bits: pointer to the HMC memory
724 * @ce_info: a description of the struct to be read from
725 * @src: the struct to be read from
726 **/
727 static void i40e_write_byte(u8 *hmc_bits,
728 struct i40e_context_ele *ce_info,
729 u8 *src)
730 {
731 u8 src_byte, dest_byte, mask;
732 u8 *from, *dest;
733 u16 shift_width;
734
735 /* copy from the next struct field */
736 from = src + ce_info->offset;
737
738 /* prepare the bits and mask */
739 shift_width = ce_info->lsb % 8;
740 mask = (u8)(BIT(ce_info->width) - 1);
741
742 src_byte = *from;
743 src_byte &= mask;
744
745 /* shift to correct alignment */
746 mask <<= shift_width;
747 src_byte <<= shift_width;
748
749 /* get the current bits from the target bit string */
750 dest = hmc_bits + (ce_info->lsb / 8);
751
752 memcpy(&dest_byte, dest, sizeof(dest_byte));
753
754 dest_byte &= ~mask; /* get the bits not changing */
755 dest_byte |= src_byte; /* add in the new bits */
756
757 /* put it all back */
758 memcpy(dest, &dest_byte, sizeof(dest_byte));
759 }
760
761 /**
762 * i40e_write_word - replace HMC context word
763 * @hmc_bits: pointer to the HMC memory
764 * @ce_info: a description of the struct to be read from
765 * @src: the struct to be read from
766 **/
767 static void i40e_write_word(u8 *hmc_bits,
768 struct i40e_context_ele *ce_info,
769 u8 *src)
770 {
771 u16 src_word, mask;
772 u8 *from, *dest;
773 u16 shift_width;
774 __le16 dest_word;
775
776 /* copy from the next struct field */
777 from = src + ce_info->offset;
778
779 /* prepare the bits and mask */
780 shift_width = ce_info->lsb % 8;
781 mask = BIT(ce_info->width) - 1;
782
783 /* don't swizzle the bits until after the mask because the mask bits
784 * will be in a different bit position on big endian machines
785 */
786 src_word = *(u16 *)from;
787 src_word &= mask;
788
789 /* shift to correct alignment */
790 mask <<= shift_width;
791 src_word <<= shift_width;
792
793 /* get the current bits from the target bit string */
794 dest = hmc_bits + (ce_info->lsb / 8);
795
796 memcpy(&dest_word, dest, sizeof(dest_word));
797
798 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */
799 dest_word |= cpu_to_le16(src_word); /* add in the new bits */
800
801 /* put it all back */
802 memcpy(dest, &dest_word, sizeof(dest_word));
803 }
804
805 /**
806 * i40e_write_dword - replace HMC context dword
807 * @hmc_bits: pointer to the HMC memory
808 * @ce_info: a description of the struct to be read from
809 * @src: the struct to be read from
810 **/
811 static void i40e_write_dword(u8 *hmc_bits,
812 struct i40e_context_ele *ce_info,
813 u8 *src)
814 {
815 u32 src_dword, mask;
816 u8 *from, *dest;
817 u16 shift_width;
818 __le32 dest_dword;
819
820 /* copy from the next struct field */
821 from = src + ce_info->offset;
822
823 /* prepare the bits and mask */
824 shift_width = ce_info->lsb % 8;
825
826 /* if the field width is exactly 32 on an x86 machine, then the shift
827 * operation will not work because the SHL instructions count is masked
828 * to 5 bits so the shift will do nothing
829 */
830 if (ce_info->width < 32)
831 mask = BIT(ce_info->width) - 1;
832 else
833 mask = ~(u32)0;
834
835 /* don't swizzle the bits until after the mask because the mask bits
836 * will be in a different bit position on big endian machines
837 */
838 src_dword = *(u32 *)from;
839 src_dword &= mask;
840
841 /* shift to correct alignment */
842 mask <<= shift_width;
843 src_dword <<= shift_width;
844
845 /* get the current bits from the target bit string */
846 dest = hmc_bits + (ce_info->lsb / 8);
847
848 memcpy(&dest_dword, dest, sizeof(dest_dword));
849
850 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */
851 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */
852
853 /* put it all back */
854 memcpy(dest, &dest_dword, sizeof(dest_dword));
855 }
856
857 /**
858 * i40e_write_qword - replace HMC context qword
859 * @hmc_bits: pointer to the HMC memory
860 * @ce_info: a description of the struct to be read from
861 * @src: the struct to be read from
862 **/
863 static void i40e_write_qword(u8 *hmc_bits,
864 struct i40e_context_ele *ce_info,
865 u8 *src)
866 {
867 u64 src_qword, mask;
868 u8 *from, *dest;
869 u16 shift_width;
870 __le64 dest_qword;
871
872 /* copy from the next struct field */
873 from = src + ce_info->offset;
874
875 /* prepare the bits and mask */
876 shift_width = ce_info->lsb % 8;
877
878 /* if the field width is exactly 64 on an x86 machine, then the shift
879 * operation will not work because the SHL instructions count is masked
880 * to 6 bits so the shift will do nothing
881 */
882 if (ce_info->width < 64)
883 mask = BIT_ULL(ce_info->width) - 1;
884 else
885 mask = ~(u64)0;
886
887 /* don't swizzle the bits until after the mask because the mask bits
888 * will be in a different bit position on big endian machines
889 */
890 src_qword = *(u64 *)from;
891 src_qword &= mask;
892
893 /* shift to correct alignment */
894 mask <<= shift_width;
895 src_qword <<= shift_width;
896
897 /* get the current bits from the target bit string */
898 dest = hmc_bits + (ce_info->lsb / 8);
899
900 memcpy(&dest_qword, dest, sizeof(dest_qword));
901
902 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */
903 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */
904
905 /* put it all back */
906 memcpy(dest, &dest_qword, sizeof(dest_qword));
907 }
908
909 /**
910 * i40e_clear_hmc_context - zero out the HMC context bits
911 * @hw: the hardware struct
912 * @context_bytes: pointer to the context bit array (DMA memory)
913 * @hmc_type: the type of HMC resource
914 **/
915 static int i40e_clear_hmc_context(struct i40e_hw *hw,
916 u8 *context_bytes,
917 enum i40e_hmc_lan_rsrc_type hmc_type)
918 {
919 /* clean the bit array */
920 memset(context_bytes, 0, (u32)hw->hmc.hmc_obj[hmc_type].size);
921
922 return 0;
923 }
924
925 /**
926 * i40e_set_hmc_context - replace HMC context bits
927 * @context_bytes: pointer to the context bit array
928 * @ce_info: a description of the struct to be filled
929 * @dest: the struct to be filled
930 **/
931 static int i40e_set_hmc_context(u8 *context_bytes,
932 struct i40e_context_ele *ce_info,
933 u8 *dest)
934 {
935 int f;
936
937 for (f = 0; ce_info[f].width != 0; f++) {
938
939 /* we have to deal with each element of the HMC using the
940 * correct size so that we are correct regardless of the
941 * endianness of the machine
942 */
943 switch (ce_info[f].size_of) {
944 case 1:
945 i40e_write_byte(context_bytes, &ce_info[f], dest);
946 break;
947 case 2:
948 i40e_write_word(context_bytes, &ce_info[f], dest);
949 break;
950 case 4:
951 i40e_write_dword(context_bytes, &ce_info[f], dest);
952 break;
953 case 8:
954 i40e_write_qword(context_bytes, &ce_info[f], dest);
955 break;
956 }
957 }
958
959 return 0;
960 }
961
962 /**
963 * i40e_hmc_get_object_va - retrieves an object's virtual address
964 * @hw: the hardware struct, from which we obtain the i40e_hmc_info pointer
965 * @object_base: pointer to u64 to get the va
966 * @rsrc_type: the hmc resource type
967 * @obj_idx: hmc object index
968 *
969 * This function retrieves the object's virtual address from the object
970 * base pointer. This function is used for LAN Queue contexts.
971 **/
972 static
973 int i40e_hmc_get_object_va(struct i40e_hw *hw, u8 **object_base,
974 enum i40e_hmc_lan_rsrc_type rsrc_type,
975 u32 obj_idx)
976 {
977 struct i40e_hmc_info *hmc_info = &hw->hmc;
978 u32 obj_offset_in_sd, obj_offset_in_pd;
979 struct i40e_hmc_sd_entry *sd_entry;
980 struct i40e_hmc_pd_entry *pd_entry;
981 u32 pd_idx, pd_lmt, rel_pd_idx;
982 u64 obj_offset_in_fpm;
983 u32 sd_idx, sd_lmt;
984 int ret_code = 0;
985
986 if (NULL == hmc_info) {
987 ret_code = -EINVAL;
988 hw_dbg(hw, "i40e_hmc_get_object_va: bad hmc_info ptr\n");
989 goto exit;
990 }
991 if (NULL == hmc_info->hmc_obj) {
992 ret_code = -EINVAL;
993 hw_dbg(hw, "i40e_hmc_get_object_va: bad hmc_info->hmc_obj ptr\n");
994 goto exit;
995 }
996 if (NULL == object_base) {
997 ret_code = -EINVAL;
998 hw_dbg(hw, "i40e_hmc_get_object_va: bad object_base ptr\n");
999 goto exit;
1000 }
1001 if (I40E_HMC_INFO_SIGNATURE != hmc_info->signature) {
1002 ret_code = -EINVAL;
1003 hw_dbg(hw, "i40e_hmc_get_object_va: bad hmc_info->signature\n");
1004 goto exit;
1005 }
1006 if (obj_idx >= hmc_info->hmc_obj[rsrc_type].cnt) {
1007 hw_dbg(hw, "i40e_hmc_get_object_va: returns error %d\n",
1008 ret_code);
1009 ret_code = -EINVAL;
1010 goto exit;
1011 }
1012 /* find sd index and limit */
1013 I40E_FIND_SD_INDEX_LIMIT(hmc_info, rsrc_type, obj_idx, 1,
1014 &sd_idx, &sd_lmt);
1015
1016 sd_entry = &hmc_info->sd_table.sd_entry[sd_idx];
1017 obj_offset_in_fpm = hmc_info->hmc_obj[rsrc_type].base +
1018 hmc_info->hmc_obj[rsrc_type].size * obj_idx;
1019
1020 if (I40E_SD_TYPE_PAGED == sd_entry->entry_type) {
1021 I40E_FIND_PD_INDEX_LIMIT(hmc_info, rsrc_type, obj_idx, 1,
1022 &pd_idx, &pd_lmt);
1023 rel_pd_idx = pd_idx % I40E_HMC_PD_CNT_IN_SD;
1024 pd_entry = &sd_entry->u.pd_table.pd_entry[rel_pd_idx];
1025 obj_offset_in_pd = (u32)(obj_offset_in_fpm %
1026 I40E_HMC_PAGED_BP_SIZE);
1027 *object_base = (u8 *)pd_entry->bp.addr.va + obj_offset_in_pd;
1028 } else {
1029 obj_offset_in_sd = (u32)(obj_offset_in_fpm %
1030 I40E_HMC_DIRECT_BP_SIZE);
1031 *object_base = (u8 *)sd_entry->u.bp.addr.va + obj_offset_in_sd;
1032 }
1033 exit:
1034 return ret_code;
1035 }
1036
1037 /**
1038 * i40e_clear_lan_tx_queue_context - clear the HMC context for the queue
1039 * @hw: the hardware struct
1040 * @queue: the queue we care about
1041 **/
1042 int i40e_clear_lan_tx_queue_context(struct i40e_hw *hw,
1043 u16 queue)
1044 {
1045 u8 *context_bytes;
1046 int err;
1047
1048 err = i40e_hmc_get_object_va(hw, &context_bytes,
1049 I40E_HMC_LAN_TX, queue);
1050 if (err < 0)
1051 return err;
1052
1053 return i40e_clear_hmc_context(hw, context_bytes, I40E_HMC_LAN_TX);
1054 }
1055
1056 /**
1057 * i40e_set_lan_tx_queue_context - set the HMC context for the queue
1058 * @hw: the hardware struct
1059 * @queue: the queue we care about
1060 * @s: the struct to be filled
1061 **/
1062 int i40e_set_lan_tx_queue_context(struct i40e_hw *hw,
1063 u16 queue,
1064 struct i40e_hmc_obj_txq *s)
1065 {
1066 u8 *context_bytes;
1067 int err;
1068
1069 err = i40e_hmc_get_object_va(hw, &context_bytes,
1070 I40E_HMC_LAN_TX, queue);
1071 if (err < 0)
1072 return err;
1073
1074 return i40e_set_hmc_context(context_bytes,
1075 i40e_hmc_txq_ce_info, (u8 *)s);
1076 }
1077
1078 /**
1079 * i40e_clear_lan_rx_queue_context - clear the HMC context for the queue
1080 * @hw: the hardware struct
1081 * @queue: the queue we care about
1082 **/
1083 int i40e_clear_lan_rx_queue_context(struct i40e_hw *hw,
1084 u16 queue)
1085 {
1086 u8 *context_bytes;
1087 int err;
1088
1089 err = i40e_hmc_get_object_va(hw, &context_bytes,
1090 I40E_HMC_LAN_RX, queue);
1091 if (err < 0)
1092 return err;
1093
1094 return i40e_clear_hmc_context(hw, context_bytes, I40E_HMC_LAN_RX);
1095 }
1096
1097 /**
1098 * i40e_set_lan_rx_queue_context - set the HMC context for the queue
1099 * @hw: the hardware struct
1100 * @queue: the queue we care about
1101 * @s: the struct to be filled
1102 **/
1103 int i40e_set_lan_rx_queue_context(struct i40e_hw *hw,
1104 u16 queue,
1105 struct i40e_hmc_obj_rxq *s)
1106 {
1107 u8 *context_bytes;
1108 int err;
1109
1110 err = i40e_hmc_get_object_va(hw, &context_bytes,
1111 I40E_HMC_LAN_RX, queue);
1112 if (err < 0)
1113 return err;
1114
1115 return i40e_set_hmc_context(context_bytes,
1116 i40e_hmc_rxq_ce_info, (u8 *)s);
1117 }
Kernel DRM miscellaneous fixes and cross-tree changes