drivers/net/ethernet/intel/i40e/i40e_lan_hmc.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
   3
   4 #ifndef _I40E_LAN_HMC_H_
   5 #define _I40E_LAN_HMC_H_
   6
   7 #include "i40e_hmc.h"
   8
   9 /* forward-declare the HW struct for the compiler */
  10 struct i40e_hw;
  11
  12 /* HMC element context information */
  13
  14 /* Rx queue context data
  15  *
  16  * The sizes of the variables may be larger than needed due to crossing byte
  17  * boundaries. If we do not have the width of the variable set to the correct
  18  * size then we could end up shifting bits off the top of the variable when the
  19  * variable is at the top of a byte and crosses over into the next byte.
  20  */
  21 struct i40e_hmc_obj_rxq {
  22         u16 head;
  23         u16 cpuid; /* bigger than needed, see above for reason */
  24         u64 base;
  25         u16 qlen;
  26 #define I40E_RXQ_CTX_DBUFF_SHIFT 7
  27         u16 dbuff; /* bigger than needed, see above for reason */
  28 #define I40E_RXQ_CTX_HBUFF_SHIFT 6
  29         u16 hbuff; /* bigger than needed, see above for reason */
  30         u8  dtype;
  31         u8  dsize;
  32         u8  crcstrip;
  33         u8  fc_ena;
  34         u8  l2tsel;
  35         u8  hsplit_0;
  36         u8  hsplit_1;
  37         u8  showiv;
  38         u32 rxmax; /* bigger than needed, see above for reason */
  39         u8  tphrdesc_ena;
  40         u8  tphwdesc_ena;
  41         u8  tphdata_ena;
  42         u8  tphhead_ena;
  43         u16 lrxqthresh; /* bigger than needed, see above for reason */
  44         u8  prefena;    /* NOTE: normally must be set to 1 at init */
  45 };
  46
  47 /* Tx queue context data
  48 *
  49 * The sizes of the variables may be larger than needed due to crossing byte
  50 * boundaries. If we do not have the width of the variable set to the correct
  51 * size then we could end up shifting bits off the top of the variable when the
  52 * variable is at the top of a byte and crosses over into the next byte.
  53 */
  54 struct i40e_hmc_obj_txq {
  55         u16 head;
  56         u8  new_context;
  57         u64 base;
  58         u8  fc_ena;
  59         u8  timesync_ena;
  60         u8  fd_ena;
  61         u8  alt_vlan_ena;
  62         u16 thead_wb;
  63         u8  cpuid;
  64         u8  head_wb_ena;
  65         u16 qlen;
  66         u8  tphrdesc_ena;
  67         u8  tphrpacket_ena;
  68         u8  tphwdesc_ena;
  69         u64 head_wb_addr;
  70         u32 crc;
  71         u16 rdylist;
  72         u8  rdylist_act;
  73 };
  74
  75 /* for hsplit_0 field of Rx HMC context */
  76 enum i40e_hmc_obj_rx_hsplit_0 {
  77         I40E_HMC_OBJ_RX_HSPLIT_0_NO_SPLIT      = 0,
  78         I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_L2      = 1,
  79         I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_IP      = 2,
  80         I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_TCP_UDP = 4,
  81         I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_SCTP    = 8,
  82 };
  83
  84 /* fcoe_cntx and fcoe_filt are for debugging purpose only */
  85 struct i40e_hmc_obj_fcoe_cntx {
  86         u32 rsv[32];
  87 };
  88
  89 struct i40e_hmc_obj_fcoe_filt {
  90         u32 rsv[8];
  91 };
  92
  93 /* Context sizes for LAN objects */
  94 enum i40e_hmc_lan_object_size {
  95         I40E_HMC_LAN_OBJ_SZ_8   = 0x3,
  96         I40E_HMC_LAN_OBJ_SZ_16  = 0x4,
  97         I40E_HMC_LAN_OBJ_SZ_32  = 0x5,
  98         I40E_HMC_LAN_OBJ_SZ_64  = 0x6,
  99         I40E_HMC_LAN_OBJ_SZ_128 = 0x7,
 100         I40E_HMC_LAN_OBJ_SZ_256 = 0x8,
 101         I40E_HMC_LAN_OBJ_SZ_512 = 0x9,
 102 };
 103
 104 #define I40E_HMC_L2OBJ_BASE_ALIGNMENT 512
 105 #define I40E_HMC_OBJ_SIZE_TXQ         128
 106 #define I40E_HMC_OBJ_SIZE_RXQ         32
 107 #define I40E_HMC_OBJ_SIZE_FCOE_CNTX   64
 108 #define I40E_HMC_OBJ_SIZE_FCOE_FILT   64
 109
 110 enum i40e_hmc_lan_rsrc_type {
 111         I40E_HMC_LAN_FULL  = 0,
 112         I40E_HMC_LAN_TX    = 1,
 113         I40E_HMC_LAN_RX    = 2,
 114         I40E_HMC_FCOE_CTX  = 3,
 115         I40E_HMC_FCOE_FILT = 4,
 116         I40E_HMC_LAN_MAX   = 5
 117 };
 118
 119 enum i40e_hmc_model {
 120         I40E_HMC_MODEL_DIRECT_PREFERRED = 0,
 121         I40E_HMC_MODEL_DIRECT_ONLY      = 1,
 122         I40E_HMC_MODEL_PAGED_ONLY       = 2,
 123         I40E_HMC_MODEL_UNKNOWN,
 124 };
 125
 126 struct i40e_hmc_lan_create_obj_info {
 127         struct i40e_hmc_info *hmc_info;
 128         u32 rsrc_type;
 129         u32 start_idx;
 130         u32 count;
 131         enum i40e_sd_entry_type entry_type;
 132         u64 direct_mode_sz;
 133 };
 134
 135 struct i40e_hmc_lan_delete_obj_info {
 136         struct i40e_hmc_info *hmc_info;
 137         u32 rsrc_type;
 138         u32 start_idx;
 139         u32 count;
 140 };
 141
 142 int i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
 143                       u32 rxq_num, u32 fcoe_cntx_num,
 144                       u32 fcoe_filt_num);
 145 int i40e_configure_lan_hmc(struct i40e_hw *hw,
 146                            enum i40e_hmc_model model);
 147 int i40e_shutdown_lan_hmc(struct i40e_hw *hw);
 148
 149 int i40e_clear_lan_tx_queue_context(struct i40e_hw *hw,
 150                                     u16 queue);
 151 int i40e_set_lan_tx_queue_context(struct i40e_hw *hw,
 152                                   u16 queue,
 153                                   struct i40e_hmc_obj_txq *s);
 154 int i40e_clear_lan_rx_queue_context(struct i40e_hw *hw,
 155                                     u16 queue);
 156 int i40e_set_lan_rx_queue_context(struct i40e_hw *hw,
 157                                   u16 queue,
 158                                   struct i40e_hmc_obj_rxq *s);
 159
 160 #endif /* _I40E_LAN_HMC_H_ */