drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
   3
   4 #include "ixgbe_x540.h"
   5 #include "ixgbe_type.h"
   6 #include "ixgbe_common.h"
   7 #include "ixgbe_mbx.h"
   8 #include "ixgbe_phy.h"
   9
  10 static int ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed);
  11 static int ixgbe_setup_fc_x550em(struct ixgbe_hw *);
  12 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *);
  13 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *);
  14 static int ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *);
  15
  16 static int ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)
  17 {
  18         struct ixgbe_mac_info *mac = &hw->mac;
  19         struct ixgbe_phy_info *phy = &hw->phy;
  20         struct ixgbe_link_info *link = &hw->link;
  21
  22         /* Start with X540 invariants, since so simular */
  23         ixgbe_get_invariants_X540(hw);
  24
  25         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
  26                 phy->ops.set_phy_power = NULL;
  27
  28         link->addr = IXGBE_CS4227;
  29
  30         return 0;
  31 }
  32
  33 static int ixgbe_get_invariants_X550_x_fw(struct ixgbe_hw *hw)
  34 {
  35         struct ixgbe_phy_info *phy = &hw->phy;
  36
  37         /* Start with X540 invariants, since so similar */
  38         ixgbe_get_invariants_X540(hw);
  39
  40         phy->ops.set_phy_power = NULL;
  41
  42         return 0;
  43 }
  44
  45 static int ixgbe_get_invariants_X550_a(struct ixgbe_hw *hw)
  46 {
  47         struct ixgbe_mac_info *mac = &hw->mac;
  48         struct ixgbe_phy_info *phy = &hw->phy;
  49
  50         /* Start with X540 invariants, since so simular */
  51         ixgbe_get_invariants_X540(hw);
  52
  53         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
  54                 phy->ops.set_phy_power = NULL;
  55
  56         return 0;
  57 }
  58
  59 static int ixgbe_get_invariants_X550_a_fw(struct ixgbe_hw *hw)
  60 {
  61         struct ixgbe_phy_info *phy = &hw->phy;
  62
  63         /* Start with X540 invariants, since so similar */
  64         ixgbe_get_invariants_X540(hw);
  65
  66         phy->ops.set_phy_power = NULL;
  67
  68         return 0;
  69 }
  70
  71 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
  72  *  @hw: pointer to hardware structure
  73  **/
  74 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
  75 {
  76         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  77
  78         if (hw->bus.lan_id) {
  79                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
  80                 esdp |= IXGBE_ESDP_SDP1_DIR;
  81         }
  82         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
  83         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
  84         IXGBE_WRITE_FLUSH(hw);
  85 }
  86
  87 /**
  88  * ixgbe_read_cs4227 - Read CS4227 register
  89  * @hw: pointer to hardware structure
  90  * @reg: register number to write
  91  * @value: pointer to receive value read
  92  *
  93  * Returns status code
  94  */
  95 static int ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  96 {
  97         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
  98 }
  99
 100 /**
 101  * ixgbe_write_cs4227 - Write CS4227 register
 102  * @hw: pointer to hardware structure
 103  * @reg: register number to write
 104  * @value: value to write to register
 105  *
 106  * Returns status code
 107  */
 108 static int ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 109 {
 110         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 111 }
 112
 113 /**
 114  * ixgbe_read_pe - Read register from port expander
 115  * @hw: pointer to hardware structure
 116  * @reg: register number to read
 117  * @value: pointer to receive read value
 118  *
 119  * Returns status code
 120  */
 121 static int ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 122 {
 123         int status;
 124
 125         status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value);
 126         if (status)
 127                 hw_err(hw, "port expander access failed with %d\n", status);
 128         return status;
 129 }
 130
 131 /**
 132  * ixgbe_write_pe - Write register to port expander
 133  * @hw: pointer to hardware structure
 134  * @reg: register number to write
 135  * @value: value to write
 136  *
 137  * Returns status code
 138  */
 139 static int ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 140 {
 141         int status;
 142
 143         status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE,
 144                                                        value);
 145         if (status)
 146                 hw_err(hw, "port expander access failed with %d\n", status);
 147         return status;
 148 }
 149
 150 /**
 151  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 152  * @hw: pointer to hardware structure
 153  *
 154  * This function assumes that the caller has acquired the proper semaphore.
 155  * Returns error code
 156  */
 157 static int ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 158 {
 159         int status;
 160         u32 retry;
 161         u16 value;
 162         u8 reg;
 163
 164         /* Trigger hard reset. */
 165         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 166         if (status)
 167                 return status;
 168         reg |= IXGBE_PE_BIT1;
 169         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 170         if (status)
 171                 return status;
 172
 173         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 174         if (status)
 175                 return status;
 176         reg &= ~IXGBE_PE_BIT1;
 177         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 178         if (status)
 179                 return status;
 180
 181         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 182         if (status)
 183                 return status;
 184         reg &= ~IXGBE_PE_BIT1;
 185         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 186         if (status)
 187                 return status;
 188
 189         usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100);
 190
 191         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 192         if (status)
 193                 return status;
 194         reg |= IXGBE_PE_BIT1;
 195         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 196         if (status)
 197                 return status;
 198
 199         /* Wait for the reset to complete. */
 200         msleep(IXGBE_CS4227_RESET_DELAY);
 201         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 202                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 203                                            &value);
 204                 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK)
 205                         break;
 206                 msleep(IXGBE_CS4227_CHECK_DELAY);
 207         }
 208         if (retry == IXGBE_CS4227_RETRIES) {
 209                 hw_err(hw, "CS4227 reset did not complete\n");
 210                 return -EIO;
 211         }
 212
 213         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 214         if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 215                 hw_err(hw, "CS4227 EEPROM did not load successfully\n");
 216                 return -EIO;
 217         }
 218
 219         return 0;
 220 }
 221
 222 /**
 223  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 224  * @hw: pointer to hardware structure
 225  */
 226 static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 227 {
 228         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 229         int status;
 230         u16 value;
 231         u8 retry;
 232
 233         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 234                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 235                 if (status) {
 236                         hw_err(hw, "semaphore failed with %d\n", status);
 237                         msleep(IXGBE_CS4227_CHECK_DELAY);
 238                         continue;
 239                 }
 240
 241                 /* Get status of reset flow. */
 242                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 243                 if (!status && value == IXGBE_CS4227_RESET_COMPLETE)
 244                         goto out;
 245
 246                 if (status || value != IXGBE_CS4227_RESET_PENDING)
 247                         break;
 248
 249                 /* Reset is pending. Wait and check again. */
 250                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 251                 msleep(IXGBE_CS4227_CHECK_DELAY);
 252         }
 253         /* If still pending, assume other instance failed. */
 254         if (retry == IXGBE_CS4227_RETRIES) {
 255                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 256                 if (status) {
 257                         hw_err(hw, "semaphore failed with %d\n", status);
 258                         return;
 259                 }
 260         }
 261
 262         /* Reset the CS4227. */
 263         status = ixgbe_reset_cs4227(hw);
 264         if (status) {
 265                 hw_err(hw, "CS4227 reset failed: %d", status);
 266                 goto out;
 267         }
 268
 269         /* Reset takes so long, temporarily release semaphore in case the
 270          * other driver instance is waiting for the reset indication.
 271          */
 272         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 273                            IXGBE_CS4227_RESET_PENDING);
 274         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 275         usleep_range(10000, 12000);
 276         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 277         if (status) {
 278                 hw_err(hw, "semaphore failed with %d", status);
 279                 return;
 280         }
 281
 282         /* Record completion for next time. */
 283         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 284                                     IXGBE_CS4227_RESET_COMPLETE);
 285
 286 out:
 287         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 288         msleep(hw->eeprom.semaphore_delay);
 289 }
 290
 291 /** ixgbe_identify_phy_x550em - Get PHY type based on device id
 292  *  @hw: pointer to hardware structure
 293  *
 294  *  Returns error code
 295  */
 296 static int ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 297 {
 298         switch (hw->device_id) {
 299         case IXGBE_DEV_ID_X550EM_A_SFP:
 300                 if (hw->bus.lan_id)
 301                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 302                 else
 303                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 304                 return ixgbe_identify_module_generic(hw);
 305         case IXGBE_DEV_ID_X550EM_X_SFP:
 306                 /* set up for CS4227 usage */
 307                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 308                 ixgbe_setup_mux_ctl(hw);
 309                 ixgbe_check_cs4227(hw);
 310                 fallthrough;
 311         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 312                 return ixgbe_identify_module_generic(hw);
 313         case IXGBE_DEV_ID_X550EM_X_KX4:
 314                 hw->phy.type = ixgbe_phy_x550em_kx4;
 315                 break;
 316         case IXGBE_DEV_ID_X550EM_X_XFI:
 317                 hw->phy.type = ixgbe_phy_x550em_xfi;
 318                 break;
 319         case IXGBE_DEV_ID_X550EM_X_KR:
 320         case IXGBE_DEV_ID_X550EM_A_KR:
 321         case IXGBE_DEV_ID_X550EM_A_KR_L:
 322                 hw->phy.type = ixgbe_phy_x550em_kr;
 323                 break;
 324         case IXGBE_DEV_ID_X550EM_A_10G_T:
 325                 if (hw->bus.lan_id)
 326                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 327                 else
 328                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 329                 fallthrough;
 330         case IXGBE_DEV_ID_X550EM_X_10G_T:
 331                 return ixgbe_identify_phy_generic(hw);
 332         case IXGBE_DEV_ID_X550EM_X_1G_T:
 333                 hw->phy.type = ixgbe_phy_ext_1g_t;
 334                 break;
 335         case IXGBE_DEV_ID_X550EM_A_1G_T:
 336         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 337                 hw->phy.type = ixgbe_phy_fw;
 338                 hw->phy.ops.read_reg = NULL;
 339                 hw->phy.ops.write_reg = NULL;
 340                 if (hw->bus.lan_id)
 341                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 342                 else
 343                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 344                 break;
 345         default:
 346                 break;
 347         }
 348         return 0;
 349 }
 350
 351 static int ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 352                                      u32 device_type, u16 *phy_data)
 353 {
 354         return -EOPNOTSUPP;
 355 }
 356
 357 static int ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 358                                       u32 device_type, u16 phy_data)
 359 {
 360         return -EOPNOTSUPP;
 361 }
 362
 363 /**
 364  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 365  * @hw: pointer to the hardware structure
 366  * @addr: I2C bus address to read from
 367  * @reg: I2C device register to read from
 368  * @val: pointer to location to receive read value
 369  *
 370  * Returns an error code on error.
 371  **/
 372 static int ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 373                                            u16 reg, u16 *val)
 374 {
 375         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 376 }
 377
 378 /**
 379  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 380  * @hw: pointer to the hardware structure
 381  * @addr: I2C bus address to read from
 382  * @reg: I2C device register to read from
 383  * @val: pointer to location to receive read value
 384  *
 385  * Returns an error code on error.
 386  **/
 387 static int
 388 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 389                                          u16 reg, u16 *val)
 390 {
 391         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 392 }
 393
 394 /**
 395  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 396  * @hw: pointer to the hardware structure
 397  * @addr: I2C bus address to write to
 398  * @reg: I2C device register to write to
 399  * @val: value to write
 400  *
 401  * Returns an error code on error.
 402  **/
 403 static int ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 404                                             u8 addr, u16 reg, u16 val)
 405 {
 406         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 407 }
 408
 409 /**
 410  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 411  * @hw: pointer to the hardware structure
 412  * @addr: I2C bus address to write to
 413  * @reg: I2C device register to write to
 414  * @val: value to write
 415  *
 416  * Returns an error code on error.
 417  **/
 418 static int
 419 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 420                                           u8 addr, u16 reg, u16 val)
 421 {
 422         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 423 }
 424
 425 /**
 426  * ixgbe_fw_phy_activity - Perform an activity on a PHY
 427  * @hw: pointer to hardware structure
 428  * @activity: activity to perform
 429  * @data: Pointer to 4 32-bit words of data
 430  */
 431 int ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
 432                           u32 (*data)[FW_PHY_ACT_DATA_COUNT])
 433 {
 434         union {
 435                 struct ixgbe_hic_phy_activity_req cmd;
 436                 struct ixgbe_hic_phy_activity_resp rsp;
 437         } hic;
 438         u16 retries = FW_PHY_ACT_RETRIES;
 439         int rc;
 440         u32 i;
 441
 442         do {
 443                 memset(&hic, 0, sizeof(hic));
 444                 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
 445                 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
 446                 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 447                 hic.cmd.port_number = hw->bus.lan_id;
 448                 hic.cmd.activity_id = cpu_to_le16(activity);
 449                 for (i = 0; i < ARRAY_SIZE(hic.cmd.data); ++i)
 450                         hic.cmd.data[i] = cpu_to_be32((*data)[i]);
 451
 452                 rc = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
 453                                                   IXGBE_HI_COMMAND_TIMEOUT,
 454                                                   true);
 455                 if (rc)
 456                         return rc;
 457                 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
 458                     FW_CEM_RESP_STATUS_SUCCESS) {
 459                         for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 460                                 (*data)[i] = be32_to_cpu(hic.rsp.data[i]);
 461                         return 0;
 462                 }
 463                 usleep_range(20, 30);
 464                 --retries;
 465         } while (retries > 0);
 466
 467         return -EIO;
 468 }
 469
 470 static const struct {
 471         u16 fw_speed;
 472         ixgbe_link_speed phy_speed;
 473 } ixgbe_fw_map[] = {
 474         { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
 475         { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
 476         { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
 477         { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
 478         { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
 479         { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
 480 };
 481
 482 /**
 483  * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
 484  * @hw: pointer to hardware structure
 485  *
 486  * Returns error code
 487  */
 488 static int ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
 489 {
 490         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
 491         u16 phy_speeds;
 492         u16 phy_id_lo;
 493         int rc;
 494         u16 i;
 495
 496         if (hw->phy.id)
 497                 return 0;
 498
 499         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
 500         if (rc)
 501                 return rc;
 502
 503         hw->phy.speeds_supported = 0;
 504         phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
 505         for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) {
 506                 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
 507                         hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
 508         }
 509
 510         hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
 511         phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
 512         hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
 513         hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
 514         if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
 515                 return -EFAULT;
 516
 517         hw->phy.autoneg_advertised = hw->phy.speeds_supported;
 518         hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
 519                                        IXGBE_LINK_SPEED_1GB_FULL;
 520         hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 521         return 0;
 522 }
 523
 524 /**
 525  * ixgbe_identify_phy_fw - Get PHY type based on firmware command
 526  * @hw: pointer to hardware structure
 527  *
 528  * Returns error code
 529  */
 530 static int ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
 531 {
 532         if (hw->bus.lan_id)
 533                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 534         else
 535                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 536
 537         hw->phy.type = ixgbe_phy_fw;
 538         hw->phy.ops.read_reg = NULL;
 539         hw->phy.ops.write_reg = NULL;
 540         return ixgbe_get_phy_id_fw(hw);
 541 }
 542
 543 /**
 544  * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
 545  * @hw: pointer to hardware structure
 546  *
 547  * Returns error code
 548  */
 549 static int ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
 550 {
 551         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 552
 553         setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
 554         return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
 555 }
 556
 557 /**
 558  * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
 559  * @hw: pointer to hardware structure
 560  */
 561 static int ixgbe_setup_fw_link(struct ixgbe_hw *hw)
 562 {
 563         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 564         int rc;
 565         u16 i;
 566
 567         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
 568                 return 0;
 569
 570         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 571                 hw_err(hw, "rx_pause not valid in strict IEEE mode\n");
 572                 return -EINVAL;
 573         }
 574
 575         switch (hw->fc.requested_mode) {
 576         case ixgbe_fc_full:
 577                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
 578                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 579                 break;
 580         case ixgbe_fc_rx_pause:
 581                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
 582                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 583                 break;
 584         case ixgbe_fc_tx_pause:
 585                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
 586                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 587                 break;
 588         default:
 589                 break;
 590         }
 591
 592         for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) {
 593                 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
 594                         setup[0] |= ixgbe_fw_map[i].fw_speed;
 595         }
 596         setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
 597
 598         if (hw->phy.eee_speeds_advertised)
 599                 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
 600
 601         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
 602         if (rc)
 603                 return rc;
 604
 605         if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
 606                 return -EIO;
 607
 608         return 0;
 609 }
 610
 611 /**
 612  * ixgbe_fc_autoneg_fw - Set up flow control for FW-controlled PHYs
 613  * @hw: pointer to hardware structure
 614  *
 615  * Called at init time to set up flow control.
 616  */
 617 static int ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
 618 {
 619         if (hw->fc.requested_mode == ixgbe_fc_default)
 620                 hw->fc.requested_mode = ixgbe_fc_full;
 621
 622         return ixgbe_setup_fw_link(hw);
 623 }
 624
 625 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 626  *  @hw: pointer to hardware structure
 627  *
 628  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 629  *  ixgbe_hw struct in order to set up EEPROM access.
 630  **/
 631 static int ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 632 {
 633         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 634
 635         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 636                 u16 eeprom_size;
 637                 u32 eec;
 638
 639                 eeprom->semaphore_delay = 10;
 640                 eeprom->type = ixgbe_flash;
 641
 642                 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
 643                 eeprom_size = FIELD_GET(IXGBE_EEC_SIZE, eec);
 644                 eeprom->word_size = BIT(eeprom_size +
 645                                         IXGBE_EEPROM_WORD_SIZE_SHIFT);
 646
 647                 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
 648                        eeprom->type, eeprom->word_size);
 649         }
 650
 651         return 0;
 652 }
 653
 654 /**
 655  * ixgbe_iosf_wait - Wait for IOSF command completion
 656  * @hw: pointer to hardware structure
 657  * @ctrl: pointer to location to receive final IOSF control value
 658  *
 659  * Return: failing status on timeout
 660  *
 661  * Note: ctrl can be NULL if the IOSF control register value is not needed
 662  */
 663 static int ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 664 {
 665         u32 i, command;
 666
 667         /* Check every 10 usec to see if the address cycle completed.
 668          * The SB IOSF BUSY bit will clear when the operation is
 669          * complete.
 670          */
 671         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 672                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 673                 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
 674                         break;
 675                 udelay(10);
 676         }
 677         if (ctrl)
 678                 *ctrl = command;
 679         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 680                 hw_dbg(hw, "IOSF wait timed out\n");
 681                 return -EIO;
 682         }
 683
 684         return 0;
 685 }
 686
 687 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
 688  *  IOSF device
 689  *  @hw: pointer to hardware structure
 690  *  @reg_addr: 32 bit PHY register to write
 691  *  @device_type: 3 bit device type
 692  *  @phy_data: Pointer to read data from the register
 693  **/
 694 static int ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 695                                        u32 device_type, u32 *data)
 696 {
 697         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 698         u32 command, error;
 699         int ret;
 700
 701         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
 702         if (ret)
 703                 return ret;
 704
 705         ret = ixgbe_iosf_wait(hw, NULL);
 706         if (ret)
 707                 goto out;
 708
 709         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 710                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 711
 712         /* Write IOSF control register */
 713         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 714
 715         ret = ixgbe_iosf_wait(hw, &command);
 716
 717         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 718                 error = FIELD_GET(IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK, command);
 719                 hw_dbg(hw, "Failed to read, error %x\n", error);
 720                 ret = -EIO;
 721                 goto out;
 722         }
 723
 724         if (!ret)
 725                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 726
 727 out:
 728         hw->mac.ops.release_swfw_sync(hw, gssr);
 729         return ret;
 730 }
 731
 732 /**
 733  * ixgbe_get_phy_token - Get the token for shared PHY access
 734  * @hw: Pointer to hardware structure
 735  */
 736 static int ixgbe_get_phy_token(struct ixgbe_hw *hw)
 737 {
 738         struct ixgbe_hic_phy_token_req token_cmd;
 739         int status;
 740
 741         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
 742         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
 743         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
 744         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 745         token_cmd.port_number = hw->bus.lan_id;
 746         token_cmd.command_type = FW_PHY_TOKEN_REQ;
 747         token_cmd.pad = 0;
 748         status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
 749                                               IXGBE_HI_COMMAND_TIMEOUT,
 750                                               true);
 751         if (status)
 752                 return status;
 753         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
 754                 return 0;
 755         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
 756                 return -EIO;
 757
 758         return -EAGAIN;
 759 }
 760
 761 /**
 762  * ixgbe_put_phy_token - Put the token for shared PHY access
 763  * @hw: Pointer to hardware structure
 764  */
 765 static int ixgbe_put_phy_token(struct ixgbe_hw *hw)
 766 {
 767         struct ixgbe_hic_phy_token_req token_cmd;
 768         int status;
 769
 770         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
 771         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
 772         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
 773         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 774         token_cmd.port_number = hw->bus.lan_id;
 775         token_cmd.command_type = FW_PHY_TOKEN_REL;
 776         token_cmd.pad = 0;
 777         status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
 778                                               IXGBE_HI_COMMAND_TIMEOUT,
 779                                               true);
 780         if (status)
 781                 return status;
 782         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
 783                 return 0;
 784         return -EIO;
 785 }
 786
 787 /**
 788  *  ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register
 789  *  @hw: pointer to hardware structure
 790  *  @reg_addr: 32 bit PHY register to write
 791  *  @device_type: 3 bit device type
 792  *  @data: Data to write to the register
 793  **/
 794 static int ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
 795                                          __always_unused u32 device_type,
 796                                          u32 data)
 797 {
 798         struct ixgbe_hic_internal_phy_req write_cmd;
 799
 800         memset(&write_cmd, 0, sizeof(write_cmd));
 801         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
 802         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
 803         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 804         write_cmd.port_number = hw->bus.lan_id;
 805         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
 806         write_cmd.address = cpu_to_be16(reg_addr);
 807         write_cmd.write_data = cpu_to_be32(data);
 808
 809         return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd),
 810                                             IXGBE_HI_COMMAND_TIMEOUT, false);
 811 }
 812
 813 /**
 814  *  ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register
 815  *  @hw: pointer to hardware structure
 816  *  @reg_addr: 32 bit PHY register to write
 817  *  @device_type: 3 bit device type
 818  *  @data: Pointer to read data from the register
 819  **/
 820 static int ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
 821                                         __always_unused u32 device_type,
 822                                         u32 *data)
 823 {
 824         union {
 825                 struct ixgbe_hic_internal_phy_req cmd;
 826                 struct ixgbe_hic_internal_phy_resp rsp;
 827         } hic;
 828         int status;
 829
 830         memset(&hic, 0, sizeof(hic));
 831         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
 832         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
 833         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 834         hic.cmd.port_number = hw->bus.lan_id;
 835         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
 836         hic.cmd.address = cpu_to_be16(reg_addr);
 837
 838         status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
 839                                               IXGBE_HI_COMMAND_TIMEOUT, true);
 840
 841         /* Extract the register value from the response. */
 842         *data = be32_to_cpu(hic.rsp.read_data);
 843
 844         return status;
 845 }
 846
 847 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
 848  *  @hw: pointer to hardware structure
 849  *  @offset: offset of  word in the EEPROM to read
 850  *  @words: number of words
 851  *  @data: word(s) read from the EEPROM
 852  *
 853  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
 854  **/
 855 static int ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
 856                                             u16 offset, u16 words, u16 *data)
 857 {
 858         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
 859         struct ixgbe_hic_read_shadow_ram buffer;
 860         u32 current_word = 0;
 861         u16 words_to_read;
 862         int status;
 863         u32 i;
 864
 865         /* Take semaphore for the entire operation. */
 866         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
 867         if (status) {
 868                 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
 869                 return status;
 870         }
 871
 872         while (words) {
 873                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
 874                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
 875                 else
 876                         words_to_read = words;
 877
 878                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 879                 buffer.hdr.req.buf_lenh = 0;
 880                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 881                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 882
 883                 /* convert offset from words to bytes */
 884                 buffer.address = (__force u32)cpu_to_be32((offset +
 885                                                            current_word) * 2);
 886                 buffer.length = (__force u16)cpu_to_be16(words_to_read * 2);
 887                 buffer.pad2 = 0;
 888                 buffer.pad3 = 0;
 889
 890                 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
 891                                             IXGBE_HI_COMMAND_TIMEOUT);
 892                 if (status) {
 893                         hw_dbg(hw, "Host interface command failed\n");
 894                         goto out;
 895                 }
 896
 897                 for (i = 0; i < words_to_read; i++) {
 898                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
 899                                   2 * i;
 900                         u32 value = IXGBE_READ_REG(hw, reg);
 901
 902                         data[current_word] = (u16)(value & 0xffff);
 903                         current_word++;
 904                         i++;
 905                         if (i < words_to_read) {
 906                                 value >>= 16;
 907                                 data[current_word] = (u16)(value & 0xffff);
 908                                 current_word++;
 909                         }
 910                 }
 911                 words -= words_to_read;
 912         }
 913
 914 out:
 915         hw->mac.ops.release_swfw_sync(hw, mask);
 916         return status;
 917 }
 918
 919 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region
 920  *  @hw: pointer to hardware structure
 921  *  @ptr: pointer offset in eeprom
 922  *  @size: size of section pointed by ptr, if 0 first word will be used as size
 923  *  @csum: address of checksum to update
 924  *
 925  *  Returns error status for any failure
 926  **/
 927 static int ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
 928                                    u16 size, u16 *csum, u16 *buffer,
 929                                    u32 buffer_size)
 930 {
 931         u16 length, bufsz, i, start;
 932         u16 *local_buffer;
 933         u16 buf[256];
 934         int status;
 935
 936         bufsz = ARRAY_SIZE(buf);
 937
 938         /* Read a chunk at the pointer location */
 939         if (!buffer) {
 940                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
 941                 if (status) {
 942                         hw_dbg(hw, "Failed to read EEPROM image\n");
 943                         return status;
 944                 }
 945                 local_buffer = buf;
 946         } else {
 947                 if (buffer_size < ptr)
 948                         return  -EINVAL;
 949                 local_buffer = &buffer[ptr];
 950         }
 951
 952         if (size) {
 953                 start = 0;
 954                 length = size;
 955         } else {
 956                 start = 1;
 957                 length = local_buffer[0];
 958
 959                 /* Skip pointer section if length is invalid. */
 960                 if (length == 0xFFFF || length == 0 ||
 961                     (ptr + length) >= hw->eeprom.word_size)
 962                         return 0;
 963         }
 964
 965         if (buffer && ((u32)start + (u32)length > buffer_size))
 966                 return -EINVAL;
 967
 968         for (i = start; length; i++, length--) {
 969                 if (i == bufsz && !buffer) {
 970                         ptr += bufsz;
 971                         i = 0;
 972                         if (length < bufsz)
 973                                 bufsz = length;
 974
 975                         /* Read a chunk at the pointer location */
 976                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
 977                                                                   bufsz, buf);
 978                         if (status) {
 979                                 hw_dbg(hw, "Failed to read EEPROM image\n");
 980                                 return status;
 981                         }
 982                 }
 983                 *csum += local_buffer[i];
 984         }
 985         return 0;
 986 }
 987
 988 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
 989  *  @hw: pointer to hardware structure
 990  *  @buffer: pointer to buffer containing calculated checksum
 991  *  @buffer_size: size of buffer
 992  *
 993  *  Returns a negative error code on error, or the 16-bit checksum
 994  **/
 995 static int ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
 996                                     u32 buffer_size)
 997 {
 998         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
 999         u16 pointer, i, size;
1000         u16 *local_buffer;
1001         u16 checksum = 0;
1002         int status;
1003
1004         hw->eeprom.ops.init_params(hw);
1005
1006         if (!buffer) {
1007                 /* Read pointer area */
1008                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1009                                                 IXGBE_EEPROM_LAST_WORD + 1,
1010                                                 eeprom_ptrs);
1011                 if (status) {
1012                         hw_dbg(hw, "Failed to read EEPROM image\n");
1013                         return status;
1014                 }
1015                 local_buffer = eeprom_ptrs;
1016         } else {
1017                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
1018                         return -EINVAL;
1019                 local_buffer = buffer;
1020         }
1021
1022         /* For X550 hardware include 0x0-0x41 in the checksum, skip the
1023          * checksum word itself
1024          */
1025         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1026                 if (i != IXGBE_EEPROM_CHECKSUM)
1027                         checksum += local_buffer[i];
1028
1029         /* Include all data from pointers 0x3, 0x6-0xE.  This excludes the
1030          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1031          */
1032         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1033                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1034                         continue;
1035
1036                 pointer = local_buffer[i];
1037
1038                 /* Skip pointer section if the pointer is invalid. */
1039                 if (pointer == 0xFFFF || pointer == 0 ||
1040                     pointer >= hw->eeprom.word_size)
1041                         continue;
1042
1043                 switch (i) {
1044                 case IXGBE_PCIE_GENERAL_PTR:
1045                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1046                         break;
1047                 case IXGBE_PCIE_CONFIG0_PTR:
1048                 case IXGBE_PCIE_CONFIG1_PTR:
1049                         size = IXGBE_PCIE_CONFIG_SIZE;
1050                         break;
1051                 default:
1052                         size = 0;
1053                         break;
1054                 }
1055
1056                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
1057                                                  buffer, buffer_size);
1058                 if (status)
1059                         return status;
1060         }
1061
1062         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1063
1064         return (int)checksum;
1065 }
1066
1067 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1068  *  @hw: pointer to hardware structure
1069  *
1070  *  Returns a negative error code on error, or the 16-bit checksum
1071  **/
1072 static int ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1073 {
1074         return ixgbe_calc_checksum_X550(hw, NULL, 0);
1075 }
1076
1077 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1078  *  @hw: pointer to hardware structure
1079  *  @offset: offset of  word in the EEPROM to read
1080  *  @data: word read from the EEPROM
1081  *
1082  *   Reads a 16 bit word from the EEPROM using the hostif.
1083  **/
1084 static int ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
1085 {
1086         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
1087         struct ixgbe_hic_read_shadow_ram buffer;
1088         int status;
1089
1090         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1091         buffer.hdr.req.buf_lenh = 0;
1092         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1093         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1094
1095         /* convert offset from words to bytes */
1096         buffer.address = (__force u32)cpu_to_be32(offset * 2);
1097         /* one word */
1098         buffer.length = (__force u16)cpu_to_be16(sizeof(u16));
1099
1100         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
1101         if (status)
1102                 return status;
1103
1104         status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
1105                                     IXGBE_HI_COMMAND_TIMEOUT);
1106         if (!status) {
1107                 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1108                                                   FW_NVM_DATA_OFFSET);
1109         }
1110
1111         hw->mac.ops.release_swfw_sync(hw, mask);
1112         return status;
1113 }
1114
1115 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1116  *  @hw: pointer to hardware structure
1117  *  @checksum_val: calculated checksum
1118  *
1119  *  Performs checksum calculation and validates the EEPROM checksum.  If the
1120  *  caller does not need checksum_val, the value can be NULL.
1121  **/
1122 static int ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
1123                                                u16 *checksum_val)
1124 {
1125         u16 read_checksum = 0;
1126         u16 checksum;
1127         int status;
1128
1129         /* Read the first word from the EEPROM. If this times out or fails, do
1130          * not continue or we could be in for a very long wait while every
1131          * EEPROM read fails
1132          */
1133         status = hw->eeprom.ops.read(hw, 0, &checksum);
1134         if (status) {
1135                 hw_dbg(hw, "EEPROM read failed\n");
1136                 return status;
1137         }
1138
1139         status = hw->eeprom.ops.calc_checksum(hw);
1140         if (status < 0)
1141                 return status;
1142
1143         checksum = (u16)(status & 0xffff);
1144
1145         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1146                                            &read_checksum);
1147         if (status)
1148                 return status;
1149
1150         /* Verify read checksum from EEPROM is the same as
1151          * calculated checksum
1152          */
1153         if (read_checksum != checksum) {
1154                 status = -EIO;
1155                 hw_dbg(hw, "Invalid EEPROM checksum");
1156         }
1157
1158         /* If the user cares, return the calculated checksum */
1159         if (checksum_val)
1160                 *checksum_val = checksum;
1161
1162         return status;
1163 }
1164
1165 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1166  *  @hw: pointer to hardware structure
1167  *  @offset: offset of  word in the EEPROM to write
1168  *  @data: word write to the EEPROM
1169  *
1170  *  Write a 16 bit word to the EEPROM using the hostif.
1171  **/
1172 static int ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1173                                            u16 data)
1174 {
1175         struct ixgbe_hic_write_shadow_ram buffer;
1176         int status;
1177
1178         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1179         buffer.hdr.req.buf_lenh = 0;
1180         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1181         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1182
1183         /* one word */
1184         buffer.length = cpu_to_be16(sizeof(u16));
1185         buffer.data = data;
1186         buffer.address = cpu_to_be32(offset * 2);
1187
1188         status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
1189                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1190         return status;
1191 }
1192
1193 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1194  *  @hw: pointer to hardware structure
1195  *  @offset: offset of  word in the EEPROM to write
1196  *  @data: word write to the EEPROM
1197  *
1198  *  Write a 16 bit word to the EEPROM using the hostif.
1199  **/
1200 static int ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
1201 {
1202         int status = 0;
1203
1204         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
1205                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1206                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1207         } else {
1208                 hw_dbg(hw, "write ee hostif failed to get semaphore");
1209                 status = -EBUSY;
1210         }
1211
1212         return status;
1213 }
1214
1215 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1216  *  @hw: pointer to hardware structure
1217  *
1218  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1219  **/
1220 static int ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1221 {
1222         union ixgbe_hic_hdr2 buffer;
1223         int status = 0;
1224
1225         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
1226         buffer.req.buf_lenh = 0;
1227         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
1228         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
1229
1230         status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
1231                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1232         return status;
1233 }
1234
1235 /**
1236  * ixgbe_get_bus_info_X550em - Set PCI bus info
1237  * @hw: pointer to hardware structure
1238  *
1239  * Sets bus link width and speed to unknown because X550em is
1240  * not a PCI device.
1241  **/
1242 static int ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
1243 {
1244         hw->bus.type  = ixgbe_bus_type_internal;
1245         hw->bus.width = ixgbe_bus_width_unknown;
1246         hw->bus.speed = ixgbe_bus_speed_unknown;
1247
1248         hw->mac.ops.set_lan_id(hw);
1249
1250         return 0;
1251 }
1252
1253 /**
1254  * ixgbe_fw_recovery_mode_X550 - Check FW NVM recovery mode
1255  * @hw: pointer t hardware structure
1256  *
1257  * Returns true if in FW NVM recovery mode.
1258  */
1259 static bool ixgbe_fw_recovery_mode_X550(struct ixgbe_hw *hw)
1260 {
1261         u32 fwsm;
1262
1263         fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
1264         return !!(fwsm & IXGBE_FWSM_FW_NVM_RECOVERY_MODE);
1265 }
1266
1267 /** ixgbe_disable_rx_x550 - Disable RX unit
1268  *
1269  *  Enables the Rx DMA unit for x550
1270  **/
1271 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
1272 {
1273         struct ixgbe_hic_disable_rxen fw_cmd;
1274         u32 rxctrl, pfdtxgswc;
1275         int status;
1276
1277         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1278         if (rxctrl & IXGBE_RXCTRL_RXEN) {
1279                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
1280                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
1281                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
1282                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
1283                         hw->mac.set_lben = true;
1284                 } else {
1285                         hw->mac.set_lben = false;
1286                 }
1287
1288                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
1289                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
1290                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1291                 fw_cmd.port_number = hw->bus.lan_id;
1292
1293                 status = ixgbe_host_interface_command(hw, &fw_cmd,
1294                                         sizeof(struct ixgbe_hic_disable_rxen),
1295                                         IXGBE_HI_COMMAND_TIMEOUT, true);
1296
1297                 /* If we fail - disable RX using register write */
1298                 if (status) {
1299                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1300                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
1301                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
1302                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
1303                         }
1304                 }
1305         }
1306 }
1307
1308 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1309  *  @hw: pointer to hardware structure
1310  *
1311  *  After writing EEPROM to shadow RAM using EEWR register, software calculates
1312  *  checksum and updates the EEPROM and instructs the hardware to update
1313  *  the flash.
1314  **/
1315 static int ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1316 {
1317         u16 checksum = 0;
1318         int status;
1319
1320         /* Read the first word from the EEPROM. If this times out or fails, do
1321          * not continue or we could be in for a very long wait while every
1322          * EEPROM read fails
1323          */
1324         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1325         if (status) {
1326                 hw_dbg(hw, "EEPROM read failed\n");
1327                 return status;
1328         }
1329
1330         status = ixgbe_calc_eeprom_checksum_X550(hw);
1331         if (status < 0)
1332                 return status;
1333
1334         checksum = (u16)(status & 0xffff);
1335
1336         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1337                                             checksum);
1338         if (status)
1339                 return status;
1340
1341         status = ixgbe_update_flash_X550(hw);
1342
1343         return status;
1344 }
1345
1346 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1347  *  @hw: pointer to hardware structure
1348  *  @offset: offset of  word in the EEPROM to write
1349  *  @words: number of words
1350  *  @data: word(s) write to the EEPROM
1351  *
1352  *
1353  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1354  **/
1355 static int ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1356                                              u16 offset, u16 words,
1357                                              u16 *data)
1358 {
1359         int status = 0;
1360         u32 i = 0;
1361
1362         /* Take semaphore for the entire operation. */
1363         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1364         if (status) {
1365                 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
1366                 return status;
1367         }
1368
1369         for (i = 0; i < words; i++) {
1370                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1371                                                          data[i]);
1372                 if (status) {
1373                         hw_dbg(hw, "Eeprom buffered write failed\n");
1374                         break;
1375                 }
1376         }
1377
1378         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1379
1380         return status;
1381 }
1382
1383 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
1384  *  IOSF device
1385  *
1386  *  @hw: pointer to hardware structure
1387  *  @reg_addr: 32 bit PHY register to write
1388  *  @device_type: 3 bit device type
1389  *  @data: Data to write to the register
1390  **/
1391 static int ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1392                                         u32 device_type, u32 data)
1393 {
1394         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1395         u32 command, error;
1396         int ret;
1397
1398         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
1399         if (ret)
1400                 return ret;
1401
1402         ret = ixgbe_iosf_wait(hw, NULL);
1403         if (ret)
1404                 goto out;
1405
1406         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1407                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1408
1409         /* Write IOSF control register */
1410         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1411
1412         /* Write IOSF data register */
1413         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1414
1415         ret = ixgbe_iosf_wait(hw, &command);
1416
1417         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1418                 error = FIELD_GET(IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK, command);
1419                 hw_dbg(hw, "Failed to write, error %x\n", error);
1420                 return -EIO;
1421         }
1422
1423 out:
1424         hw->mac.ops.release_swfw_sync(hw, gssr);
1425         return ret;
1426 }
1427
1428 /**
1429  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
1430  *  @hw: pointer to hardware structure
1431  *
1432  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
1433  **/
1434 static int ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
1435 {
1436         u32 reg_val;
1437         int status;
1438
1439         /* Disable training protocol FSM. */
1440         status = ixgbe_read_iosf_sb_reg_x550(hw,
1441                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1442                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1443         if (status)
1444                 return status;
1445
1446         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1447         status = ixgbe_write_iosf_sb_reg_x550(hw,
1448                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1449                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1450         if (status)
1451                 return status;
1452
1453         /* Disable Flex from training TXFFE. */
1454         status = ixgbe_read_iosf_sb_reg_x550(hw,
1455                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1456                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1457         if (status)
1458                 return status;
1459
1460         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1461         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1462         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1463         status = ixgbe_write_iosf_sb_reg_x550(hw,
1464                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1465                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1466         if (status)
1467                 return status;
1468
1469         status = ixgbe_read_iosf_sb_reg_x550(hw,
1470                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1471                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1472         if (status)
1473                 return status;
1474
1475         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1476         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1477         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1478         status = ixgbe_write_iosf_sb_reg_x550(hw,
1479                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1480                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1481         if (status)
1482                 return status;
1483
1484         /* Enable override for coefficients. */
1485         status = ixgbe_read_iosf_sb_reg_x550(hw,
1486                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1487                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1488         if (status)
1489                 return status;
1490
1491         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1492         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1493         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1494         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1495         status = ixgbe_write_iosf_sb_reg_x550(hw,
1496                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1497                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1498         return status;
1499 }
1500
1501 /**
1502  *  ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1503  *  internal PHY
1504  *  @hw: pointer to hardware structure
1505  **/
1506 static int ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1507 {
1508         u32 link_ctrl;
1509         int status;
1510
1511         /* Restart auto-negotiation. */
1512         status = hw->mac.ops.read_iosf_sb_reg(hw,
1513                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1514                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1515
1516         if (status) {
1517                 hw_dbg(hw, "Auto-negotiation did not complete\n");
1518                 return status;
1519         }
1520
1521         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1522         status = hw->mac.ops.write_iosf_sb_reg(hw,
1523                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1524                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1525
1526         if (hw->mac.type == ixgbe_mac_x550em_a) {
1527                 u32 flx_mask_st20;
1528
1529                 /* Indicate to FW that AN restart has been asserted */
1530                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1531                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1532                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1533
1534                 if (status) {
1535                         hw_dbg(hw, "Auto-negotiation did not complete\n");
1536                         return status;
1537                 }
1538
1539                 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1540                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1541                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1542                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1543         }
1544
1545         return status;
1546 }
1547
1548 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1549  *  @hw: pointer to hardware structure
1550  *  @speed: the link speed to force
1551  *
1552  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1553  *  internal and external PHY at a specific speed, without autonegotiation.
1554  **/
1555 static int ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1556 {
1557         struct ixgbe_mac_info *mac = &hw->mac;
1558         u32 reg_val;
1559         int status;
1560
1561         /* iXFI is only supported with X552 */
1562         if (mac->type != ixgbe_mac_X550EM_x)
1563                 return -EIO;
1564
1565         /* Disable AN and force speed to 10G Serial. */
1566         status = ixgbe_read_iosf_sb_reg_x550(hw,
1567                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1568                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1569         if (status)
1570                 return status;
1571
1572         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1573         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1574
1575         /* Select forced link speed for internal PHY. */
1576         switch (*speed) {
1577         case IXGBE_LINK_SPEED_10GB_FULL:
1578                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1579                 break;
1580         case IXGBE_LINK_SPEED_1GB_FULL:
1581                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1582                 break;
1583         default:
1584                 /* Other link speeds are not supported by internal KR PHY. */
1585                 return -EINVAL;
1586         }
1587
1588         status = ixgbe_write_iosf_sb_reg_x550(hw,
1589                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1590                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1591         if (status)
1592                 return status;
1593
1594         /* Additional configuration needed for x550em_x */
1595         if (hw->mac.type == ixgbe_mac_X550EM_x) {
1596                 status = ixgbe_setup_ixfi_x550em_x(hw);
1597                 if (status)
1598                         return status;
1599         }
1600
1601         /* Toggle port SW reset by AN reset. */
1602         status = ixgbe_restart_an_internal_phy_x550em(hw);
1603
1604         return status;
1605 }
1606
1607 /**
1608  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1609  *  @hw: pointer to hardware structure
1610  *  @linear: true if SFP module is linear
1611  */
1612 static int ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1613 {
1614         switch (hw->phy.sfp_type) {
1615         case ixgbe_sfp_type_not_present:
1616                 return -ENOENT;
1617         case ixgbe_sfp_type_da_cu_core0:
1618         case ixgbe_sfp_type_da_cu_core1:
1619                 *linear = true;
1620                 break;
1621         case ixgbe_sfp_type_srlr_core0:
1622         case ixgbe_sfp_type_srlr_core1:
1623         case ixgbe_sfp_type_da_act_lmt_core0:
1624         case ixgbe_sfp_type_da_act_lmt_core1:
1625         case ixgbe_sfp_type_1g_sx_core0:
1626         case ixgbe_sfp_type_1g_sx_core1:
1627         case ixgbe_sfp_type_1g_lx_core0:
1628         case ixgbe_sfp_type_1g_lx_core1:
1629                 *linear = false;
1630                 break;
1631         case ixgbe_sfp_type_unknown:
1632         case ixgbe_sfp_type_1g_cu_core0:
1633         case ixgbe_sfp_type_1g_cu_core1:
1634         default:
1635                 return -EOPNOTSUPP;
1636         }
1637
1638         return 0;
1639 }
1640
1641 /**
1642  * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1643  * @hw: pointer to hardware structure
1644  * @speed: the link speed to force
1645  * @autoneg_wait_to_complete: unused
1646  *
1647  * Configures the extern PHY and the integrated KR PHY for SFP support.
1648  */
1649 static int
1650 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1651                                 ixgbe_link_speed speed,
1652                                 __always_unused bool autoneg_wait_to_complete)
1653 {
1654         bool setup_linear = false;
1655         u16 reg_slice, reg_val;
1656         int status;
1657
1658         /* Check if SFP module is supported and linear */
1659         status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1660
1661         /* If no SFP module present, then return success. Return success since
1662          * there is no reason to configure CS4227 and SFP not present error is
1663          * not accepted in the setup MAC link flow.
1664          */
1665         if (status == -ENOENT)
1666                 return 0;
1667
1668         if (status)
1669                 return status;
1670
1671         /* Configure internal PHY for KR/KX. */
1672         ixgbe_setup_kr_speed_x550em(hw, speed);
1673
1674         /* Configure CS4227 LINE side to proper mode. */
1675         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1676         if (setup_linear)
1677                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1678         else
1679                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1680
1681         status = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
1682                                          reg_val);
1683
1684         return status;
1685 }
1686
1687 /**
1688  * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
1689  * @hw: pointer to hardware structure
1690  * @speed: the link speed to force
1691  *
1692  * Configures the integrated PHY for native SFI mode. Used to connect the
1693  * internal PHY directly to an SFP cage, without autonegotiation.
1694  **/
1695 static int ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1696 {
1697         struct ixgbe_mac_info *mac = &hw->mac;
1698         u32 reg_val;
1699         int status;
1700
1701         /* Disable all AN and force speed to 10G Serial. */
1702         status = mac->ops.read_iosf_sb_reg(hw,
1703                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1704                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1705         if (status)
1706                 return status;
1707
1708         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1709         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1710         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1711         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1712
1713         /* Select forced link speed for internal PHY. */
1714         switch (*speed) {
1715         case IXGBE_LINK_SPEED_10GB_FULL:
1716                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
1717                 break;
1718         case IXGBE_LINK_SPEED_1GB_FULL:
1719                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1720                 break;
1721         default:
1722                 /* Other link speeds are not supported by internal PHY. */
1723                 return -EINVAL;
1724         }
1725
1726         status = mac->ops.write_iosf_sb_reg(hw,
1727                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1728                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1729
1730         /* Toggle port SW reset by AN reset. */
1731         status = ixgbe_restart_an_internal_phy_x550em(hw);
1732
1733         return status;
1734 }
1735
1736 /**
1737  * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP
1738  * @hw: pointer to hardware structure
1739  * @speed: link speed
1740  * @autoneg_wait_to_complete: unused
1741  *
1742  * Configure the integrated PHY for native SFP support.
1743  */
1744 static int
1745 ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1746                            __always_unused bool autoneg_wait_to_complete)
1747 {
1748         bool setup_linear = false;
1749         u32 reg_phy_int;
1750         int ret_val;
1751
1752         /* Check if SFP module is supported and linear */
1753         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1754
1755         /* If no SFP module present, then return success. Return success since
1756          * SFP not present error is not excepted in the setup MAC link flow.
1757          */
1758         if (ret_val == -ENOENT)
1759                 return 0;
1760
1761         if (ret_val)
1762                 return ret_val;
1763
1764         /* Configure internal PHY for native SFI based on module type */
1765         ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
1766                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1767                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
1768         if (ret_val)
1769                 return ret_val;
1770
1771         reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
1772         if (!setup_linear)
1773                 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
1774
1775         ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
1776                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1777                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
1778         if (ret_val)
1779                 return ret_val;
1780
1781         /* Setup SFI internal link. */
1782         return ixgbe_setup_sfi_x550a(hw, &speed);
1783 }
1784
1785 /**
1786  * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
1787  * @hw: pointer to hardware structure
1788  * @speed: link speed
1789  * @autoneg_wait_to_complete: unused
1790  *
1791  * Configure the integrated PHY for SFP support.
1792  */
1793 static int
1794 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1795                                __always_unused bool autoneg_wait_to_complete)
1796 {
1797         u32 reg_slice, slice_offset;
1798         bool setup_linear = false;
1799         u16 reg_phy_ext;
1800         int ret_val;
1801
1802         /* Check if SFP module is supported and linear */
1803         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1804
1805         /* If no SFP module present, then return success. Return success since
1806          * SFP not present error is not excepted in the setup MAC link flow.
1807          */
1808         if (ret_val == -ENOENT)
1809                 return 0;
1810
1811         if (ret_val)
1812                 return ret_val;
1813
1814         /* Configure internal PHY for KR/KX. */
1815         ixgbe_setup_kr_speed_x550em(hw, speed);
1816
1817         if (hw->phy.mdio.prtad == MDIO_PRTAD_NONE)
1818                 return -EFAULT;
1819
1820         /* Get external PHY SKU id */
1821         ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
1822                                        IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
1823         if (ret_val)
1824                 return ret_val;
1825
1826         /* When configuring quad port CS4223, the MAC instance is part
1827          * of the slice offset.
1828          */
1829         if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
1830                 slice_offset = (hw->bus.lan_id +
1831                                 (hw->bus.instance_id << 1)) << 12;
1832         else
1833                 slice_offset = hw->bus.lan_id << 12;
1834
1835         /* Configure CS4227/CS4223 LINE side to proper mode. */
1836         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
1837
1838         ret_val = hw->phy.ops.read_reg(hw, reg_slice,
1839                                        IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
1840         if (ret_val)
1841                 return ret_val;
1842
1843         reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
1844                          (IXGBE_CS4227_EDC_MODE_SR << 1));
1845
1846         if (setup_linear)
1847                 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1848         else
1849                 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1850
1851         ret_val = hw->phy.ops.write_reg(hw, reg_slice,
1852                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
1853         if (ret_val)
1854                 return ret_val;
1855
1856         /* Flush previous write with a read */
1857         return hw->phy.ops.read_reg(hw, reg_slice,
1858                                     IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
1859 }
1860
1861 /**
1862  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
1863  * @hw: pointer to hardware structure
1864  * @speed: new link speed
1865  * @autoneg_wait: true when waiting for completion is needed
1866  *
1867  * Setup internal/external PHY link speed based on link speed, then set
1868  * external PHY auto advertised link speed.
1869  *
1870  * Returns error status for any failure
1871  **/
1872 static int ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
1873                                          ixgbe_link_speed speed,
1874                                          bool autoneg_wait)
1875 {
1876         ixgbe_link_speed force_speed;
1877         int status;
1878
1879         /* Setup internal/external PHY link speed to iXFI (10G), unless
1880          * only 1G is auto advertised then setup KX link.
1881          */
1882         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1883                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1884         else
1885                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1886
1887         /* If X552 and internal link mode is XFI, then setup XFI internal link.
1888          */
1889         if (hw->mac.type == ixgbe_mac_X550EM_x &&
1890             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1891                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
1892
1893                 if (status)
1894                         return status;
1895         }
1896
1897         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1898 }
1899
1900 /** ixgbe_check_link_t_X550em - Determine link and speed status
1901   * @hw: pointer to hardware structure
1902   * @speed: pointer to link speed
1903   * @link_up: true when link is up
1904   * @link_up_wait_to_complete: bool used to wait for link up or not
1905   *
1906   * Check that both the MAC and X557 external PHY have link.
1907   **/
1908 static int ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
1909                                      ixgbe_link_speed *speed,
1910                                      bool *link_up,
1911                                      bool link_up_wait_to_complete)
1912 {
1913         u32 status;
1914         u16 i, autoneg_status;
1915
1916         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1917                 return -EIO;
1918
1919         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
1920                                               link_up_wait_to_complete);
1921
1922         /* If check link fails or MAC link is not up, then return */
1923         if (status || !(*link_up))
1924                 return status;
1925
1926         /* MAC link is up, so check external PHY link.
1927          * Link status is latching low, and can only be used to detect link
1928          * drop, and not the current status of the link without performing
1929          * back-to-back reads.
1930          */
1931         for (i = 0; i < 2; i++) {
1932                 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
1933                                               &autoneg_status);
1934
1935                 if (status)
1936                         return status;
1937         }
1938
1939         /* If external PHY link is not up, then indicate link not up */
1940         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1941                 *link_up = false;
1942
1943         return 0;
1944 }
1945
1946 /**
1947  * ixgbe_setup_sgmii - Set up link for sgmii
1948  * @hw: pointer to hardware structure
1949  * @speed: unused
1950  * @autoneg_wait_to_complete: unused
1951  */
1952 static int
1953 ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed,
1954                   __always_unused bool autoneg_wait_to_complete)
1955 {
1956         struct ixgbe_mac_info *mac = &hw->mac;
1957         u32 lval, sval, flx_val;
1958         int rc;
1959
1960         rc = mac->ops.read_iosf_sb_reg(hw,
1961                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1962                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1963         if (rc)
1964                 return rc;
1965
1966         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1967         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1968         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1969         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1970         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1971         rc = mac->ops.write_iosf_sb_reg(hw,
1972                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1973                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1974         if (rc)
1975                 return rc;
1976
1977         rc = mac->ops.read_iosf_sb_reg(hw,
1978                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1979                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1980         if (rc)
1981                 return rc;
1982
1983         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1984         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1985         rc = mac->ops.write_iosf_sb_reg(hw,
1986                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1987                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1988         if (rc)
1989                 return rc;
1990
1991         rc = mac->ops.read_iosf_sb_reg(hw,
1992                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1993                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1994         if (rc)
1995                 return rc;
1996
1997         rc = mac->ops.read_iosf_sb_reg(hw,
1998                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1999                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
2000         if (rc)
2001                 return rc;
2002
2003         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2004         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2005         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2006         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2007         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2008
2009         rc = mac->ops.write_iosf_sb_reg(hw,
2010                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2011                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
2012         if (rc)
2013                 return rc;
2014
2015         rc = ixgbe_restart_an_internal_phy_x550em(hw);
2016         return rc;
2017 }
2018
2019 /**
2020  * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
2021  * @hw: pointer to hardware structure
2022  * @speed: the link speed to force
2023  * @autoneg_wait: true when waiting for completion is needed
2024  */
2025 static int ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
2026                                 bool autoneg_wait)
2027 {
2028         struct ixgbe_mac_info *mac = &hw->mac;
2029         u32 lval, sval, flx_val;
2030         int rc;
2031
2032         rc = mac->ops.read_iosf_sb_reg(hw,
2033                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2034                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
2035         if (rc)
2036                 return rc;
2037
2038         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2039         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2040         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
2041         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
2042         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2043         rc = mac->ops.write_iosf_sb_reg(hw,
2044                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2045                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
2046         if (rc)
2047                 return rc;
2048
2049         rc = mac->ops.read_iosf_sb_reg(hw,
2050                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2051                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
2052         if (rc)
2053                 return rc;
2054
2055         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
2056         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
2057         rc = mac->ops.write_iosf_sb_reg(hw,
2058                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2059                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
2060         if (rc)
2061                 return rc;
2062
2063         rc = mac->ops.write_iosf_sb_reg(hw,
2064                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2065                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
2066         if (rc)
2067                 return rc;
2068
2069         rc = mac->ops.read_iosf_sb_reg(hw,
2070                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2071                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
2072         if (rc)
2073                 return rc;
2074
2075         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2076         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2077         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2078         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2079         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2080
2081         rc = mac->ops.write_iosf_sb_reg(hw,
2082                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2083                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
2084         if (rc)
2085                 return rc;
2086
2087         ixgbe_restart_an_internal_phy_x550em(hw);
2088
2089         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
2090 }
2091
2092 /**
2093  * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
2094  * @hw: pointer to hardware structure
2095  *
2096  * Enable flow control according to IEEE clause 37.
2097  */
2098 static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
2099 {
2100         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
2101         ixgbe_link_speed speed;
2102         int status = -EIO;
2103         bool link_up;
2104
2105         /* AN should have completed when the cable was plugged in.
2106          * Look for reasons to bail out.  Bail out if:
2107          * - FC autoneg is disabled, or if
2108          * - link is not up.
2109          */
2110         if (hw->fc.disable_fc_autoneg)
2111                 goto out;
2112
2113         hw->mac.ops.check_link(hw, &speed, &link_up, false);
2114         if (!link_up)
2115                 goto out;
2116
2117         /* Check if auto-negotiation has completed */
2118         status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
2119         if (status || !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
2120                 status = -EIO;
2121                 goto out;
2122         }
2123
2124         /* Negotiate the flow control */
2125         status = ixgbe_negotiate_fc(hw, info[0], info[0],
2126                                     FW_PHY_ACT_GET_LINK_INFO_FC_RX,
2127                                     FW_PHY_ACT_GET_LINK_INFO_FC_TX,
2128                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
2129                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
2130
2131 out:
2132         if (!status) {
2133                 hw->fc.fc_was_autonegged = true;
2134         } else {
2135                 hw->fc.fc_was_autonegged = false;
2136                 hw->fc.current_mode = hw->fc.requested_mode;
2137         }
2138 }
2139
2140 /** ixgbe_init_mac_link_ops_X550em_a - Init mac link function pointers
2141  *  @hw: pointer to hardware structure
2142  **/
2143 static void ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw *hw)
2144 {
2145         struct ixgbe_mac_info *mac = &hw->mac;
2146
2147         switch (mac->ops.get_media_type(hw)) {
2148         case ixgbe_media_type_fiber:
2149                 mac->ops.setup_fc = NULL;
2150                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
2151                 break;
2152         case ixgbe_media_type_copper:
2153                 if (hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T &&
2154                     hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T_L) {
2155                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2156                         break;
2157                 }
2158                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
2159                 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
2160                 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
2161                 mac->ops.check_link = ixgbe_check_mac_link_generic;
2162                 break;
2163         case ixgbe_media_type_backplane:
2164                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
2165                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
2166                 break;
2167         default:
2168                 break;
2169         }
2170 }
2171
2172 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
2173  *  @hw: pointer to hardware structure
2174  **/
2175 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
2176 {
2177         struct ixgbe_mac_info *mac = &hw->mac;
2178
2179         mac->ops.setup_fc = ixgbe_setup_fc_x550em;
2180
2181         switch (mac->ops.get_media_type(hw)) {
2182         case ixgbe_media_type_fiber:
2183                 /* CS4227 does not support autoneg, so disable the laser control
2184                  * functions for SFP+ fiber
2185                  */
2186                 mac->ops.disable_tx_laser = NULL;
2187                 mac->ops.enable_tx_laser = NULL;
2188                 mac->ops.flap_tx_laser = NULL;
2189                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
2190                 switch (hw->device_id) {
2191                 case IXGBE_DEV_ID_X550EM_A_SFP_N:
2192                         mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n;
2193                         break;
2194                 case IXGBE_DEV_ID_X550EM_A_SFP:
2195                         mac->ops.setup_mac_link =
2196                                                 ixgbe_setup_mac_link_sfp_x550a;
2197                         break;
2198                 default:
2199                         mac->ops.setup_mac_link =
2200                                                 ixgbe_setup_mac_link_sfp_x550em;
2201                         break;
2202                 }
2203                 mac->ops.set_rate_select_speed =
2204                                         ixgbe_set_soft_rate_select_speed;
2205                 break;
2206         case ixgbe_media_type_copper:
2207                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T)
2208                         break;
2209                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2210                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
2211                 mac->ops.check_link = ixgbe_check_link_t_X550em;
2212                 break;
2213         case ixgbe_media_type_backplane:
2214                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
2215                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
2216                         mac->ops.setup_link = ixgbe_setup_sgmii;
2217                 break;
2218         default:
2219                 break;
2220         }
2221
2222         /* Additional modification for X550em_a devices */
2223         if (hw->mac.type == ixgbe_mac_x550em_a)
2224                 ixgbe_init_mac_link_ops_X550em_a(hw);
2225 }
2226
2227 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module
2228  * @hw: pointer to hardware structure
2229  */
2230 static int ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
2231 {
2232         bool linear;
2233         int status;
2234
2235         /* Check if SFP module is supported */
2236         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
2237         if (status)
2238                 return status;
2239
2240         ixgbe_init_mac_link_ops_X550em(hw);
2241         hw->phy.ops.reset = NULL;
2242
2243         return 0;
2244 }
2245
2246 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities
2247  * @hw: pointer to hardware structure
2248  * @speed: pointer to link speed
2249  * @autoneg: true when autoneg or autotry is enabled
2250  **/
2251 static int ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
2252                                               ixgbe_link_speed *speed,
2253                                               bool *autoneg)
2254 {
2255         if (hw->phy.type == ixgbe_phy_fw) {
2256                 *autoneg = true;
2257                 *speed = hw->phy.speeds_supported;
2258                 return 0;
2259         }
2260
2261         /* SFP */
2262         if (hw->phy.media_type == ixgbe_media_type_fiber) {
2263                 /* CS4227 SFP must not enable auto-negotiation */
2264                 *autoneg = false;
2265
2266                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
2267                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
2268                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
2269                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
2270                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2271                         return 0;
2272                 }
2273
2274                 /* Link capabilities are based on SFP */
2275                 if (hw->phy.multispeed_fiber)
2276                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
2277                                  IXGBE_LINK_SPEED_1GB_FULL;
2278                 else
2279                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
2280         } else {
2281                 switch (hw->phy.type) {
2282                 case ixgbe_phy_x550em_kx4:
2283                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
2284                                  IXGBE_LINK_SPEED_2_5GB_FULL |
2285                                  IXGBE_LINK_SPEED_10GB_FULL;
2286                         break;
2287                 case ixgbe_phy_x550em_xfi:
2288                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
2289                                  IXGBE_LINK_SPEED_10GB_FULL;
2290                         break;
2291                 case ixgbe_phy_ext_1g_t:
2292                 case ixgbe_phy_sgmii:
2293                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2294                         break;
2295                 case ixgbe_phy_x550em_kr:
2296                         if (hw->mac.type == ixgbe_mac_x550em_a) {
2297                                 /* check different backplane modes */
2298                                 if (hw->phy.nw_mng_if_sel &
2299                                     IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
2300                                         *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
2301                                         break;
2302                                 } else if (hw->device_id ==
2303                                            IXGBE_DEV_ID_X550EM_A_KR_L) {
2304                                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2305                                         break;
2306                                 }
2307                         }
2308                         fallthrough;
2309                 default:
2310                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
2311                                  IXGBE_LINK_SPEED_1GB_FULL;
2312                         break;
2313                 }
2314                 *autoneg = true;
2315         }
2316         return 0;
2317 }
2318
2319 /**
2320  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2321  * @hw: pointer to hardware structure
2322  * @lsc: pointer to boolean flag which indicates whether external Base T
2323  *       PHY interrupt is lsc
2324  * @is_overtemp: indicate whether an overtemp event encountered
2325  *
2326  * Determime if external Base T PHY interrupt cause is high temperature
2327  * failure alarm or link status change.
2328  **/
2329 static int ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc,
2330                                        bool *is_overtemp)
2331 {
2332         u32 status;
2333         u16 reg;
2334
2335         *is_overtemp = false;
2336         *lsc = false;
2337
2338         /* Vendor alarm triggered */
2339         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2340                                       MDIO_MMD_VEND1,
2341                                       &reg);
2342
2343         if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2344                 return status;
2345
2346         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2347         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2348                                       MDIO_MMD_VEND1,
2349                                       &reg);
2350
2351         if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2352                                 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2353                 return status;
2354
2355         /* Global alarm triggered */
2356         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2357                                       MDIO_MMD_VEND1,
2358                                       &reg);
2359
2360         if (status)
2361                 return status;
2362
2363         /* If high temperature failure, then return over temp error and exit */
2364         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2365                 /* power down the PHY in case the PHY FW didn't already */
2366                 ixgbe_set_copper_phy_power(hw, false);
2367                 *is_overtemp = true;
2368                 return -EIO;
2369         }
2370         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2371                 /*  device fault alarm triggered */
2372                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2373                                           MDIO_MMD_VEND1,
2374                                           &reg);
2375                 if (status)
2376                         return status;
2377
2378                 /* if device fault was due to high temp alarm handle and exit */
2379                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2380                         /* power down the PHY in case the PHY FW didn't */
2381                         ixgbe_set_copper_phy_power(hw, false);
2382                         *is_overtemp = true;
2383                         return -EIO;
2384                 }
2385         }
2386
2387         /* Vendor alarm 2 triggered */
2388         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2389                                       MDIO_MMD_AN, &reg);
2390
2391         if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2392                 return status;
2393
2394         /* link connect/disconnect event occurred */
2395         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2396                                       MDIO_MMD_AN, &reg);
2397
2398         if (status)
2399                 return status;
2400
2401         /* Indicate LSC */
2402         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2403                 *lsc = true;
2404
2405         return 0;
2406 }
2407
2408 /**
2409  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2410  * @hw: pointer to hardware structure
2411  *
2412  * Enable link status change and temperature failure alarm for the external
2413  * Base T PHY
2414  *
2415  * Returns PHY access status
2416  **/
2417 static int ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2418 {
2419         bool lsc, overtemp;
2420         u32 status;
2421         u16 reg;
2422
2423         /* Clear interrupt flags */
2424         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc, &overtemp);
2425
2426         /* Enable link status change alarm */
2427
2428         /* Enable the LASI interrupts on X552 devices to receive notifications
2429          * of the link configurations of the external PHY and correspondingly
2430          * support the configuration of the internal iXFI link, since iXFI does
2431          * not support auto-negotiation. This is not required for X553 devices
2432          * having KR support, which performs auto-negotiations and which is used
2433          * as the internal link to the external PHY. Hence adding a check here
2434          * to avoid enabling LASI interrupts for X553 devices.
2435          */
2436         if (hw->mac.type != ixgbe_mac_x550em_a) {
2437                 status = hw->phy.ops.read_reg(hw,
2438                                             IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2439                                             MDIO_MMD_AN, &reg);
2440                 if (status)
2441                         return status;
2442
2443                 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2444
2445                 status = hw->phy.ops.write_reg(hw,
2446                                             IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2447                                             MDIO_MMD_AN, reg);
2448                 if (status)
2449                         return status;
2450         }
2451
2452         /* Enable high temperature failure and global fault alarms */
2453         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2454                                       MDIO_MMD_VEND1,
2455                                       &reg);
2456         if (status)
2457                 return status;
2458
2459         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2460                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2461
2462         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2463                                        MDIO_MMD_VEND1,
2464                                        reg);
2465         if (status)
2466                 return status;
2467
2468         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2469         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2470                                       MDIO_MMD_VEND1,
2471                                       &reg);
2472         if (status)
2473                 return status;
2474
2475         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2476                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2477
2478         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2479                                        MDIO_MMD_VEND1,
2480                                        reg);
2481         if (status)
2482                 return status;
2483
2484         /* Enable chip-wide vendor alarm */
2485         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2486                                       MDIO_MMD_VEND1,
2487                                       &reg);
2488         if (status)
2489                 return status;
2490
2491         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2492
2493         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2494                                        MDIO_MMD_VEND1,
2495                                        reg);
2496
2497         return status;
2498 }
2499
2500 /**
2501  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2502  * @hw: pointer to hardware structure
2503  * @is_overtemp: indicate whether an overtemp event encountered
2504  *
2505  * Handle external Base T PHY interrupt. If high temperature
2506  * failure alarm then return error, else if link status change
2507  * then setup internal/external PHY link
2508  **/
2509 static int ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw,
2510                                           bool *is_overtemp)
2511 {
2512         struct ixgbe_phy_info *phy = &hw->phy;
2513         bool lsc;
2514         u32 status;
2515
2516         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc, is_overtemp);
2517         if (status)
2518                 return status;
2519
2520         if (lsc && phy->ops.setup_internal_link)
2521                 return phy->ops.setup_internal_link(hw);
2522
2523         return 0;
2524 }
2525
2526 /**
2527  * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2528  * @hw: pointer to hardware structure
2529  * @speed: link speed
2530  *
2531  * Configures the integrated KR PHY.
2532  **/
2533 static int ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2534                                        ixgbe_link_speed speed)
2535 {
2536         u32 reg_val;
2537         int status;
2538
2539         status = hw->mac.ops.read_iosf_sb_reg(hw,
2540                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2541                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2542         if (status)
2543                 return status;
2544
2545         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2546         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2547                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2548
2549         /* Advertise 10G support. */
2550         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2551                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2552
2553         /* Advertise 1G support. */
2554         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2555                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2556
2557         status = hw->mac.ops.write_iosf_sb_reg(hw,
2558                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2559                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2560
2561         if (hw->mac.type == ixgbe_mac_x550em_a) {
2562                 /* Set lane mode  to KR auto negotiation */
2563                 status = hw->mac.ops.read_iosf_sb_reg(hw,
2564                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2565                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2566
2567                 if (status)
2568                         return status;
2569
2570                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2571                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2572                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2573                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2574                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2575
2576                 status = hw->mac.ops.write_iosf_sb_reg(hw,
2577                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2578                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2579         }
2580
2581         return ixgbe_restart_an_internal_phy_x550em(hw);
2582 }
2583
2584 /**
2585  * ixgbe_setup_kr_x550em - Configure the KR PHY
2586  * @hw: pointer to hardware structure
2587  **/
2588 static int ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2589 {
2590         /* leave link alone for 2.5G */
2591         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2592                 return 0;
2593
2594         if (ixgbe_check_reset_blocked(hw))
2595                 return 0;
2596
2597         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2598 }
2599
2600 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2601  *  @hw: address of hardware structure
2602  *  @link_up: address of boolean to indicate link status
2603  *
2604  *  Returns error code if unable to get link status.
2605  **/
2606 static int ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2607 {
2608         u32 ret;
2609         u16 autoneg_status;
2610
2611         *link_up = false;
2612
2613         /* read this twice back to back to indicate current status */
2614         ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2615                                    &autoneg_status);
2616         if (ret)
2617                 return ret;
2618
2619         ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2620                                    &autoneg_status);
2621         if (ret)
2622                 return ret;
2623
2624         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2625
2626         return 0;
2627 }
2628
2629 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2630  *  @hw: point to hardware structure
2631  *
2632  *  Configures the link between the integrated KR PHY and the external X557 PHY
2633  *  The driver will call this function when it gets a link status change
2634  *  interrupt from the X557 PHY. This function configures the link speed
2635  *  between the PHYs to match the link speed of the BASE-T link.
2636  *
2637  * A return of a non-zero value indicates an error, and the base driver should
2638  * not report link up.
2639  **/
2640 static int ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2641 {
2642         ixgbe_link_speed force_speed;
2643         bool link_up;
2644         u32 status;
2645         u16 speed;
2646
2647         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2648                 return -EIO;
2649
2650         if (!(hw->mac.type == ixgbe_mac_X550EM_x &&
2651               !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))) {
2652                 speed = IXGBE_LINK_SPEED_10GB_FULL |
2653                         IXGBE_LINK_SPEED_1GB_FULL;
2654                 return ixgbe_setup_kr_speed_x550em(hw, speed);
2655         }
2656
2657         /* If link is not up, then there is no setup necessary so return  */
2658         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2659         if (status)
2660                 return status;
2661
2662         if (!link_up)
2663                 return 0;
2664
2665         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2666                                       MDIO_MMD_AN,
2667                                       &speed);
2668         if (status)
2669                 return status;
2670
2671         /* If link is not still up, then no setup is necessary so return */
2672         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2673         if (status)
2674                 return status;
2675
2676         if (!link_up)
2677                 return 0;
2678
2679         /* clear everything but the speed and duplex bits */
2680         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2681
2682         switch (speed) {
2683         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2684                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2685                 break;
2686         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2687                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2688                 break;
2689         default:
2690                 /* Internal PHY does not support anything else */
2691                 return -EINVAL;
2692         }
2693
2694         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2695 }
2696
2697 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2698  *  @hw: pointer to hardware structure
2699  **/
2700 static int ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2701 {
2702         int status;
2703
2704         status = ixgbe_reset_phy_generic(hw);
2705
2706         if (status)
2707                 return status;
2708
2709         /* Configure Link Status Alarm and Temperature Threshold interrupts */
2710         return ixgbe_enable_lasi_ext_t_x550em(hw);
2711 }
2712
2713 /**
2714  *  ixgbe_led_on_t_x550em - Turns on the software controllable LEDs.
2715  *  @hw: pointer to hardware structure
2716  *  @led_idx: led number to turn on
2717  **/
2718 static int ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2719 {
2720         u16 phy_data;
2721
2722         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2723                 return -EINVAL;
2724
2725         /* To turn on the LED, set mode to ON. */
2726         hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2727                              MDIO_MMD_VEND1, &phy_data);
2728         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
2729         hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2730                               MDIO_MMD_VEND1, phy_data);
2731
2732         return 0;
2733 }
2734
2735 /**
2736  *  ixgbe_led_off_t_x550em - Turns off the software controllable LEDs.
2737  *  @hw: pointer to hardware structure
2738  *  @led_idx: led number to turn off
2739  **/
2740 static int ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2741 {
2742         u16 phy_data;
2743
2744         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2745                 return -EINVAL;
2746
2747         /* To turn on the LED, set mode to ON. */
2748         hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2749                              MDIO_MMD_VEND1, &phy_data);
2750         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
2751         hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2752                               MDIO_MMD_VEND1, phy_data);
2753
2754         return 0;
2755 }
2756
2757 /**
2758  *  ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
2759  *  @hw: pointer to the HW structure
2760  *  @maj: driver version major number
2761  *  @min: driver version minor number
2762  *  @build: driver version build number
2763  *  @sub: driver version sub build number
2764  *  @len: length of driver_ver string
2765  *  @driver_ver: driver string
2766  *
2767  *  Sends driver version number to firmware through the manageability
2768  *  block.  On success return 0
2769  *  else returns -EBUSY when encountering an error acquiring
2770  *  semaphore, -EIO when command fails or -ENIVAL when incorrect
2771  *  params passed.
2772  **/
2773 static int ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
2774                                      u8 build, u8 sub, u16 len,
2775                                      const char *driver_ver)
2776 {
2777         struct ixgbe_hic_drv_info2 fw_cmd;
2778         int ret_val;
2779         int i;
2780
2781         if (!len || !driver_ver || (len > sizeof(fw_cmd.driver_string)))
2782                 return -EINVAL;
2783
2784         fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
2785         fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
2786         fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
2787         fw_cmd.port_num = (u8)hw->bus.func;
2788         fw_cmd.ver_maj = maj;
2789         fw_cmd.ver_min = min;
2790         fw_cmd.ver_build = build;
2791         fw_cmd.ver_sub = sub;
2792         fw_cmd.hdr.checksum = 0;
2793         memcpy(fw_cmd.driver_string, driver_ver, len);
2794         fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
2795                               (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
2796
2797         for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
2798                 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2799                                                        sizeof(fw_cmd),
2800                                                        IXGBE_HI_COMMAND_TIMEOUT,
2801                                                        true);
2802                 if (ret_val)
2803                         continue;
2804
2805                 if (fw_cmd.hdr.cmd_or_resp.ret_status !=
2806                     FW_CEM_RESP_STATUS_SUCCESS)
2807                         return -EIO;
2808                 return 0;
2809         }
2810
2811         return ret_val;
2812 }
2813
2814 /** ixgbe_get_lcd_x550em - Determine lowest common denominator
2815  *  @hw: pointer to hardware structure
2816  *  @lcd_speed: pointer to lowest common link speed
2817  *
2818  *  Determine lowest common link speed with link partner.
2819  **/
2820 static int ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
2821                                   ixgbe_link_speed *lcd_speed)
2822 {
2823         u16 word = hw->eeprom.ctrl_word_3;
2824         u16 an_lp_status;
2825         int status;
2826
2827         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2828
2829         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2830                                       MDIO_MMD_AN,
2831                                       &an_lp_status);
2832         if (status)
2833                 return status;
2834
2835         /* If link partner advertised 1G, return 1G */
2836         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2837                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2838                 return 0;
2839         }
2840
2841         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2842         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2843             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2844                 return 0;
2845
2846         /* Link partner not capable of lower speeds, return 10G */
2847         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2848         return 0;
2849 }
2850
2851 /**
2852  * ixgbe_setup_fc_x550em - Set up flow control
2853  * @hw: pointer to hardware structure
2854  */
2855 static int ixgbe_setup_fc_x550em(struct ixgbe_hw *hw)
2856 {
2857         bool pause, asm_dir;
2858         u32 reg_val;
2859         int rc = 0;
2860
2861         /* Validate the requested mode */
2862         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2863                 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2864                 return -EINVAL;
2865         }
2866
2867         /* 10gig parts do not have a word in the EEPROM to determine the
2868          * default flow control setting, so we explicitly set it to full.
2869          */
2870         if (hw->fc.requested_mode == ixgbe_fc_default)
2871                 hw->fc.requested_mode = ixgbe_fc_full;
2872
2873         /* Determine PAUSE and ASM_DIR bits. */
2874         switch (hw->fc.requested_mode) {
2875         case ixgbe_fc_none:
2876                 pause = false;
2877                 asm_dir = false;
2878                 break;
2879         case ixgbe_fc_tx_pause:
2880                 pause = false;
2881                 asm_dir = true;
2882                 break;
2883         case ixgbe_fc_rx_pause:
2884                 /* Rx Flow control is enabled and Tx Flow control is
2885                  * disabled by software override. Since there really
2886                  * isn't a way to advertise that we are capable of RX
2887                  * Pause ONLY, we will advertise that we support both
2888                  * symmetric and asymmetric Rx PAUSE, as such we fall
2889                  * through to the fc_full statement.  Later, we will
2890                  * disable the adapter's ability to send PAUSE frames.
2891                  */
2892                 fallthrough;
2893         case ixgbe_fc_full:
2894                 pause = true;
2895                 asm_dir = true;
2896                 break;
2897         default:
2898                 hw_err(hw, "Flow control param set incorrectly\n");
2899                 return -EIO;
2900         }
2901
2902         switch (hw->device_id) {
2903         case IXGBE_DEV_ID_X550EM_X_KR:
2904         case IXGBE_DEV_ID_X550EM_A_KR:
2905         case IXGBE_DEV_ID_X550EM_A_KR_L:
2906                 rc = hw->mac.ops.read_iosf_sb_reg(hw,
2907                                             IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2908                                             IXGBE_SB_IOSF_TARGET_KR_PHY,
2909                                             &reg_val);
2910                 if (rc)
2911                         return rc;
2912
2913                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2914                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2915                 if (pause)
2916                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2917                 if (asm_dir)
2918                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2919                 rc = hw->mac.ops.write_iosf_sb_reg(hw,
2920                                             IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2921                                             IXGBE_SB_IOSF_TARGET_KR_PHY,
2922                                             reg_val);
2923
2924                 /* This device does not fully support AN. */
2925                 hw->fc.disable_fc_autoneg = true;
2926                 break;
2927         case IXGBE_DEV_ID_X550EM_X_XFI:
2928                 hw->fc.disable_fc_autoneg = true;
2929                 break;
2930         default:
2931                 break;
2932         }
2933         return rc;
2934 }
2935
2936 /**
2937  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
2938  *  @hw: pointer to hardware structure
2939  **/
2940 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
2941 {
2942         u32 link_s1, lp_an_page_low, an_cntl_1;
2943         ixgbe_link_speed speed;
2944         int status = -EIO;
2945         bool link_up;
2946
2947         /* AN should have completed when the cable was plugged in.
2948          * Look for reasons to bail out.  Bail out if:
2949          * - FC autoneg is disabled, or if
2950          * - link is not up.
2951          */
2952         if (hw->fc.disable_fc_autoneg) {
2953                 hw_err(hw, "Flow control autoneg is disabled");
2954                 goto out;
2955         }
2956
2957         hw->mac.ops.check_link(hw, &speed, &link_up, false);
2958         if (!link_up) {
2959                 hw_err(hw, "The link is down");
2960                 goto out;
2961         }
2962
2963         /* Check at auto-negotiation has completed */
2964         status = hw->mac.ops.read_iosf_sb_reg(hw,
2965                                         IXGBE_KRM_LINK_S1(hw->bus.lan_id),
2966                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
2967
2968         if (status || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
2969                 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2970                 status = -EIO;
2971                 goto out;
2972         }
2973
2974         /* Read the 10g AN autoc and LP ability registers and resolve
2975          * local flow control settings accordingly
2976          */
2977         status = hw->mac.ops.read_iosf_sb_reg(hw,
2978                                 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2979                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
2980
2981         if (status) {
2982                 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2983                 goto out;
2984         }
2985
2986         status = hw->mac.ops.read_iosf_sb_reg(hw,
2987                                 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
2988                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
2989
2990         if (status) {
2991                 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2992                 goto out;
2993         }
2994
2995         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
2996                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
2997                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
2998                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
2999                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
3000
3001 out:
3002         if (!status) {
3003                 hw->fc.fc_was_autonegged = true;
3004         } else {
3005                 hw->fc.fc_was_autonegged = false;
3006                 hw->fc.current_mode = hw->fc.requested_mode;
3007         }
3008 }
3009
3010 /**
3011  *  ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
3012  *  @hw: pointer to hardware structure
3013  **/
3014 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
3015 {
3016         hw->fc.fc_was_autonegged = false;
3017         hw->fc.current_mode = hw->fc.requested_mode;
3018 }
3019
3020 /** ixgbe_enter_lplu_x550em - Transition to low power states
3021  *  @hw: pointer to hardware structure
3022  *
3023  *  Configures Low Power Link Up on transition to low power states
3024  *  (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
3025  *  the X557 PHY immediately prior to entering LPLU.
3026  **/
3027 static int ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3028 {
3029         u16 an_10g_cntl_reg, autoneg_reg, speed;
3030         ixgbe_link_speed lcd_speed;
3031         u32 save_autoneg;
3032         bool link_up;
3033         int status;
3034
3035         /* If blocked by MNG FW, then don't restart AN */
3036         if (ixgbe_check_reset_blocked(hw))
3037                 return 0;
3038
3039         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3040         if (status)
3041                 return status;
3042
3043         status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
3044                                      &hw->eeprom.ctrl_word_3);
3045         if (status)
3046                 return status;
3047
3048         /* If link is down, LPLU disabled in NVM, WoL disabled, or
3049          * manageability disabled, then force link down by entering
3050          * low power mode.
3051          */
3052         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3053             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3054                 return ixgbe_set_copper_phy_power(hw, false);
3055
3056         /* Determine LCD */
3057         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3058         if (status)
3059                 return status;
3060
3061         /* If no valid LCD link speed, then force link down and exit. */
3062         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3063                 return ixgbe_set_copper_phy_power(hw, false);
3064
3065         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3066                                       MDIO_MMD_AN,
3067                                       &speed);
3068         if (status)
3069                 return status;
3070
3071         /* If no link now, speed is invalid so take link down */
3072         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3073         if (status)
3074                 return ixgbe_set_copper_phy_power(hw, false);
3075
3076         /* clear everything but the speed bits */
3077         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3078
3079         /* If current speed is already LCD, then exit. */
3080         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3081              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3082             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3083              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3084                 return 0;
3085
3086         /* Clear AN completed indication */
3087         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3088                                       MDIO_MMD_AN,
3089                                       &autoneg_reg);
3090         if (status)
3091                 return status;
3092
3093         status = hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
3094                                       MDIO_MMD_AN,
3095                                       &an_10g_cntl_reg);
3096         if (status)
3097                 return status;
3098
3099         status = hw->phy.ops.read_reg(hw,
3100                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3101                                       MDIO_MMD_AN,
3102                                       &autoneg_reg);
3103         if (status)
3104                 return status;
3105
3106         save_autoneg = hw->phy.autoneg_advertised;
3107
3108         /* Setup link at least common link speed */
3109         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3110
3111         /* restore autoneg from before setting lplu speed */
3112         hw->phy.autoneg_advertised = save_autoneg;
3113
3114         return status;
3115 }
3116
3117 /**
3118  * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
3119  * @hw: pointer to hardware structure
3120  */
3121 static int ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
3122 {
3123         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
3124         int rc;
3125
3126         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
3127                 return 0;
3128
3129         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
3130         if (rc)
3131                 return rc;
3132         memset(store, 0, sizeof(store));
3133
3134         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
3135         if (rc)
3136                 return rc;
3137
3138         return ixgbe_setup_fw_link(hw);
3139 }
3140
3141 /**
3142  * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
3143  * @hw: pointer to hardware structure
3144  *
3145  * Return true when an overtemp event detected, otherwise false.
3146  */
3147 static bool ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
3148 {
3149         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
3150         int rc;
3151
3152         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
3153         if (rc)
3154                 return false;
3155
3156         if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
3157                 ixgbe_shutdown_fw_phy(hw);
3158                 return true;
3159         }
3160         return false;
3161 }
3162
3163 /**
3164  * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
3165  * @hw: pointer to hardware structure
3166  *
3167  * Read NW_MNG_IF_SEL register and save field values.
3168  */
3169 static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
3170 {
3171         /* Save NW management interface connected on board. This is used
3172          * to determine internal PHY mode.
3173          */
3174         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
3175
3176         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
3177          * PHY address. This register field was has only been used for X552.
3178          */
3179         if (hw->mac.type == ixgbe_mac_x550em_a &&
3180             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
3181                 hw->phy.mdio.prtad = FIELD_GET(IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD,
3182                                                hw->phy.nw_mng_if_sel);
3183         }
3184 }
3185
3186 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
3187  *  @hw: pointer to hardware structure
3188  *
3189  *  Initialize any function pointers that were not able to be
3190  *  set during init_shared_code because the PHY/SFP type was
3191  *  not known.  Perform the SFP init if necessary.
3192  **/
3193 static int ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
3194 {
3195         struct ixgbe_phy_info *phy = &hw->phy;
3196         int ret_val;
3197
3198         hw->mac.ops.set_lan_id(hw);
3199
3200         ixgbe_read_mng_if_sel_x550em(hw);
3201
3202         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
3203                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
3204                 ixgbe_setup_mux_ctl(hw);
3205         }
3206
3207         /* Identify the PHY or SFP module */
3208         ret_val = phy->ops.identify(hw);
3209         if (ret_val == -EOPNOTSUPP || ret_val == -EFAULT)
3210                 return ret_val;
3211
3212         /* Setup function pointers based on detected hardware */
3213         ixgbe_init_mac_link_ops_X550em(hw);
3214         if (phy->sfp_type != ixgbe_sfp_type_unknown)
3215                 phy->ops.reset = NULL;
3216
3217         /* Set functions pointers based on phy type */
3218         switch (hw->phy.type) {
3219         case ixgbe_phy_x550em_kx4:
3220                 phy->ops.setup_link = NULL;
3221                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3222                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3223                 break;
3224         case ixgbe_phy_x550em_kr:
3225                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
3226                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3227                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3228                 break;
3229         case ixgbe_phy_x550em_xfi:
3230                 /* link is managed by HW */
3231                 phy->ops.setup_link = NULL;
3232                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3233                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3234                 break;
3235         case ixgbe_phy_x550em_ext_t:
3236                 /* Save NW management interface connected on board. This is used
3237                  * to determine internal PHY mode
3238                  */
3239                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
3240
3241                 /* If internal link mode is XFI, then setup iXFI internal link,
3242                  * else setup KR now.
3243                  */
3244                 phy->ops.setup_internal_link =
3245                                               ixgbe_setup_internal_phy_t_x550em;
3246
3247                 /* setup SW LPLU only for first revision */
3248                 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3249                     !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) &
3250                       IXGBE_FUSES0_REV_MASK))
3251                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
3252
3253                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
3254                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
3255                 break;
3256         case ixgbe_phy_sgmii:
3257                 phy->ops.setup_link = NULL;
3258                 break;
3259         case ixgbe_phy_fw:
3260                 phy->ops.setup_link = ixgbe_setup_fw_link;
3261                 phy->ops.reset = ixgbe_reset_phy_fw;
3262                 break;
3263         case ixgbe_phy_ext_1g_t:
3264                 phy->ops.setup_link = NULL;
3265                 phy->ops.read_reg = NULL;
3266                 phy->ops.write_reg = NULL;
3267                 phy->ops.reset = NULL;
3268                 break;
3269         default:
3270                 break;
3271         }
3272
3273         return ret_val;
3274 }
3275
3276 /** ixgbe_get_media_type_X550em - Get media type
3277  *  @hw: pointer to hardware structure
3278  *
3279  *  Returns the media type (fiber, copper, backplane)
3280  *
3281  */
3282 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
3283 {
3284         enum ixgbe_media_type media_type;
3285
3286         /* Detect if there is a copper PHY attached. */
3287         switch (hw->device_id) {
3288         case IXGBE_DEV_ID_X550EM_A_SGMII:
3289         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
3290                 hw->phy.type = ixgbe_phy_sgmii;
3291                 fallthrough;
3292         case IXGBE_DEV_ID_X550EM_X_KR:
3293         case IXGBE_DEV_ID_X550EM_X_KX4:
3294         case IXGBE_DEV_ID_X550EM_X_XFI:
3295         case IXGBE_DEV_ID_X550EM_A_KR:
3296         case IXGBE_DEV_ID_X550EM_A_KR_L:
3297                 media_type = ixgbe_media_type_backplane;
3298                 break;
3299         case IXGBE_DEV_ID_X550EM_X_SFP:
3300         case IXGBE_DEV_ID_X550EM_A_SFP:
3301         case IXGBE_DEV_ID_X550EM_A_SFP_N:
3302                 media_type = ixgbe_media_type_fiber;
3303                 break;
3304         case IXGBE_DEV_ID_X550EM_X_1G_T:
3305         case IXGBE_DEV_ID_X550EM_X_10G_T:
3306         case IXGBE_DEV_ID_X550EM_A_10G_T:
3307         case IXGBE_DEV_ID_X550EM_A_1G_T:
3308         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
3309                 media_type = ixgbe_media_type_copper;
3310                 break;
3311         default:
3312                 media_type = ixgbe_media_type_unknown;
3313                 break;
3314         }
3315         return media_type;
3316 }
3317
3318 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
3319  ** @hw: pointer to hardware structure
3320  **/
3321 static int ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
3322 {
3323         int status;
3324         u16 reg;
3325
3326         status = hw->phy.ops.read_reg(hw,
3327                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
3328                                       MDIO_MMD_PMAPMD,
3329                                       &reg);
3330         if (status)
3331                 return status;
3332
3333         /* If PHY FW reset completed bit is set then this is the first
3334          * SW instance after a power on so the PHY FW must be un-stalled.
3335          */
3336         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
3337                 status = hw->phy.ops.read_reg(hw,
3338                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
3339                                         MDIO_MMD_VEND1,
3340                                         &reg);
3341                 if (status)
3342                         return status;
3343
3344                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
3345
3346                 status = hw->phy.ops.write_reg(hw,
3347                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
3348                                         MDIO_MMD_VEND1,
3349                                         reg);
3350                 if (status)
3351                         return status;
3352         }
3353
3354         return status;
3355 }
3356
3357 /**
3358  * ixgbe_set_mdio_speed - Set MDIO clock speed
3359  * @hw: pointer to hardware structure
3360  */
3361 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
3362 {
3363         u32 hlreg0;
3364
3365         switch (hw->device_id) {
3366         case IXGBE_DEV_ID_X550EM_X_10G_T:
3367         case IXGBE_DEV_ID_X550EM_A_SGMII:
3368         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
3369         case IXGBE_DEV_ID_X550EM_A_10G_T:
3370         case IXGBE_DEV_ID_X550EM_A_SFP:
3371                 /* Config MDIO clock speed before the first MDIO PHY access */
3372                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3373                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
3374                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3375                 break;
3376         case IXGBE_DEV_ID_X550EM_A_1G_T:
3377         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
3378                 /* Select fast MDIO clock speed for these devices */
3379                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3380                 hlreg0 |= IXGBE_HLREG0_MDCSPD;
3381                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3382                 break;
3383         default:
3384                 break;
3385         }
3386 }
3387
3388 /**  ixgbe_reset_hw_X550em - Perform hardware reset
3389  **  @hw: pointer to hardware structure
3390  **
3391  **  Resets the hardware by resetting the transmit and receive units, masks
3392  **  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
3393  **  reset.
3394  **/
3395 static int ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
3396 {
3397         u32 swfw_mask = hw->phy.phy_semaphore_mask;
3398         ixgbe_link_speed link_speed;
3399         bool link_up = false;
3400         u32 ctrl = 0;
3401         int status;
3402         u32 i;
3403
3404         /* Call adapter stop to disable Tx/Rx and clear interrupts */
3405         status = hw->mac.ops.stop_adapter(hw);
3406         if (status)
3407                 return status;
3408
3409         /* flush pending Tx transactions */
3410         ixgbe_clear_tx_pending(hw);
3411
3412         /* set MDIO speed before talking to the PHY in case it's the 1st time */
3413         ixgbe_set_mdio_speed(hw);
3414
3415         /* PHY ops must be identified and initialized prior to reset */
3416         status = hw->phy.ops.init(hw);
3417         if (status == -EOPNOTSUPP || status == -EFAULT)
3418                 return status;
3419
3420         /* start the external PHY */
3421         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
3422                 status = ixgbe_init_ext_t_x550em(hw);
3423                 if (status)
3424                         return status;
3425         }
3426
3427         /* Setup SFP module if there is one present. */
3428         if (hw->phy.sfp_setup_needed) {
3429                 status = hw->mac.ops.setup_sfp(hw);
3430                 hw->phy.sfp_setup_needed = false;
3431         }
3432
3433         if (status == -EOPNOTSUPP)
3434                 return status;
3435
3436         /* Reset PHY */
3437         if (!hw->phy.reset_disable && hw->phy.ops.reset)
3438                 hw->phy.ops.reset(hw);
3439
3440 mac_reset_top:
3441         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
3442          * If link reset is used when link is up, it might reset the PHY when
3443          * mng is using it.  If link is down or the flag to force full link
3444          * reset is set, then perform link reset.
3445          */
3446         ctrl = IXGBE_CTRL_LNK_RST;
3447
3448         if (!hw->force_full_reset) {
3449                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3450                 if (link_up)
3451                         ctrl = IXGBE_CTRL_RST;
3452         }
3453
3454         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
3455         if (status) {
3456                 hw_dbg(hw, "semaphore failed with %d", status);
3457                 return -EBUSY;
3458         }
3459
3460         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
3461         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3462         IXGBE_WRITE_FLUSH(hw);
3463         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3464         usleep_range(1000, 1200);
3465
3466         /* Poll for reset bit to self-clear meaning reset is complete */
3467         for (i = 0; i < 10; i++) {
3468                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3469                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
3470                         break;
3471                 udelay(1);
3472         }
3473
3474         if (ctrl & IXGBE_CTRL_RST_MASK) {
3475                 status = -EIO;
3476                 hw_dbg(hw, "Reset polling failed to complete.\n");
3477         }
3478
3479         msleep(50);
3480
3481         /* Double resets are required for recovery from certain error
3482          * clear the multicast table.  Also reset num_rar_entries to 128,
3483          * since we modify this value when programming the SAN MAC address.
3484          */
3485         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
3486                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3487                 goto mac_reset_top;
3488         }
3489
3490         /* Store the permanent mac address */
3491         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
3492
3493         /* Store MAC address from RAR0, clear receive address registers, and
3494          * clear the multicast table.  Also reset num_rar_entries to 128,
3495          * since we modify this value when programming the SAN MAC address.
3496          */
3497         hw->mac.num_rar_entries = 128;
3498         hw->mac.ops.init_rx_addrs(hw);
3499
3500         ixgbe_set_mdio_speed(hw);
3501
3502         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
3503                 ixgbe_setup_mux_ctl(hw);
3504
3505         return status;
3506 }
3507
3508 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
3509  *      anti-spoofing
3510  *  @hw:  pointer to hardware structure
3511  *  @enable: enable or disable switch for Ethertype anti-spoofing
3512  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
3513  **/
3514 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
3515                                                    bool enable, int vf)
3516 {
3517         int vf_target_reg = vf >> 3;
3518         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
3519         u32 pfvfspoof;
3520
3521         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3522         if (enable)
3523                 pfvfspoof |= BIT(vf_target_shift);
3524         else
3525                 pfvfspoof &= ~BIT(vf_target_shift);
3526
3527         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3528 }
3529
3530 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
3531  *  @hw: pointer to hardware structure
3532  *  @enable: enable or disable source address pruning
3533  *  @pool: Rx pool to set source address pruning for
3534  **/
3535 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
3536                                                   bool enable,
3537                                                   unsigned int pool)
3538 {
3539         u64 pfflp;
3540
3541         /* max rx pool is 63 */
3542         if (pool > 63)
3543                 return;
3544
3545         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
3546         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
3547
3548         if (enable)
3549                 pfflp |= (1ULL << pool);
3550         else
3551                 pfflp &= ~(1ULL << pool);
3552
3553         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
3554         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
3555 }
3556
3557 /**
3558  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
3559  *  @hw: pointer to hardware structure
3560  *
3561  *  Called at init time to set up flow control.
3562  **/
3563 static int ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
3564 {
3565         u32 an_cntl = 0;
3566         int status = 0;
3567
3568         /* Validate the requested mode */
3569         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3570                 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3571                 return -EINVAL;
3572         }
3573
3574         if (hw->fc.requested_mode == ixgbe_fc_default)
3575                 hw->fc.requested_mode = ixgbe_fc_full;
3576
3577         /* Set up the 1G and 10G flow control advertisement registers so the
3578          * HW will be able to do FC autoneg once the cable is plugged in.  If
3579          * we link at 10G, the 1G advertisement is harmless and vice versa.
3580          */
3581         status = hw->mac.ops.read_iosf_sb_reg(hw,
3582                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3583                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
3584
3585         if (status) {
3586                 hw_dbg(hw, "Auto-Negotiation did not complete\n");
3587                 return status;
3588         }
3589
3590         /* The possible values of fc.requested_mode are:
3591          * 0: Flow control is completely disabled
3592          * 1: Rx flow control is enabled (we can receive pause frames,
3593          *    but not send pause frames).
3594          * 2: Tx flow control is enabled (we can send pause frames but
3595          *    we do not support receiving pause frames).
3596          * 3: Both Rx and Tx flow control (symmetric) are enabled.
3597          * other: Invalid.
3598          */
3599         switch (hw->fc.requested_mode) {
3600         case ixgbe_fc_none:
3601                 /* Flow control completely disabled by software override. */
3602                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3603                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3604                 break;
3605         case ixgbe_fc_tx_pause:
3606                 /* Tx Flow control is enabled, and Rx Flow control is
3607                  * disabled by software override.
3608                  */
3609                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3610                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3611                 break;
3612         case ixgbe_fc_rx_pause:
3613                 /* Rx Flow control is enabled and Tx Flow control is
3614                  * disabled by software override. Since there really
3615                  * isn't a way to advertise that we are capable of RX
3616                  * Pause ONLY, we will advertise that we support both
3617                  * symmetric and asymmetric Rx PAUSE, as such we fall
3618                  * through to the fc_full statement.  Later, we will
3619                  * disable the adapter's ability to send PAUSE frames.
3620                  */
3621         case ixgbe_fc_full:
3622                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3623                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3624                            IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3625                 break;
3626         default:
3627                 hw_err(hw, "Flow control param set incorrectly\n");
3628                 return -EIO;
3629         }
3630
3631         status = hw->mac.ops.write_iosf_sb_reg(hw,
3632                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3633                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
3634
3635         /* Restart auto-negotiation. */
3636         status = ixgbe_restart_an_internal_phy_x550em(hw);
3637
3638         return status;
3639 }
3640
3641 /**
3642  * ixgbe_set_mux - Set mux for port 1 access with CS4227
3643  * @hw: pointer to hardware structure
3644  * @state: set mux if 1, clear if 0
3645  */
3646 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3647 {
3648         u32 esdp;
3649
3650         if (!hw->bus.lan_id)
3651                 return;
3652         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3653         if (state)
3654                 esdp |= IXGBE_ESDP_SDP1;
3655         else
3656                 esdp &= ~IXGBE_ESDP_SDP1;
3657         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3658         IXGBE_WRITE_FLUSH(hw);
3659 }
3660
3661 /**
3662  * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3663  * @hw: pointer to hardware structure
3664  * @mask: Mask to specify which semaphore to acquire
3665  *
3666  * Acquires the SWFW semaphore and sets the I2C MUX
3667  */
3668 static int ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3669 {
3670         int status;
3671
3672         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3673         if (status)
3674                 return status;
3675
3676         if (mask & IXGBE_GSSR_I2C_MASK)
3677                 ixgbe_set_mux(hw, 1);
3678
3679         return 0;
3680 }
3681
3682 /**
3683  * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3684  * @hw: pointer to hardware structure
3685  * @mask: Mask to specify which semaphore to release
3686  *
3687  * Releases the SWFW semaphore and sets the I2C MUX
3688  */
3689 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3690 {
3691         if (mask & IXGBE_GSSR_I2C_MASK)
3692                 ixgbe_set_mux(hw, 0);
3693
3694         ixgbe_release_swfw_sync_X540(hw, mask);
3695 }
3696
3697 /**
3698  * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore
3699  * @hw: pointer to hardware structure
3700  * @mask: Mask to specify which semaphore to acquire
3701  *
3702  * Acquires the SWFW semaphore and get the shared PHY token as needed
3703  */
3704 static int ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3705 {
3706         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3707         int retries = FW_PHY_TOKEN_RETRIES;
3708         int status;
3709
3710         while (--retries) {
3711                 status = 0;
3712                 if (hmask)
3713                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3714                 if (status)
3715                         return status;
3716                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3717                         return 0;
3718
3719                 status = ixgbe_get_phy_token(hw);
3720                 if (!status)
3721                         return 0;
3722                 if (hmask)
3723                         ixgbe_release_swfw_sync_X540(hw, hmask);
3724                 if (status != -EAGAIN)
3725                         return status;
3726                 msleep(FW_PHY_TOKEN_DELAY);
3727         }
3728
3729         return status;
3730 }
3731
3732 /**
3733  * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore
3734  * @hw: pointer to hardware structure
3735  * @mask: Mask to specify which semaphore to release
3736  *
3737  * Release the SWFW semaphore and puts the shared PHY token as needed
3738  */
3739 static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3740 {
3741         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3742
3743         if (mask & IXGBE_GSSR_TOKEN_SM)
3744                 ixgbe_put_phy_token(hw);
3745
3746         if (hmask)
3747                 ixgbe_release_swfw_sync_X540(hw, hmask);
3748 }
3749
3750 /**
3751  * ixgbe_read_phy_reg_x550a - Reads specified PHY register
3752  * @hw: pointer to hardware structure
3753  * @reg_addr: 32 bit address of PHY register to read
3754  * @device_type: 5 bit device type
3755  * @phy_data: Pointer to read data from PHY register
3756  *
3757  * Reads a value from a specified PHY register using the SWFW lock and PHY
3758  * Token. The PHY Token is needed since the MDIO is shared between to MAC
3759  * instances.
3760  */
3761 static int ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3762                                     u32 device_type, u16 *phy_data)
3763 {
3764         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3765         int status;
3766
3767         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3768                 return -EBUSY;
3769
3770         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
3771
3772         hw->mac.ops.release_swfw_sync(hw, mask);
3773
3774         return status;
3775 }
3776
3777 /**
3778  * ixgbe_write_phy_reg_x550a - Writes specified PHY register
3779  * @hw: pointer to hardware structure
3780  * @reg_addr: 32 bit PHY register to write
3781  * @device_type: 5 bit device type
3782  * @phy_data: Data to write to the PHY register
3783  *
3784  * Writes a value to specified PHY register using the SWFW lock and PHY Token.
3785  * The PHY Token is needed since the MDIO is shared between to MAC instances.
3786  */
3787 static int ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3788                                      u32 device_type, u16 phy_data)
3789 {
3790         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3791         int status;
3792
3793         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3794                 return -EBUSY;
3795
3796         status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data);
3797         hw->mac.ops.release_swfw_sync(hw, mask);
3798
3799         return status;
3800 }
3801
3802 #define X550_COMMON_MAC \
3803         .init_hw                        = &ixgbe_init_hw_generic, \
3804         .start_hw                       = &ixgbe_start_hw_X540, \
3805         .clear_hw_cntrs                 = &ixgbe_clear_hw_cntrs_generic, \
3806         .enable_rx_dma                  = &ixgbe_enable_rx_dma_generic, \
3807         .get_mac_addr                   = &ixgbe_get_mac_addr_generic, \
3808         .get_device_caps                = &ixgbe_get_device_caps_generic, \
3809         .stop_adapter                   = &ixgbe_stop_adapter_generic, \
3810         .set_lan_id                     = &ixgbe_set_lan_id_multi_port_pcie, \
3811         .read_analog_reg8               = NULL, \
3812         .write_analog_reg8              = NULL, \
3813         .set_rxpba                      = &ixgbe_set_rxpba_generic, \
3814         .check_link                     = &ixgbe_check_mac_link_generic, \
3815         .blink_led_start                = &ixgbe_blink_led_start_X540, \
3816         .blink_led_stop                 = &ixgbe_blink_led_stop_X540, \
3817         .set_rar                        = &ixgbe_set_rar_generic, \
3818         .clear_rar                      = &ixgbe_clear_rar_generic, \
3819         .set_vmdq                       = &ixgbe_set_vmdq_generic, \
3820         .set_vmdq_san_mac               = &ixgbe_set_vmdq_san_mac_generic, \
3821         .clear_vmdq                     = &ixgbe_clear_vmdq_generic, \
3822         .init_rx_addrs                  = &ixgbe_init_rx_addrs_generic, \
3823         .update_mc_addr_list            = &ixgbe_update_mc_addr_list_generic, \
3824         .enable_mc                      = &ixgbe_enable_mc_generic, \
3825         .disable_mc                     = &ixgbe_disable_mc_generic, \
3826         .clear_vfta                     = &ixgbe_clear_vfta_generic, \
3827         .set_vfta                       = &ixgbe_set_vfta_generic, \
3828         .fc_enable                      = &ixgbe_fc_enable_generic, \
3829         .set_fw_drv_ver                 = &ixgbe_set_fw_drv_ver_x550, \
3830         .init_uta_tables                = &ixgbe_init_uta_tables_generic, \
3831         .set_mac_anti_spoofing          = &ixgbe_set_mac_anti_spoofing, \
3832         .set_vlan_anti_spoofing         = &ixgbe_set_vlan_anti_spoofing, \
3833         .set_source_address_pruning     = \
3834                                 &ixgbe_set_source_address_pruning_X550, \
3835         .set_ethertype_anti_spoofing    = \
3836                                 &ixgbe_set_ethertype_anti_spoofing_X550, \
3837         .disable_rx_buff                = &ixgbe_disable_rx_buff_generic, \
3838         .enable_rx_buff                 = &ixgbe_enable_rx_buff_generic, \
3839         .get_thermal_sensor_data        = NULL, \
3840         .init_thermal_sensor_thresh     = NULL, \
3841         .fw_recovery_mode               = &ixgbe_fw_recovery_mode_X550, \
3842         .enable_rx                      = &ixgbe_enable_rx_generic, \
3843         .disable_rx                     = &ixgbe_disable_rx_x550, \
3844
3845 static const struct ixgbe_mac_operations mac_ops_X550 = {
3846         X550_COMMON_MAC
3847         .led_on                 = ixgbe_led_on_generic,
3848         .led_off                = ixgbe_led_off_generic,
3849         .init_led_link_act      = ixgbe_init_led_link_act_generic,
3850         .reset_hw               = &ixgbe_reset_hw_X540,
3851         .get_media_type         = &ixgbe_get_media_type_X540,
3852         .get_san_mac_addr       = &ixgbe_get_san_mac_addr_generic,
3853         .get_wwn_prefix         = &ixgbe_get_wwn_prefix_generic,
3854         .setup_link             = &ixgbe_setup_mac_link_X540,
3855         .get_link_capabilities  = &ixgbe_get_copper_link_capabilities_generic,
3856         .get_bus_info           = &ixgbe_get_bus_info_generic,
3857         .setup_sfp              = NULL,
3858         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X540,
3859         .release_swfw_sync      = &ixgbe_release_swfw_sync_X540,
3860         .init_swfw_sync         = &ixgbe_init_swfw_sync_X540,
3861         .prot_autoc_read        = prot_autoc_read_generic,
3862         .prot_autoc_write       = prot_autoc_write_generic,
3863         .setup_fc               = ixgbe_setup_fc_generic,
3864         .fc_autoneg             = ixgbe_fc_autoneg,
3865 };
3866
3867 static const struct ixgbe_mac_operations mac_ops_X550EM_x = {
3868         X550_COMMON_MAC
3869         .led_on                 = ixgbe_led_on_t_x550em,
3870         .led_off                = ixgbe_led_off_t_x550em,
3871         .init_led_link_act      = ixgbe_init_led_link_act_generic,
3872         .reset_hw               = &ixgbe_reset_hw_X550em,
3873         .get_media_type         = &ixgbe_get_media_type_X550em,
3874         .get_san_mac_addr       = NULL,
3875         .get_wwn_prefix         = NULL,
3876         .setup_link             = &ixgbe_setup_mac_link_X540,
3877         .get_link_capabilities  = &ixgbe_get_link_capabilities_X550em,
3878         .get_bus_info           = &ixgbe_get_bus_info_X550em,
3879         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
3880         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X550em,
3881         .release_swfw_sync      = &ixgbe_release_swfw_sync_X550em,
3882         .init_swfw_sync         = &ixgbe_init_swfw_sync_X540,
3883         .setup_fc               = NULL, /* defined later */
3884         .fc_autoneg             = ixgbe_fc_autoneg,
3885         .read_iosf_sb_reg       = ixgbe_read_iosf_sb_reg_x550,
3886         .write_iosf_sb_reg      = ixgbe_write_iosf_sb_reg_x550,
3887 };
3888
3889 static const struct ixgbe_mac_operations mac_ops_X550EM_x_fw = {
3890         X550_COMMON_MAC
3891         .led_on                 = NULL,
3892         .led_off                = NULL,
3893         .init_led_link_act      = NULL,
3894         .reset_hw               = &ixgbe_reset_hw_X550em,
3895         .get_media_type         = &ixgbe_get_media_type_X550em,
3896         .get_san_mac_addr       = NULL,
3897         .get_wwn_prefix         = NULL,
3898         .setup_link             = &ixgbe_setup_mac_link_X540,
3899         .get_link_capabilities  = &ixgbe_get_link_capabilities_X550em,
3900         .get_bus_info           = &ixgbe_get_bus_info_X550em,
3901         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
3902         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X550em,
3903         .release_swfw_sync      = &ixgbe_release_swfw_sync_X550em,
3904         .init_swfw_sync         = &ixgbe_init_swfw_sync_X540,
3905         .setup_fc               = NULL,
3906         .fc_autoneg             = ixgbe_fc_autoneg,
3907         .read_iosf_sb_reg       = ixgbe_read_iosf_sb_reg_x550,
3908         .write_iosf_sb_reg      = ixgbe_write_iosf_sb_reg_x550,
3909 };
3910
3911 static const struct ixgbe_mac_operations mac_ops_x550em_a = {
3912         X550_COMMON_MAC
3913         .led_on                 = ixgbe_led_on_t_x550em,
3914         .led_off                = ixgbe_led_off_t_x550em,
3915         .init_led_link_act      = ixgbe_init_led_link_act_generic,
3916         .reset_hw               = ixgbe_reset_hw_X550em,
3917         .get_media_type         = ixgbe_get_media_type_X550em,
3918         .get_san_mac_addr       = NULL,
3919         .get_wwn_prefix         = NULL,
3920         .setup_link             = &ixgbe_setup_mac_link_X540,
3921         .get_link_capabilities  = ixgbe_get_link_capabilities_X550em,
3922         .get_bus_info           = ixgbe_get_bus_info_X550em,
3923         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
3924         .acquire_swfw_sync      = ixgbe_acquire_swfw_sync_x550em_a,
3925         .release_swfw_sync      = ixgbe_release_swfw_sync_x550em_a,
3926         .setup_fc               = ixgbe_setup_fc_x550em,
3927         .fc_autoneg             = ixgbe_fc_autoneg,
3928         .read_iosf_sb_reg       = ixgbe_read_iosf_sb_reg_x550a,
3929         .write_iosf_sb_reg      = ixgbe_write_iosf_sb_reg_x550a,
3930 };
3931
3932 static const struct ixgbe_mac_operations mac_ops_x550em_a_fw = {
3933         X550_COMMON_MAC
3934         .led_on                 = ixgbe_led_on_generic,
3935         .led_off                = ixgbe_led_off_generic,
3936         .init_led_link_act      = ixgbe_init_led_link_act_generic,
3937         .reset_hw               = ixgbe_reset_hw_X550em,
3938         .get_media_type         = ixgbe_get_media_type_X550em,
3939         .get_san_mac_addr       = NULL,
3940         .get_wwn_prefix         = NULL,
3941         .setup_link             = NULL, /* defined later */
3942         .get_link_capabilities  = ixgbe_get_link_capabilities_X550em,
3943         .get_bus_info           = ixgbe_get_bus_info_X550em,
3944         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
3945         .acquire_swfw_sync      = ixgbe_acquire_swfw_sync_x550em_a,
3946         .release_swfw_sync      = ixgbe_release_swfw_sync_x550em_a,
3947         .setup_fc               = ixgbe_setup_fc_x550em,
3948         .fc_autoneg             = ixgbe_fc_autoneg,
3949         .read_iosf_sb_reg       = ixgbe_read_iosf_sb_reg_x550a,
3950         .write_iosf_sb_reg      = ixgbe_write_iosf_sb_reg_x550a,
3951 };
3952
3953 #define X550_COMMON_EEP \
3954         .read                   = &ixgbe_read_ee_hostif_X550, \
3955         .read_buffer            = &ixgbe_read_ee_hostif_buffer_X550, \
3956         .write                  = &ixgbe_write_ee_hostif_X550, \
3957         .write_buffer           = &ixgbe_write_ee_hostif_buffer_X550, \
3958         .validate_checksum      = &ixgbe_validate_eeprom_checksum_X550, \
3959         .update_checksum        = &ixgbe_update_eeprom_checksum_X550, \
3960         .calc_checksum          = &ixgbe_calc_eeprom_checksum_X550, \
3961
3962 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = {
3963         X550_COMMON_EEP
3964         .init_params            = &ixgbe_init_eeprom_params_X550,
3965 };
3966
3967 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
3968         X550_COMMON_EEP
3969         .init_params            = &ixgbe_init_eeprom_params_X540,
3970 };
3971
3972 #define X550_COMMON_PHY \
3973         .identify_sfp           = &ixgbe_identify_module_generic, \
3974         .reset                  = NULL, \
3975         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic, \
3976         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic, \
3977         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic, \
3978         .read_i2c_sff8472       = &ixgbe_read_i2c_sff8472_generic, \
3979         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic, \
3980         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic, \
3981         .setup_link             = &ixgbe_setup_phy_link_generic, \
3982         .set_phy_power          = NULL,
3983
3984 static const struct ixgbe_phy_operations phy_ops_X550 = {
3985         X550_COMMON_PHY
3986         .check_overtemp         = &ixgbe_tn_check_overtemp,
3987         .init                   = NULL,
3988         .identify               = &ixgbe_identify_phy_generic,
3989         .read_reg               = &ixgbe_read_phy_reg_generic,
3990         .write_reg              = &ixgbe_write_phy_reg_generic,
3991 };
3992
3993 static const struct ixgbe_phy_operations phy_ops_X550EM_x = {
3994         X550_COMMON_PHY
3995         .check_overtemp         = &ixgbe_tn_check_overtemp,
3996         .init                   = &ixgbe_init_phy_ops_X550em,
3997         .identify               = &ixgbe_identify_phy_x550em,
3998         .read_reg               = &ixgbe_read_phy_reg_generic,
3999         .write_reg              = &ixgbe_write_phy_reg_generic,
4000 };
4001
4002 static const struct ixgbe_phy_operations phy_ops_x550em_x_fw = {
4003         X550_COMMON_PHY
4004         .check_overtemp         = NULL,
4005         .init                   = ixgbe_init_phy_ops_X550em,
4006         .identify               = ixgbe_identify_phy_x550em,
4007         .read_reg               = NULL,
4008         .write_reg              = NULL,
4009         .read_reg_mdi           = NULL,
4010         .write_reg_mdi          = NULL,
4011 };
4012
4013 static const struct ixgbe_phy_operations phy_ops_x550em_a = {
4014         X550_COMMON_PHY
4015         .check_overtemp         = &ixgbe_tn_check_overtemp,
4016         .init                   = &ixgbe_init_phy_ops_X550em,
4017         .identify               = &ixgbe_identify_phy_x550em,
4018         .read_reg               = &ixgbe_read_phy_reg_x550a,
4019         .write_reg              = &ixgbe_write_phy_reg_x550a,
4020         .read_reg_mdi           = &ixgbe_read_phy_reg_mdi,
4021         .write_reg_mdi          = &ixgbe_write_phy_reg_mdi,
4022 };
4023
4024 static const struct ixgbe_phy_operations phy_ops_x550em_a_fw = {
4025         X550_COMMON_PHY
4026         .check_overtemp         = ixgbe_check_overtemp_fw,
4027         .init                   = ixgbe_init_phy_ops_X550em,
4028         .identify               = ixgbe_identify_phy_fw,
4029         .read_reg               = NULL,
4030         .write_reg              = NULL,
4031         .read_reg_mdi           = NULL,
4032         .write_reg_mdi          = NULL,
4033 };
4034
4035 static const struct ixgbe_link_operations link_ops_x550em_x = {
4036         .read_link              = &ixgbe_read_i2c_combined_generic,
4037         .read_link_unlocked     = &ixgbe_read_i2c_combined_generic_unlocked,
4038         .write_link             = &ixgbe_write_i2c_combined_generic,
4039         .write_link_unlocked    = &ixgbe_write_i2c_combined_generic_unlocked,
4040 };
4041
4042 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
4043         IXGBE_MVALS_INIT(X550)
4044 };
4045
4046 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
4047         IXGBE_MVALS_INIT(X550EM_x)
4048 };
4049
4050 static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = {
4051         IXGBE_MVALS_INIT(X550EM_a)
4052 };
4053
4054 const struct ixgbe_info ixgbe_X550_info = {
4055         .mac                    = ixgbe_mac_X550,
4056         .get_invariants         = &ixgbe_get_invariants_X540,
4057         .mac_ops                = &mac_ops_X550,
4058         .eeprom_ops             = &eeprom_ops_X550,
4059         .phy_ops                = &phy_ops_X550,
4060         .mbx_ops                = &mbx_ops_generic,
4061         .mvals                  = ixgbe_mvals_X550,
4062 };
4063
4064 const struct ixgbe_info ixgbe_X550EM_x_info = {
4065         .mac                    = ixgbe_mac_X550EM_x,
4066         .get_invariants         = &ixgbe_get_invariants_X550_x,
4067         .mac_ops                = &mac_ops_X550EM_x,
4068         .eeprom_ops             = &eeprom_ops_X550EM_x,
4069         .phy_ops                = &phy_ops_X550EM_x,
4070         .mbx_ops                = &mbx_ops_generic,
4071         .mvals                  = ixgbe_mvals_X550EM_x,
4072         .link_ops               = &link_ops_x550em_x,
4073 };
4074
4075 const struct ixgbe_info ixgbe_x550em_x_fw_info = {
4076         .mac                    = ixgbe_mac_X550EM_x,
4077         .get_invariants         = ixgbe_get_invariants_X550_x_fw,
4078         .mac_ops                = &mac_ops_X550EM_x_fw,
4079         .eeprom_ops             = &eeprom_ops_X550EM_x,
4080         .phy_ops                = &phy_ops_x550em_x_fw,
4081         .mbx_ops                = &mbx_ops_generic,
4082         .mvals                  = ixgbe_mvals_X550EM_x,
4083 };
4084
4085 const struct ixgbe_info ixgbe_x550em_a_info = {
4086         .mac                    = ixgbe_mac_x550em_a,
4087         .get_invariants         = &ixgbe_get_invariants_X550_a,
4088         .mac_ops                = &mac_ops_x550em_a,
4089         .eeprom_ops             = &eeprom_ops_X550EM_x,
4090         .phy_ops                = &phy_ops_x550em_a,
4091         .mbx_ops                = &mbx_ops_generic,
4092         .mvals                  = ixgbe_mvals_x550em_a,
4093 };
4094
4095 const struct ixgbe_info ixgbe_x550em_a_fw_info = {
4096         .mac                    = ixgbe_mac_x550em_a,
4097         .get_invariants         = ixgbe_get_invariants_X550_a_fw,
4098         .mac_ops                = &mac_ops_x550em_a_fw,
4099         .eeprom_ops             = &eeprom_ops_X550EM_x,
4100         .phy_ops                = &phy_ops_x550em_a_fw,
4101         .mbx_ops                = &mbx_ops_generic,
4102         .mvals                  = ixgbe_mvals_x550em_a,
4103 };