drivers/net/ethernet/lantiq_etop.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *
   4  *   Copyright (C) 2011 John Crispin <blogic@openwrt.org>
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/slab.h>
   9 #include <linux/errno.h>
  10 #include <linux/types.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/uaccess.h>
  13 #include <linux/in.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/phy.h>
  17 #include <linux/ip.h>
  18 #include <linux/tcp.h>
  19 #include <linux/skbuff.h>
  20 #include <linux/mm.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/ethtool.h>
  23 #include <linux/init.h>
  24 #include <linux/delay.h>
  25 #include <linux/io.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/module.h>
  28 #include <linux/property.h>
  29
  30 #include <asm/checksum.h>
  31
  32 #include <lantiq_soc.h>
  33 #include <xway_dma.h>
  34 #include <lantiq_platform.h>
  35
  36 #define LTQ_ETOP_MDIO           0x11804
  37 #define MDIO_REQUEST            0x80000000
  38 #define MDIO_READ               0x40000000
  39 #define MDIO_ADDR_MASK          0x1f
  40 #define MDIO_ADDR_OFFSET        0x15
  41 #define MDIO_REG_MASK           0x1f
  42 #define MDIO_REG_OFFSET         0x10
  43 #define MDIO_VAL_MASK           0xffff
  44
  45 #define PPE32_CGEN              0x800
  46 #define LQ_PPE32_ENET_MAC_CFG   0x1840
  47
  48 #define LTQ_ETOP_ENETS0         0x11850
  49 #define LTQ_ETOP_MAC_DA0        0x1186C
  50 #define LTQ_ETOP_MAC_DA1        0x11870
  51 #define LTQ_ETOP_CFG            0x16020
  52 #define LTQ_ETOP_IGPLEN         0x16080
  53
  54 #define MAX_DMA_CHAN            0x8
  55 #define MAX_DMA_CRC_LEN         0x4
  56 #define MAX_DMA_DATA_LEN        0x600
  57
  58 #define ETOP_FTCU               BIT(28)
  59 #define ETOP_MII_MASK           0xf
  60 #define ETOP_MII_NORMAL         0xd
  61 #define ETOP_MII_REVERSE        0xe
  62 #define ETOP_PLEN_UNDER         0x40
  63 #define ETOP_CGEN               0x800
  64
  65 /* use 2 static channels for TX/RX */
  66 #define LTQ_ETOP_TX_CHANNEL     1
  67 #define LTQ_ETOP_RX_CHANNEL     6
  68 #define IS_TX(x)                ((x) == LTQ_ETOP_TX_CHANNEL)
  69 #define IS_RX(x)                ((x) == LTQ_ETOP_RX_CHANNEL)
  70
  71 #define ltq_etop_r32(x)         ltq_r32(ltq_etop_membase + (x))
  72 #define ltq_etop_w32(x, y)      ltq_w32(x, ltq_etop_membase + (y))
  73 #define ltq_etop_w32_mask(x, y, z)      \
  74                 ltq_w32_mask(x, y, ltq_etop_membase + (z))
  75
  76 #define DRV_VERSION     "1.0"
  77
  78 static void __iomem *ltq_etop_membase;
  79
  80 struct ltq_etop_chan {
  81         int idx;
  82         int tx_free;
  83         struct net_device *netdev;
  84         struct napi_struct napi;
  85         struct ltq_dma_channel dma;
  86         struct sk_buff *skb[LTQ_DESC_NUM];
  87 };
  88
  89 struct ltq_etop_priv {
  90         struct net_device *netdev;
  91         struct platform_device *pdev;
  92         struct ltq_eth_data *pldata;
  93         struct resource *res;
  94
  95         struct mii_bus *mii_bus;
  96
  97         struct ltq_etop_chan ch[MAX_DMA_CHAN];
  98
  99         int tx_burst_len;
 100         int rx_burst_len;
 101
 102         spinlock_t lock;
 103 };
 104
 105 static int
 106 ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
 107 {
 108         struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
 109
 110         ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
 111         if (!ch->skb[ch->dma.desc])
 112                 return -ENOMEM;
 113         ch->dma.desc_base[ch->dma.desc].addr =
 114                 dma_map_single(&priv->pdev->dev, ch->skb[ch->dma.desc]->data,
 115                                MAX_DMA_DATA_LEN, DMA_FROM_DEVICE);
 116         ch->dma.desc_base[ch->dma.desc].addr =
 117                 CPHYSADDR(ch->skb[ch->dma.desc]->data);
 118         ch->dma.desc_base[ch->dma.desc].ctl =
 119                 LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
 120                 MAX_DMA_DATA_LEN;
 121         skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
 122         return 0;
 123 }
 124
 125 static void
 126 ltq_etop_hw_receive(struct ltq_etop_chan *ch)
 127 {
 128         struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
 129         struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
 130         struct sk_buff *skb = ch->skb[ch->dma.desc];
 131         int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN;
 132         unsigned long flags;
 133
 134         spin_lock_irqsave(&priv->lock, flags);
 135         if (ltq_etop_alloc_skb(ch)) {
 136                 netdev_err(ch->netdev,
 137                            "failed to allocate new rx buffer, stopping DMA\n");
 138                 ltq_dma_close(&ch->dma);
 139         }
 140         ch->dma.desc++;
 141         ch->dma.desc %= LTQ_DESC_NUM;
 142         spin_unlock_irqrestore(&priv->lock, flags);
 143
 144         skb_put(skb, len);
 145         skb->protocol = eth_type_trans(skb, ch->netdev);
 146         netif_receive_skb(skb);
 147 }
 148
 149 static int
 150 ltq_etop_poll_rx(struct napi_struct *napi, int budget)
 151 {
 152         struct ltq_etop_chan *ch = container_of(napi,
 153                                 struct ltq_etop_chan, napi);
 154         int work_done = 0;
 155
 156         while (work_done < budget) {
 157                 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
 158
 159                 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) != LTQ_DMA_C)
 160                         break;
 161                 ltq_etop_hw_receive(ch);
 162                 work_done++;
 163         }
 164         if (work_done < budget) {
 165                 napi_complete_done(&ch->napi, work_done);
 166                 ltq_dma_ack_irq(&ch->dma);
 167         }
 168         return work_done;
 169 }
 170
 171 static int
 172 ltq_etop_poll_tx(struct napi_struct *napi, int budget)
 173 {
 174         struct ltq_etop_chan *ch =
 175                 container_of(napi, struct ltq_etop_chan, napi);
 176         struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
 177         struct netdev_queue *txq =
 178                 netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
 179         unsigned long flags;
 180
 181         spin_lock_irqsave(&priv->lock, flags);
 182         while ((ch->dma.desc_base[ch->tx_free].ctl &
 183                         (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
 184                 dev_kfree_skb_any(ch->skb[ch->tx_free]);
 185                 ch->skb[ch->tx_free] = NULL;
 186                 memset(&ch->dma.desc_base[ch->tx_free], 0,
 187                        sizeof(struct ltq_dma_desc));
 188                 ch->tx_free++;
 189                 ch->tx_free %= LTQ_DESC_NUM;
 190         }
 191         spin_unlock_irqrestore(&priv->lock, flags);
 192
 193         if (netif_tx_queue_stopped(txq))
 194                 netif_tx_start_queue(txq);
 195         napi_complete(&ch->napi);
 196         ltq_dma_ack_irq(&ch->dma);
 197         return 1;
 198 }
 199
 200 static irqreturn_t
 201 ltq_etop_dma_irq(int irq, void *_priv)
 202 {
 203         struct ltq_etop_priv *priv = _priv;
 204         int ch = irq - LTQ_DMA_CH0_INT;
 205
 206         napi_schedule(&priv->ch[ch].napi);
 207         return IRQ_HANDLED;
 208 }
 209
 210 static void
 211 ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
 212 {
 213         struct ltq_etop_priv *priv = netdev_priv(dev);
 214
 215         ltq_dma_free(&ch->dma);
 216         if (ch->dma.irq)
 217                 free_irq(ch->dma.irq, priv);
 218         if (IS_RX(ch->idx)) {
 219                 struct ltq_dma_channel *dma = &ch->dma;
 220
 221                 for (dma->desc = 0; dma->desc < LTQ_DESC_NUM; dma->desc++)
 222                         dev_kfree_skb_any(ch->skb[ch->dma.desc]);
 223         }
 224 }
 225
 226 static void
 227 ltq_etop_hw_exit(struct net_device *dev)
 228 {
 229         struct ltq_etop_priv *priv = netdev_priv(dev);
 230         int i;
 231
 232         ltq_pmu_disable(PMU_PPE);
 233         for (i = 0; i < MAX_DMA_CHAN; i++)
 234                 if (IS_TX(i) || IS_RX(i))
 235                         ltq_etop_free_channel(dev, &priv->ch[i]);
 236 }
 237
 238 static int
 239 ltq_etop_hw_init(struct net_device *dev)
 240 {
 241         struct ltq_etop_priv *priv = netdev_priv(dev);
 242         int i;
 243         int err;
 244
 245         ltq_pmu_enable(PMU_PPE);
 246
 247         switch (priv->pldata->mii_mode) {
 248         case PHY_INTERFACE_MODE_RMII:
 249                 ltq_etop_w32_mask(ETOP_MII_MASK, ETOP_MII_REVERSE,
 250                                   LTQ_ETOP_CFG);
 251                 break;
 252
 253         case PHY_INTERFACE_MODE_MII:
 254                 ltq_etop_w32_mask(ETOP_MII_MASK, ETOP_MII_NORMAL,
 255                                   LTQ_ETOP_CFG);
 256                 break;
 257
 258         default:
 259                 netdev_err(dev, "unknown mii mode %d\n",
 260                            priv->pldata->mii_mode);
 261                 return -ENOTSUPP;
 262         }
 263
 264         /* enable crc generation */
 265         ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
 266
 267         ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, priv->rx_burst_len);
 268
 269         for (i = 0; i < MAX_DMA_CHAN; i++) {
 270                 int irq = LTQ_DMA_CH0_INT + i;
 271                 struct ltq_etop_chan *ch = &priv->ch[i];
 272
 273                 ch->dma.nr = i;
 274                 ch->idx = ch->dma.nr;
 275                 ch->dma.dev = &priv->pdev->dev;
 276
 277                 if (IS_TX(i)) {
 278                         ltq_dma_alloc_tx(&ch->dma);
 279                         err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
 280                         if (err) {
 281                                 netdev_err(dev,
 282                                            "Unable to get Tx DMA IRQ %d\n",
 283                                            irq);
 284                                 return err;
 285                         }
 286                 } else if (IS_RX(i)) {
 287                         ltq_dma_alloc_rx(&ch->dma);
 288                         for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
 289                                         ch->dma.desc++)
 290                                 if (ltq_etop_alloc_skb(ch))
 291                                         return -ENOMEM;
 292                         ch->dma.desc = 0;
 293                         err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
 294                         if (err) {
 295                                 netdev_err(dev,
 296                                            "Unable to get Rx DMA IRQ %d\n",
 297                                            irq);
 298                                 return err;
 299                         }
 300                 }
 301                 ch->dma.irq = irq;
 302         }
 303         return 0;
 304 }
 305
 306 static void
 307 ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
 308 {
 309         strscpy(info->driver, "Lantiq ETOP", sizeof(info->driver));
 310         strscpy(info->bus_info, "internal", sizeof(info->bus_info));
 311         strscpy(info->version, DRV_VERSION, sizeof(info->version));
 312 }
 313
 314 static const struct ethtool_ops ltq_etop_ethtool_ops = {
 315         .get_drvinfo = ltq_etop_get_drvinfo,
 316         .nway_reset = phy_ethtool_nway_reset,
 317         .get_link_ksettings = phy_ethtool_get_link_ksettings,
 318         .set_link_ksettings = phy_ethtool_set_link_ksettings,
 319 };
 320
 321 static int
 322 ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
 323 {
 324         u32 val = MDIO_REQUEST |
 325                 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
 326                 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
 327                 phy_data;
 328
 329         while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
 330                 ;
 331         ltq_etop_w32(val, LTQ_ETOP_MDIO);
 332         return 0;
 333 }
 334
 335 static int
 336 ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg)
 337 {
 338         u32 val = MDIO_REQUEST | MDIO_READ |
 339                 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
 340                 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
 341
 342         while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
 343                 ;
 344         ltq_etop_w32(val, LTQ_ETOP_MDIO);
 345         while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
 346                 ;
 347         val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
 348         return val;
 349 }
 350
 351 static void
 352 ltq_etop_mdio_link(struct net_device *dev)
 353 {
 354         /* nothing to do  */
 355 }
 356
 357 static int
 358 ltq_etop_mdio_probe(struct net_device *dev)
 359 {
 360         struct ltq_etop_priv *priv = netdev_priv(dev);
 361         struct phy_device *phydev;
 362
 363         phydev = phy_find_first(priv->mii_bus);
 364
 365         if (!phydev) {
 366                 netdev_err(dev, "no PHY found\n");
 367                 return -ENODEV;
 368         }
 369
 370         phydev = phy_connect(dev, phydev_name(phydev),
 371                              &ltq_etop_mdio_link, priv->pldata->mii_mode);
 372
 373         if (IS_ERR(phydev)) {
 374                 netdev_err(dev, "Could not attach to PHY\n");
 375                 return PTR_ERR(phydev);
 376         }
 377
 378         phy_set_max_speed(phydev, SPEED_100);
 379
 380         phy_attached_info(phydev);
 381
 382         return 0;
 383 }
 384
 385 static int
 386 ltq_etop_mdio_init(struct net_device *dev)
 387 {
 388         struct ltq_etop_priv *priv = netdev_priv(dev);
 389         int err;
 390
 391         priv->mii_bus = mdiobus_alloc();
 392         if (!priv->mii_bus) {
 393                 netdev_err(dev, "failed to allocate mii bus\n");
 394                 err = -ENOMEM;
 395                 goto err_out;
 396         }
 397
 398         priv->mii_bus->priv = dev;
 399         priv->mii_bus->read = ltq_etop_mdio_rd;
 400         priv->mii_bus->write = ltq_etop_mdio_wr;
 401         priv->mii_bus->name = "ltq_mii";
 402         snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
 403                  priv->pdev->name, priv->pdev->id);
 404         if (mdiobus_register(priv->mii_bus)) {
 405                 err = -ENXIO;
 406                 goto err_out_free_mdiobus;
 407         }
 408
 409         if (ltq_etop_mdio_probe(dev)) {
 410                 err = -ENXIO;
 411                 goto err_out_unregister_bus;
 412         }
 413         return 0;
 414
 415 err_out_unregister_bus:
 416         mdiobus_unregister(priv->mii_bus);
 417 err_out_free_mdiobus:
 418         mdiobus_free(priv->mii_bus);
 419 err_out:
 420         return err;
 421 }
 422
 423 static void
 424 ltq_etop_mdio_cleanup(struct net_device *dev)
 425 {
 426         struct ltq_etop_priv *priv = netdev_priv(dev);
 427
 428         phy_disconnect(dev->phydev);
 429         mdiobus_unregister(priv->mii_bus);
 430         mdiobus_free(priv->mii_bus);
 431 }
 432
 433 static int
 434 ltq_etop_open(struct net_device *dev)
 435 {
 436         struct ltq_etop_priv *priv = netdev_priv(dev);
 437         int i;
 438
 439         for (i = 0; i < MAX_DMA_CHAN; i++) {
 440                 struct ltq_etop_chan *ch = &priv->ch[i];
 441
 442                 if (!IS_TX(i) && (!IS_RX(i)))
 443                         continue;
 444                 ltq_dma_open(&ch->dma);
 445                 ltq_dma_enable_irq(&ch->dma);
 446                 napi_enable(&ch->napi);
 447         }
 448         phy_start(dev->phydev);
 449         netif_tx_start_all_queues(dev);
 450         return 0;
 451 }
 452
 453 static int
 454 ltq_etop_stop(struct net_device *dev)
 455 {
 456         struct ltq_etop_priv *priv = netdev_priv(dev);
 457         int i;
 458
 459         netif_tx_stop_all_queues(dev);
 460         phy_stop(dev->phydev);
 461         for (i = 0; i < MAX_DMA_CHAN; i++) {
 462                 struct ltq_etop_chan *ch = &priv->ch[i];
 463
 464                 if (!IS_RX(i) && !IS_TX(i))
 465                         continue;
 466                 napi_disable(&ch->napi);
 467                 ltq_dma_close(&ch->dma);
 468         }
 469         return 0;
 470 }
 471
 472 static netdev_tx_t
 473 ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
 474 {
 475         int queue = skb_get_queue_mapping(skb);
 476         struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
 477         struct ltq_etop_priv *priv = netdev_priv(dev);
 478         struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
 479         struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
 480         int len;
 481         unsigned long flags;
 482         u32 byte_offset;
 483
 484         if (skb_put_padto(skb, ETH_ZLEN))
 485                 return NETDEV_TX_OK;
 486         len = skb->len;
 487
 488         if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
 489                 netdev_err(dev, "tx ring full\n");
 490                 netif_tx_stop_queue(txq);
 491                 return NETDEV_TX_BUSY;
 492         }
 493
 494         /* dma needs to start on a burst length value aligned address */
 495         byte_offset = CPHYSADDR(skb->data) % (priv->tx_burst_len * 4);
 496         ch->skb[ch->dma.desc] = skb;
 497
 498         netif_trans_update(dev);
 499
 500         spin_lock_irqsave(&priv->lock, flags);
 501         desc->addr = ((unsigned int)dma_map_single(&priv->pdev->dev, skb->data, len,
 502                                                 DMA_TO_DEVICE)) - byte_offset;
 503         /* Make sure the address is written before we give it to HW */
 504         wmb();
 505         desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
 506                 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
 507         ch->dma.desc++;
 508         ch->dma.desc %= LTQ_DESC_NUM;
 509         spin_unlock_irqrestore(&priv->lock, flags);
 510
 511         if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
 512                 netif_tx_stop_queue(txq);
 513
 514         return NETDEV_TX_OK;
 515 }
 516
 517 static int
 518 ltq_etop_change_mtu(struct net_device *dev, int new_mtu)
 519 {
 520         struct ltq_etop_priv *priv = netdev_priv(dev);
 521         unsigned long flags;
 522
 523         WRITE_ONCE(dev->mtu, new_mtu);
 524
 525         spin_lock_irqsave(&priv->lock, flags);
 526         ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN);
 527         spin_unlock_irqrestore(&priv->lock, flags);
 528
 529         return 0;
 530 }
 531
 532 static int
 533 ltq_etop_set_mac_address(struct net_device *dev, void *p)
 534 {
 535         int ret = eth_mac_addr(dev, p);
 536
 537         if (!ret) {
 538                 struct ltq_etop_priv *priv = netdev_priv(dev);
 539                 unsigned long flags;
 540
 541                 /* store the mac for the unicast filter */
 542                 spin_lock_irqsave(&priv->lock, flags);
 543                 ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0);
 544                 ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16,
 545                              LTQ_ETOP_MAC_DA1);
 546                 spin_unlock_irqrestore(&priv->lock, flags);
 547         }
 548         return ret;
 549 }
 550
 551 static void
 552 ltq_etop_set_multicast_list(struct net_device *dev)
 553 {
 554         struct ltq_etop_priv *priv = netdev_priv(dev);
 555         unsigned long flags;
 556
 557         /* ensure that the unicast filter is not enabled in promiscious mode */
 558         spin_lock_irqsave(&priv->lock, flags);
 559         if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI))
 560                 ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0);
 561         else
 562                 ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0);
 563         spin_unlock_irqrestore(&priv->lock, flags);
 564 }
 565
 566 static int
 567 ltq_etop_init(struct net_device *dev)
 568 {
 569         struct ltq_etop_priv *priv = netdev_priv(dev);
 570         struct sockaddr mac;
 571         int err;
 572         bool random_mac = false;
 573
 574         dev->watchdog_timeo = 10 * HZ;
 575         err = ltq_etop_hw_init(dev);
 576         if (err)
 577                 goto err_hw;
 578         ltq_etop_change_mtu(dev, 1500);
 579
 580         memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
 581         if (!is_valid_ether_addr(mac.sa_data)) {
 582                 pr_warn("etop: invalid MAC, using random\n");
 583                 eth_random_addr(mac.sa_data);
 584                 random_mac = true;
 585         }
 586
 587         err = ltq_etop_set_mac_address(dev, &mac);
 588         if (err)
 589                 goto err_netdev;
 590
 591         /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
 592         if (random_mac)
 593                 dev->addr_assign_type = NET_ADDR_RANDOM;
 594
 595         ltq_etop_set_multicast_list(dev);
 596         err = ltq_etop_mdio_init(dev);
 597         if (err)
 598                 goto err_netdev;
 599         return 0;
 600
 601 err_netdev:
 602         unregister_netdev(dev);
 603         free_netdev(dev);
 604 err_hw:
 605         ltq_etop_hw_exit(dev);
 606         return err;
 607 }
 608
 609 static void
 610 ltq_etop_tx_timeout(struct net_device *dev, unsigned int txqueue)
 611 {
 612         int err;
 613
 614         ltq_etop_hw_exit(dev);
 615         err = ltq_etop_hw_init(dev);
 616         if (err)
 617                 goto err_hw;
 618         netif_trans_update(dev);
 619         netif_wake_queue(dev);
 620         return;
 621
 622 err_hw:
 623         ltq_etop_hw_exit(dev);
 624         netdev_err(dev, "failed to restart etop after TX timeout\n");
 625 }
 626
 627 static const struct net_device_ops ltq_eth_netdev_ops = {
 628         .ndo_open = ltq_etop_open,
 629         .ndo_stop = ltq_etop_stop,
 630         .ndo_start_xmit = ltq_etop_tx,
 631         .ndo_change_mtu = ltq_etop_change_mtu,
 632         .ndo_eth_ioctl = phy_do_ioctl,
 633         .ndo_set_mac_address = ltq_etop_set_mac_address,
 634         .ndo_validate_addr = eth_validate_addr,
 635         .ndo_set_rx_mode = ltq_etop_set_multicast_list,
 636         .ndo_select_queue = dev_pick_tx_zero,
 637         .ndo_init = ltq_etop_init,
 638         .ndo_tx_timeout = ltq_etop_tx_timeout,
 639 };
 640
 641 static int __init
 642 ltq_etop_probe(struct platform_device *pdev)
 643 {
 644         struct net_device *dev;
 645         struct ltq_etop_priv *priv;
 646         struct resource *res;
 647         int err;
 648         int i;
 649
 650         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 651         if (!res) {
 652                 dev_err(&pdev->dev, "failed to get etop resource\n");
 653                 err = -ENOENT;
 654                 goto err_out;
 655         }
 656
 657         res = devm_request_mem_region(&pdev->dev, res->start,
 658                                       resource_size(res), dev_name(&pdev->dev));
 659         if (!res) {
 660                 dev_err(&pdev->dev, "failed to request etop resource\n");
 661                 err = -EBUSY;
 662                 goto err_out;
 663         }
 664
 665         ltq_etop_membase = devm_ioremap(&pdev->dev, res->start,
 666                                         resource_size(res));
 667         if (!ltq_etop_membase) {
 668                 dev_err(&pdev->dev, "failed to remap etop engine %d\n",
 669                         pdev->id);
 670                 err = -ENOMEM;
 671                 goto err_out;
 672         }
 673
 674         dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
 675         if (!dev) {
 676                 err = -ENOMEM;
 677                 goto err_out;
 678         }
 679         dev->netdev_ops = &ltq_eth_netdev_ops;
 680         dev->ethtool_ops = &ltq_etop_ethtool_ops;
 681         priv = netdev_priv(dev);
 682         priv->res = res;
 683         priv->pdev = pdev;
 684         priv->pldata = dev_get_platdata(&pdev->dev);
 685         priv->netdev = dev;
 686         spin_lock_init(&priv->lock);
 687         SET_NETDEV_DEV(dev, &pdev->dev);
 688
 689         err = device_property_read_u32(&pdev->dev, "lantiq,tx-burst-length", &priv->tx_burst_len);
 690         if (err < 0) {
 691                 dev_err(&pdev->dev, "unable to read tx-burst-length property\n");
 692                 goto err_free;
 693         }
 694
 695         err = device_property_read_u32(&pdev->dev, "lantiq,rx-burst-length", &priv->rx_burst_len);
 696         if (err < 0) {
 697                 dev_err(&pdev->dev, "unable to read rx-burst-length property\n");
 698                 goto err_free;
 699         }
 700
 701         for (i = 0; i < MAX_DMA_CHAN; i++) {
 702                 if (IS_TX(i))
 703                         netif_napi_add_weight(dev, &priv->ch[i].napi,
 704                                               ltq_etop_poll_tx, 8);
 705                 else if (IS_RX(i))
 706                         netif_napi_add_weight(dev, &priv->ch[i].napi,
 707                                               ltq_etop_poll_rx, 32);
 708                 priv->ch[i].netdev = dev;
 709         }
 710
 711         err = register_netdev(dev);
 712         if (err)
 713                 goto err_free;
 714
 715         platform_set_drvdata(pdev, dev);
 716         return 0;
 717
 718 err_free:
 719         free_netdev(dev);
 720 err_out:
 721         return err;
 722 }
 723
 724 static void ltq_etop_remove(struct platform_device *pdev)
 725 {
 726         struct net_device *dev = platform_get_drvdata(pdev);
 727
 728         if (dev) {
 729                 netif_tx_stop_all_queues(dev);
 730                 ltq_etop_hw_exit(dev);
 731                 ltq_etop_mdio_cleanup(dev);
 732                 unregister_netdev(dev);
 733         }
 734 }
 735
 736 static struct platform_driver ltq_mii_driver = {
 737         .remove = ltq_etop_remove,
 738         .driver = {
 739                 .name = "ltq_etop",
 740         },
 741 };
 742
 743 static int __init
 744 init_ltq_etop(void)
 745 {
 746         int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
 747
 748         if (ret)
 749                 pr_err("ltq_etop: Error registering platform driver!");
 750         return ret;
 751 }
 752
 753 static void __exit
 754 exit_ltq_etop(void)
 755 {
 756         platform_driver_unregister(&ltq_mii_driver);
 757 }
 758
 759 module_init(init_ltq_etop);
 760 module_exit(exit_ltq_etop);
 761
 762 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 763 MODULE_DESCRIPTION("Lantiq SoC ETOP");
 764 MODULE_LICENSE("GPL");