drivers/net/ethernet/meta/fbnic/fbnic_csr.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (c) Meta Platforms, Inc. and affiliates. */
   3
   4 #ifndef _FBNIC_CSR_H_
   5 #define _FBNIC_CSR_H_
   6
   7 #include <linux/bitops.h>
   8
   9 #define CSR_BIT(nr)             (1u << (nr))
  10 #define CSR_GENMASK(h, l)       GENMASK(h, l)
  11
  12 #define DESC_BIT(nr)            BIT_ULL(nr)
  13 #define DESC_GENMASK(h, l)      GENMASK_ULL(h, l)
  14
  15 /* Defines the minimum firmware version required by the driver */
  16 #define MIN_FW_MAJOR_VERSION    0
  17 #define MIN_FW_MINOR_VERSION    10
  18 #define MIN_FW_BUILD_VERSION    6
  19 #define MIN_FW_VERSION_CODE     (MIN_FW_MAJOR_VERSION * (1u << 24) + \
  20                                  MIN_FW_MINOR_VERSION * (1u << 16) + \
  21                                  MIN_FW_BUILD_VERSION)
  22
  23 #define PCI_DEVICE_ID_META_FBNIC_ASIC           0x0013
  24
  25 #define FBNIC_CLOCK_FREQ        (600 * (1000 * 1000))
  26
  27 /* Transmit Work Descriptor Format */
  28 /* Length, Type, Offset Masks and Shifts */
  29 #define FBNIC_TWD_L2_HLEN_MASK                  DESC_GENMASK(5, 0)
  30
  31 #define FBNIC_TWD_L3_TYPE_MASK                  DESC_GENMASK(7, 6)
  32 enum {
  33         FBNIC_TWD_L3_TYPE_OTHER = 0,
  34         FBNIC_TWD_L3_TYPE_IPV4  = 1,
  35         FBNIC_TWD_L3_TYPE_IPV6  = 2,
  36         FBNIC_TWD_L3_TYPE_V6V6  = 3,
  37 };
  38
  39 #define FBNIC_TWD_L3_OHLEN_MASK                 DESC_GENMASK(15, 8)
  40 #define FBNIC_TWD_L3_IHLEN_MASK                 DESC_GENMASK(23, 16)
  41
  42 enum {
  43         FBNIC_TWD_L4_TYPE_OTHER = 0,
  44         FBNIC_TWD_L4_TYPE_TCP   = 1,
  45         FBNIC_TWD_L4_TYPE_UDP   = 2,
  46 };
  47
  48 #define FBNIC_TWD_CSUM_OFFSET_MASK              DESC_GENMASK(27, 24)
  49 #define FBNIC_TWD_L4_HLEN_MASK                  DESC_GENMASK(31, 28)
  50
  51 /* Flags and Type */
  52 #define FBNIC_TWD_L4_TYPE_MASK                  DESC_GENMASK(33, 32)
  53 #define FBNIC_TWD_FLAG_REQ_TS                   DESC_BIT(34)
  54 #define FBNIC_TWD_FLAG_REQ_LSO                  DESC_BIT(35)
  55 #define FBNIC_TWD_FLAG_REQ_CSO                  DESC_BIT(36)
  56 #define FBNIC_TWD_FLAG_REQ_COMPLETION           DESC_BIT(37)
  57 #define FBNIC_TWD_FLAG_DEST_MAC                 DESC_BIT(43)
  58 #define FBNIC_TWD_FLAG_DEST_BMC                 DESC_BIT(44)
  59 #define FBNIC_TWD_FLAG_DEST_FW                  DESC_BIT(45)
  60 #define FBNIC_TWD_TYPE_MASK                     DESC_GENMASK(47, 46)
  61 enum {
  62         FBNIC_TWD_TYPE_META     = 0,
  63         FBNIC_TWD_TYPE_OPT_META = 1,
  64         FBNIC_TWD_TYPE_AL       = 2,
  65         FBNIC_TWD_TYPE_LAST_AL  = 3,
  66 };
  67
  68 /* MSS and Completion Req */
  69 #define FBNIC_TWD_MSS_MASK                      DESC_GENMASK(61, 48)
  70
  71 #define FBNIC_TWD_TS_MASK                       DESC_GENMASK(39, 0)
  72 #define FBNIC_TWD_ADDR_MASK                     DESC_GENMASK(45, 0)
  73 #define FBNIC_TWD_LEN_MASK                      DESC_GENMASK(63, 48)
  74
  75 /* Tx Completion Descriptor Format */
  76 #define FBNIC_TCD_TYPE0_HEAD0_MASK              DESC_GENMASK(15, 0)
  77 #define FBNIC_TCD_TYPE0_HEAD1_MASK              DESC_GENMASK(31, 16)
  78
  79 #define FBNIC_TCD_TYPE1_TS_MASK                 DESC_GENMASK(39, 0)
  80
  81 #define FBNIC_TCD_STATUS_MASK                   DESC_GENMASK(59, 48)
  82 #define FBNIC_TCD_STATUS_TS_INVALID             DESC_BIT(48)
  83 #define FBNIC_TCD_STATUS_ILLEGAL_TS_REQ         DESC_BIT(49)
  84 #define FBNIC_TCD_TWQ1                          DESC_BIT(60)
  85 #define FBNIC_TCD_TYPE_MASK                     DESC_GENMASK(62, 61)
  86 enum {
  87         FBNIC_TCD_TYPE_0        = 0,
  88         FBNIC_TCD_TYPE_1        = 1,
  89 };
  90
  91 #define FBNIC_TCD_DONE                          DESC_BIT(63)
  92
  93 /* Rx Buffer Descriptor Format
  94  *
  95  * The layout of this can vary depending on the page size of the system.
  96  *
  97  * If the page size is 4K then the layout will simply consist of ID for
  98  * the 16 most significant bits, and the lower 46 are essentially the page
  99  * address with the lowest 12 bits being reserved 0 due to the fact that
 100  * a page will be aligned.
 101  *
 102  * If the page size is larger than 4K then the lower n bits of the ID and
 103  * page address will be reserved for the fragment ID. This fragment will
 104  * be 4K in size and will be used to index both the DMA address and the ID
 105  * by the same amount.
 106  */
 107 #define FBNIC_BD_DESC_ADDR_MASK                 DESC_GENMASK(45, 12)
 108 #define FBNIC_BD_DESC_ID_MASK                   DESC_GENMASK(63, 48)
 109 #define FBNIC_BD_FRAG_SIZE \
 110         (FBNIC_BD_DESC_ADDR_MASK & ~(FBNIC_BD_DESC_ADDR_MASK - 1))
 111 #define FBNIC_BD_FRAG_COUNT \
 112         (PAGE_SIZE / FBNIC_BD_FRAG_SIZE)
 113 #define FBNIC_BD_FRAG_ADDR_MASK \
 114         (FBNIC_BD_DESC_ADDR_MASK & \
 115          ~(FBNIC_BD_DESC_ADDR_MASK * FBNIC_BD_FRAG_COUNT))
 116 #define FBNIC_BD_FRAG_ID_MASK \
 117         (FBNIC_BD_DESC_ID_MASK & \
 118          ~(FBNIC_BD_DESC_ID_MASK * FBNIC_BD_FRAG_COUNT))
 119 #define FBNIC_BD_PAGE_ADDR_MASK \
 120         (FBNIC_BD_DESC_ADDR_MASK & ~FBNIC_BD_FRAG_ADDR_MASK)
 121 #define FBNIC_BD_PAGE_ID_MASK \
 122         (FBNIC_BD_DESC_ID_MASK & ~FBNIC_BD_FRAG_ID_MASK)
 123
 124 /* Rx Completion Queue Descriptors */
 125 #define FBNIC_RCD_TYPE_MASK                     DESC_GENMASK(62, 61)
 126 enum {
 127         FBNIC_RCD_TYPE_HDR_AL   = 0,
 128         FBNIC_RCD_TYPE_PAY_AL   = 1,
 129         FBNIC_RCD_TYPE_OPT_META = 2,
 130         FBNIC_RCD_TYPE_META     = 3,
 131 };
 132
 133 #define FBNIC_RCD_DONE                          DESC_BIT(63)
 134
 135 /* Address/Length Completion Descriptors */
 136 #define FBNIC_RCD_AL_BUFF_ID_MASK               DESC_GENMASK(15, 0)
 137 #define FBNIC_RCD_AL_BUFF_FRAG_MASK             (FBNIC_BD_FRAG_COUNT - 1)
 138 #define FBNIC_RCD_AL_BUFF_PAGE_MASK \
 139         (FBNIC_RCD_AL_BUFF_ID_MASK & ~FBNIC_RCD_AL_BUFF_FRAG_MASK)
 140 #define FBNIC_RCD_AL_BUFF_LEN_MASK              DESC_GENMASK(28, 16)
 141 #define FBNIC_RCD_AL_BUFF_OFF_MASK              DESC_GENMASK(43, 32)
 142 #define FBNIC_RCD_AL_PAGE_FIN                   DESC_BIT(60)
 143
 144 /* Header AL specific values */
 145 #define FBNIC_RCD_HDR_AL_OVERFLOW               DESC_BIT(53)
 146 #define FBNIC_RCD_HDR_AL_DMA_HINT_MASK          DESC_GENMASK(59, 54)
 147 enum {
 148         FBNIC_RCD_HDR_AL_DMA_HINT_NONE  = 0,
 149         FBNIC_RCD_HDR_AL_DMA_HINT_L2    = 1,
 150         FBNIC_RCD_HDR_AL_DMA_HINT_L3    = 2,
 151         FBNIC_RCD_HDR_AL_DMA_HINT_L4    = 4,
 152 };
 153
 154 /* Optional Metadata Completion Descriptors */
 155 #define FBNIC_RCD_OPT_META_TS_MASK              DESC_GENMASK(39, 0)
 156 #define FBNIC_RCD_OPT_META_ACTION_MASK          DESC_GENMASK(45, 40)
 157 #define FBNIC_RCD_OPT_META_ACTION               DESC_BIT(57)
 158 #define FBNIC_RCD_OPT_META_TS                   DESC_BIT(58)
 159 #define FBNIC_RCD_OPT_META_TYPE_MASK            DESC_GENMASK(60, 59)
 160
 161 /* Metadata Completion Descriptors */
 162 #define FBNIC_RCD_META_RSS_HASH_MASK            DESC_GENMASK(31, 0)
 163 #define FBNIC_RCD_META_L2_CSUM_MASK             DESC_GENMASK(47, 32)
 164 #define FBNIC_RCD_META_L3_TYPE_MASK             DESC_GENMASK(49, 48)
 165 enum {
 166         FBNIC_RCD_META_L3_TYPE_OTHER    = 0,
 167         FBNIC_RCD_META_L3_TYPE_IPV4     = 1,
 168         FBNIC_RCD_META_L3_TYPE_IPV6     = 2,
 169         FBNIC_RCD_META_L3_TYPE_V6V6     = 3,
 170 };
 171
 172 #define FBNIC_RCD_META_L4_TYPE_MASK             DESC_GENMASK(51, 50)
 173 enum {
 174         FBNIC_RCD_META_L4_TYPE_OTHER    = 0,
 175         FBNIC_RCD_META_L4_TYPE_TCP      = 1,
 176         FBNIC_RCD_META_L4_TYPE_UDP      = 2,
 177 };
 178
 179 #define FBNIC_RCD_META_L4_CSUM_UNNECESSARY      DESC_BIT(52)
 180 #define FBNIC_RCD_META_ERR_MAC_EOP              DESC_BIT(53)
 181 #define FBNIC_RCD_META_ERR_TRUNCATED_FRAME      DESC_BIT(54)
 182 #define FBNIC_RCD_META_ERR_PARSER               DESC_BIT(55)
 183 #define FBNIC_RCD_META_UNCORRECTABLE_ERR_MASK   \
 184         (FBNIC_RCD_META_ERR_MAC_EOP | FBNIC_RCD_META_ERR_TRUNCATED_FRAME)
 185 #define FBNIC_RCD_META_ECN                      DESC_BIT(60)
 186
 187 /* Register Definitions
 188  *
 189  * The registers are laid as indexes into an le32 array. As such the actual
 190  * address is 4 times the index value. Below each register is defined as 3
 191  * fields, name, index, and Address.
 192  *
 193  *      Name                            Index           Address
 194  *************************************************************************/
 195 /* Interrupt Registers */
 196 #define FBNIC_CSR_START_INTR            0x00000 /* CSR section delimiter */
 197 #define FBNIC_INTR_STATUS(n)            (0x00000 + (n)) /* 0x00000 + 4*n */
 198 #define FBNIC_INTR_STATUS_CNT                   8
 199 #define FBNIC_INTR_MASK(n)              (0x00008 + (n)) /* 0x00020 + 4*n */
 200 #define FBNIC_INTR_MASK_CNT                     8
 201 #define FBNIC_INTR_SET(n)               (0x00010 + (n)) /* 0x00040 + 4*n */
 202 #define FBNIC_INTR_SET_CNT                      8
 203 #define FBNIC_INTR_CLEAR(n)             (0x00018 + (n)) /* 0x00060 + 4*n */
 204 #define FBNIC_INTR_CLEAR_CNT                    8
 205 #define FBNIC_INTR_SW_STATUS(n)         (0x00020 + (n)) /* 0x00080 + 4*n */
 206 #define FBNIC_INTR_SW_STATUS_CNT                8
 207 #define FBNIC_INTR_SW_AC_MODE(n)        (0x00028 + (n)) /* 0x000a0 + 4*n */
 208 #define FBNIC_INTR_SW_AC_MODE_CNT               8
 209 #define FBNIC_INTR_MASK_SET(n)          (0x00030 + (n)) /* 0x000c0 + 4*n */
 210 #define FBNIC_INTR_MASK_SET_CNT                 8
 211 #define FBNIC_INTR_MASK_CLEAR(n)        (0x00038 + (n)) /* 0x000e0 + 4*n */
 212 #define FBNIC_INTR_MASK_CLEAR_CNT               8
 213 #define FBNIC_MAX_MSIX_VECS             256U
 214 #define FBNIC_INTR_MSIX_CTRL(n)         (0x00040 + (n)) /* 0x00100 + 4*n */
 215 #define FBNIC_INTR_MSIX_CTRL_VECTOR_MASK        CSR_GENMASK(7, 0)
 216 #define FBNIC_INTR_MSIX_CTRL_ENABLE             CSR_BIT(31)
 217 enum {
 218         FBNIC_INTR_MSIX_CTRL_PCS_IDX    = 34,
 219 };
 220
 221 #define FBNIC_CSR_END_INTR              0x0005f /* CSR section delimiter */
 222
 223 /* Interrupt MSIX Registers */
 224 #define FBNIC_CSR_START_INTR_CQ         0x00400 /* CSR section delimiter */
 225 #define FBNIC_INTR_CQ_REARM(n) \
 226                                 (0x00400 + 4 * (n))     /* 0x01000 + 16*n */
 227 #define FBNIC_INTR_CQ_REARM_CNT                 256
 228 #define FBNIC_INTR_CQ_REARM_RCQ_TIMEOUT         CSR_GENMASK(13, 0)
 229 #define FBNIC_INTR_CQ_REARM_RCQ_TIMEOUT_UPD_EN  CSR_BIT(14)
 230 #define FBNIC_INTR_CQ_REARM_TCQ_TIMEOUT         CSR_GENMASK(28, 15)
 231 #define FBNIC_INTR_CQ_REARM_TCQ_TIMEOUT_UPD_EN  CSR_BIT(29)
 232 #define FBNIC_INTR_CQ_REARM_INTR_RELOAD         CSR_BIT(30)
 233 #define FBNIC_INTR_CQ_REARM_INTR_UNMASK         CSR_BIT(31)
 234
 235 #define FBNIC_INTR_RCQ_TIMEOUT(n) \
 236                                 (0x00401 + 4 * (n))     /* 0x01004 + 16*n */
 237 #define FBNIC_INTR_RCQ_TIMEOUT_CNT              256
 238 #define FBNIC_INTR_TCQ_TIMEOUT(n) \
 239                                 (0x00402 + 4 * (n))     /* 0x01008 + 16*n */
 240 #define FBNIC_INTR_TCQ_TIMEOUT_CNT              256
 241 #define FBNIC_CSR_END_INTR_CQ           0x007fe /* CSR section delimiter */
 242
 243 /* Global QM Tx registers */
 244 #define FBNIC_CSR_START_QM_TX           0x00800 /* CSR section delimiter */
 245 #define FBNIC_QM_TWQ_IDLE(n)            (0x00800 + (n)) /* 0x02000 + 4*n */
 246 #define FBNIC_QM_TWQ_IDLE_CNT                   8
 247 #define FBNIC_QM_TWQ_DEFAULT_META_L     0x00818         /* 0x02060 */
 248 #define FBNIC_QM_TWQ_DEFAULT_META_H     0x00819         /* 0x02064 */
 249
 250 #define FBNIC_QM_TQS_CTL0               0x0081b         /* 0x0206c */
 251 #define FBNIC_QM_TQS_CTL0_LSO_TS_MASK   CSR_BIT(0)
 252 enum {
 253         FBNIC_QM_TQS_CTL0_LSO_TS_FIRST  = 0,
 254         FBNIC_QM_TQS_CTL0_LSO_TS_LAST   = 1,
 255 };
 256
 257 #define FBNIC_QM_TQS_CTL0_PREFETCH_THRESH       CSR_GENMASK(7, 1)
 258 enum {
 259         FBNIC_QM_TQS_CTL0_PREFETCH_THRESH_MIN   = 16,
 260 };
 261
 262 #define FBNIC_QM_TQS_CTL1               0x0081c         /* 0x02070 */
 263 #define FBNIC_QM_TQS_CTL1_MC_MAX_CREDITS        CSR_GENMASK(7, 0)
 264 #define FBNIC_QM_TQS_CTL1_BULK_MAX_CREDITS      CSR_GENMASK(15, 8)
 265 #define FBNIC_QM_TQS_MTU_CTL0           0x0081d         /* 0x02074 */
 266 #define FBNIC_QM_TQS_MTU_CTL1           0x0081e         /* 0x02078 */
 267 #define FBNIC_QM_TQS_MTU_CTL1_BULK              CSR_GENMASK(13, 0)
 268 #define FBNIC_QM_TCQ_IDLE(n)            (0x00821 + (n)) /* 0x02084 + 4*n */
 269 #define FBNIC_QM_TCQ_IDLE_CNT                   4
 270 #define FBNIC_QM_TCQ_CTL0               0x0082d         /* 0x020b4 */
 271 #define FBNIC_QM_TCQ_CTL0_COAL_WAIT             CSR_GENMASK(15, 0)
 272 #define FBNIC_QM_TCQ_CTL0_TICK_CYCLES           CSR_GENMASK(26, 16)
 273 #define FBNIC_QM_TQS_IDLE(n)            (0x00830 + (n)) /* 0x020c0 + 4*n */
 274 #define FBNIC_QM_TQS_IDLE_CNT                   8
 275 #define FBNIC_QM_TQS_EDT_TS_RANGE       0x00849         /* 0x2124 */
 276 #define FBNIC_QM_TDE_IDLE(n)            (0x00853 + (n)) /* 0x0214c + 4*n */
 277 #define FBNIC_QM_TDE_IDLE_CNT                   8
 278 #define FBNIC_QM_TNI_TDF_CTL            0x0086c         /* 0x021b0 */
 279 #define FBNIC_QM_TNI_TDF_CTL_MRRS               CSR_GENMASK(1, 0)
 280 #define FBNIC_QM_TNI_TDF_CTL_CLS                CSR_GENMASK(3, 2)
 281 #define FBNIC_QM_TNI_TDF_CTL_MAX_OT             CSR_GENMASK(11, 4)
 282 #define FBNIC_QM_TNI_TDF_CTL_MAX_OB             CSR_GENMASK(23, 12)
 283 #define FBNIC_QM_TNI_TDE_CTL            0x0086d         /* 0x021b4 */
 284 #define FBNIC_QM_TNI_TDE_CTL_MRRS               CSR_GENMASK(1, 0)
 285 #define FBNIC_QM_TNI_TDE_CTL_CLS                CSR_GENMASK(3, 2)
 286 #define FBNIC_QM_TNI_TDE_CTL_MAX_OT             CSR_GENMASK(11, 4)
 287 #define FBNIC_QM_TNI_TDE_CTL_MAX_OB             CSR_GENMASK(24, 12)
 288 #define FBNIC_QM_TNI_TDE_CTL_MRRS_1K            CSR_BIT(25)
 289 #define FBNIC_QM_TNI_TCM_CTL            0x0086e         /* 0x021b8 */
 290 #define FBNIC_QM_TNI_TCM_CTL_MPS                CSR_GENMASK(1, 0)
 291 #define FBNIC_QM_TNI_TCM_CTL_CLS                CSR_GENMASK(3, 2)
 292 #define FBNIC_QM_TNI_TCM_CTL_MAX_OT             CSR_GENMASK(11, 4)
 293 #define FBNIC_QM_TNI_TCM_CTL_MAX_OB             CSR_GENMASK(23, 12)
 294 #define FBNIC_CSR_END_QM_TX             0x00873 /* CSR section delimiter */
 295
 296 /* Global QM Rx registers */
 297 #define FBNIC_CSR_START_QM_RX           0x00c00 /* CSR section delimiter */
 298 #define FBNIC_QM_RCQ_IDLE(n)            (0x00c00 + (n)) /* 0x03000 + 4*n */
 299 #define FBNIC_QM_RCQ_IDLE_CNT                   4
 300 #define FBNIC_QM_RCQ_CTL0               0x00c0c         /* 0x03030 */
 301 #define FBNIC_QM_RCQ_CTL0_COAL_WAIT             CSR_GENMASK(15, 0)
 302 #define FBNIC_QM_RCQ_CTL0_TICK_CYCLES           CSR_GENMASK(26, 16)
 303 #define FBNIC_QM_HPQ_IDLE(n)            (0x00c0f + (n)) /* 0x0303c + 4*n */
 304 #define FBNIC_QM_HPQ_IDLE_CNT                   4
 305 #define FBNIC_QM_PPQ_IDLE(n)            (0x00c13 + (n)) /* 0x0304c + 4*n */
 306 #define FBNIC_QM_PPQ_IDLE_CNT                   4
 307 #define FBNIC_QM_RNI_RBP_CTL            0x00c2d         /* 0x030b4 */
 308 #define FBNIC_QM_RNI_RBP_CTL_MRRS               CSR_GENMASK(1, 0)
 309 #define FBNIC_QM_RNI_RBP_CTL_CLS                CSR_GENMASK(3, 2)
 310 #define FBNIC_QM_RNI_RBP_CTL_MAX_OT             CSR_GENMASK(11, 4)
 311 #define FBNIC_QM_RNI_RBP_CTL_MAX_OB             CSR_GENMASK(23, 12)
 312 #define FBNIC_QM_RNI_RDE_CTL            0x00c2e         /* 0x030b8 */
 313 #define FBNIC_QM_RNI_RDE_CTL_MPS                CSR_GENMASK(1, 0)
 314 #define FBNIC_QM_RNI_RDE_CTL_CLS                CSR_GENMASK(3, 2)
 315 #define FBNIC_QM_RNI_RDE_CTL_MAX_OT             CSR_GENMASK(11, 4)
 316 #define FBNIC_QM_RNI_RDE_CTL_MAX_OB             CSR_GENMASK(23, 12)
 317 #define FBNIC_QM_RNI_RCM_CTL            0x00c2f         /* 0x030bc */
 318 #define FBNIC_QM_RNI_RCM_CTL_MPS                CSR_GENMASK(1, 0)
 319 #define FBNIC_QM_RNI_RCM_CTL_CLS                CSR_GENMASK(3, 2)
 320 #define FBNIC_QM_RNI_RCM_CTL_MAX_OT             CSR_GENMASK(11, 4)
 321 #define FBNIC_QM_RNI_RCM_CTL_MAX_OB             CSR_GENMASK(23, 12)
 322 #define FBNIC_CSR_END_QM_RX             0x00c34 /* CSR section delimiter */
 323
 324 /* TCE registers */
 325 #define FBNIC_CSR_START_TCE             0x04000 /* CSR section delimiter */
 326 #define FBNIC_TCE_REG_BASE              0x04000         /* 0x10000 */
 327
 328 #define FBNIC_TCE_LSO_CTRL              0x04000         /* 0x10000 */
 329 #define FBNIC_TCE_LSO_CTRL_TCPF_CLR_1ST         CSR_GENMASK(8, 0)
 330 #define FBNIC_TCE_LSO_CTRL_TCPF_CLR_MID         CSR_GENMASK(17, 9)
 331 #define FBNIC_TCE_LSO_CTRL_TCPF_CLR_END         CSR_GENMASK(26, 18)
 332 #define FBNIC_TCE_LSO_CTRL_IPID_MODE_INC        CSR_BIT(27)
 333
 334 #define FBNIC_TCE_CSO_CTRL              0x04001         /* 0x10004 */
 335 #define FBNIC_TCE_CSO_CTRL_TCP_ZERO_CSUM        CSR_BIT(0)
 336
 337 #define FBNIC_TCE_TXB_CTRL              0x04002         /* 0x10008 */
 338 #define FBNIC_TCE_TXB_CTRL_LOAD                 CSR_BIT(0)
 339 #define FBNIC_TCE_TXB_CTRL_TCAM_ENABLE          CSR_BIT(1)
 340 #define FBNIC_TCE_TXB_CTRL_DISABLE              CSR_BIT(2)
 341
 342 #define FBNIC_TCE_TXB_ENQ_WRR_CTRL      0x04003         /* 0x1000c */
 343 #define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT0      CSR_GENMASK(7, 0)
 344 #define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT1      CSR_GENMASK(15, 8)
 345 #define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT2      CSR_GENMASK(23, 16)
 346
 347 #define FBNIC_TCE_TXB_TEI_Q0_CTRL       0x04004         /* 0x10010 */
 348 #define FBNIC_TCE_TXB_TEI_Q1_CTRL       0x04005         /* 0x10014 */
 349 #define FBNIC_TCE_TXB_MC_Q_CTRL         0x04006         /* 0x10018 */
 350 #define FBNIC_TCE_TXB_RX_TEI_Q_CTRL     0x04007         /* 0x1001c */
 351 #define FBNIC_TCE_TXB_RX_BMC_Q_CTRL     0x04008         /* 0x10020 */
 352 #define FBNIC_TCE_TXB_Q_CTRL_START              CSR_GENMASK(10, 0)
 353 #define FBNIC_TCE_TXB_Q_CTRL_SIZE               CSR_GENMASK(22, 11)
 354
 355 #define FBNIC_TCE_TXB_TEI_DWRR_CTRL     0x04009         /* 0x10024 */
 356 #define FBNIC_TCE_TXB_TEI_DWRR_CTRL_QUANTUM0    CSR_GENMASK(7, 0)
 357 #define FBNIC_TCE_TXB_TEI_DWRR_CTRL_QUANTUM1    CSR_GENMASK(15, 8)
 358 #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL   0x0400a         /* 0x10028 */
 359 #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM0  CSR_GENMASK(7, 0)
 360 #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM1  CSR_GENMASK(15, 8)
 361 #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM2  CSR_GENMASK(23, 16)
 362
 363 #define FBNIC_TCE_TXB_CLDR_CFG          0x0400b         /* 0x1002c */
 364 #define FBNIC_TCE_TXB_CLDR_CFG_NUM_SLOT         CSR_GENMASK(5, 0)
 365 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG(n)  (0x0400c + (n)) /* 0x10030 + 4*n */
 366 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_CNT         16
 367 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_0 CSR_GENMASK(1, 0)
 368 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_1 CSR_GENMASK(3, 2)
 369 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_2 CSR_GENMASK(5, 4)
 370 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_3 CSR_GENMASK(7, 6)
 371 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_0 CSR_GENMASK(9, 8)
 372 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_1 CSR_GENMASK(11, 10)
 373 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_2 CSR_GENMASK(13, 12)
 374 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_3 CSR_GENMASK(15, 14)
 375 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_0 CSR_GENMASK(17, 16)
 376 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_1 CSR_GENMASK(19, 18)
 377 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_2 CSR_GENMASK(21, 20)
 378 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_3 CSR_GENMASK(23, 22)
 379 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_0 CSR_GENMASK(25, 24)
 380 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_1 CSR_GENMASK(27, 26)
 381 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_2 CSR_GENMASK(29, 28)
 382 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_3 CSR_GENMASK(31, 30)
 383
 384 #define FBNIC_TCE_BMC_MAX_PKTSZ         0x0403a         /* 0x100e8 */
 385 #define FBNIC_TCE_BMC_MAX_PKTSZ_TX              CSR_GENMASK(13, 0)
 386 #define FBNIC_TCE_BMC_MAX_PKTSZ_RX              CSR_GENMASK(27, 14)
 387 #define FBNIC_TCE_MC_MAX_PKTSZ          0x0403b         /* 0x100ec */
 388 #define FBNIC_TCE_MC_MAX_PKTSZ_TMI              CSR_GENMASK(13, 0)
 389
 390 #define FBNIC_TCE_SOP_PROT_CTRL         0x0403c         /* 0x100f0 */
 391 #define FBNIC_TCE_SOP_PROT_CTRL_TBI             CSR_GENMASK(7, 0)
 392 #define FBNIC_TCE_SOP_PROT_CTRL_TTI_FRM         CSR_GENMASK(14, 8)
 393 #define FBNIC_TCE_SOP_PROT_CTRL_TTI_CM          CSR_GENMASK(18, 15)
 394
 395 #define FBNIC_TCE_DROP_CTRL             0x0403d         /* 0x100f4 */
 396 #define FBNIC_TCE_DROP_CTRL_TTI_CM_DROP_EN      CSR_BIT(0)
 397 #define FBNIC_TCE_DROP_CTRL_TTI_FRM_DROP_EN     CSR_BIT(1)
 398 #define FBNIC_TCE_DROP_CTRL_TTI_TBI_DROP_EN     CSR_BIT(2)
 399
 400 #define FBNIC_TCE_TCAM_IDX2DEST_MAP     0x0404A         /* 0x10128 */
 401 #define FBNIC_TCE_TCAM_IDX2DEST_MAP_DEST_ID_0   CSR_GENMASK(3, 0)
 402 enum {
 403         FBNIC_TCE_TCAM_DEST_MAC         = 1,
 404         FBNIC_TCE_TCAM_DEST_BMC         = 2,
 405         FBNIC_TCE_TCAM_DEST_FW          = 4,
 406 };
 407
 408 #define FBNIC_TCE_TXB_TX_BMC_Q_CTRL     0x0404B         /* 0x1012c */
 409 #define FBNIC_TCE_TXB_BMC_DWRR_CTRL     0x0404C         /* 0x10130 */
 410 #define FBNIC_TCE_TXB_BMC_DWRR_CTRL_QUANTUM0    CSR_GENMASK(7, 0)
 411 #define FBNIC_TCE_TXB_BMC_DWRR_CTRL_QUANTUM1    CSR_GENMASK(15, 8)
 412 #define FBNIC_TCE_TXB_TEI_DWRR_CTRL_EXT 0x0404D         /* 0x10134 */
 413 #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_EXT \
 414                                         0x0404E         /* 0x10138 */
 415 #define FBNIC_TCE_TXB_BMC_DWRR_CTRL_EXT 0x0404F         /* 0x1013c */
 416 #define FBNIC_CSR_END_TCE               0x04050 /* CSR section delimiter */
 417
 418 /* TCE RAM registers */
 419 #define FBNIC_CSR_START_TCE_RAM         0x04200 /* CSR section delimiter */
 420 #define FBNIC_TCE_RAM_TCAM(m, n) \
 421         (0x04200 + 0x8 * (n) + (m))             /* 0x10800 + 32*n + 4*m */
 422 #define FBNIC_TCE_RAM_TCAM_MASK                 CSR_GENMASK(15, 0)
 423 #define FBNIC_TCE_RAM_TCAM_VALUE                CSR_GENMASK(31, 16)
 424 #define FBNIC_TCE_RAM_TCAM3(n)          (0x04218 + (n)) /* 0x010860 + 4*n */
 425 #define FBNIC_TCE_RAM_TCAM3_DEST_MASK           CSR_GENMASK(5, 3)
 426 #define FBNIC_TCE_RAM_TCAM3_MCQ_MASK            CSR_BIT(7)
 427 #define FBNIC_TCE_RAM_TCAM3_VALIDATE            CSR_BIT(31)
 428 #define FBNIC_CSR_END_TCE_RAM           0x0421F /* CSR section delimiter */
 429
 430 /* TMI registers */
 431 #define FBNIC_CSR_START_TMI             0x04400 /* CSR section delimiter */
 432 #define FBNIC_TMI_SOP_PROT_CTRL         0x04400         /* 0x11000 */
 433 #define FBNIC_TMI_DROP_CTRL             0x04401         /* 0x11004 */
 434 #define FBNIC_TMI_DROP_CTRL_EN                  CSR_BIT(0)
 435 #define FBNIC_CSR_END_TMI               0x0443f /* CSR section delimiter */
 436
 437 /* Precision Time Protocol Registers */
 438 #define FBNIC_CSR_START_PTP             0x04800 /* CSR section delimiter */
 439 #define FBNIC_PTP_REG_BASE              0x04800         /* 0x12000 */
 440
 441 #define FBNIC_PTP_CTRL                  0x04800         /* 0x12000 */
 442 #define FBNIC_PTP_CTRL_EN                       CSR_BIT(0)
 443 #define FBNIC_PTP_CTRL_MONO_EN                  CSR_BIT(4)
 444 #define FBNIC_PTP_CTRL_TQS_OUT_EN               CSR_BIT(8)
 445 #define FBNIC_PTP_CTRL_MAC_OUT_IVAL             CSR_GENMASK(16, 12)
 446 #define FBNIC_PTP_CTRL_TICK_IVAL                CSR_GENMASK(23, 20)
 447
 448 #define FBNIC_PTP_ADJUST                0x04801         /* 0x12004 */
 449 #define FBNIC_PTP_ADJUST_INIT                   CSR_BIT(0)
 450 #define FBNIC_PTP_ADJUST_SUB_NUDGE              CSR_BIT(8)
 451 #define FBNIC_PTP_ADJUST_ADD_NUDGE              CSR_BIT(16)
 452 #define FBNIC_PTP_ADJUST_ADDEND_SET             CSR_BIT(24)
 453
 454 #define FBNIC_PTP_INIT_HI               0x04802         /* 0x12008 */
 455 #define FBNIC_PTP_INIT_LO               0x04803         /* 0x1200c */
 456
 457 #define FBNIC_PTP_NUDGE_NS              0x04804         /* 0x12010 */
 458 #define FBNIC_PTP_NUDGE_SUBNS           0x04805         /* 0x12014 */
 459
 460 #define FBNIC_PTP_ADD_VAL_NS            0x04806         /* 0x12018 */
 461 #define FBNIC_PTP_ADD_VAL_NS_MASK               CSR_GENMASK(15, 0)
 462 #define FBNIC_PTP_ADD_VAL_SUBNS         0x04807 /* 0x1201c */
 463
 464 #define FBNIC_PTP_CTR_VAL_HI            0x04808         /* 0x12020 */
 465 #define FBNIC_PTP_CTR_VAL_LO            0x04809         /* 0x12024 */
 466
 467 #define FBNIC_PTP_MONO_PTP_CTR_HI       0x0480a         /* 0x12028 */
 468 #define FBNIC_PTP_MONO_PTP_CTR_LO       0x0480b         /* 0x1202c */
 469
 470 #define FBNIC_PTP_CDC_FIFO_STATUS       0x0480c         /* 0x12030 */
 471 #define FBNIC_PTP_SPARE                 0x0480d         /* 0x12034 */
 472 #define FBNIC_CSR_END_PTP               0x0480d /* CSR section delimiter */
 473
 474 /* Rx Buffer Registers */
 475 #define FBNIC_CSR_START_RXB             0x08000 /* CSR section delimiter */
 476 enum {
 477         FBNIC_RXB_FIFO_MC               = 0,
 478         /* Unused */
 479         /* Unused */
 480         FBNIC_RXB_FIFO_NET_TO_BMC       = 3,
 481         FBNIC_RXB_FIFO_HOST             = 4,
 482         /* Unused */
 483         FBNIC_RXB_FIFO_BMC_TO_HOST      = 6,
 484         /* Unused */
 485         FBNIC_RXB_FIFO_INDICES          = 8
 486 };
 487
 488 #define FBNIC_RXB_CT_SIZE(n)            (0x08000 + (n)) /* 0x20000 + 4*n */
 489 #define FBNIC_RXB_CT_SIZE_CNT                   8
 490 #define FBNIC_RXB_CT_SIZE_HEADER                CSR_GENMASK(5, 0)
 491 #define FBNIC_RXB_CT_SIZE_PAYLOAD               CSR_GENMASK(11, 6)
 492 #define FBNIC_RXB_CT_SIZE_ENABLE                CSR_BIT(12)
 493 #define FBNIC_RXB_PAUSE_DROP_CTRL       0x08008         /* 0x20020 */
 494 #define FBNIC_RXB_PAUSE_DROP_CTRL_DROP_ENABLE   CSR_GENMASK(7, 0)
 495 #define FBNIC_RXB_PAUSE_DROP_CTRL_PAUSE_ENABLE  CSR_GENMASK(15, 8)
 496 #define FBNIC_RXB_PAUSE_DROP_CTRL_ECN_ENABLE    CSR_GENMASK(23, 16)
 497 #define FBNIC_RXB_PAUSE_DROP_CTRL_PS_ENABLE     CSR_GENMASK(27, 24)
 498 #define FBNIC_RXB_PAUSE_THLD(n)         (0x08009 + (n)) /* 0x20024 + 4*n */
 499 #define FBNIC_RXB_PAUSE_THLD_CNT                8
 500 #define FBNIC_RXB_PAUSE_THLD_ON                 CSR_GENMASK(12, 0)
 501 #define FBNIC_RXB_PAUSE_THLD_OFF                CSR_GENMASK(25, 13)
 502 #define FBNIC_RXB_DROP_THLD(n)          (0x08011 + (n)) /* 0x20044 + 4*n */
 503 #define FBNIC_RXB_DROP_THLD_CNT                 8
 504 #define FBNIC_RXB_DROP_THLD_ON                  CSR_GENMASK(12, 0)
 505 #define FBNIC_RXB_DROP_THLD_OFF                 CSR_GENMASK(25, 13)
 506 #define FBNIC_RXB_ECN_THLD(n)           (0x0801e + (n)) /* 0x20078 + 4*n */
 507 #define FBNIC_RXB_ECN_THLD_CNT                  8
 508 #define FBNIC_RXB_ECN_THLD_ON                   CSR_GENMASK(12, 0)
 509 #define FBNIC_RXB_ECN_THLD_OFF                  CSR_GENMASK(25, 13)
 510 #define FBNIC_RXB_PBUF_CFG(n)           (0x08027 + (n)) /* 0x2009c + 4*n */
 511 #define FBNIC_RXB_PBUF_CFG_CNT                  8
 512 #define FBNIC_RXB_PBUF_BASE_ADDR                CSR_GENMASK(12, 0)
 513 #define FBNIC_RXB_PBUF_SIZE                     CSR_GENMASK(21, 13)
 514 #define FBNIC_RXB_DWRR_RDE_WEIGHT0      0x0802f         /* 0x200bc */
 515 #define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM0     CSR_GENMASK(7, 0)
 516 #define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM1     CSR_GENMASK(15, 8)
 517 #define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM2     CSR_GENMASK(23, 16)
 518 #define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM3     CSR_GENMASK(31, 24)
 519 #define FBNIC_RXB_DWRR_RDE_WEIGHT1      0x08030         /* 0x200c0 */
 520 #define FBNIC_RXB_DWRR_RDE_WEIGHT1_QUANTUM4     CSR_GENMASK(7, 0)
 521 #define FBNIC_RXB_DWRR_BMC_WEIGHT       0x08031         /* 0x200c4 */
 522 #define FBNIC_RXB_CLDR_PRIO_CFG(n)      (0x8034 + (n))  /* 0x200d0 + 4*n */
 523 #define FBNIC_RXB_CLDR_PRIO_CFG_CNT             16
 524 #define FBNIC_RXB_ENDIAN_FCS            0x08044         /* 0x20110 */
 525 enum {
 526         /* Unused */
 527         /* Unused */
 528         FBNIC_RXB_DEQUEUE_BMC           = 2,
 529         FBNIC_RXB_DEQUEUE_HOST          = 3,
 530         FBNIC_RXB_DEQUEUE_INDICES       = 4
 531 };
 532
 533 #define FBNIC_RXB_PBUF_CREDIT(n)        (0x08047 + (n)) /* 0x2011C + 4*n */
 534 #define FBNIC_RXB_PBUF_CREDIT_CNT               8
 535 #define FBNIC_RXB_PBUF_CREDIT_MASK              CSR_GENMASK(13, 0)
 536 #define FBNIC_RXB_INTF_CREDIT           0x0804f         /* 0x2013C */
 537 #define FBNIC_RXB_INTF_CREDIT_MASK0             CSR_GENMASK(3, 0)
 538 #define FBNIC_RXB_INTF_CREDIT_MASK1             CSR_GENMASK(7, 4)
 539 #define FBNIC_RXB_INTF_CREDIT_MASK2             CSR_GENMASK(11, 8)
 540 #define FBNIC_RXB_INTF_CREDIT_MASK3             CSR_GENMASK(15, 12)
 541
 542 #define FBNIC_RXB_PAUSE_EVENT_CNT(n)    (0x08053 + (n)) /* 0x2014c + 4*n */
 543 #define FBNIC_RXB_DROP_FRMS_STS(n)      (0x08057 + (n)) /* 0x2015c + 4*n */
 544 #define FBNIC_RXB_DROP_BYTES_STS_L(n) \
 545                                 (0x08080 + 2 * (n))     /* 0x20200 + 8*n */
 546 #define FBNIC_RXB_DROP_BYTES_STS_H(n) \
 547                                 (0x08081 + 2 * (n))     /* 0x20204 + 8*n */
 548 #define FBNIC_RXB_TRUN_FRMS_STS(n)      (0x08091 + (n)) /* 0x20244 + 4*n */
 549 #define FBNIC_RXB_TRUN_BYTES_STS_L(n) \
 550                                 (0x080c0 + 2 * (n))     /* 0x20300 + 8*n */
 551 #define FBNIC_RXB_TRUN_BYTES_STS_H(n) \
 552                                 (0x080c1 + 2 * (n))     /* 0x20304 + 8*n */
 553 #define FBNIC_RXB_TRANS_PAUSE_STS(n)    (0x080d1 + (n)) /* 0x20344 + 4*n */
 554 #define FBNIC_RXB_TRANS_DROP_STS(n)     (0x080d9 + (n)) /* 0x20364 + 4*n */
 555 #define FBNIC_RXB_TRANS_ECN_STS(n)      (0x080e1 + (n)) /* 0x20384 + 4*n */
 556 enum {
 557         FBNIC_RXB_ENQUEUE_NET           = 0,
 558         FBNIC_RXB_ENQUEUE_BMC           = 1,
 559         /* Unused */
 560         /* Unused */
 561         FBNIC_RXB_ENQUEUE_INDICES       = 4
 562 };
 563
 564 #define FBNIC_RXB_DRBO_FRM_CNT_SRC(n)   (0x080f9 + (n)) /* 0x203e4 + 4*n */
 565 #define FBNIC_RXB_DRBO_BYTE_CNT_SRC_L(n) \
 566                                         (0x080fd + (n)) /* 0x203f4 + 4*n */
 567 #define FBNIC_RXB_DRBO_BYTE_CNT_SRC_H(n) \
 568                                         (0x08101 + (n)) /* 0x20404 + 4*n */
 569 #define FBNIC_RXB_INTF_FRM_CNT_DST(n)   (0x08105 + (n)) /* 0x20414 + 4*n */
 570 #define FBNIC_RXB_INTF_BYTE_CNT_DST_L(n) \
 571                                         (0x08109 + (n)) /* 0x20424 + 4*n */
 572 #define FBNIC_RXB_INTF_BYTE_CNT_DST_H(n) \
 573                                         (0x0810d + (n)) /* 0x20434 + 4*n */
 574 #define FBNIC_RXB_PBUF_FRM_CNT_DST(n)   (0x08111 + (n)) /* 0x20444 + 4*n */
 575 #define FBNIC_RXB_PBUF_BYTE_CNT_DST_L(n) \
 576                                         (0x08115 + (n)) /* 0x20454 + 4*n */
 577 #define FBNIC_RXB_PBUF_BYTE_CNT_DST_H(n) \
 578                                         (0x08119 + (n)) /* 0x20464 + 4*n */
 579
 580 #define FBNIC_RXB_PBUF_FIFO_LEVEL(n)    (0x0811d + (n)) /* 0x20474 + 4*n */
 581
 582 #define FBNIC_RXB_INTEGRITY_ERR(n)      (0x0812f + (n)) /* 0x204bc + 4*n */
 583 #define FBNIC_RXB_MAC_ERR(n)            (0x08133 + (n)) /* 0x204cc + 4*n */
 584 #define FBNIC_RXB_PARSER_ERR(n)         (0x08137 + (n)) /* 0x204dc + 4*n */
 585 #define FBNIC_RXB_FRM_ERR(n)            (0x0813b + (n)) /* 0x204ec + 4*n */
 586
 587 #define FBNIC_RXB_DWRR_RDE_WEIGHT0_EXT  0x08143         /* 0x2050c */
 588 #define FBNIC_RXB_DWRR_RDE_WEIGHT1_EXT  0x08144         /* 0x20510 */
 589 #define FBNIC_CSR_END_RXB               0x081b1 /* CSR section delimiter */
 590
 591 /* Rx Parser and Classifier Registers */
 592 #define FBNIC_CSR_START_RPC             0x08400 /* CSR section delimiter */
 593 #define FBNIC_RPC_RMI_CONFIG            0x08400         /* 0x21000 */
 594 #define FBNIC_RPC_RMI_CONFIG_OH_BYTES           CSR_GENMASK(4, 0)
 595 #define FBNIC_RPC_RMI_CONFIG_FCS_PRESENT        CSR_BIT(8)
 596 #define FBNIC_RPC_RMI_CONFIG_ENABLE             CSR_BIT(12)
 597 #define FBNIC_RPC_RMI_CONFIG_MTU                CSR_GENMASK(31, 16)
 598
 599 #define FBNIC_RPC_ACT_TBL0_DEFAULT      0x0840a         /* 0x21028 */
 600 #define FBNIC_RPC_ACT_TBL0_DROP                 CSR_BIT(0)
 601 #define FBNIC_RPC_ACT_TBL0_DEST_MASK            CSR_GENMASK(3, 1)
 602 enum {
 603         FBNIC_RPC_ACT_TBL0_DEST_HOST    = 1,
 604         FBNIC_RPC_ACT_TBL0_DEST_BMC     = 2,
 605         FBNIC_RPC_ACT_TBL0_DEST_EI      = 4,
 606 };
 607
 608 #define FBNIC_RPC_ACT_TBL0_DMA_HINT             CSR_GENMASK(24, 16)
 609 #define FBNIC_RPC_ACT_TBL0_TS_ENA               CSR_BIT(28)
 610 #define FBNIC_RPC_ACT_TBL0_RSS_CTXT_ID          CSR_BIT(30)
 611
 612 #define FBNIC_RPC_ACT_TBL1_DEFAULT      0x0840b         /* 0x2102c */
 613 #define FBNIC_RPC_ACT_TBL1_RSS_ENA_MASK         CSR_GENMASK(15, 0)
 614 enum {
 615         FBNIC_RPC_ACT_TBL1_RSS_ENA_IP_SRC       = 1,
 616         FBNIC_RPC_ACT_TBL1_RSS_ENA_IP_DST       = 2,
 617         FBNIC_RPC_ACT_TBL1_RSS_ENA_L4_SRC       = 4,
 618         FBNIC_RPC_ACT_TBL1_RSS_ENA_L4_DST       = 8,
 619         FBNIC_RPC_ACT_TBL1_RSS_ENA_L2_DA        = 16,
 620         FBNIC_RPC_ACT_TBL1_RSS_ENA_L4_RSS_BYTE  = 32,
 621         FBNIC_RPC_ACT_TBL1_RSS_ENA_IV6_FL_LBL   = 64,
 622         FBNIC_RPC_ACT_TBL1_RSS_ENA_OV6_FL_LBL   = 128,
 623         FBNIC_RPC_ACT_TBL1_RSS_ENA_DSCP         = 256,
 624         FBNIC_RPC_ACT_TBL1_RSS_ENA_L3_PROT      = 512,
 625         FBNIC_RPC_ACT_TBL1_RSS_ENA_L4_PROT      = 1024,
 626 };
 627
 628 #define FBNIC_RPC_RSS_KEY(n)            (0x0840c + (n)) /* 0x21030 + 4*n */
 629 #define FBNIC_RPC_RSS_KEY_BIT_LEN               425
 630 #define FBNIC_RPC_RSS_KEY_BYTE_LEN \
 631         DIV_ROUND_UP(FBNIC_RPC_RSS_KEY_BIT_LEN, 8)
 632 #define FBNIC_RPC_RSS_KEY_DWORD_LEN \
 633         DIV_ROUND_UP(FBNIC_RPC_RSS_KEY_BIT_LEN, 32)
 634 #define FBNIC_RPC_RSS_KEY_LAST_IDX \
 635         (FBNIC_RPC_RSS_KEY_DWORD_LEN - 1)
 636 #define FBNIC_RPC_RSS_KEY_LAST_MASK \
 637         CSR_GENMASK(31, \
 638                     FBNIC_RPC_RSS_KEY_DWORD_LEN * 32 - \
 639                     FBNIC_RPC_RSS_KEY_BIT_LEN)
 640
 641 #define FBNIC_RPC_CNTR_TCP_OPT_ERR      0x0849e         /* 0x21278 */
 642 #define FBNIC_RPC_CNTR_UNKN_ETYPE       0x0849f         /* 0x2127c */
 643 #define FBNIC_RPC_CNTR_IPV4_FRAG        0x084a0         /* 0x21280 */
 644 #define FBNIC_RPC_CNTR_IPV6_FRAG        0x084a1         /* 0x21284 */
 645 #define FBNIC_RPC_CNTR_IPV4_ESP         0x084a2         /* 0x21288 */
 646 #define FBNIC_RPC_CNTR_IPV6_ESP         0x084a3         /* 0x2128c */
 647 #define FBNIC_RPC_CNTR_UNKN_EXT_HDR     0x084a4         /* 0x21290 */
 648 #define FBNIC_RPC_CNTR_OUT_OF_HDR_ERR   0x084a5         /* 0x21294 */
 649 #define FBNIC_RPC_CNTR_OVR_SIZE_ERR     0x084a6         /* 0x21298 */
 650
 651 #define FBNIC_RPC_TCAM_MACDA_VALIDATE   0x0852d         /* 0x214b4 */
 652 #define FBNIC_CSR_END_RPC               0x0856b /* CSR section delimiter */
 653
 654 /* RPC RAM Registers */
 655
 656 #define FBNIC_CSR_START_RPC_RAM         0x08800 /* CSR section delimiter */
 657 #define FBNIC_RPC_ACT_TBL0(n)           (0x08800 + (n)) /* 0x22000 + 4*n */
 658 #define FBNIC_RPC_ACT_TBL1(n)           (0x08840 + (n)) /* 0x22100 + 4*n */
 659 #define FBNIC_RPC_ACT_TBL_NUM_ENTRIES           64
 660
 661 /* TCAM Tables */
 662 #define FBNIC_RPC_TCAM_VALIDATE                 CSR_BIT(31)
 663
 664 /* 64 Action TCAM Entries, 12 registers
 665  * 3 mixed, src port, dst port, 6 L4 words, and Validate
 666  */
 667 #define FBNIC_RPC_TCAM_ACT(m, n) \
 668         (0x08880 + 0x40 * (n) + (m))            /* 0x22200 + 256*n + 4*m */
 669
 670 #define FBNIC_RPC_TCAM_ACT_VALUE                CSR_GENMASK(15, 0)
 671 #define FBNIC_RPC_TCAM_ACT_MASK                 CSR_GENMASK(31, 16)
 672
 673 #define FBNIC_RPC_TCAM_MACDA(m, n) \
 674         (0x08b80 + 0x20 * (n) + (m))            /* 0x022e00 + 128*n + 4*m */
 675 #define FBNIC_RPC_TCAM_MACDA_VALUE              CSR_GENMASK(15, 0)
 676 #define FBNIC_RPC_TCAM_MACDA_MASK               CSR_GENMASK(31, 16)
 677
 678 #define FBNIC_RPC_TCAM_OUTER_IPSRC(m, n)\
 679         (0x08c00 + 0x08 * (n) + (m))            /* 0x023000 + 32*n + 4*m */
 680 #define FBNIC_RPC_TCAM_OUTER_IPDST(m, n)\
 681         (0x08c48 + 0x08 * (n) + (m))            /* 0x023120 + 32*n + 4*m */
 682 #define FBNIC_RPC_TCAM_IPSRC(m, n)\
 683         (0x08c90 + 0x08 * (n) + (m))            /* 0x023240 + 32*n + 4*m */
 684 #define FBNIC_RPC_TCAM_IPDST(m, n)\
 685         (0x08cd8 + 0x08 * (n) + (m))            /* 0x023360 + 32*n + 4*m */
 686
 687 #define FBNIC_RPC_RSS_TBL(n, m) \
 688         (0x08d20 + 0x100 * (n) + (m))           /* 0x023480 + 1024*n + 4*m */
 689 #define FBNIC_RPC_RSS_TBL_COUNT                 2
 690 #define FBNIC_RPC_RSS_TBL_SIZE                  256
 691 #define FBNIC_CSR_END_RPC_RAM           0x08f1f /* CSR section delimiter */
 692
 693 /* Fab Registers */
 694 #define FBNIC_CSR_START_FAB             0x0C000 /* CSR section delimiter */
 695 #define FBNIC_FAB_AXI4_AR_SPACER_2_CFG          0x0C005         /* 0x30014 */
 696 #define FBNIC_FAB_AXI4_AR_SPACER_MASK           CSR_BIT(16)
 697 #define FBNIC_FAB_AXI4_AR_SPACER_THREADSHOLD    CSR_GENMASK(15, 0)
 698 #define FBNIC_CSR_END_FAB               0x0C020     /* CSR section delimiter */
 699
 700 /* Master Registers */
 701 #define FBNIC_CSR_START_MASTER          0x0C400 /* CSR section delimiter */
 702 #define FBNIC_MASTER_SPARE_0            0x0C41B         /* 0x3106c */
 703 #define FBNIC_CSR_END_MASTER            0x0C452 /* CSR section delimiter */
 704
 705 /* MAC PCS registers */
 706 #define FBNIC_CSR_START_PCS             0x10000 /* CSR section delimiter */
 707 #define FBNIC_CSR_END_PCS               0x10668 /* CSR section delimiter */
 708
 709 #define FBNIC_CSR_START_RSFEC           0x10800 /* CSR section delimiter */
 710 #define FBNIC_CSR_END_RSFEC             0x108c8 /* CSR section delimiter */
 711
 712 /* MAC MAC registers (ASIC only) */
 713 #define FBNIC_CSR_START_MAC_MAC         0x11000 /* CSR section delimiter */
 714 #define FBNIC_MAC_COMMAND_CONFIG        0x11002         /* 0x44008 */
 715 #define FBNIC_MAC_COMMAND_CONFIG_RX_PAUSE_DIS   CSR_BIT(29)
 716 #define FBNIC_MAC_COMMAND_CONFIG_TX_PAUSE_DIS   CSR_BIT(28)
 717 #define FBNIC_MAC_COMMAND_CONFIG_FLT_HDL_DIS    CSR_BIT(27)
 718 #define FBNIC_MAC_COMMAND_CONFIG_TX_PAD_EN      CSR_BIT(11)
 719 #define FBNIC_MAC_COMMAND_CONFIG_LOOPBACK_EN    CSR_BIT(10)
 720 #define FBNIC_MAC_COMMAND_CONFIG_PROMISC_EN     CSR_BIT(4)
 721 #define FBNIC_MAC_COMMAND_CONFIG_RX_ENA         CSR_BIT(1)
 722 #define FBNIC_MAC_COMMAND_CONFIG_TX_ENA         CSR_BIT(0)
 723 #define FBNIC_MAC_CL01_PAUSE_QUANTA     0x11015         /* 0x44054 */
 724 #define FBNIC_MAC_CL01_QUANTA_THRESH    0x11019         /* 0x44064 */
 725 #define FBNIC_CSR_END_MAC_MAC           0x11028 /* CSR section delimiter */
 726
 727 /* Signals from MAC, AN, PCS, and LED CSR registers (ASIC only) */
 728 #define FBNIC_CSR_START_SIG             0x11800 /* CSR section delimiter */
 729 #define FBNIC_SIG_MAC_IN0               0x11800         /* 0x46000 */
 730 #define FBNIC_SIG_MAC_IN0_RESET_FF_TX_CLK       CSR_BIT(14)
 731 #define FBNIC_SIG_MAC_IN0_RESET_FF_RX_CLK       CSR_BIT(13)
 732 #define FBNIC_SIG_MAC_IN0_RESET_TX_CLK          CSR_BIT(12)
 733 #define FBNIC_SIG_MAC_IN0_RESET_RX_CLK          CSR_BIT(11)
 734 #define FBNIC_SIG_MAC_IN0_TX_CRC                CSR_BIT(8)
 735 #define FBNIC_SIG_MAC_IN0_CFG_MODE128           CSR_BIT(10)
 736 #define FBNIC_SIG_PCS_OUT0              0x11808         /* 0x46020 */
 737 #define FBNIC_SIG_PCS_OUT0_LINK                 CSR_BIT(27)
 738 #define FBNIC_SIG_PCS_OUT0_BLOCK_LOCK           CSR_GENMASK(24, 5)
 739 #define FBNIC_SIG_PCS_OUT0_AMPS_LOCK            CSR_GENMASK(4, 1)
 740 #define FBNIC_SIG_PCS_OUT1              0x11809         /* 0x46024 */
 741 #define FBNIC_SIG_PCS_OUT1_FCFEC_LOCK           CSR_GENMASK(11, 8)
 742 #define FBNIC_SIG_PCS_INTR_STS          0x11814         /* 0x46050 */
 743 #define FBNIC_SIG_PCS_INTR_LINK_DOWN            CSR_BIT(1)
 744 #define FBNIC_SIG_PCS_INTR_LINK_UP              CSR_BIT(0)
 745 #define FBNIC_SIG_PCS_INTR_MASK         0x11816         /* 0x46058 */
 746 #define FBNIC_CSR_END_SIG               0x1184e /* CSR section delimiter */
 747
 748 #define FBNIC_CSR_START_MAC_STAT        0x11a00
 749 #define FBNIC_MAC_STAT_RX_BYTE_COUNT_L  0x11a08         /* 0x46820 */
 750 #define FBNIC_MAC_STAT_RX_BYTE_COUNT_H  0x11a09         /* 0x46824 */
 751 #define FBNIC_MAC_STAT_RX_ALIGN_ERROR_L \
 752                                         0x11a0a         /* 0x46828 */
 753 #define FBNIC_MAC_STAT_RX_ALIGN_ERROR_H \
 754                                         0x11a0b         /* 0x4682c */
 755 #define FBNIC_MAC_STAT_RX_TOOLONG_L     0x11a0e         /* 0x46838 */
 756 #define FBNIC_MAC_STAT_RX_TOOLONG_H     0x11a0f         /* 0x4683c */
 757 #define FBNIC_MAC_STAT_RX_RECEIVED_OK_L \
 758                                         0x11a12         /* 0x46848 */
 759 #define FBNIC_MAC_STAT_RX_RECEIVED_OK_H \
 760                                         0x11a13         /* 0x4684c */
 761 #define FBNIC_MAC_STAT_RX_PACKET_BAD_FCS_L \
 762                                         0x11a14         /* 0x46850 */
 763 #define FBNIC_MAC_STAT_RX_PACKET_BAD_FCS_H \
 764                                         0x11a15         /* 0x46854 */
 765 #define FBNIC_MAC_STAT_RX_IFINERRORS_L  0x11a18         /* 0x46860 */
 766 #define FBNIC_MAC_STAT_RX_IFINERRORS_H  0x11a19         /* 0x46864 */
 767 #define FBNIC_MAC_STAT_RX_MULTICAST_L   0x11a1c         /* 0x46870 */
 768 #define FBNIC_MAC_STAT_RX_MULTICAST_H   0x11a1d         /* 0x46874 */
 769 #define FBNIC_MAC_STAT_RX_BROADCAST_L   0x11a1e         /* 0x46878 */
 770 #define FBNIC_MAC_STAT_RX_BROADCAST_H   0x11a1f         /* 0x4687c */
 771 #define FBNIC_MAC_STAT_TX_BYTE_COUNT_L  0x11a3e         /* 0x468f8 */
 772 #define FBNIC_MAC_STAT_TX_BYTE_COUNT_H  0x11a3f         /* 0x468fc */
 773 #define FBNIC_MAC_STAT_TX_TRANSMITTED_OK_L \
 774                                         0x11a42         /* 0x46908 */
 775 #define FBNIC_MAC_STAT_TX_TRANSMITTED_OK_H \
 776                                         0x11a43         /* 0x4690c */
 777 #define FBNIC_MAC_STAT_TX_IFOUTERRORS_L \
 778                                         0x11a46         /* 0x46918 */
 779 #define FBNIC_MAC_STAT_TX_IFOUTERRORS_H \
 780                                         0x11a47         /* 0x4691c */
 781 #define FBNIC_MAC_STAT_TX_MULTICAST_L   0x11a4a         /* 0x46928 */
 782 #define FBNIC_MAC_STAT_TX_MULTICAST_H   0x11a4b         /* 0x4692c */
 783 #define FBNIC_MAC_STAT_TX_BROADCAST_L   0x11a4c         /* 0x46930 */
 784 #define FBNIC_MAC_STAT_TX_BROADCAST_H   0x11a4d         /* 0x46934 */
 785 /* PUL User Registers */
 786 #define FBNIC_CSR_START_PUL_USER        0x31000 /* CSR section delimiter */
 787 #define FBNIC_PUL_OB_TLP_HDR_AW_CFG     0x3103d         /* 0xc40f4 */
 788 #define FBNIC_PUL_OB_TLP_HDR_AW_CFG_BME         CSR_BIT(18)
 789 #define FBNIC_PUL_OB_TLP_HDR_AR_CFG     0x3103e         /* 0xc40f8 */
 790 #define FBNIC_PUL_OB_TLP_HDR_AR_CFG_BME         CSR_BIT(18)
 791 #define FBNIC_CSR_END_PUL_USER  0x31080 /* CSR section delimiter */
 792
 793 /* Queue Registers
 794  *
 795  * The queue register offsets are specific for a given queue grouping. So to
 796  * find the actual register offset it is necessary to combine FBNIC_QUEUE(n)
 797  * with the register to get the actual register offset like so:
 798  *   FBNIC_QUEUE_TWQ0_CTL(n) == FBNIC_QUEUE(n) + FBNIC_QUEUE_TWQ0_CTL
 799  */
 800 #define FBNIC_CSR_START_QUEUE           0x40000 /* CSR section delimiter */
 801 #define FBNIC_QUEUE_STRIDE              0x400           /* 0x1000 */
 802 #define FBNIC_QUEUE(n)\
 803         (0x40000 + FBNIC_QUEUE_STRIDE * (n))    /* 0x100000 + 4096*n */
 804
 805 #define FBNIC_QUEUE_TWQ0_CTL            0x000           /* 0x000 */
 806 #define FBNIC_QUEUE_TWQ1_CTL            0x001           /* 0x004 */
 807 #define FBNIC_QUEUE_TWQ_CTL_RESET               CSR_BIT(0)
 808 #define FBNIC_QUEUE_TWQ_CTL_ENABLE              CSR_BIT(1)
 809 #define FBNIC_QUEUE_TWQ0_TAIL           0x002           /* 0x008 */
 810 #define FBNIC_QUEUE_TWQ1_TAIL           0x003           /* 0x00c */
 811
 812 #define FBNIC_QUEUE_TWQ0_SIZE           0x00a           /* 0x028 */
 813 #define FBNIC_QUEUE_TWQ1_SIZE           0x00b           /* 0x02c */
 814 #define FBNIC_QUEUE_TWQ_SIZE_MASK               CSR_GENMASK(3, 0)
 815
 816 #define FBNIC_QUEUE_TWQ0_BAL            0x020           /* 0x080 */
 817 #define FBNIC_QUEUE_BAL_MASK                    CSR_GENMASK(31, 7)
 818 #define FBNIC_QUEUE_TWQ0_BAH            0x021           /* 0x084 */
 819 #define FBNIC_QUEUE_TWQ1_BAL            0x022           /* 0x088 */
 820 #define FBNIC_QUEUE_TWQ1_BAH            0x023           /* 0x08c */
 821
 822 /* Tx Completion Queue Registers */
 823 #define FBNIC_QUEUE_TCQ_CTL             0x080           /* 0x200 */
 824 #define FBNIC_QUEUE_TCQ_CTL_RESET               CSR_BIT(0)
 825 #define FBNIC_QUEUE_TCQ_CTL_ENABLE              CSR_BIT(1)
 826
 827 #define FBNIC_QUEUE_TCQ_HEAD            0x081           /* 0x204 */
 828
 829 #define FBNIC_QUEUE_TCQ_SIZE            0x084           /* 0x210 */
 830 #define FBNIC_QUEUE_TCQ_SIZE_MASK               CSR_GENMASK(3, 0)
 831
 832 #define FBNIC_QUEUE_TCQ_BAL             0x0a0           /* 0x280 */
 833 #define FBNIC_QUEUE_TCQ_BAH             0x0a1           /* 0x284 */
 834
 835 /* Tx Interrupt Manager Registers */
 836 #define FBNIC_QUEUE_TIM_CTL             0x0c0           /* 0x300 */
 837 #define FBNIC_QUEUE_TIM_CTL_MSIX_MASK           CSR_GENMASK(7, 0)
 838
 839 #define FBNIC_QUEUE_TIM_THRESHOLD       0x0c1           /* 0x304 */
 840 #define FBNIC_QUEUE_TIM_THRESHOLD_TWD_MASK      CSR_GENMASK(14, 0)
 841
 842 #define FBNIC_QUEUE_TIM_CLEAR           0x0c2           /* 0x308 */
 843 #define FBNIC_QUEUE_TIM_CLEAR_MASK              CSR_BIT(0)
 844 #define FBNIC_QUEUE_TIM_SET             0x0c3           /* 0x30c */
 845 #define FBNIC_QUEUE_TIM_SET_MASK                CSR_BIT(0)
 846 #define FBNIC_QUEUE_TIM_MASK            0x0c4           /* 0x310 */
 847 #define FBNIC_QUEUE_TIM_MASK_MASK               CSR_BIT(0)
 848
 849 #define FBNIC_QUEUE_TIM_TIMER           0x0c5           /* 0x314 */
 850
 851 #define FBNIC_QUEUE_TIM_COUNTS          0x0c6           /* 0x318 */
 852 #define FBNIC_QUEUE_TIM_COUNTS_CNT1_MASK        CSR_GENMASK(30, 16)
 853 #define FBNIC_QUEUE_TIM_COUNTS_CNT0_MASK        CSR_GENMASK(14, 0)
 854
 855 /* Rx Completion Queue Registers */
 856 #define FBNIC_QUEUE_RCQ_CTL             0x200           /* 0x800 */
 857 #define FBNIC_QUEUE_RCQ_CTL_RESET               CSR_BIT(0)
 858 #define FBNIC_QUEUE_RCQ_CTL_ENABLE              CSR_BIT(1)
 859
 860 #define FBNIC_QUEUE_RCQ_HEAD            0x201           /* 0x804 */
 861
 862 #define FBNIC_QUEUE_RCQ_SIZE            0x204           /* 0x810 */
 863 #define FBNIC_QUEUE_RCQ_SIZE_MASK               CSR_GENMASK(3, 0)
 864
 865 #define FBNIC_QUEUE_RCQ_BAL             0x220           /* 0x880 */
 866 #define FBNIC_QUEUE_RCQ_BAH             0x221           /* 0x884 */
 867
 868 /* Rx Buffer Descriptor Queue Registers */
 869 #define FBNIC_QUEUE_BDQ_CTL             0x240           /* 0x900 */
 870 #define FBNIC_QUEUE_BDQ_CTL_RESET               CSR_BIT(0)
 871 #define FBNIC_QUEUE_BDQ_CTL_ENABLE              CSR_BIT(1)
 872 #define FBNIC_QUEUE_BDQ_CTL_PPQ_ENABLE          CSR_BIT(30)
 873
 874 #define FBNIC_QUEUE_BDQ_HPQ_TAIL        0x241           /* 0x904 */
 875 #define FBNIC_QUEUE_BDQ_PPQ_TAIL        0x242           /* 0x908 */
 876
 877 #define FBNIC_QUEUE_BDQ_HPQ_SIZE        0x247           /* 0x91c */
 878 #define FBNIC_QUEUE_BDQ_PPQ_SIZE        0x248           /* 0x920 */
 879 #define FBNIC_QUEUE_BDQ_SIZE_MASK               CSR_GENMASK(3, 0)
 880
 881 #define FBNIC_QUEUE_BDQ_HPQ_BAL         0x260           /* 0x980 */
 882 #define FBNIC_QUEUE_BDQ_HPQ_BAH         0x261           /* 0x984 */
 883 #define FBNIC_QUEUE_BDQ_PPQ_BAL         0x262           /* 0x988 */
 884 #define FBNIC_QUEUE_BDQ_PPQ_BAH         0x263           /* 0x98c */
 885
 886 /* Rx DMA Engine Configuration */
 887 #define FBNIC_QUEUE_RDE_CTL0            0x2a0           /* 0xa80 */
 888 #define FBNIC_QUEUE_RDE_CTL0_EN_HDR_SPLIT       CSR_BIT(31)
 889 #define FBNIC_QUEUE_RDE_CTL0_DROP_MODE_MASK     CSR_GENMASK(30, 29)
 890 enum {
 891         FBNIC_QUEUE_RDE_CTL0_DROP_IMMEDIATE     = 0,
 892         FBNIC_QUEUE_RDE_CTL0_DROP_WAIT          = 1,
 893         FBNIC_QUEUE_RDE_CTL0_DROP_NEVER         = 2,
 894 };
 895
 896 #define FBNIC_QUEUE_RDE_CTL0_MIN_HROOM_MASK     CSR_GENMASK(28, 20)
 897 #define FBNIC_QUEUE_RDE_CTL0_MIN_TROOM_MASK     CSR_GENMASK(19, 11)
 898
 899 #define FBNIC_QUEUE_RDE_CTL1            0x2a1           /* 0xa84 */
 900 #define FBNIC_QUEUE_RDE_CTL1_MAX_HDR_MASK       CSR_GENMASK(24, 12)
 901 #define FBNIC_QUEUE_RDE_CTL1_PAYLD_OFF_MASK     CSR_GENMASK(11, 9)
 902 #define FBNIC_QUEUE_RDE_CTL1_PAYLD_PG_CL_MASK   CSR_GENMASK(8, 6)
 903 #define FBNIC_QUEUE_RDE_CTL1_PADLEN_MASK        CSR_GENMASK(5, 2)
 904 #define FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_MASK    CSR_GENMASK(1, 0)
 905 enum {
 906         FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_NONE    = 0,
 907         FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_ALL     = 1,
 908         FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_RSS     = 2,
 909 };
 910
 911 /* Rx Interrupt Manager Registers */
 912 #define FBNIC_QUEUE_RIM_CTL             0x2c0           /* 0xb00 */
 913 #define FBNIC_QUEUE_RIM_CTL_MSIX_MASK           CSR_GENMASK(7, 0)
 914
 915 #define FBNIC_QUEUE_RIM_THRESHOLD       0x2c1           /* 0xb04 */
 916 #define FBNIC_QUEUE_RIM_THRESHOLD_RCD_MASK      CSR_GENMASK(14, 0)
 917
 918 #define FBNIC_QUEUE_RIM_CLEAR           0x2c2           /* 0xb08 */
 919 #define FBNIC_QUEUE_RIM_CLEAR_MASK              CSR_BIT(0)
 920 #define FBNIC_QUEUE_RIM_SET             0x2c3           /* 0xb0c */
 921 #define FBNIC_QUEUE_RIM_SET_MASK                CSR_BIT(0)
 922 #define FBNIC_QUEUE_RIM_MASK            0x2c4           /* 0xb10 */
 923 #define FBNIC_QUEUE_RIM_MASK_MASK               CSR_BIT(0)
 924
 925 #define FBNIC_QUEUE_RIM_COAL_STATUS     0x2c5           /* 0xb14 */
 926 #define FBNIC_QUEUE_RIM_RCD_COUNT_MASK          CSR_GENMASK(30, 16)
 927 #define FBNIC_QUEUE_RIM_TIMER_MASK              CSR_GENMASK(13, 0)
 928 #define FBNIC_MAX_QUEUES                128
 929 #define FBNIC_CSR_END_QUEUE     (0x40000 + 0x400 * FBNIC_MAX_QUEUES - 1)
 930
 931 /* PUL User Registers*/
 932 #define FBNIC_PUL_USER_OB_RD_TLP_CNT_31_0 \
 933                                         0x3106e         /* 0xc41b8 */
 934 #define FBNIC_PUL_USER_OB_RD_DWORD_CNT_31_0 \
 935                                         0x31070         /* 0xc41c0 */
 936 #define FBNIC_PUL_USER_OB_RD_DWORD_CNT_63_32 \
 937                                         0x31071         /* 0xc41c4 */
 938 #define FBNIC_PUL_USER_OB_WR_TLP_CNT_31_0 \
 939                                         0x31072         /* 0xc41c8 */
 940 #define FBNIC_PUL_USER_OB_WR_TLP_CNT_63_32 \
 941                                         0x31073         /* 0xc41cc */
 942 #define FBNIC_PUL_USER_OB_WR_DWORD_CNT_31_0 \
 943                                         0x31074         /* 0xc41d0 */
 944 #define FBNIC_PUL_USER_OB_WR_DWORD_CNT_63_32 \
 945                                         0x31075         /* 0xc41d4 */
 946 #define FBNIC_PUL_USER_OB_CPL_TLP_CNT_31_0 \
 947                                         0x31076         /* 0xc41d8 */
 948 #define FBNIC_PUL_USER_OB_CPL_TLP_CNT_63_32 \
 949                                         0x31077         /* 0xc41dc */
 950 #define FBNIC_PUL_USER_OB_CPL_DWORD_CNT_31_0 \
 951                                         0x31078         /* 0xc41e0 */
 952 #define FBNIC_PUL_USER_OB_CPL_DWORD_CNT_63_32 \
 953                                         0x31079         /* 0xc41e4 */
 954 #define FBNIC_PUL_USER_OB_RD_DBG_CNT_CPL_CRED_31_0 \
 955                                         0x3107a         /* 0xc41e8 */
 956 #define FBNIC_PUL_USER_OB_RD_DBG_CNT_CPL_CRED_63_32 \
 957                                         0x3107b         /* 0xc41ec */
 958 #define FBNIC_PUL_USER_OB_RD_DBG_CNT_TAG_31_0 \
 959                                         0x3107c         /* 0xc41f0 */
 960 #define FBNIC_PUL_USER_OB_RD_DBG_CNT_TAG_63_32 \
 961                                         0x3107d         /* 0xc41f4 */
 962 #define FBNIC_PUL_USER_OB_RD_DBG_CNT_NP_CRED_31_0 \
 963                                         0x3107e         /* 0xc41f8 */
 964 #define FBNIC_PUL_USER_OB_RD_DBG_CNT_NP_CRED_63_32 \
 965                                         0x3107f         /* 0xc41fc */
 966 #define FBNIC_CSR_END_PUL_USER  0x31080 /* CSR section delimiter */
 967
 968 /* BAR 4 CSRs */
 969
 970 /* The IPC mailbox consists of 32 mailboxes, with each mailbox consisting
 971  * of 32 4 byte registers. We will use 2 registers per descriptor so the
 972  * length of the mailbox is reduced to 16.
 973  *
 974  * Currently we use an offset of 0x6000 on BAR4 for the mailbox so we just
 975  * have to do the math and determine the offset based on the mailbox
 976  * direction and index inside that mailbox.
 977  */
 978 #define FBNIC_IPC_MBX_DESC_LEN  16
 979 #define FBNIC_IPC_MBX(mbx_idx, desc_idx)        \
 980         ((((mbx_idx) * FBNIC_IPC_MBX_DESC_LEN + (desc_idx)) * 2) + 0x6000)
 981
 982 /* Use first register in mailbox to flush writes */
 983 #define FBNIC_FW_ZERO_REG       FBNIC_IPC_MBX(0, 0)
 984
 985 enum {
 986         FBNIC_IPC_MBX_RX_IDX,
 987         FBNIC_IPC_MBX_TX_IDX,
 988         FBNIC_IPC_MBX_INDICES,
 989 };
 990
 991 #define FBNIC_IPC_MBX_DESC_LEN_MASK     DESC_GENMASK(63, 48)
 992 #define FBNIC_IPC_MBX_DESC_EOM          DESC_BIT(46)
 993 #define FBNIC_IPC_MBX_DESC_ADDR_MASK    DESC_GENMASK(45, 3)
 994 #define FBNIC_IPC_MBX_DESC_FW_CMPL      DESC_BIT(1)
 995 #define FBNIC_IPC_MBX_DESC_HOST_CMPL    DESC_BIT(0)
 996
 997 #endif /* _FBNIC_CSR_H_ */