drivers/net/ethernet/microchip/sparx5/sparx5_main.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /* Microchip Sparx5 Switch driver
   3  *
   4  * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
   5  */
   6
   7 #ifndef __SPARX5_MAIN_H__
   8 #define __SPARX5_MAIN_H__
   9
  10 #include <linux/types.h>
  11 #include <linux/phy/phy.h>
  12 #include <linux/netdevice.h>
  13 #include <linux/phy.h>
  14 #include <linux/if_vlan.h>
  15 #include <linux/bitmap.h>
  16 #include <linux/phylink.h>
  17 #include <linux/net_tstamp.h>
  18 #include <linux/ptp_clock_kernel.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/debugfs.h>
  21 #include <net/flow_offload.h>
  22
  23 #include <fdma_api.h>
  24
  25 #include "sparx5_main_regs.h"
  26
  27 /* Target chip type */
  28 enum spx5_target_chiptype {
  29         SPX5_TARGET_CT_7546       = 0x7546,  /* SparX-5-64  Enterprise */
  30         SPX5_TARGET_CT_7549       = 0x7549,  /* SparX-5-90  Enterprise */
  31         SPX5_TARGET_CT_7552       = 0x7552,  /* SparX-5-128 Enterprise */
  32         SPX5_TARGET_CT_7556       = 0x7556,  /* SparX-5-160 Enterprise */
  33         SPX5_TARGET_CT_7558       = 0x7558,  /* SparX-5-200 Enterprise */
  34         SPX5_TARGET_CT_7546TSN    = 0x47546, /* SparX-5-64i Industrial */
  35         SPX5_TARGET_CT_7549TSN    = 0x47549, /* SparX-5-90i Industrial */
  36         SPX5_TARGET_CT_7552TSN    = 0x47552, /* SparX-5-128i Industrial */
  37         SPX5_TARGET_CT_7556TSN    = 0x47556, /* SparX-5-160i Industrial */
  38         SPX5_TARGET_CT_7558TSN    = 0x47558, /* SparX-5-200i Industrial */
  39         SPX5_TARGET_CT_LAN9694    = 0x9694,  /* lan969x-40 */
  40         SPX5_TARGET_CT_LAN9691VAO = 0x9691,  /* lan969x-40-VAO */
  41         SPX5_TARGET_CT_LAN9694TSN = 0x9695,  /* lan969x-40-TSN */
  42         SPX5_TARGET_CT_LAN9694RED = 0x969A,  /* lan969x-40-RED */
  43         SPX5_TARGET_CT_LAN9696    = 0x9696,  /* lan969x-60 */
  44         SPX5_TARGET_CT_LAN9692VAO = 0x9692,  /* lan969x-65-VAO */
  45         SPX5_TARGET_CT_LAN9696TSN = 0x9697,  /* lan969x-60-TSN */
  46         SPX5_TARGET_CT_LAN9696RED = 0x969B,  /* lan969x-60-RED */
  47         SPX5_TARGET_CT_LAN9698    = 0x9698,  /* lan969x-100 */
  48         SPX5_TARGET_CT_LAN9693VAO = 0x9693,  /* lan969x-100-VAO */
  49         SPX5_TARGET_CT_LAN9698TSN = 0x9699,  /* lan969x-100-TSN */
  50         SPX5_TARGET_CT_LAN9698RED = 0x969C,  /* lan969x-100-RED */
  51 };
  52
  53 enum sparx5_port_max_tags {
  54         SPX5_PORT_MAX_TAGS_NONE,  /* No extra tags allowed */
  55         SPX5_PORT_MAX_TAGS_ONE,   /* Single tag allowed */
  56         SPX5_PORT_MAX_TAGS_TWO    /* Single and double tag allowed */
  57 };
  58
  59 enum sparx5_vlan_port_type {
  60         SPX5_VLAN_PORT_TYPE_UNAWARE, /* VLAN unaware port */
  61         SPX5_VLAN_PORT_TYPE_C,       /* C-port */
  62         SPX5_VLAN_PORT_TYPE_S,       /* S-port */
  63         SPX5_VLAN_PORT_TYPE_S_CUSTOM /* S-port using custom type */
  64 };
  65
  66 /* This is used in calendar configuration */
  67 enum sparx5_cal_bw {
  68         SPX5_CAL_SPEED_NONE = 0,
  69         SPX5_CAL_SPEED_1G   = 1,
  70         SPX5_CAL_SPEED_2G5  = 2,
  71         SPX5_CAL_SPEED_5G   = 3,
  72         SPX5_CAL_SPEED_10G  = 4,
  73         SPX5_CAL_SPEED_25G  = 5,
  74         SPX5_CAL_SPEED_0G5  = 6,
  75         SPX5_CAL_SPEED_12G5 = 7
  76 };
  77
  78 enum sparx5_feature {
  79         SPX5_FEATURE_PSFP = BIT(0),
  80         SPX5_FEATURE_PTP  = BIT(1),
  81 };
  82
  83 #define SPX5_PORTS             65
  84 #define SPX5_PORTS_ALL         70 /* Total number of ports */
  85
  86 #define SPX5_PORT_CPU_0        0 /* CPU Port 0 */
  87 #define SPX5_PORT_CPU_1        1 /* CPU Port 1 */
  88 #define SPX5_PORT_VD0          2 /* VD0/Port used for IPMC */
  89 #define SPX5_PORT_VD1          3 /* VD1/Port used for AFI/OAM */
  90 #define SPX5_PORT_VD2          4 /* VD2/Port used for IPinIP*/
  91
  92 #define PGID_UC_FLOOD          0
  93 #define PGID_MC_FLOOD          1
  94 #define PGID_IPV4_MC_DATA      2
  95 #define PGID_IPV4_MC_CTRL      3
  96 #define PGID_IPV6_MC_DATA      4
  97 #define PGID_IPV6_MC_CTRL      5
  98 #define PGID_BCAST             6
  99 #define PGID_CPU               7
 100 #define PGID_MCAST_START       8
 101
 102 #define PGID_TABLE_SIZE        3290
 103
 104 #define IFH_LEN                9 /* 36 bytes */
 105 #define NULL_VID               0
 106 #define SPX5_MACT_PULL_DELAY   (2 * HZ)
 107 #define SPX5_STATS_CHECK_DELAY (1 * HZ)
 108 #define SPX5_PRIOS             8     /* Number of priority queues */
 109 #define SPX5_BUFFER_CELL_SZ    184   /* Cell size  */
 110 #define SPX5_BUFFER_MEMORY     4194280 /* 22795 words * 184 bytes */
 111
 112 #define XTR_QUEUE     0
 113 #define INJ_QUEUE     0
 114
 115 #define FDMA_DCB_MAX                    64
 116 #define FDMA_RX_DCB_MAX_DBS             15
 117 #define FDMA_TX_DCB_MAX_DBS             1
 118
 119 #define SPARX5_PHC_COUNT                3
 120 #define SPARX5_PHC_PORT                 0
 121
 122 #define IFH_REW_OP_NOOP                 0x0
 123 #define IFH_REW_OP_ONE_STEP_PTP         0x3
 124 #define IFH_REW_OP_TWO_STEP_PTP         0x4
 125
 126 #define IFH_PDU_TYPE_NONE               0x0
 127 #define IFH_PDU_TYPE_PTP                0x5
 128 #define IFH_PDU_TYPE_IPV4_UDP_PTP       0x6
 129 #define IFH_PDU_TYPE_IPV6_UDP_PTP       0x7
 130
 131 #define SPX5_DSM_CAL_LEN               64
 132 #define SPX5_DSM_CAL_MAX_DEVS_PER_TAXI 13
 133 #define SPX5_DSM_CAL_EMPTY             0xFFFF
 134
 135 #define SPARX5_MAX_PTP_ID       512
 136
 137 struct sparx5;
 138
 139 struct sparx5_calendar_data {
 140         u32 schedule[SPX5_DSM_CAL_LEN];
 141         u32 avg_dist[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI];
 142         u32 taxi_ports[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI];
 143         u32 taxi_speeds[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI];
 144         u32 dev_slots[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI];
 145         u32 new_slots[SPX5_DSM_CAL_LEN];
 146         u32 temp_sched[SPX5_DSM_CAL_LEN];
 147         u32 indices[SPX5_DSM_CAL_LEN];
 148         u32 short_list[SPX5_DSM_CAL_LEN];
 149         u32 long_list[SPX5_DSM_CAL_LEN];
 150 };
 151
 152 /* Frame DMA receive state:
 153  * For each DB, there is a SKB, and the skb data pointer is mapped in
 154  * the DB. Once a frame is received the skb is given to the upper layers
 155  * and a new skb is added to the dcb.
 156  * When the db_index reached FDMA_RX_DCB_MAX_DBS the DB is reused.
 157  */
 158 struct sparx5_rx {
 159         struct fdma fdma;
 160         struct sk_buff *skb[FDMA_DCB_MAX][FDMA_RX_DCB_MAX_DBS];
 161         dma_addr_t dma;
 162         struct napi_struct napi;
 163         struct net_device *ndev;
 164         u64 packets;
 165 };
 166
 167 /* Frame DMA transmit state:
 168  * DCBs are chained using the DCBs nextptr field.
 169  */
 170 struct sparx5_tx {
 171         struct fdma fdma;
 172         u64 packets;
 173         u64 dropped;
 174 };
 175
 176 struct sparx5_port_config {
 177         phy_interface_t portmode;
 178         u32 bandwidth;
 179         int speed;
 180         int duplex;
 181         enum phy_media media;
 182         bool inband;
 183         bool power_down;
 184         bool autoneg;
 185         bool serdes_reset;
 186         u32 pause;
 187         u32 pause_adv;
 188         phy_interface_t phy_mode;
 189         u32 sd_sgpio;
 190 };
 191
 192 struct sparx5_port {
 193         struct net_device *ndev;
 194         struct sparx5 *sparx5;
 195         struct device_node *of_node;
 196         struct phy *serdes;
 197         struct sparx5_port_config conf;
 198         struct phylink_config phylink_config;
 199         struct phylink *phylink;
 200         struct phylink_pcs phylink_pcs;
 201         struct flow_stats mirror_stats;
 202         u16 portno;
 203         /* Ingress default VLAN (pvid) */
 204         u16 pvid;
 205         /* Egress default VLAN (vid) */
 206         u16 vid;
 207         bool signd_internal;
 208         bool signd_active_high;
 209         bool signd_enable;
 210         bool flow_control;
 211         enum sparx5_port_max_tags max_vlan_tags;
 212         enum sparx5_vlan_port_type vlan_type;
 213         u32 custom_etype;
 214         bool vlan_aware;
 215         struct hrtimer inj_timer;
 216         /* ptp */
 217         u8 ptp_cmd;
 218         u16 ts_id;
 219         struct sk_buff_head tx_skbs;
 220         bool is_mrouter;
 221         struct list_head tc_templates; /* list of TC templates on this port */
 222 };
 223
 224 enum sparx5_core_clockfreq {
 225         SPX5_CORE_CLOCK_DEFAULT,  /* Defaults to the highest supported frequency */
 226         SPX5_CORE_CLOCK_250MHZ,   /* 250MHZ core clock frequency */
 227         SPX5_CORE_CLOCK_328MHZ,   /* 328MHZ core clock frequency */
 228         SPX5_CORE_CLOCK_500MHZ,   /* 500MHZ core clock frequency */
 229         SPX5_CORE_CLOCK_625MHZ,   /* 625MHZ core clock frequency */
 230 };
 231
 232 struct sparx5_phc {
 233         struct ptp_clock *clock;
 234         struct ptp_clock_info info;
 235         struct kernel_hwtstamp_config hwtstamp_config;
 236         struct sparx5 *sparx5;
 237         u8 index;
 238 };
 239
 240 struct sparx5_skb_cb {
 241         u8 rew_op;
 242         u8 pdu_type;
 243         u8 pdu_w16_offset;
 244         u16 ts_id;
 245         unsigned long jiffies;
 246 };
 247
 248 struct sparx5_mdb_entry {
 249         struct list_head list;
 250         DECLARE_BITMAP(port_mask, SPX5_PORTS);
 251         unsigned char addr[ETH_ALEN];
 252         bool cpu_copy;
 253         u16 vid;
 254         u16 pgid_idx;
 255 };
 256
 257 struct sparx5_mall_mirror_entry {
 258         u32 idx;
 259         struct sparx5_port *port;
 260 };
 261
 262 struct sparx5_mall_entry {
 263         struct list_head list;
 264         struct sparx5_port *port;
 265         unsigned long cookie;
 266         enum flow_action_id type;
 267         bool ingress;
 268         union {
 269                 struct sparx5_mall_mirror_entry mirror;
 270         };
 271 };
 272
 273 #define SPARX5_PTP_TIMEOUT              msecs_to_jiffies(10)
 274 #define SPARX5_SKB_CB(skb) \
 275         ((struct sparx5_skb_cb *)((skb)->cb))
 276
 277 struct sparx5_regs {
 278         const unsigned int *tsize;
 279         const unsigned int *gaddr;
 280         const unsigned int *gcnt;
 281         const unsigned int *gsize;
 282         const unsigned int *raddr;
 283         const unsigned int *rcnt;
 284         const unsigned int *fpos;
 285         const unsigned int *fsize;
 286 };
 287
 288 struct sparx5_consts {
 289         u32 n_ports;             /* Number of front ports */
 290         u32 n_ports_all;         /* Number of front ports + internal ports */
 291         u32 n_hsch_l1_elems;     /* Number of HSCH layer 1 elements */
 292         u32 n_hsch_queues;       /* Number of HSCH queues */
 293         u32 n_lb_groups;         /* Number of leacky bucket groupd */
 294         u32 n_pgids;             /* Number of PGID's */
 295         u32 n_sio_clks;          /* Number of serial IO clocks */
 296         u32 n_own_upsids;        /* Number of own UPSID's */
 297         u32 n_auto_cals;         /* Number of auto calendars */
 298         u32 n_filters;           /* Number of PSFP filters */
 299         u32 n_gates;             /* Number of PSFP gates */
 300         u32 n_sdlbs;             /* Number of service dual leaky buckets */
 301         u32 n_dsm_cal_taxis;     /* Number of DSM calendar taxis */
 302         u32 buf_size;            /* Amount of QLIM watermark memory */
 303         u32 qres_max_prio_idx;   /* Maximum QRES prio index */
 304         u32 qres_max_colour_idx; /* Maximum QRES colour index */
 305         u32 tod_pin;             /* PTP TOD pin */
 306         const struct sparx5_vcap_inst *vcaps_cfg;
 307         const struct vcap_info *vcaps;
 308         const struct vcap_statistics *vcap_stats;
 309 };
 310
 311 struct sparx5_ops {
 312         bool (*is_port_2g5)(int portno);
 313         bool (*is_port_5g)(int portno);
 314         bool (*is_port_10g)(int portno);
 315         bool (*is_port_25g)(int portno);
 316         u32  (*get_port_dev_index)(struct sparx5 *sparx5, int port);
 317         u32  (*get_port_dev_bit)(struct sparx5 *sparx5, int port);
 318         u32  (*get_hsch_max_group_rate)(int grp);
 319         struct sparx5_sdlb_group *(*get_sdlb_group)(int idx);
 320         int (*set_port_mux)(struct sparx5 *sparx5, struct sparx5_port *port,
 321                             struct sparx5_port_config *conf);
 322
 323         irqreturn_t (*ptp_irq_handler)(int irq, void *args);
 324         int (*dsm_calendar_calc)(struct sparx5 *sparx5, u32 taxi,
 325                                  struct sparx5_calendar_data *data);
 326 };
 327
 328 struct sparx5_main_io_resource {
 329         enum sparx5_target id;
 330         phys_addr_t offset;
 331         int range;
 332 };
 333
 334 struct sparx5_match_data {
 335         const struct sparx5_regs *regs;
 336         const struct sparx5_consts *consts;
 337         const struct sparx5_ops *ops;
 338         const struct sparx5_main_io_resource *iomap;
 339         int ioranges;
 340         int iomap_size;
 341 };
 342
 343 struct sparx5 {
 344         struct platform_device *pdev;
 345         struct device *dev;
 346         u32 chip_id;
 347         enum spx5_target_chiptype target_ct;
 348         u32 features;
 349         void __iomem *regs[NUM_TARGETS];
 350         int port_count;
 351         struct mutex lock; /* MAC reg lock */
 352         /* port structures are in net device */
 353         struct sparx5_port *ports[SPX5_PORTS];
 354         enum sparx5_core_clockfreq coreclock;
 355         /* Statistics */
 356         u32 num_stats;
 357         u32 num_ethtool_stats;
 358         const char * const *stats_layout;
 359         u64 *stats;
 360         /* Workqueue for reading stats */
 361         struct mutex queue_stats_lock;
 362         struct delayed_work stats_work;
 363         struct workqueue_struct *stats_queue;
 364         /* Notifiers */
 365         struct notifier_block netdevice_nb;
 366         struct notifier_block switchdev_nb;
 367         struct notifier_block switchdev_blocking_nb;
 368         /* Switch state */
 369         u8 base_mac[ETH_ALEN];
 370         /* Associated bridge device (when bridged) */
 371         struct net_device *hw_bridge_dev;
 372         /* Bridged interfaces */
 373         DECLARE_BITMAP(bridge_mask, SPX5_PORTS);
 374         DECLARE_BITMAP(bridge_fwd_mask, SPX5_PORTS);
 375         DECLARE_BITMAP(bridge_lrn_mask, SPX5_PORTS);
 376         DECLARE_BITMAP(vlan_mask[VLAN_N_VID], SPX5_PORTS);
 377         /* SW MAC table */
 378         struct list_head mact_entries;
 379         /* mac table list (mact_entries) mutex */
 380         struct mutex mact_lock;
 381         /* SW MDB table */
 382         struct list_head mdb_entries;
 383         /* mdb list mutex */
 384         struct mutex mdb_lock;
 385         struct delayed_work mact_work;
 386         struct workqueue_struct *mact_queue;
 387         /* Board specifics */
 388         bool sd_sgpio_remapping;
 389         /* Register based inj/xtr */
 390         int xtr_irq;
 391         /* Frame DMA */
 392         int fdma_irq;
 393         spinlock_t tx_lock; /* lock for frame transmission */
 394         struct sparx5_rx rx;
 395         struct sparx5_tx tx;
 396         /* PTP */
 397         bool ptp;
 398         struct sparx5_phc phc[SPARX5_PHC_COUNT];
 399         spinlock_t ptp_clock_lock; /* lock for phc */
 400         spinlock_t ptp_ts_id_lock; /* lock for ts_id */
 401         struct mutex ptp_lock; /* lock for ptp interface state */
 402         u16 ptp_skbs;
 403         int ptp_irq;
 404         /* VCAP */
 405         struct vcap_control *vcap_ctrl;
 406         /* PGID allocation map */
 407         u8 pgid_map[PGID_TABLE_SIZE];
 408         struct list_head mall_entries;
 409         /* Common root for debugfs */
 410         struct dentry *debugfs_root;
 411         const struct sparx5_match_data *data;
 412 };
 413
 414 /* sparx5_main.c */
 415 bool is_sparx5(struct sparx5 *sparx5);
 416 bool sparx5_has_feature(struct sparx5 *sparx5, enum sparx5_feature feature);
 417
 418 /* sparx5_switchdev.c */
 419 int sparx5_register_notifier_blocks(struct sparx5 *sparx5);
 420 void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5);
 421
 422 /* sparx5_packet.c */
 423 struct frame_info {
 424         int src_port;
 425         u32 timestamp;
 426 };
 427
 428 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp);
 429 void sparx5_ifh_parse(struct sparx5 *sparx5, u32 *ifh, struct frame_info *info);
 430 irqreturn_t sparx5_xtr_handler(int irq, void *_priv);
 431 netdev_tx_t sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev);
 432 int sparx5_manual_injection_mode(struct sparx5 *sparx5);
 433 void sparx5_port_inj_timer_setup(struct sparx5_port *port);
 434
 435 /* sparx5_fdma.c */
 436 int sparx5_fdma_start(struct sparx5 *sparx5);
 437 int sparx5_fdma_stop(struct sparx5 *sparx5);
 438 int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb);
 439 irqreturn_t sparx5_fdma_handler(int irq, void *args);
 440
 441 /* sparx5_mactable.c */
 442 void sparx5_mact_pull_work(struct work_struct *work);
 443 int sparx5_mact_learn(struct sparx5 *sparx5, int port,
 444                       const unsigned char mac[ETH_ALEN], u16 vid);
 445 bool sparx5_mact_getnext(struct sparx5 *sparx5,
 446                          unsigned char mac[ETH_ALEN], u16 *vid, u32 *pcfg2);
 447 int sparx5_mact_find(struct sparx5 *sparx5,
 448                      const unsigned char mac[ETH_ALEN], u16 vid, u32 *pcfg2);
 449 int sparx5_mact_forget(struct sparx5 *sparx5,
 450                        const unsigned char mac[ETH_ALEN], u16 vid);
 451 int sparx5_add_mact_entry(struct sparx5 *sparx5,
 452                           struct net_device *dev,
 453                           u16 portno,
 454                           const unsigned char *addr, u16 vid);
 455 int sparx5_del_mact_entry(struct sparx5 *sparx5,
 456                           const unsigned char *addr,
 457                           u16 vid);
 458 int sparx5_mc_sync(struct net_device *dev, const unsigned char *addr);
 459 int sparx5_mc_unsync(struct net_device *dev, const unsigned char *addr);
 460 void sparx5_set_ageing(struct sparx5 *sparx5, int msecs);
 461 void sparx5_mact_init(struct sparx5 *sparx5);
 462
 463 /* sparx5_vlan.c */
 464 void sparx5_pgid_update_mask(struct sparx5_port *port, int pgid, bool enable);
 465 void sparx5_pgid_clear(struct sparx5 *spx5, int pgid);
 466 void sparx5_pgid_read_mask(struct sparx5 *sparx5, int pgid, u32 portmask[3]);
 467 void sparx5_update_fwd(struct sparx5 *sparx5);
 468 void sparx5_vlan_init(struct sparx5 *sparx5);
 469 void sparx5_vlan_port_setup(struct sparx5 *sparx5, int portno);
 470 int sparx5_vlan_vid_add(struct sparx5_port *port, u16 vid, bool pvid,
 471                         bool untagged);
 472 int sparx5_vlan_vid_del(struct sparx5_port *port, u16 vid);
 473 void sparx5_vlan_port_apply(struct sparx5 *sparx5, struct sparx5_port *port);
 474
 475 /* sparx5_calendar.c */
 476 int sparx5_config_auto_calendar(struct sparx5 *sparx5);
 477 int sparx5_config_dsm_calendar(struct sparx5 *sparx5);
 478 int sparx5_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi,
 479                              struct sparx5_calendar_data *data);
 480 u32 sparx5_cal_speed_to_value(enum sparx5_cal_bw speed);
 481 enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, u32 portno);
 482
 483
 484 /* sparx5_ethtool.c */
 485 void sparx5_get_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats);
 486 int sparx_stats_init(struct sparx5 *sparx5);
 487
 488 /* sparx5_dcb.c */
 489 #ifdef CONFIG_SPARX5_DCB
 490 int sparx5_dcb_init(struct sparx5 *sparx5);
 491 #else
 492 static inline int sparx5_dcb_init(struct sparx5 *sparx5)
 493 {
 494         return 0;
 495 }
 496 #endif
 497
 498 /* sparx5_netdev.c */
 499 void sparx5_set_port_ifh_timestamp(struct sparx5 *sparx5, void *ifh_hdr,
 500                                    u64 timestamp);
 501 void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op);
 502 void sparx5_set_port_ifh_pdu_type(struct sparx5 *sparx5, void *ifh_hdr,
 503                                   u32 pdu_type);
 504 void sparx5_set_port_ifh_pdu_w16_offset(struct sparx5 *sparx5, void *ifh_hdr,
 505                                         u32 pdu_w16_offset);
 506 void sparx5_set_port_ifh(struct sparx5 *sparx5, void *ifh_hdr, u16 portno);
 507 bool sparx5_netdevice_check(const struct net_device *dev);
 508 struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno);
 509 int sparx5_register_netdevs(struct sparx5 *sparx5);
 510 void sparx5_destroy_netdevs(struct sparx5 *sparx5);
 511 void sparx5_unregister_netdevs(struct sparx5 *sparx5);
 512
 513 /* sparx5_ptp.c */
 514 int sparx5_ptp_init(struct sparx5 *sparx5);
 515 void sparx5_ptp_deinit(struct sparx5 *sparx5);
 516 int sparx5_ptp_hwtstamp_set(struct sparx5_port *port,
 517                             struct kernel_hwtstamp_config *cfg,
 518                             struct netlink_ext_ack *extack);
 519 void sparx5_ptp_hwtstamp_get(struct sparx5_port *port,
 520                              struct kernel_hwtstamp_config *cfg);
 521 void sparx5_ptp_rxtstamp(struct sparx5 *sparx5, struct sk_buff *skb,
 522                          u64 timestamp);
 523 int sparx5_ptp_txtstamp_request(struct sparx5_port *port,
 524                                 struct sk_buff *skb);
 525 void sparx5_ptp_txtstamp_release(struct sparx5_port *port,
 526                                  struct sk_buff *skb);
 527 irqreturn_t sparx5_ptp_irq_handler(int irq, void *args);
 528 int sparx5_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts);
 529 void sparx5_get_hwtimestamp(struct sparx5 *sparx5,
 530                             struct timespec64 *ts,
 531                             u32 nsec);
 532
 533 /* sparx5_vcap_impl.c */
 534 int sparx5_vcap_init(struct sparx5 *sparx5);
 535 void sparx5_vcap_destroy(struct sparx5 *sparx5);
 536
 537 /* sparx5_pgid.c */
 538 enum sparx5_pgid_type {
 539         SPX5_PGID_FREE,
 540         SPX5_PGID_RESERVED,
 541         SPX5_PGID_MULTICAST,
 542 };
 543
 544 void sparx5_pgid_init(struct sparx5 *spx5);
 545 int sparx5_pgid_alloc_mcast(struct sparx5 *spx5, u16 *idx);
 546 int sparx5_pgid_free(struct sparx5 *spx5, u16 idx);
 547 int sparx5_get_pgid(struct sparx5 *sparx5, int pgid);
 548
 549 /* sparx5_pool.c */
 550 struct sparx5_pool_entry {
 551         u16 ref_cnt;
 552         u32 idx; /* tc index */
 553 };
 554
 555 u32 sparx5_pool_idx_to_id(u32 idx);
 556 int sparx5_pool_put(struct sparx5_pool_entry *pool, int size, u32 id);
 557 int sparx5_pool_get(struct sparx5_pool_entry *pool, int size, u32 *id);
 558 int sparx5_pool_get_with_idx(struct sparx5_pool_entry *pool, int size, u32 idx,
 559                              u32 *id);
 560
 561 /* sparx5_port.c */
 562 int sparx5_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port,
 563                         struct sparx5_port_config *conf);
 564 int sparx5_get_internal_port(struct sparx5 *sparx5, int port);
 565
 566 /* sparx5_sdlb.c */
 567 #define SPX5_SDLB_PUP_TOKEN_DISABLE 0x1FFF
 568 #define SPX5_SDLB_PUP_TOKEN_MAX (SPX5_SDLB_PUP_TOKEN_DISABLE - 1)
 569 #define SPX5_SDLB_GROUP_RATE_MAX 25000000000ULL
 570 #define SPX5_SDLB_2CYCLES_TYPE2_THRES_OFFSET 13
 571 #define SPX5_SDLB_CNT 4096
 572 #define SPX5_SDLB_GROUP_CNT 10
 573 #define SPX5_CLK_PER_100PS_DEFAULT 16
 574
 575 struct sparx5_sdlb_group {
 576         u64 max_rate;
 577         u32 min_burst;
 578         u32 frame_size;
 579         u32 pup_interval;
 580         u32 nsets;
 581 };
 582
 583 extern struct sparx5_sdlb_group sdlb_groups[SPX5_SDLB_GROUP_CNT];
 584 struct sparx5_sdlb_group *sparx5_get_sdlb_group(int idx);
 585 int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval,
 586                               u64 rate);
 587
 588 u64 sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5);
 589 int sparx5_sdlb_group_get_by_rate(struct sparx5 *sparx5, u32 rate, u32 burst);
 590 int sparx5_sdlb_group_get_by_index(struct sparx5 *sparx5, u32 idx, u32 *group);
 591
 592 int sparx5_sdlb_group_add(struct sparx5 *sparx5, u32 group, u32 idx);
 593 int sparx5_sdlb_group_del(struct sparx5 *sparx5, u32 group, u32 idx);
 594
 595 void sparx5_sdlb_group_init(struct sparx5 *sparx5, u64 max_rate, u32 min_burst,
 596                             u32 frame_size, u32 idx);
 597
 598 /* sparx5_police.c */
 599 enum {
 600         /* More policer types will be added later */
 601         SPX5_POL_SERVICE
 602 };
 603
 604 struct sparx5_policer {
 605         u32 type;
 606         u32 idx;
 607         u64 rate;
 608         u32 burst;
 609         u32 group;
 610         u8 event_mask;
 611 };
 612
 613 int sparx5_policer_conf_set(struct sparx5 *sparx5, struct sparx5_policer *pol);
 614
 615 /* sparx5_psfp.c */
 616 #define SPX5_PSFP_GCE_CNT 4
 617 #define SPX5_PSFP_SG_CNT 1024
 618 #define SPX5_PSFP_SG_MIN_CYCLE_TIME_NS (1 * NSEC_PER_USEC)
 619 #define SPX5_PSFP_SG_MAX_CYCLE_TIME_NS ((1 * NSEC_PER_SEC) - 1)
 620 #define SPX5_PSFP_SG_MAX_IPV (SPX5_PRIOS - 1)
 621 #define SPX5_PSFP_SG_OPEN (SPX5_PSFP_SG_CNT - 1)
 622 #define SPX5_PSFP_SG_CYCLE_TIME_DEFAULT 1000000
 623 #define SPX5_PSFP_SF_MAX_SDU 16383
 624
 625 struct sparx5_psfp_fm {
 626         struct sparx5_policer pol;
 627 };
 628
 629 struct sparx5_psfp_gce {
 630         bool gate_state;            /* StreamGateState */
 631         u32 interval;               /* TimeInterval */
 632         u32 ipv;                    /* InternalPriorityValue */
 633         u32 maxoctets;              /* IntervalOctetMax */
 634 };
 635
 636 struct sparx5_psfp_sg {
 637         bool gate_state;            /* PSFPAdminGateStates */
 638         bool gate_enabled;          /* PSFPGateEnabled */
 639         u32 ipv;                    /* PSFPAdminIPV */
 640         struct timespec64 basetime; /* PSFPAdminBaseTime */
 641         u32 cycletime;              /* PSFPAdminCycleTime */
 642         u32 cycletimeext;           /* PSFPAdminCycleTimeExtension */
 643         u32 num_entries;            /* PSFPAdminControlListLength */
 644         struct sparx5_psfp_gce gce[SPX5_PSFP_GCE_CNT];
 645 };
 646
 647 struct sparx5_psfp_sf {
 648         bool sblock_osize_ena;
 649         bool sblock_osize;
 650         u32 max_sdu;
 651         u32 sgid; /* Gate id */
 652         u32 fmid; /* Flow meter id */
 653 };
 654
 655 int sparx5_psfp_fm_add(struct sparx5 *sparx5, u32 uidx,
 656                        struct sparx5_psfp_fm *fm, u32 *id);
 657 int sparx5_psfp_fm_del(struct sparx5 *sparx5, u32 id);
 658
 659 int sparx5_psfp_sg_add(struct sparx5 *sparx5, u32 uidx,
 660                        struct sparx5_psfp_sg *sg, u32 *id);
 661 int sparx5_psfp_sg_del(struct sparx5 *sparx5, u32 id);
 662
 663 int sparx5_psfp_sf_add(struct sparx5 *sparx5, const struct sparx5_psfp_sf *sf,
 664                        u32 *id);
 665 int sparx5_psfp_sf_del(struct sparx5 *sparx5, u32 id);
 666
 667 u32 sparx5_psfp_isdx_get_sf(struct sparx5 *sparx5, u32 isdx);
 668 u32 sparx5_psfp_isdx_get_fm(struct sparx5 *sparx5, u32 isdx);
 669 u32 sparx5_psfp_sf_get_sg(struct sparx5 *sparx5, u32 sfid);
 670 void sparx5_isdx_conf_set(struct sparx5 *sparx5, u32 isdx, u32 sfid, u32 fmid);
 671
 672 void sparx5_psfp_init(struct sparx5 *sparx5);
 673
 674 /* sparx5_qos.c */
 675 void sparx5_new_base_time(struct sparx5 *sparx5, const u32 cycle_time,
 676                           const ktime_t org_base_time, ktime_t *new_base_time);
 677
 678 /* sparx5_mirror.c */
 679 int sparx5_mirror_add(struct sparx5_mall_entry *entry);
 680 void sparx5_mirror_del(struct sparx5_mall_entry *entry);
 681 void sparx5_mirror_stats(struct sparx5_mall_entry *entry,
 682                          struct flow_stats *fstats);
 683
 684 /* Clock period in picoseconds */
 685 static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock)
 686 {
 687         switch (cclock) {
 688         case SPX5_CORE_CLOCK_250MHZ:
 689                 return 4000;
 690         case SPX5_CORE_CLOCK_328MHZ:
 691                 return 3048;
 692         case SPX5_CORE_CLOCK_500MHZ:
 693                 return 2000;
 694         case SPX5_CORE_CLOCK_625MHZ:
 695         default:
 696                 return 1600;
 697         }
 698 }
 699
 700 static inline bool sparx5_is_baser(phy_interface_t interface)
 701 {
 702         return interface == PHY_INTERFACE_MODE_5GBASER ||
 703                    interface == PHY_INTERFACE_MODE_10GBASER ||
 704                    interface == PHY_INTERFACE_MODE_25GBASER;
 705 }
 706
 707 extern const struct phylink_mac_ops sparx5_phylink_mac_ops;
 708 extern const struct phylink_pcs_ops sparx5_phylink_pcs_ops;
 709 extern const struct ethtool_ops sparx5_ethtool_ops;
 710 extern const struct dcbnl_rtnl_ops sparx5_dcbnl_ops;
 711
 712 /* Calculate raw offset */
 713 static inline __pure int spx5_offset(int id, int tinst, int tcnt,
 714                                      int gbase, int ginst,
 715                                      int gcnt, int gwidth,
 716                                      int raddr, int rinst,
 717                                      int rcnt, int rwidth)
 718 {
 719         WARN_ON((tinst) >= tcnt);
 720         WARN_ON((ginst) >= gcnt);
 721         WARN_ON((rinst) >= rcnt);
 722         return gbase + ((ginst) * gwidth) +
 723                 raddr + ((rinst) * rwidth);
 724 }
 725
 726 /* Read, Write and modify registers content.
 727  * The register definition macros start at the id
 728  */
 729 static inline void __iomem *spx5_addr(void __iomem *base[],
 730                                       int id, int tinst, int tcnt,
 731                                       int gbase, int ginst,
 732                                       int gcnt, int gwidth,
 733                                       int raddr, int rinst,
 734                                       int rcnt, int rwidth)
 735 {
 736         WARN_ON((tinst) >= tcnt);
 737         WARN_ON((ginst) >= gcnt);
 738         WARN_ON((rinst) >= rcnt);
 739         return base[id + (tinst)] +
 740                 gbase + ((ginst) * gwidth) +
 741                 raddr + ((rinst) * rwidth);
 742 }
 743
 744 static inline void __iomem *spx5_inst_addr(void __iomem *base,
 745                                            int gbase, int ginst,
 746                                            int gcnt, int gwidth,
 747                                            int raddr, int rinst,
 748                                            int rcnt, int rwidth)
 749 {
 750         WARN_ON((ginst) >= gcnt);
 751         WARN_ON((rinst) >= rcnt);
 752         return base +
 753                 gbase + ((ginst) * gwidth) +
 754                 raddr + ((rinst) * rwidth);
 755 }
 756
 757 static inline u32 spx5_rd(struct sparx5 *sparx5, int id, int tinst, int tcnt,
 758                           int gbase, int ginst, int gcnt, int gwidth,
 759                           int raddr, int rinst, int rcnt, int rwidth)
 760 {
 761         return readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst,
 762                                gcnt, gwidth, raddr, rinst, rcnt, rwidth));
 763 }
 764
 765 static inline u32 spx5_inst_rd(void __iomem *iomem, int id, int tinst, int tcnt,
 766                                int gbase, int ginst, int gcnt, int gwidth,
 767                                int raddr, int rinst, int rcnt, int rwidth)
 768 {
 769         return readl(spx5_inst_addr(iomem, gbase, ginst,
 770                                      gcnt, gwidth, raddr, rinst, rcnt, rwidth));
 771 }
 772
 773 static inline void spx5_wr(u32 val, struct sparx5 *sparx5,
 774                            int id, int tinst, int tcnt,
 775                            int gbase, int ginst, int gcnt, int gwidth,
 776                            int raddr, int rinst, int rcnt, int rwidth)
 777 {
 778         writel(val, spx5_addr(sparx5->regs, id, tinst, tcnt,
 779                               gbase, ginst, gcnt, gwidth,
 780                               raddr, rinst, rcnt, rwidth));
 781 }
 782
 783 static inline void spx5_inst_wr(u32 val, void __iomem *iomem,
 784                                 int id, int tinst, int tcnt,
 785                                 int gbase, int ginst, int gcnt, int gwidth,
 786                                 int raddr, int rinst, int rcnt, int rwidth)
 787 {
 788         writel(val, spx5_inst_addr(iomem,
 789                                    gbase, ginst, gcnt, gwidth,
 790                                    raddr, rinst, rcnt, rwidth));
 791 }
 792
 793 static inline void spx5_rmw(u32 val, u32 mask, struct sparx5 *sparx5,
 794                             int id, int tinst, int tcnt,
 795                             int gbase, int ginst, int gcnt, int gwidth,
 796                             int raddr, int rinst, int rcnt, int rwidth)
 797 {
 798         u32 nval;
 799
 800         nval = readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst,
 801                                gcnt, gwidth, raddr, rinst, rcnt, rwidth));
 802         nval = (nval & ~mask) | (val & mask);
 803         writel(nval, spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst,
 804                                gcnt, gwidth, raddr, rinst, rcnt, rwidth));
 805 }
 806
 807 static inline void spx5_inst_rmw(u32 val, u32 mask, void __iomem *iomem,
 808                                  int id, int tinst, int tcnt,
 809                                  int gbase, int ginst, int gcnt, int gwidth,
 810                                  int raddr, int rinst, int rcnt, int rwidth)
 811 {
 812         u32 nval;
 813
 814         nval = readl(spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr,
 815                                     rinst, rcnt, rwidth));
 816         nval = (nval & ~mask) | (val & mask);
 817         writel(nval, spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr,
 818                                     rinst, rcnt, rwidth));
 819 }
 820
 821 static inline void __iomem *spx5_inst_get(struct sparx5 *sparx5, int id, int tinst)
 822 {
 823         return sparx5->regs[id + tinst];
 824 }
 825
 826 static inline void __iomem *spx5_reg_get(struct sparx5 *sparx5,
 827                                          int id, int tinst, int tcnt,
 828                                          int gbase, int ginst, int gcnt, int gwidth,
 829                                          int raddr, int rinst, int rcnt, int rwidth)
 830 {
 831         return spx5_addr(sparx5->regs, id, tinst, tcnt,
 832                          gbase, ginst, gcnt, gwidth,
 833                          raddr, rinst, rcnt, rwidth);
 834 }
 835
 836 #endif  /* __SPARX5_MAIN_H__ */