drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Microchip Sparx5 Switch driver
   3  *
   4  * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
   5  */
   6
   7 #include "sparx5_main_regs.h"
   8 #include "sparx5_main.h"
   9 #include "sparx5_port.h"
  10 #include "sparx5_tc.h"
  11
  12 /* The IFH bit position of the first VSTAX bit. This is because the
  13  * VSTAX bit positions in Data sheet is starting from zero.
  14  */
  15 #define VSTAX 73
  16
  17 #define ifh_encode_bitfield(ifh, value, pos, _width)                    \
  18         ({                                                              \
  19                 u32 width = (_width);                                   \
  20                                                                         \
  21                 /* Max width is 5 bytes - 40 bits. In worst case this will
  22                  * spread over 6 bytes - 48 bits
  23                  */                                                     \
  24                 compiletime_assert(width <= 40,                         \
  25                                    "Unsupported width, must be <= 40"); \
  26                 __ifh_encode_bitfield((ifh), (value), (pos), width);    \
  27         })
  28
  29 static void __ifh_encode_bitfield(void *ifh, u64 value, u32 pos, u32 width)
  30 {
  31         u8 *ifh_hdr = ifh;
  32         /* Calculate the Start IFH byte position of this IFH bit position */
  33         u32 byte = (35 - (pos / 8));
  34         /* Calculate the Start bit position in the Start IFH byte */
  35         u32 bit  = (pos % 8);
  36         u64 encode = GENMASK_ULL(bit + width - 1, bit) & (value << bit);
  37
  38         /* The b0-b7 goes into the start IFH byte */
  39         if (encode & 0xFF)
  40                 ifh_hdr[byte] |= (u8)((encode & 0xFF));
  41         /* The b8-b15 goes into the next IFH byte */
  42         if (encode & 0xFF00)
  43                 ifh_hdr[byte - 1] |= (u8)((encode & 0xFF00) >> 8);
  44         /* The b16-b23 goes into the next IFH byte */
  45         if (encode & 0xFF0000)
  46                 ifh_hdr[byte - 2] |= (u8)((encode & 0xFF0000) >> 16);
  47         /* The b24-b31 goes into the next IFH byte */
  48         if (encode & 0xFF000000)
  49                 ifh_hdr[byte - 3] |= (u8)((encode & 0xFF000000) >> 24);
  50         /* The b32-b39 goes into the next IFH byte */
  51         if (encode & 0xFF00000000)
  52                 ifh_hdr[byte - 4] |= (u8)((encode & 0xFF00000000) >> 32);
  53         /* The b40-b47 goes into the next IFH byte */
  54         if (encode & 0xFF0000000000)
  55                 ifh_hdr[byte - 5] |= (u8)((encode & 0xFF0000000000) >> 40);
  56 }
  57
  58 void sparx5_set_port_ifh(struct sparx5 *sparx5, void *ifh_hdr, u16 portno)
  59 {
  60         /* VSTAX.RSV = 1. MSBit must be 1 */
  61         ifh_encode_bitfield(ifh_hdr, 1, VSTAX + 79,  1);
  62         /* VSTAX.INGR_DROP_MODE = Enable. Don't make head-of-line blocking */
  63         ifh_encode_bitfield(ifh_hdr, 1, VSTAX + 55,  1);
  64         /* MISC.CPU_MASK/DPORT = Destination port */
  65         ifh_encode_bitfield(ifh_hdr, portno,   29, 8);
  66         /* MISC.PIPELINE_PT */
  67         ifh_encode_bitfield(ifh_hdr, is_sparx5(sparx5) ? 16 : 17, 37, 5);
  68         /* MISC.PIPELINE_ACT */
  69         ifh_encode_bitfield(ifh_hdr, 1,        42, 3);
  70         /* FWD.SRC_PORT = CPU */
  71         ifh_encode_bitfield(ifh_hdr, sparx5_get_pgid(sparx5, SPX5_PORT_CPU_0),
  72                             46, is_sparx5(sparx5) ? 7 : 6);
  73         /* FWD.SFLOW_ID (disable SFlow sampling) */
  74         ifh_encode_bitfield(ifh_hdr, 124,      is_sparx5(sparx5) ? 57 : 56, 7);
  75         /* FWD.UPDATE_FCS = Enable. Enforce update of FCS. */
  76         ifh_encode_bitfield(ifh_hdr, 1,        is_sparx5(sparx5) ? 67 : 66, 1);
  77 }
  78
  79 void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op)
  80 {
  81         ifh_encode_bitfield(ifh_hdr, rew_op, VSTAX + 32,  10);
  82 }
  83
  84 void sparx5_set_port_ifh_pdu_type(struct sparx5 *sparx5, void *ifh_hdr,
  85                                   u32 pdu_type)
  86 {
  87         ifh_encode_bitfield(ifh_hdr, pdu_type, is_sparx5(sparx5) ? 191 : 190,
  88                             4);
  89 }
  90
  91 void sparx5_set_port_ifh_pdu_w16_offset(struct sparx5 *sparx5, void *ifh_hdr,
  92                                         u32 pdu_w16_offset)
  93 {
  94         ifh_encode_bitfield(ifh_hdr, pdu_w16_offset,
  95                             is_sparx5(sparx5) ? 195 : 194, 6);
  96 }
  97
  98 void sparx5_set_port_ifh_timestamp(struct sparx5 *sparx5, void *ifh_hdr,
  99                                    u64 timestamp)
 100 {
 101         ifh_encode_bitfield(ifh_hdr, timestamp, 232,
 102                             is_sparx5(sparx5) ? 40 : 38);
 103 }
 104
 105 static int sparx5_port_open(struct net_device *ndev)
 106 {
 107         struct sparx5_port *port = netdev_priv(ndev);
 108         int err = 0;
 109
 110         sparx5_port_enable(port, true);
 111         err = phylink_of_phy_connect(port->phylink, port->of_node, 0);
 112         if (err) {
 113                 netdev_err(ndev, "Could not attach to PHY\n");
 114                 goto err_connect;
 115         }
 116
 117         phylink_start(port->phylink);
 118
 119         if (!ndev->phydev) {
 120                 /* power up serdes */
 121                 port->conf.power_down = false;
 122                 if (port->conf.serdes_reset)
 123                         err = sparx5_serdes_set(port->sparx5, port, &port->conf);
 124                 else
 125                         err = phy_power_on(port->serdes);
 126                 if (err) {
 127                         netdev_err(ndev, "%s failed\n", __func__);
 128                         goto out_power;
 129                 }
 130         }
 131
 132         return 0;
 133
 134 out_power:
 135         phylink_stop(port->phylink);
 136         phylink_disconnect_phy(port->phylink);
 137 err_connect:
 138         sparx5_port_enable(port, false);
 139
 140         return err;
 141 }
 142
 143 static int sparx5_port_stop(struct net_device *ndev)
 144 {
 145         struct sparx5_port *port = netdev_priv(ndev);
 146         int err = 0;
 147
 148         sparx5_port_enable(port, false);
 149         phylink_stop(port->phylink);
 150         phylink_disconnect_phy(port->phylink);
 151
 152         if (!ndev->phydev) {
 153                 /* power down serdes */
 154                 port->conf.power_down = true;
 155                 if (port->conf.serdes_reset)
 156                         err = sparx5_serdes_set(port->sparx5, port, &port->conf);
 157                 else
 158                         err = phy_power_off(port->serdes);
 159                 if (err)
 160                         netdev_err(ndev, "%s failed\n", __func__);
 161         }
 162         return 0;
 163 }
 164
 165 static void sparx5_set_rx_mode(struct net_device *dev)
 166 {
 167         struct sparx5_port *port = netdev_priv(dev);
 168         struct sparx5 *sparx5 = port->sparx5;
 169
 170         if (!test_bit(port->portno, sparx5->bridge_mask))
 171                 __dev_mc_sync(dev, sparx5_mc_sync, sparx5_mc_unsync);
 172 }
 173
 174 static int sparx5_port_get_phys_port_name(struct net_device *dev,
 175                                           char *buf, size_t len)
 176 {
 177         struct sparx5_port *port = netdev_priv(dev);
 178         int ret;
 179
 180         ret = snprintf(buf, len, "p%d", port->portno);
 181         if (ret >= len)
 182                 return -EINVAL;
 183
 184         return 0;
 185 }
 186
 187 static int sparx5_set_mac_address(struct net_device *dev, void *p)
 188 {
 189         struct sparx5_port *port = netdev_priv(dev);
 190         struct sparx5 *sparx5 = port->sparx5;
 191         const struct sockaddr *addr = p;
 192
 193         if (!is_valid_ether_addr(addr->sa_data))
 194                 return -EADDRNOTAVAIL;
 195
 196         /* Remove current */
 197         sparx5_mact_forget(sparx5, dev->dev_addr,  port->pvid);
 198
 199         /* Add new */
 200         sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU),
 201                           addr->sa_data, port->pvid);
 202
 203         /* Record the address */
 204         eth_hw_addr_set(dev, addr->sa_data);
 205
 206         return 0;
 207 }
 208
 209 static int sparx5_get_port_parent_id(struct net_device *dev,
 210                                      struct netdev_phys_item_id *ppid)
 211 {
 212         struct sparx5_port *sparx5_port = netdev_priv(dev);
 213         struct sparx5 *sparx5 = sparx5_port->sparx5;
 214
 215         ppid->id_len = sizeof(sparx5->base_mac);
 216         memcpy(&ppid->id, &sparx5->base_mac, ppid->id_len);
 217
 218         return 0;
 219 }
 220
 221 static int sparx5_port_hwtstamp_get(struct net_device *dev,
 222                                     struct kernel_hwtstamp_config *cfg)
 223 {
 224         struct sparx5_port *sparx5_port = netdev_priv(dev);
 225         struct sparx5 *sparx5 = sparx5_port->sparx5;
 226
 227         if (!sparx5->ptp)
 228                 return -EOPNOTSUPP;
 229
 230         sparx5_ptp_hwtstamp_get(sparx5_port, cfg);
 231
 232         return 0;
 233 }
 234
 235 static int sparx5_port_hwtstamp_set(struct net_device *dev,
 236                                     struct kernel_hwtstamp_config *cfg,
 237                                     struct netlink_ext_ack *extack)
 238 {
 239         struct sparx5_port *sparx5_port = netdev_priv(dev);
 240         struct sparx5 *sparx5 = sparx5_port->sparx5;
 241
 242         if (!sparx5->ptp)
 243                 return -EOPNOTSUPP;
 244
 245         return sparx5_ptp_hwtstamp_set(sparx5_port, cfg, extack);
 246 }
 247
 248 static const struct net_device_ops sparx5_port_netdev_ops = {
 249         .ndo_open               = sparx5_port_open,
 250         .ndo_stop               = sparx5_port_stop,
 251         .ndo_start_xmit         = sparx5_port_xmit_impl,
 252         .ndo_set_rx_mode        = sparx5_set_rx_mode,
 253         .ndo_get_phys_port_name = sparx5_port_get_phys_port_name,
 254         .ndo_set_mac_address    = sparx5_set_mac_address,
 255         .ndo_validate_addr      = eth_validate_addr,
 256         .ndo_get_stats64        = sparx5_get_stats64,
 257         .ndo_get_port_parent_id = sparx5_get_port_parent_id,
 258         .ndo_eth_ioctl          = phy_do_ioctl,
 259         .ndo_setup_tc           = sparx5_port_setup_tc,
 260         .ndo_hwtstamp_get       = sparx5_port_hwtstamp_get,
 261         .ndo_hwtstamp_set       = sparx5_port_hwtstamp_set,
 262 };
 263
 264 bool sparx5_netdevice_check(const struct net_device *dev)
 265 {
 266         return dev && (dev->netdev_ops == &sparx5_port_netdev_ops);
 267 }
 268
 269 struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno)
 270 {
 271         struct sparx5_port *spx5_port;
 272         struct net_device *ndev;
 273
 274         ndev = devm_alloc_etherdev_mqs(sparx5->dev, sizeof(struct sparx5_port),
 275                                        SPX5_PRIOS, 1);
 276         if (!ndev)
 277                 return ERR_PTR(-ENOMEM);
 278
 279         ndev->hw_features |= NETIF_F_HW_TC;
 280         ndev->features |= NETIF_F_HW_TC;
 281
 282         SET_NETDEV_DEV(ndev, sparx5->dev);
 283         spx5_port = netdev_priv(ndev);
 284         spx5_port->ndev = ndev;
 285         spx5_port->sparx5 = sparx5;
 286         spx5_port->portno = portno;
 287
 288         ndev->netdev_ops = &sparx5_port_netdev_ops;
 289         ndev->ethtool_ops = &sparx5_ethtool_ops;
 290
 291         eth_hw_addr_gen(ndev, sparx5->base_mac, portno + 1);
 292
 293         return ndev;
 294 }
 295
 296 int sparx5_register_netdevs(struct sparx5 *sparx5)
 297 {
 298         int portno;
 299         int err;
 300
 301         for (portno = 0; portno < sparx5->data->consts->n_ports; portno++)
 302                 if (sparx5->ports[portno]) {
 303                         err = register_netdev(sparx5->ports[portno]->ndev);
 304                         if (err) {
 305                                 dev_err(sparx5->dev,
 306                                         "port: %02u: netdev registration failed\n",
 307                                         portno);
 308                                 return err;
 309                         }
 310                         sparx5_port_inj_timer_setup(sparx5->ports[portno]);
 311                 }
 312         return 0;
 313 }
 314
 315 void sparx5_destroy_netdevs(struct sparx5 *sparx5)
 316 {
 317         struct sparx5_port *port;
 318         int portno;
 319
 320         for (portno = 0; portno < sparx5->data->consts->n_ports; portno++) {
 321                 port = sparx5->ports[portno];
 322                 if (port && port->phylink) {
 323                         /* Disconnect the phy */
 324                         rtnl_lock();
 325                         sparx5_port_stop(port->ndev);
 326                         phylink_disconnect_phy(port->phylink);
 327                         rtnl_unlock();
 328                         phylink_destroy(port->phylink);
 329                         port->phylink = NULL;
 330                 }
 331         }
 332 }
 333
 334 void sparx5_unregister_netdevs(struct sparx5 *sparx5)
 335 {
 336         int portno;
 337
 338         for (portno = 0; portno < sparx5->data->consts->n_ports; portno++)
 339                 if (sparx5->ports[portno])
 340                         unregister_netdev(sparx5->ports[portno]->ndev);
 341 }