1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
4 * Copyright (c) 2024 Microchip Technology Inc.
7 /* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200.
8 * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b
11 #include "sparx5_regs.h"
13 const unsigned int sparx5_tsize
[TSIZE_LAST
] = {
21 const unsigned int sparx5_raddr
[RADDR_LAST
] = {
22 [RA_CPU_PROC_CTRL
] = 176,
23 [RA_GCB_SOFT_RST
] = 8,
24 [RA_GCB_HW_SGPIO_TO_SD_MAP_CFG
] = 24,
27 const unsigned int sparx5_rcnt
[RCNT_LAST
] = {
28 [RC_ANA_AC_OWN_UPSID
] = 3,
29 [RC_ANA_ACL_VCAP_S2_CFG
] = 70,
30 [RC_ANA_ACL_OWN_UPSID
] = 3,
31 [RC_ANA_CL_OWN_UPSID
] = 3,
32 [RC_ANA_L2_OWN_UPSID
] = 3,
33 [RC_ASM_PORT_CFG
] = 67,
34 [RC_DSM_BUF_CFG
] = 67,
35 [RC_DSM_DEV_TX_STOP_WM_CFG
] = 67,
36 [RC_DSM_RX_PAUSE_CFG
] = 67,
37 [RC_DSM_MAC_CFG
] = 67,
38 [RC_DSM_MAC_ADDR_BASE_HIGH_CFG
] = 65,
39 [RC_DSM_MAC_ADDR_BASE_LOW_CFG
] = 65,
40 [RC_DSM_TAXI_CAL_CFG
] = 9,
41 [RC_GCB_HW_SGPIO_TO_SD_MAP_CFG
] = 65,
42 [RC_HSCH_PORT_MODE
] = 70,
43 [RC_QFWD_SWITCH_PORT_MODE
] = 70,
44 [RC_QSYS_PAUSE_CFG
] = 70,
46 [RC_QSYS_FWD_PRESSURE
] = 70,
47 [RC_QSYS_CAL_AUTO
] = 7,
48 [RC_REW_OWN_UPSID
] = 3,
49 [RC_REW_RTAG_ETAG_CTRL
] = 70,
52 const unsigned int sparx5_gaddr
[GADDR_LAST
] = {
53 [GA_ANA_AC_RAM_CTRL
] = 839108,
54 [GA_ANA_AC_PS_COMMON
] = 894472,
55 [GA_ANA_AC_MIRROR_PROBE
] = 893696,
56 [GA_ANA_AC_SRC
] = 849920,
57 [GA_ANA_AC_PGID
] = 786432,
58 [GA_ANA_AC_TSN_SF
] = 839136,
59 [GA_ANA_AC_TSN_SF_CFG
] = 839680,
60 [GA_ANA_AC_TSN_SF_STATUS
] = 839072,
61 [GA_ANA_AC_SG_ACCESS
] = 839140,
62 [GA_ANA_AC_SG_CONFIG
] = 851584,
63 [GA_ANA_AC_SG_STATUS
] = 839088,
64 [GA_ANA_AC_SG_STATUS_STICKY
] = 839152,
65 [GA_ANA_AC_STAT_GLOBAL_CFG_PORT
] = 851552,
66 [GA_ANA_AC_STAT_CNT_CFG_PORT
] = 843776,
67 [GA_ANA_AC_STAT_GLOBAL_CFG_ACL
] = 893792,
68 [GA_ANA_ACL_COMMON
] = 32768,
69 [GA_ANA_ACL_KEY_SEL
] = 34200,
70 [GA_ANA_ACL_CNT_B
] = 16384,
71 [GA_ANA_ACL_STICKY
] = 36408,
72 [GA_ANA_AC_POL_POL_ALL_CFG
] = 75968,
73 [GA_ANA_AC_POL_COMMON_BDLB
] = 79048,
74 [GA_ANA_AC_POL_COMMON_BUM_SLB
] = 79056,
75 [GA_ANA_AC_SDLB_LBGRP_TBL
] = 295468,
76 [GA_ANA_CL_PORT
] = 131072,
77 [GA_ANA_CL_COMMON
] = 166912,
78 [GA_ANA_L2_COMMON
] = 566024,
79 [GA_ANA_L3_COMMON
] = 493632,
80 [GA_ANA_L3_VLAN_ARP_L3MC_STICKY
] = 491460,
82 [GA_ASM_PFC_TIMER_CFG
] = 34716,
83 [GA_ASM_LBK_WM_CFG
] = 34744,
84 [GA_ASM_LBK_MISC_CFG
] = 34756,
85 [GA_ASM_RAM_CTRL
] = 34832,
86 [GA_EACL_ES2_KEY_SELECT_PROFILE
] = 149504,
87 [GA_EACL_CNT_TBL
] = 122880,
88 [GA_EACL_POL_CFG
] = 150608,
89 [GA_EACL_ES2_STICKY
] = 118696,
90 [GA_EACL_RAM_CTRL
] = 118736,
91 [GA_GCB_SIO_CTRL
] = 876,
92 [GA_HSCH_HSCH_DWRR
] = 162816,
93 [GA_HSCH_HSCH_MISC
] = 163104,
94 [GA_HSCH_HSCH_LEAK_LISTS
] = 161664,
95 [GA_HSCH_SYSTEM
] = 184000,
96 [GA_HSCH_MMGT
] = 162368,
97 [GA_HSCH_TAS_CONFIG
] = 162384,
98 [GA_PTP_PTP_CFG
] = 320,
99 [GA_PTP_PTP_TOD_DOMAINS
] = 336,
100 [GA_PTP_PHASE_DETECTOR_CTRL
] = 420,
101 [GA_QSYS_CALCFG
] = 2304,
102 [GA_QSYS_RAM_CTRL
] = 2344,
103 [GA_REW_COMMON
] = 387264,
104 [GA_REW_PORT
] = 360448,
105 [GA_REW_VOE_PORT_LM_CNT
] = 393216,
106 [GA_REW_RAM_CTRL
] = 378696,
107 [GA_VOP_RAM_CTRL
] = 279176,
108 [GA_XQS_SYSTEM
] = 6768,
109 [GA_XQS_QLIMIT_SHR
] = 7936,
112 const unsigned int sparx5_gcnt
[GCNT_LAST
] = {
113 [GC_ANA_AC_SRC
] = 102,
114 [GC_ANA_AC_PGID
] = 3290,
115 [GC_ANA_AC_TSN_SF_CFG
] = 1024,
116 [GC_ANA_AC_STAT_CNT_CFG_PORT
] = 70,
117 [GC_ANA_ACL_KEY_SEL
] = 134,
118 [GC_ANA_ACL_CNT_A
] = 4096,
119 [GC_ANA_ACL_CNT_B
] = 4096,
120 [GC_ANA_AC_SDLB_LBGRP_TBL
] = 10,
121 [GC_ANA_AC_SDLB_LBSET_TBL
] = 4616,
122 [GC_ANA_CL_PORT
] = 70,
123 [GC_ANA_L2_ISDX_LIMIT
] = 1536,
124 [GC_ANA_L2_ISDX
] = 4096,
125 [GC_ANA_L3_VLAN
] = 5120,
126 [GC_ASM_DEV_STATISTICS
] = 65,
127 [GC_EACL_ES2_KEY_SELECT_PROFILE
] = 138,
128 [GC_EACL_CNT_TBL
] = 2048,
129 [GC_GCB_SIO_CTRL
] = 3,
130 [GC_HSCH_HSCH_CFG
] = 5040,
131 [GC_HSCH_HSCH_DWRR
] = 72,
132 [GC_PTP_PTP_PINS
] = 5,
133 [GC_PTP_PHASE_DETECTOR_CTRL
] = 5,
135 [GC_REW_VOE_PORT_LM_CNT
] = 520,
138 const unsigned int sparx5_gsize
[GSIZE_LAST
] = {
139 [GW_ANA_AC_SRC
] = 16,
140 [GW_ANA_L2_COMMON
] = 700,
142 [GW_CPU_CPU_REGS
] = 204,
143 [GW_DEV2G5_PHASE_DETECTOR_CTRL
] = 8,
144 [GW_FDMA_FDMA
] = 428,
145 [GW_GCB_CHIP_REGS
] = 424,
146 [GW_HSCH_TAS_CONFIG
] = 12,
147 [GW_PTP_PHASE_DETECTOR_CTRL
] = 8,
148 [GW_QSYS_PAUSE_CFG
] = 1128,
151 const unsigned int sparx5_fpos
[FPOS_LAST
] = {
152 [FP_CPU_PROC_CTRL_AARCH64_MODE_ENA
] = 12,
153 [FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS
] = 11,
154 [FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS
] = 10,
155 [FP_CPU_PROC_CTRL_BE_EXCEP_MODE
] = 9,
156 [FP_CPU_PROC_CTRL_VINITHI
] = 8,
157 [FP_CPU_PROC_CTRL_CFGTE
] = 7,
158 [FP_CPU_PROC_CTRL_CP15S_DISABLE
] = 6,
159 [FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE
] = 5,
160 [FP_CPU_PROC_CTRL_L2_FLUSH_REQ
] = 1,
161 [FP_DEV2G5_PHAD_CTRL_PHAD_ENA
] = 7,
162 [FP_DEV2G5_PHAD_CTRL_PHAD_FAILED
] = 6,
163 [FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE
] = 7,
164 [FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY
] = 6,
165 [FP_FDMA_CH_CFG_CH_INJ_PORT
] = 5,
166 [FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION
] = 26,
167 [FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC
] = 24,
168 [FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL
] = 23,
169 [FP_PTP_PHAD_CTRL_PHAD_ENA
] = 7,
170 [FP_PTP_PHAD_CTRL_PHAD_FAILED
] = 6,
173 const unsigned int sparx5_fsize
[FSIZE_LAST
] = {
174 [FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK
] = 32,
175 [FW_ANA_AC_SRC_CFG_PORT_MASK
] = 32,
176 [FW_ANA_AC_PGID_CFG_PORT_MASK
] = 32,
177 [FW_ANA_AC_TSN_SF_PORT_NUM
] = 9,
178 [FW_ANA_AC_TSN_SF_CFG_TSN_SGID
] = 10,
179 [FW_ANA_AC_TSN_SF_STATUS_TSN_SFID
] = 10,
180 [FW_ANA_AC_SG_ACCESS_CTRL_SGID
] = 10,
181 [FW_ANA_AC_PORT_SGE_CFG_MASK
] = 16,
182 [FW_ANA_AC_SDLB_XLB_START_LBSET_START
] = 13,
183 [FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT
] = 5,
184 [FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT
] = 13,
185 [FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT
] = 13,
186 [FW_ANA_AC_SDLB_XLB_NEXT_LBGRP
] = 4,
187 [FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR
] = 13,
188 [FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA
] = 32,
189 [FW_ANA_L2_DLB_CFG_DLB_IDX
] = 13,
190 [FW_ANA_L2_TSN_CFG_TSN_SFID
] = 10,
191 [FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK
] = 32,
192 [FW_FDMA_CH_CFG_CH_DCB_DB_CNT
] = 4,
193 [FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL
] = 9,
194 [FW_HSCH_SE_CFG_SE_DWRR_CNT
] = 7,
195 [FW_HSCH_SE_CONNECT_SE_LEAK_LINK
] = 16,
196 [FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT
] = 7,
197 [FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX
] = 13,
198 [FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST
] = 16,
199 [FW_HSCH_FLUSH_CTRL_FLUSH_PORT
] = 7,
200 [FW_HSCH_FLUSH_CTRL_FLUSH_HIER
] = 16,
201 [FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW
] = 14,
202 [FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX
] = 11,
203 [FW_LRN_AUTOAGE_CFG_2_NEXT_ROW
] = 14,
204 [FW_PTP_PTP_PIN_INTR_INTR_PTP
] = 5,
205 [FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA
] = 5,
206 [FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT
] = 5,
207 [FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT
] = 2,
208 [FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL
] = 7,
209 [FW_QRES_RES_CFG_WM_HIGH
] = 12,
210 [FW_QRES_RES_STAT_MAXUSE
] = 21,
211 [FW_QRES_RES_STAT_CUR_INUSE
] = 21,
212 [FW_QSYS_PAUSE_CFG_PAUSE_START
] = 12,
213 [FW_QSYS_PAUSE_CFG_PAUSE_STOP
] = 12,
214 [FW_QSYS_ATOP_ATOP
] = 12,
215 [FW_QSYS_ATOP_TOT_CFG_ATOP_TOT
] = 12,
216 [FW_REW_RTAG_ETAG_CTRL_IPE_TBL
] = 7,
217 [FW_XQS_STAT_CFG_STAT_VIEW
] = 13,
218 [FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP
] = 15,
219 [FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP
] = 15,
220 [FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP
] = 15,
221 [FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM
] = 15,
