1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Renesas Ethernet Switch device driver
4 * Copyright (C) 2022 Renesas Electronics Corporation
10 #include <linux/platform_device.h>
11 #include "rcar_gen4_ptp.h"
13 #define RSWITCH_MAX_NUM_QUEUES 128
15 #define RSWITCH_NUM_PORTS 3
16 #define rswitch_for_each_enabled_port(priv, i) \
17 for (i = 0; i < RSWITCH_NUM_PORTS; i++) \
18 if (priv->rdev[i]->disabled) \
22 #define rswitch_for_each_enabled_port_continue_reverse(priv, i) \
24 if (priv->rdev[i]->disabled) \
28 #define TX_RING_SIZE 1024
29 #define RX_RING_SIZE 4096
30 #define TS_RING_SIZE (TX_RING_SIZE * RSWITCH_NUM_PORTS)
32 #define RSWITCH_MAX_MTU 9600
33 #define RSWITCH_HEADROOM (NET_SKB_PAD + NET_IP_ALIGN)
34 #define RSWITCH_DESC_BUF_SIZE 2048
35 #define RSWITCH_TAILROOM SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
36 #define RSWITCH_ALIGN 128
37 #define RSWITCH_BUF_SIZE (RSWITCH_HEADROOM + RSWITCH_DESC_BUF_SIZE + \
38 RSWITCH_TAILROOM + RSWITCH_ALIGN)
39 #define RSWITCH_MAP_BUF_SIZE (RSWITCH_BUF_SIZE - RSWITCH_HEADROOM)
40 #define RSWITCH_MAX_CTAG_PCP 7
42 #define RSWITCH_TIMEOUT_US 100000
44 #define RSWITCH_TOP_OFFSET 0x00008000
45 #define RSWITCH_COMA_OFFSET 0x00009000
46 #define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */
47 #define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */
48 #define RSWITCH_GWCA0_OFFSET 0x00010000
49 #define RSWITCH_GWCA1_OFFSET 0x00012000
51 /* TODO: hardcoded ETHA/GWCA settings for now */
52 #define GWCA_IRQ_RESOURCE_NAME "gwca0_rxtx%d"
53 #define GWCA_IRQ_NAME "rswitch: gwca0_rxtx%d"
54 #define GWCA_NUM_IRQS 8
56 #define AGENT_INDEX_GWCA 3
57 #define GWCA_IPV_NUM 0
58 #define GWRO RSWITCH_GWCA0_OFFSET
60 #define GWCA_TS_IRQ_RESOURCE_NAME "gwca0_rxts0"
61 #define GWCA_TS_IRQ_NAME "rswitch: gwca0_rxts0"
62 #define GWCA_TS_IRQ_BIT BIT(0)
65 #define TPRO RSWITCH_TOP_OFFSET
66 #define CARO RSWITCH_COMA_OFFSET
71 FWTTC0
= FWRO
+ 0x0010,
72 FWTTC1
= FWRO
+ 0x0014,
73 FWLBMC
= FWRO
+ 0x0018,
74 FWCEPTC
= FWRO
+ 0x0020,
75 FWCEPRC0
= FWRO
+ 0x0024,
76 FWCEPRC1
= FWRO
+ 0x0028,
77 FWCEPRC2
= FWRO
+ 0x002c,
78 FWCLPTC
= FWRO
+ 0x0030,
79 FWCLPRC
= FWRO
+ 0x0034,
80 FWCMPTC
= FWRO
+ 0x0040,
81 FWEMPTC
= FWRO
+ 0x0044,
82 FWSDMPTC
= FWRO
+ 0x0050,
83 FWSDMPVC
= FWRO
+ 0x0054,
84 FWLBWMC0
= FWRO
+ 0x0080,
85 FWPC00
= FWRO
+ 0x0100,
86 FWPC10
= FWRO
+ 0x0104,
87 FWPC20
= FWRO
+ 0x0108,
88 FWCTGC00
= FWRO
+ 0x0400,
89 FWCTGC10
= FWRO
+ 0x0404,
90 FWCTTC00
= FWRO
+ 0x0408,
91 FWCTTC10
= FWRO
+ 0x040c,
92 FWCTTC200
= FWRO
+ 0x0410,
93 FWCTSC00
= FWRO
+ 0x0420,
94 FWCTSC10
= FWRO
+ 0x0424,
95 FWCTSC20
= FWRO
+ 0x0428,
96 FWCTSC30
= FWRO
+ 0x042c,
97 FWCTSC40
= FWRO
+ 0x0430,
98 FWTWBFC0
= FWRO
+ 0x1000,
99 FWTWBFVC0
= FWRO
+ 0x1004,
100 FWTHBFC0
= FWRO
+ 0x1400,
101 FWTHBFV0C0
= FWRO
+ 0x1404,
102 FWTHBFV1C0
= FWRO
+ 0x1408,
103 FWFOBFC0
= FWRO
+ 0x1800,
104 FWFOBFV0C0
= FWRO
+ 0x1804,
105 FWFOBFV1C0
= FWRO
+ 0x1808,
106 FWRFC0
= FWRO
+ 0x1c00,
107 FWRFVC0
= FWRO
+ 0x1c04,
108 FWCFC0
= FWRO
+ 0x2000,
109 FWCFMC00
= FWRO
+ 0x2004,
110 FWIP4SC
= FWRO
+ 0x4008,
111 FWIP6SC
= FWRO
+ 0x4018,
112 FWIP6OC
= FWRO
+ 0x401c,
113 FWL2SC
= FWRO
+ 0x4020,
114 FWSFHEC
= FWRO
+ 0x4030,
115 FWSHCR0
= FWRO
+ 0x4040,
116 FWSHCR1
= FWRO
+ 0x4044,
117 FWSHCR2
= FWRO
+ 0x4048,
118 FWSHCR3
= FWRO
+ 0x404c,
119 FWSHCR4
= FWRO
+ 0x4050,
120 FWSHCR5
= FWRO
+ 0x4054,
121 FWSHCR6
= FWRO
+ 0x4058,
122 FWSHCR7
= FWRO
+ 0x405c,
123 FWSHCR8
= FWRO
+ 0x4060,
124 FWSHCR9
= FWRO
+ 0x4064,
125 FWSHCR10
= FWRO
+ 0x4068,
126 FWSHCR11
= FWRO
+ 0x406c,
127 FWSHCR12
= FWRO
+ 0x4070,
128 FWSHCR13
= FWRO
+ 0x4074,
129 FWSHCRR
= FWRO
+ 0x4078,
130 FWLTHHEC
= FWRO
+ 0x4090,
131 FWLTHHC
= FWRO
+ 0x4094,
132 FWLTHTL0
= FWRO
+ 0x40a0,
133 FWLTHTL1
= FWRO
+ 0x40a4,
134 FWLTHTL2
= FWRO
+ 0x40a8,
135 FWLTHTL3
= FWRO
+ 0x40ac,
136 FWLTHTL4
= FWRO
+ 0x40b0,
137 FWLTHTL5
= FWRO
+ 0x40b4,
138 FWLTHTL6
= FWRO
+ 0x40b8,
139 FWLTHTL7
= FWRO
+ 0x40bc,
140 FWLTHTL80
= FWRO
+ 0x40c0,
141 FWLTHTL9
= FWRO
+ 0x40d0,
142 FWLTHTLR
= FWRO
+ 0x40d4,
143 FWLTHTIM
= FWRO
+ 0x40e0,
144 FWLTHTEM
= FWRO
+ 0x40e4,
145 FWLTHTS0
= FWRO
+ 0x4100,
146 FWLTHTS1
= FWRO
+ 0x4104,
147 FWLTHTS2
= FWRO
+ 0x4108,
148 FWLTHTS3
= FWRO
+ 0x410c,
149 FWLTHTS4
= FWRO
+ 0x4110,
150 FWLTHTSR0
= FWRO
+ 0x4120,
151 FWLTHTSR1
= FWRO
+ 0x4124,
152 FWLTHTSR2
= FWRO
+ 0x4128,
153 FWLTHTSR3
= FWRO
+ 0x412c,
154 FWLTHTSR40
= FWRO
+ 0x4130,
155 FWLTHTSR5
= FWRO
+ 0x4140,
156 FWLTHTR
= FWRO
+ 0x4150,
157 FWLTHTRR0
= FWRO
+ 0x4154,
158 FWLTHTRR1
= FWRO
+ 0x4158,
159 FWLTHTRR2
= FWRO
+ 0x415c,
160 FWLTHTRR3
= FWRO
+ 0x4160,
161 FWLTHTRR4
= FWRO
+ 0x4164,
162 FWLTHTRR5
= FWRO
+ 0x4168,
163 FWLTHTRR6
= FWRO
+ 0x416c,
164 FWLTHTRR7
= FWRO
+ 0x4170,
165 FWLTHTRR8
= FWRO
+ 0x4174,
166 FWLTHTRR9
= FWRO
+ 0x4180,
167 FWLTHTRR10
= FWRO
+ 0x4190,
168 FWIPHEC
= FWRO
+ 0x4214,
169 FWIPHC
= FWRO
+ 0x4218,
170 FWIPTL0
= FWRO
+ 0x4220,
171 FWIPTL1
= FWRO
+ 0x4224,
172 FWIPTL2
= FWRO
+ 0x4228,
173 FWIPTL3
= FWRO
+ 0x422c,
174 FWIPTL4
= FWRO
+ 0x4230,
175 FWIPTL5
= FWRO
+ 0x4234,
176 FWIPTL6
= FWRO
+ 0x4238,
177 FWIPTL7
= FWRO
+ 0x4240,
178 FWIPTL8
= FWRO
+ 0x4250,
179 FWIPTLR
= FWRO
+ 0x4254,
180 FWIPTIM
= FWRO
+ 0x4260,
181 FWIPTEM
= FWRO
+ 0x4264,
182 FWIPTS0
= FWRO
+ 0x4270,
183 FWIPTS1
= FWRO
+ 0x4274,
184 FWIPTS2
= FWRO
+ 0x4278,
185 FWIPTS3
= FWRO
+ 0x427c,
186 FWIPTS4
= FWRO
+ 0x4280,
187 FWIPTSR0
= FWRO
+ 0x4284,
188 FWIPTSR1
= FWRO
+ 0x4288,
189 FWIPTSR2
= FWRO
+ 0x428c,
190 FWIPTSR3
= FWRO
+ 0x4290,
191 FWIPTSR4
= FWRO
+ 0x42a0,
192 FWIPTR
= FWRO
+ 0x42b0,
193 FWIPTRR0
= FWRO
+ 0x42b4,
194 FWIPTRR1
= FWRO
+ 0x42b8,
195 FWIPTRR2
= FWRO
+ 0x42bc,
196 FWIPTRR3
= FWRO
+ 0x42c0,
197 FWIPTRR4
= FWRO
+ 0x42c4,
198 FWIPTRR5
= FWRO
+ 0x42c8,
199 FWIPTRR6
= FWRO
+ 0x42cc,
200 FWIPTRR7
= FWRO
+ 0x42d0,
201 FWIPTRR8
= FWRO
+ 0x42e0,
202 FWIPTRR9
= FWRO
+ 0x42f0,
203 FWIPHLEC
= FWRO
+ 0x4300,
204 FWIPAGUSPC
= FWRO
+ 0x4500,
205 FWIPAGC
= FWRO
+ 0x4504,
206 FWIPAGM0
= FWRO
+ 0x4510,
207 FWIPAGM1
= FWRO
+ 0x4514,
208 FWIPAGM2
= FWRO
+ 0x4518,
209 FWIPAGM3
= FWRO
+ 0x451c,
210 FWIPAGM4
= FWRO
+ 0x4520,
211 FWMACHEC
= FWRO
+ 0x4620,
212 FWMACHC
= FWRO
+ 0x4624,
213 FWMACTL0
= FWRO
+ 0x4630,
214 FWMACTL1
= FWRO
+ 0x4634,
215 FWMACTL2
= FWRO
+ 0x4638,
216 FWMACTL3
= FWRO
+ 0x463c,
217 FWMACTL4
= FWRO
+ 0x4640,
218 FWMACTL5
= FWRO
+ 0x4650,
219 FWMACTLR
= FWRO
+ 0x4654,
220 FWMACTIM
= FWRO
+ 0x4660,
221 FWMACTEM
= FWRO
+ 0x4664,
222 FWMACTS0
= FWRO
+ 0x4670,
223 FWMACTS1
= FWRO
+ 0x4674,
224 FWMACTSR0
= FWRO
+ 0x4678,
225 FWMACTSR1
= FWRO
+ 0x467c,
226 FWMACTSR2
= FWRO
+ 0x4680,
227 FWMACTSR3
= FWRO
+ 0x4690,
228 FWMACTR
= FWRO
+ 0x46a0,
229 FWMACTRR0
= FWRO
+ 0x46a4,
230 FWMACTRR1
= FWRO
+ 0x46a8,
231 FWMACTRR2
= FWRO
+ 0x46ac,
232 FWMACTRR3
= FWRO
+ 0x46b0,
233 FWMACTRR4
= FWRO
+ 0x46b4,
234 FWMACTRR5
= FWRO
+ 0x46c0,
235 FWMACTRR6
= FWRO
+ 0x46d0,
236 FWMACHLEC
= FWRO
+ 0x4700,
237 FWMACAGUSPC
= FWRO
+ 0x4880,
238 FWMACAGC
= FWRO
+ 0x4884,
239 FWMACAGM0
= FWRO
+ 0x4888,
240 FWMACAGM1
= FWRO
+ 0x488c,
241 FWVLANTEC
= FWRO
+ 0x4900,
242 FWVLANTL0
= FWRO
+ 0x4910,
243 FWVLANTL1
= FWRO
+ 0x4914,
244 FWVLANTL2
= FWRO
+ 0x4918,
245 FWVLANTL3
= FWRO
+ 0x4920,
246 FWVLANTL4
= FWRO
+ 0x4930,
247 FWVLANTLR
= FWRO
+ 0x4934,
248 FWVLANTIM
= FWRO
+ 0x4940,
249 FWVLANTEM
= FWRO
+ 0x4944,
250 FWVLANTS
= FWRO
+ 0x4950,
251 FWVLANTSR0
= FWRO
+ 0x4954,
252 FWVLANTSR1
= FWRO
+ 0x4958,
253 FWVLANTSR2
= FWRO
+ 0x4960,
254 FWVLANTSR3
= FWRO
+ 0x4970,
255 FWPBFC0
= FWRO
+ 0x4a00,
256 FWPBFCSDC00
= FWRO
+ 0x4a04,
257 FWL23URL0
= FWRO
+ 0x4e00,
258 FWL23URL1
= FWRO
+ 0x4e04,
259 FWL23URL2
= FWRO
+ 0x4e08,
260 FWL23URL3
= FWRO
+ 0x4e0c,
261 FWL23URLR
= FWRO
+ 0x4e10,
262 FWL23UTIM
= FWRO
+ 0x4e20,
263 FWL23URR
= FWRO
+ 0x4e30,
264 FWL23URRR0
= FWRO
+ 0x4e34,
265 FWL23URRR1
= FWRO
+ 0x4e38,
266 FWL23URRR2
= FWRO
+ 0x4e3c,
267 FWL23URRR3
= FWRO
+ 0x4e40,
268 FWL23URMC0
= FWRO
+ 0x4f00,
269 FWPMFGC0
= FWRO
+ 0x5000,
270 FWPGFC0
= FWRO
+ 0x5100,
271 FWPGFIGSC0
= FWRO
+ 0x5104,
272 FWPGFENC0
= FWRO
+ 0x5108,
273 FWPGFENM0
= FWRO
+ 0x510c,
274 FWPGFCSTC00
= FWRO
+ 0x5110,
275 FWPGFCSTC10
= FWRO
+ 0x5114,
276 FWPGFCSTM00
= FWRO
+ 0x5118,
277 FWPGFCSTM10
= FWRO
+ 0x511c,
278 FWPGFCTC0
= FWRO
+ 0x5120,
279 FWPGFCTM0
= FWRO
+ 0x5124,
280 FWPGFHCC0
= FWRO
+ 0x5128,
281 FWPGFSM0
= FWRO
+ 0x512c,
282 FWPGFGC0
= FWRO
+ 0x5130,
283 FWPGFGL0
= FWRO
+ 0x5500,
284 FWPGFGL1
= FWRO
+ 0x5504,
285 FWPGFGLR
= FWRO
+ 0x5518,
286 FWPGFGR
= FWRO
+ 0x5510,
287 FWPGFGRR0
= FWRO
+ 0x5514,
288 FWPGFGRR1
= FWRO
+ 0x5518,
289 FWPGFRIM
= FWRO
+ 0x5520,
290 FWPMTRFC0
= FWRO
+ 0x5600,
291 FWPMTRCBSC0
= FWRO
+ 0x5604,
292 FWPMTRC0RC0
= FWRO
+ 0x5608,
293 FWPMTREBSC0
= FWRO
+ 0x560c,
294 FWPMTREIRC0
= FWRO
+ 0x5610,
295 FWPMTRFM0
= FWRO
+ 0x5614,
296 FWFTL0
= FWRO
+ 0x6000,
297 FWFTL1
= FWRO
+ 0x6004,
298 FWFTLR
= FWRO
+ 0x6008,
299 FWFTOC
= FWRO
+ 0x6010,
300 FWFTOPC
= FWRO
+ 0x6014,
301 FWFTIM
= FWRO
+ 0x6020,
302 FWFTR
= FWRO
+ 0x6030,
303 FWFTRR0
= FWRO
+ 0x6034,
304 FWFTRR1
= FWRO
+ 0x6038,
305 FWFTRR2
= FWRO
+ 0x603c,
306 FWSEQNGC0
= FWRO
+ 0x6100,
307 FWSEQNGM0
= FWRO
+ 0x6104,
308 FWSEQNRC
= FWRO
+ 0x6200,
309 FWCTFDCN0
= FWRO
+ 0x6300,
310 FWLTHFDCN0
= FWRO
+ 0x6304,
311 FWIPFDCN0
= FWRO
+ 0x6308,
312 FWLTWFDCN0
= FWRO
+ 0x630c,
313 FWPBFDCN0
= FWRO
+ 0x6310,
314 FWMHLCN0
= FWRO
+ 0x6314,
315 FWIHLCN0
= FWRO
+ 0x6318,
316 FWICRDCN0
= FWRO
+ 0x6500,
317 FWWMRDCN0
= FWRO
+ 0x6504,
318 FWCTRDCN0
= FWRO
+ 0x6508,
319 FWLTHRDCN0
= FWRO
+ 0x650c,
320 FWIPRDCN0
= FWRO
+ 0x6510,
321 FWLTWRDCN0
= FWRO
+ 0x6514,
322 FWPBRDCN0
= FWRO
+ 0x6518,
323 FWPMFDCN0
= FWRO
+ 0x6700,
324 FWPGFDCN0
= FWRO
+ 0x6780,
325 FWPMGDCN0
= FWRO
+ 0x6800,
326 FWPMYDCN0
= FWRO
+ 0x6804,
327 FWPMRDCN0
= FWRO
+ 0x6808,
328 FWFRPPCN0
= FWRO
+ 0x6a00,
329 FWFRDPCN0
= FWRO
+ 0x6a04,
330 FWEIS00
= FWRO
+ 0x7900,
331 FWEIE00
= FWRO
+ 0x7904,
332 FWEID00
= FWRO
+ 0x7908,
333 FWEIS1
= FWRO
+ 0x7a00,
334 FWEIE1
= FWRO
+ 0x7a04,
335 FWEID1
= FWRO
+ 0x7a08,
336 FWEIS2
= FWRO
+ 0x7a10,
337 FWEIE2
= FWRO
+ 0x7a14,
338 FWEID2
= FWRO
+ 0x7a18,
339 FWEIS3
= FWRO
+ 0x7a20,
340 FWEIE3
= FWRO
+ 0x7a24,
341 FWEID3
= FWRO
+ 0x7a28,
342 FWEIS4
= FWRO
+ 0x7a30,
343 FWEIE4
= FWRO
+ 0x7a34,
344 FWEID4
= FWRO
+ 0x7a38,
345 FWEIS5
= FWRO
+ 0x7a40,
346 FWEIE5
= FWRO
+ 0x7a44,
347 FWEID5
= FWRO
+ 0x7a48,
348 FWEIS60
= FWRO
+ 0x7a50,
349 FWEIE60
= FWRO
+ 0x7a54,
350 FWEID60
= FWRO
+ 0x7a58,
351 FWEIS61
= FWRO
+ 0x7a60,
352 FWEIE61
= FWRO
+ 0x7a64,
353 FWEID61
= FWRO
+ 0x7a68,
354 FWEIS62
= FWRO
+ 0x7a70,
355 FWEIE62
= FWRO
+ 0x7a74,
356 FWEID62
= FWRO
+ 0x7a78,
357 FWEIS63
= FWRO
+ 0x7a80,
358 FWEIE63
= FWRO
+ 0x7a84,
359 FWEID63
= FWRO
+ 0x7a88,
360 FWEIS70
= FWRO
+ 0x7a90,
361 FWEIE70
= FWRO
+ 0x7A94,
362 FWEID70
= FWRO
+ 0x7a98,
363 FWEIS71
= FWRO
+ 0x7aa0,
364 FWEIE71
= FWRO
+ 0x7aa4,
365 FWEID71
= FWRO
+ 0x7aa8,
366 FWEIS72
= FWRO
+ 0x7ab0,
367 FWEIE72
= FWRO
+ 0x7ab4,
368 FWEID72
= FWRO
+ 0x7ab8,
369 FWEIS73
= FWRO
+ 0x7ac0,
370 FWEIE73
= FWRO
+ 0x7ac4,
371 FWEID73
= FWRO
+ 0x7ac8,
372 FWEIS80
= FWRO
+ 0x7ad0,
373 FWEIE80
= FWRO
+ 0x7ad4,
374 FWEID80
= FWRO
+ 0x7ad8,
375 FWEIS81
= FWRO
+ 0x7ae0,
376 FWEIE81
= FWRO
+ 0x7ae4,
377 FWEID81
= FWRO
+ 0x7ae8,
378 FWEIS82
= FWRO
+ 0x7af0,
379 FWEIE82
= FWRO
+ 0x7af4,
380 FWEID82
= FWRO
+ 0x7af8,
381 FWEIS83
= FWRO
+ 0x7b00,
382 FWEIE83
= FWRO
+ 0x7b04,
383 FWEID83
= FWRO
+ 0x7b08,
384 FWMIS0
= FWRO
+ 0x7c00,
385 FWMIE0
= FWRO
+ 0x7c04,
386 FWMID0
= FWRO
+ 0x7c08,
387 FWSCR0
= FWRO
+ 0x7d00,
388 FWSCR1
= FWRO
+ 0x7d04,
389 FWSCR2
= FWRO
+ 0x7d08,
390 FWSCR3
= FWRO
+ 0x7d0c,
391 FWSCR4
= FWRO
+ 0x7d10,
392 FWSCR5
= FWRO
+ 0x7d14,
393 FWSCR6
= FWRO
+ 0x7d18,
394 FWSCR7
= FWRO
+ 0x7d1c,
395 FWSCR8
= FWRO
+ 0x7d20,
396 FWSCR9
= FWRO
+ 0x7d24,
397 FWSCR10
= FWRO
+ 0x7d28,
398 FWSCR11
= FWRO
+ 0x7d2c,
399 FWSCR12
= FWRO
+ 0x7d30,
400 FWSCR13
= FWRO
+ 0x7d34,
401 FWSCR14
= FWRO
+ 0x7d38,
402 FWSCR15
= FWRO
+ 0x7d3c,
403 FWSCR16
= FWRO
+ 0x7d40,
404 FWSCR17
= FWRO
+ 0x7d44,
405 FWSCR18
= FWRO
+ 0x7d48,
406 FWSCR19
= FWRO
+ 0x7d4c,
407 FWSCR20
= FWRO
+ 0x7d50,
408 FWSCR21
= FWRO
+ 0x7d54,
409 FWSCR22
= FWRO
+ 0x7d58,
410 FWSCR23
= FWRO
+ 0x7d5c,
411 FWSCR24
= FWRO
+ 0x7d60,
412 FWSCR25
= FWRO
+ 0x7d64,
413 FWSCR26
= FWRO
+ 0x7d68,
414 FWSCR27
= FWRO
+ 0x7d6c,
415 FWSCR28
= FWRO
+ 0x7d70,
416 FWSCR29
= FWRO
+ 0x7d74,
417 FWSCR30
= FWRO
+ 0x7d78,
418 FWSCR31
= FWRO
+ 0x7d7c,
419 FWSCR32
= FWRO
+ 0x7d80,
420 FWSCR33
= FWRO
+ 0x7d84,
421 FWSCR34
= FWRO
+ 0x7d88,
422 FWSCR35
= FWRO
+ 0x7d8c,
423 FWSCR36
= FWRO
+ 0x7d90,
424 FWSCR37
= FWRO
+ 0x7d94,
425 FWSCR38
= FWRO
+ 0x7d98,
426 FWSCR39
= FWRO
+ 0x7d9c,
427 FWSCR40
= FWRO
+ 0x7da0,
428 FWSCR41
= FWRO
+ 0x7da4,
429 FWSCR42
= FWRO
+ 0x7da8,
430 FWSCR43
= FWRO
+ 0x7dac,
431 FWSCR44
= FWRO
+ 0x7db0,
432 FWSCR45
= FWRO
+ 0x7db4,
433 FWSCR46
= FWRO
+ 0x7db8,
435 TPEMIMC0
= TPRO
+ 0x0000,
436 TPEMIMC1
= TPRO
+ 0x0004,
437 TPEMIMC2
= TPRO
+ 0x0008,
438 TPEMIMC3
= TPRO
+ 0x000c,
439 TPEMIMC4
= TPRO
+ 0x0010,
440 TPEMIMC5
= TPRO
+ 0x0014,
441 TPEMIMC60
= TPRO
+ 0x0080,
442 TPEMIMC70
= TPRO
+ 0x0100,
443 TSIM
= TPRO
+ 0x0700,
444 TFIM
= TPRO
+ 0x0704,
445 TCIM
= TPRO
+ 0x0708,
446 TGIM0
= TPRO
+ 0x0710,
447 TGIM1
= TPRO
+ 0x0714,
448 TEIM0
= TPRO
+ 0x0720,
449 TEIM1
= TPRO
+ 0x0724,
450 TEIM2
= TPRO
+ 0x0728,
452 RIPV
= CARO
+ 0x0000,
454 RCEC
= CARO
+ 0x0008,
455 RCDC
= CARO
+ 0x000c,
456 RSSIS
= CARO
+ 0x0010,
457 RSSIE
= CARO
+ 0x0014,
458 RSSID
= CARO
+ 0x0018,
459 CABPIBWMC
= CARO
+ 0x0020,
460 CABPWMLC
= CARO
+ 0x0040,
461 CABPPFLC0
= CARO
+ 0x0050,
462 CABPPWMLC0
= CARO
+ 0x0060,
463 CABPPPFLC00
= CARO
+ 0x00a0,
464 CABPULC
= CARO
+ 0x0100,
465 CABPIRM
= CARO
+ 0x0140,
466 CABPPCM
= CARO
+ 0x0144,
467 CABPLCM
= CARO
+ 0x0148,
468 CABPCPM
= CARO
+ 0x0180,
469 CABPMCPM
= CARO
+ 0x0200,
470 CARDNM
= CARO
+ 0x0280,
471 CARDMNM
= CARO
+ 0x0284,
472 CARDCN
= CARO
+ 0x0290,
473 CAEIS0
= CARO
+ 0x0300,
474 CAEIE0
= CARO
+ 0x0304,
475 CAEID0
= CARO
+ 0x0308,
476 CAEIS1
= CARO
+ 0x0310,
477 CAEIE1
= CARO
+ 0x0314,
478 CAEID1
= CARO
+ 0x0318,
479 CAMIS0
= CARO
+ 0x0340,
480 CAMIE0
= CARO
+ 0x0344,
481 CAMID0
= CARO
+ 0x0348,
482 CAMIS1
= CARO
+ 0x0350,
483 CAMIE1
= CARO
+ 0x0354,
484 CAMID1
= CARO
+ 0x0358,
485 CASCR
= CARO
+ 0x0380,
487 EAMC
= TARO
+ 0x0000,
488 EAMS
= TARO
+ 0x0004,
489 EAIRC
= TARO
+ 0x0010,
490 EATDQSC
= TARO
+ 0x0014,
491 EATDQC
= TARO
+ 0x0018,
492 EATDQAC
= TARO
+ 0x001c,
493 EATPEC
= TARO
+ 0x0020,
494 EATMFSC0
= TARO
+ 0x0040,
495 EATDQDC0
= TARO
+ 0x0060,
496 EATDQM0
= TARO
+ 0x0080,
497 EATDQMLM0
= TARO
+ 0x00a0,
498 EACTQC
= TARO
+ 0x0100,
499 EACTDQDC
= TARO
+ 0x0104,
500 EACTDQM
= TARO
+ 0x0108,
501 EACTDQMLM
= TARO
+ 0x010c,
502 EAVCC
= TARO
+ 0x0130,
503 EAVTC
= TARO
+ 0x0134,
504 EATTFC
= TARO
+ 0x0138,
505 EACAEC
= TARO
+ 0x0200,
506 EACC
= TARO
+ 0x0204,
507 EACAIVC0
= TARO
+ 0x0220,
508 EACAULC0
= TARO
+ 0x0240,
509 EACOEM
= TARO
+ 0x0260,
510 EACOIVM0
= TARO
+ 0x0280,
511 EACOULM0
= TARO
+ 0x02a0,
512 EACGSM
= TARO
+ 0x02c0,
513 EATASC
= TARO
+ 0x0300,
514 EATASENC0
= TARO
+ 0x0320,
515 EATASCTENC
= TARO
+ 0x0340,
516 EATASENM0
= TARO
+ 0x0360,
517 EATASCTENM
= TARO
+ 0x0380,
518 EATASCSTC0
= TARO
+ 0x03a0,
519 EATASCSTC1
= TARO
+ 0x03a4,
520 EATASCSTM0
= TARO
+ 0x03a8,
521 EATASCSTM1
= TARO
+ 0x03ac,
522 EATASCTC
= TARO
+ 0x03b0,
523 EATASCTM
= TARO
+ 0x03b4,
524 EATASGL0
= TARO
+ 0x03c0,
525 EATASGL1
= TARO
+ 0x03c4,
526 EATASGLR
= TARO
+ 0x03c8,
527 EATASGR
= TARO
+ 0x03d0,
528 EATASGRR
= TARO
+ 0x03d4,
529 EATASHCC
= TARO
+ 0x03e0,
530 EATASRIRM
= TARO
+ 0x03e4,
531 EATASSM
= TARO
+ 0x03e8,
532 EAUSMFSECN
= TARO
+ 0x0400,
533 EATFECN
= TARO
+ 0x0404,
534 EAFSECN
= TARO
+ 0x0408,
535 EADQOECN
= TARO
+ 0x040c,
536 EADQSECN
= TARO
+ 0x0410,
537 EACKSECN
= TARO
+ 0x0414,
538 EAEIS0
= TARO
+ 0x0500,
539 EAEIE0
= TARO
+ 0x0504,
540 EAEID0
= TARO
+ 0x0508,
541 EAEIS1
= TARO
+ 0x0510,
542 EAEIE1
= TARO
+ 0x0514,
543 EAEID1
= TARO
+ 0x0518,
544 EAEIS2
= TARO
+ 0x0520,
545 EAEIE2
= TARO
+ 0x0524,
546 EAEID2
= TARO
+ 0x0528,
547 EASCR
= TARO
+ 0x0580,
549 MPSM
= RMRO
+ 0x0000,
550 MPIC
= RMRO
+ 0x0004,
551 MPIM
= RMRO
+ 0x0008,
552 MIOC
= RMRO
+ 0x0010,
553 MIOM
= RMRO
+ 0x0014,
554 MXMS
= RMRO
+ 0x0018,
555 MTFFC
= RMRO
+ 0x0020,
556 MTPFC
= RMRO
+ 0x0024,
557 MTPFC2
= RMRO
+ 0x0028,
558 MTPFC30
= RMRO
+ 0x0030,
559 MTATC0
= RMRO
+ 0x0050,
560 MTIM
= RMRO
+ 0x0060,
561 MRGC
= RMRO
+ 0x0080,
562 MRMAC0
= RMRO
+ 0x0084,
563 MRMAC1
= RMRO
+ 0x0088,
564 MRAFC
= RMRO
+ 0x008c,
565 MRSCE
= RMRO
+ 0x0090,
566 MRSCP
= RMRO
+ 0x0094,
567 MRSCC
= RMRO
+ 0x0098,
568 MRFSCE
= RMRO
+ 0x009c,
569 MRFSCP
= RMRO
+ 0x00a0,
570 MTRC
= RMRO
+ 0x00a4,
571 MRIM
= RMRO
+ 0x00a8,
572 MRPFM
= RMRO
+ 0x00ac,
573 MPFC0
= RMRO
+ 0x0100,
574 MLVC
= RMRO
+ 0x0180,
575 MEEEC
= RMRO
+ 0x0184,
576 MLBC
= RMRO
+ 0x0188,
577 MXGMIIC
= RMRO
+ 0x0190,
578 MPCH
= RMRO
+ 0x0194,
579 MANC
= RMRO
+ 0x0198,
580 MANM
= RMRO
+ 0x019c,
581 MPLCA1
= RMRO
+ 0x01a0,
582 MPLCA2
= RMRO
+ 0x01a4,
583 MPLCA3
= RMRO
+ 0x01a8,
584 MPLCA4
= RMRO
+ 0x01ac,
585 MPLCAM
= RMRO
+ 0x01b0,
586 MHDC1
= RMRO
+ 0x01c0,
587 MHDC2
= RMRO
+ 0x01c4,
588 MEIS
= RMRO
+ 0x0200,
589 MEIE
= RMRO
+ 0x0204,
590 MEID
= RMRO
+ 0x0208,
591 MMIS0
= RMRO
+ 0x0210,
592 MMIE0
= RMRO
+ 0x0214,
593 MMID0
= RMRO
+ 0x0218,
594 MMIS1
= RMRO
+ 0x0220,
595 MMIE1
= RMRO
+ 0x0224,
596 MMID1
= RMRO
+ 0x0228,
597 MMIS2
= RMRO
+ 0x0230,
598 MMIE2
= RMRO
+ 0x0234,
599 MMID2
= RMRO
+ 0x0238,
600 MMPFTCT
= RMRO
+ 0x0300,
601 MAPFTCT
= RMRO
+ 0x0304,
602 MPFRCT
= RMRO
+ 0x0308,
603 MFCICT
= RMRO
+ 0x030c,
604 MEEECT
= RMRO
+ 0x0310,
605 MMPCFTCT0
= RMRO
+ 0x0320,
606 MAPCFTCT0
= RMRO
+ 0x0330,
607 MPCFRCT0
= RMRO
+ 0x0340,
608 MHDCC
= RMRO
+ 0x0350,
609 MROVFC
= RMRO
+ 0x0354,
610 MRHCRCEC
= RMRO
+ 0x0358,
611 MRXBCE
= RMRO
+ 0x0400,
612 MRXBCP
= RMRO
+ 0x0404,
613 MRGFCE
= RMRO
+ 0x0408,
614 MRGFCP
= RMRO
+ 0x040c,
615 MRBFC
= RMRO
+ 0x0410,
616 MRMFC
= RMRO
+ 0x0414,
617 MRUFC
= RMRO
+ 0x0418,
618 MRPEFC
= RMRO
+ 0x041c,
619 MRNEFC
= RMRO
+ 0x0420,
620 MRFMEFC
= RMRO
+ 0x0424,
621 MRFFMEFC
= RMRO
+ 0x0428,
622 MRCFCEFC
= RMRO
+ 0x042c,
623 MRFCEFC
= RMRO
+ 0x0430,
624 MRRCFEFC
= RMRO
+ 0x0434,
625 MRUEFC
= RMRO
+ 0x043c,
626 MROEFC
= RMRO
+ 0x0440,
627 MRBOEC
= RMRO
+ 0x0444,
628 MTXBCE
= RMRO
+ 0x0500,
629 MTXBCP
= RMRO
+ 0x0504,
630 MTGFCE
= RMRO
+ 0x0508,
631 MTGFCP
= RMRO
+ 0x050c,
632 MTBFC
= RMRO
+ 0x0510,
633 MTMFC
= RMRO
+ 0x0514,
634 MTUFC
= RMRO
+ 0x0518,
635 MTEFC
= RMRO
+ 0x051c,
637 GWMC
= GWRO
+ 0x0000,
638 GWMS
= GWRO
+ 0x0004,
639 GWIRC
= GWRO
+ 0x0010,
640 GWRDQSC
= GWRO
+ 0x0014,
641 GWRDQC
= GWRO
+ 0x0018,
642 GWRDQAC
= GWRO
+ 0x001c,
643 GWRGC
= GWRO
+ 0x0020,
644 GWRMFSC0
= GWRO
+ 0x0040,
645 GWRDQDC0
= GWRO
+ 0x0060,
646 GWRDQM0
= GWRO
+ 0x0080,
647 GWRDQMLM0
= GWRO
+ 0x00a0,
648 GWMTIRM
= GWRO
+ 0x0100,
649 GWMSTLS
= GWRO
+ 0x0104,
650 GWMSTLR
= GWRO
+ 0x0108,
651 GWMSTSS
= GWRO
+ 0x010c,
652 GWMSTSR
= GWRO
+ 0x0110,
653 GWMAC0
= GWRO
+ 0x0120,
654 GWMAC1
= GWRO
+ 0x0124,
655 GWVCC
= GWRO
+ 0x0130,
656 GWVTC
= GWRO
+ 0x0134,
657 GWTTFC
= GWRO
+ 0x0138,
658 GWTDCAC00
= GWRO
+ 0x0140,
659 GWTDCAC10
= GWRO
+ 0x0144,
660 GWTSDCC0
= GWRO
+ 0x0160,
661 GWTNM
= GWRO
+ 0x0180,
662 GWTMNM
= GWRO
+ 0x0184,
663 GWAC
= GWRO
+ 0x0190,
664 GWDCBAC0
= GWRO
+ 0x0194,
665 GWDCBAC1
= GWRO
+ 0x0198,
666 GWIICBSC
= GWRO
+ 0x019c,
667 GWMDNC
= GWRO
+ 0x01a0,
668 GWTRC0
= GWRO
+ 0x0200,
669 GWTPC0
= GWRO
+ 0x0300,
670 GWARIRM
= GWRO
+ 0x0380,
671 GWDCC0
= GWRO
+ 0x0400,
672 GWAARSS
= GWRO
+ 0x0800,
673 GWAARSR0
= GWRO
+ 0x0804,
674 GWAARSR1
= GWRO
+ 0x0808,
675 GWIDAUAS0
= GWRO
+ 0x0840,
676 GWIDASM0
= GWRO
+ 0x0880,
677 GWIDASAM00
= GWRO
+ 0x0900,
678 GWIDASAM10
= GWRO
+ 0x0904,
679 GWIDACAM00
= GWRO
+ 0x0980,
680 GWIDACAM10
= GWRO
+ 0x0984,
681 GWGRLC
= GWRO
+ 0x0a00,
682 GWGRLULC
= GWRO
+ 0x0a04,
683 GWRLIVC0
= GWRO
+ 0x0a80,
684 GWRLULC0
= GWRO
+ 0x0a84,
685 GWIDPC
= GWRO
+ 0x0b00,
686 GWIDC0
= GWRO
+ 0x0c00,
687 GWDIS0
= GWRO
+ 0x1100,
688 GWDIE0
= GWRO
+ 0x1104,
689 GWDID0
= GWRO
+ 0x1108,
690 GWTSDIS
= GWRO
+ 0x1180,
691 GWTSDIE
= GWRO
+ 0x1184,
692 GWTSDID
= GWRO
+ 0x1188,
693 GWEIS0
= GWRO
+ 0x1190,
694 GWEIE0
= GWRO
+ 0x1194,
695 GWEID0
= GWRO
+ 0x1198,
696 GWEIS1
= GWRO
+ 0x11a0,
697 GWEIE1
= GWRO
+ 0x11a4,
698 GWEID1
= GWRO
+ 0x11a8,
699 GWEIS20
= GWRO
+ 0x1200,
700 GWEIE20
= GWRO
+ 0x1204,
701 GWEID20
= GWRO
+ 0x1208,
702 GWEIS3
= GWRO
+ 0x1280,
703 GWEIE3
= GWRO
+ 0x1284,
704 GWEID3
= GWRO
+ 0x1288,
705 GWEIS4
= GWRO
+ 0x1290,
706 GWEIE4
= GWRO
+ 0x1294,
707 GWEID4
= GWRO
+ 0x1298,
708 GWEIS5
= GWRO
+ 0x12a0,
709 GWEIE5
= GWRO
+ 0x12a4,
710 GWEID5
= GWRO
+ 0x12a8,
711 GWSCR0
= GWRO
+ 0x1800,
712 GWSCR1
= GWRO
+ 0x1900,
716 enum rswitch_etha_mode
{
723 #define EAMS_OPS_MASK EAMC_OPC_OPERATION
725 #define EAVCC_VEM_SC_TAG (0x3 << 16)
727 #define MPIC_PIS_MII 0x00
728 #define MPIC_PIS_GMII 0x02
729 #define MPIC_PIS_XGMII 0x04
730 #define MPIC_LSC_SHIFT 3
731 #define MPIC_LSC_100M (1 << MPIC_LSC_SHIFT)
732 #define MPIC_LSC_1G (2 << MPIC_LSC_SHIFT)
733 #define MPIC_LSC_2_5G (3 << MPIC_LSC_SHIFT)
735 #define MDIO_READ_C45 0x03
736 #define MDIO_WRITE_C45 0x01
738 #define MPSM_PSME BIT(0)
739 #define MPSM_MFF_C45 BIT(2)
740 #define MPSM_PRD_SHIFT 16
741 #define MPSM_PRD_MASK GENMASK(31, MPSM_PRD_SHIFT)
743 /* Completion flags */
744 #define MMIS1_PAACS BIT(2) /* Address */
745 #define MMIS1_PWACS BIT(1) /* Write */
746 #define MMIS1_PRACS BIT(0) /* Read */
747 #define MMIS1_CLEAR_FLAGS 0xf
749 #define MPIC_PSMCS_SHIFT 16
750 #define MPIC_PSMCS_MASK GENMASK(22, MPIC_PSMCS_SHIFT)
751 #define MPIC_PSMCS(val) ((val) << MPIC_PSMCS_SHIFT)
753 #define MPIC_PSMHT_SHIFT 24
754 #define MPIC_PSMHT_MASK GENMASK(26, MPIC_PSMHT_SHIFT)
755 #define MPIC_PSMHT(val) ((val) << MPIC_PSMHT_SHIFT)
757 #define MLVC_PLV BIT(16)
760 enum rswitch_gwca_mode
{
767 #define GWMS_OPS_MASK GWMC_OPC_OPERATION
769 #define GWMTIRM_MTIOG BIT(0)
770 #define GWMTIRM_MTR BIT(1)
772 #define GWVCC_VEM_SC_TAG (0x3 << 16)
774 #define GWARIRM_ARIOG BIT(0)
775 #define GWARIRM_ARR BIT(1)
777 #define GWMDNC_TSDMN(num) (((num) << 16) & GENMASK(17, 16))
778 #define GWMDNC_TXDMN(num) (((num) << 8) & GENMASK(12, 8))
779 #define GWMDNC_RXDMN(num) ((num) & GENMASK(4, 0))
781 #define GWDCC_BALR BIT(24)
782 #define GWDCC_DCP_MASK GENMASK(18, 16)
783 #define GWDCC_DCP(prio) FIELD_PREP(GWDCC_DCP_MASK, (prio))
784 #define GWDCC_DQT BIT(11)
785 #define GWDCC_ETS BIT(9)
786 #define GWDCC_EDE BIT(8)
788 #define GWTRC(queue) (GWTRC0 + (queue) / 32 * 4)
789 #define GWTPC_PPPL(ipv) BIT(ipv)
790 #define GWDCC_OFFS(queue) (GWDCC0 + (queue) * 4)
792 #define GWDIS(i) (GWDIS0 + (i) * 0x10)
793 #define GWDIE(i) (GWDIE0 + (i) * 0x10)
794 #define GWDID(i) (GWDID0 + (i) * 0x10)
797 #define RRC_RR BIT(0)
799 #define RCEC_ACE_DEFAULT (BIT(0) | BIT(AGENT_INDEX_GWCA))
800 #define RCEC_RCE BIT(16)
801 #define RCDC_RCD BIT(16)
803 #define CABPIRM_BPIOG BIT(0)
804 #define CABPIRM_BPR BIT(1)
806 #define CABPPFLC_INIT_VALUE 0x00800080
809 #define FWPC0_LTHTA BIT(0)
810 #define FWPC0_IP4UE BIT(3)
811 #define FWPC0_IP4TE BIT(4)
812 #define FWPC0_IP4OE BIT(5)
813 #define FWPC0_L2SE BIT(9)
814 #define FWPC0_IP4EA BIT(10)
815 #define FWPC0_IPDSA BIT(12)
816 #define FWPC0_IPHLA BIT(18)
817 #define FWPC0_MACSDA BIT(20)
818 #define FWPC0_MACHLA BIT(26)
819 #define FWPC0_MACHMA BIT(27)
820 #define FWPC0_VLANSA BIT(28)
822 #define FWPC0(i) (FWPC00 + (i) * 0x10)
823 #define FWPC0_DEFAULT (FWPC0_LTHTA | FWPC0_IP4UE | FWPC0_IP4TE | \
824 FWPC0_IP4OE | FWPC0_L2SE | FWPC0_IP4EA | \
825 FWPC0_IPDSA | FWPC0_IPHLA | FWPC0_MACSDA | \
826 FWPC0_MACHLA | FWPC0_MACHMA | FWPC0_VLANSA)
827 #define FWPC1(i) (FWPC10 + (i) * 0x10)
828 #define FWPC1_DDE BIT(0)
830 #define FWPBFC(i) (FWPBFC0 + (i) * 0x10)
832 #define FWPBFCSDC(j, i) (FWPBFCSDC00 + (i) * 0x10 + (j) * 0x04)
835 #define TPEMIMC7(queue) (TPEMIMC70 + (queue) * 4)
839 RX_DS
= 0x0fff, /* Data size */
840 RX_TR
= 0x1000, /* Truncation indication */
841 RX_EI
= 0x2000, /* Error indication */
842 RX_PS
= 0xc000, /* Padding selection */
845 enum TX_DS_TAGL_BIT
{
846 TX_DS
= 0x0fff, /* Data size */
847 TX_TAGL
= 0xf000, /* Frame tag LSBs */
863 /* HW/SW arbitration */
868 DT_FEMPTY_START
= 0x50,
869 DT_FEMPTY_MID
= 0x60,
870 DT_FEMPTY_END
= 0x70,
873 DIE
= 0x08, /* Descriptor Interrupt Enable */
876 /* Both transmission and reception */
877 #define INFO1_FMT BIT(2)
878 #define INFO1_TXC BIT(3)
880 /* For transmission */
881 #define INFO1_TSUN(val) ((u64)(val) << 8ULL)
882 #define INFO1_IPV(prio) ((u64)(prio) << 28ULL)
883 #define INFO1_CSD0(index) ((u64)(index) << 32ULL)
884 #define INFO1_CSD1(index) ((u64)(index) << 40ULL)
885 #define INFO1_DV(port_vector) ((u64)(port_vector) << 48ULL)
888 #define INFO1_SPN(port) ((u64)(port) << 36ULL)
890 /* For timestamp descriptor in dptrl (Byte 4 to 7) */
891 #define TS_DESC_TSUN(dptrl) ((dptrl) & GENMASK(7, 0))
892 #define TS_DESC_SPN(dptrl) (((dptrl) & GENMASK(10, 8)) >> 8)
893 #define TS_DESC_DPN(dptrl) (((dptrl) & GENMASK(17, 16)) >> 16)
894 #define TS_DESC_TN(dptrl) ((dptrl) & BIT(24))
896 struct rswitch_desc
{
897 __le16 info_ds
; /* Descriptor size */
898 u8 die_dt
; /* Descriptor interrupt enable and type */
899 __u8 dptrh
; /* Descriptor pointer MSB */
900 __le32 dptrl
; /* Descriptor pointer LSW */
903 struct rswitch_ts_desc
{
904 struct rswitch_desc desc
;
909 struct rswitch_ext_desc
{
910 struct rswitch_desc desc
;
914 struct rswitch_ext_ts_desc
{
915 struct rswitch_desc desc
;
921 struct rswitch_etha
{
924 void __iomem
*coma_addr
;
927 phy_interface_t phy_interface
;
929 u8 mac_addr
[MAX_ADDR_LEN
];
933 /* This hardware could not be initialized twice so that marked
934 * this flag to avoid multiple initialization.
939 /* The datasheet said descriptor "chain" and/or "queue". For consistency of
940 * name, this driver calls "queue".
942 struct rswitch_gwca_queue
{
944 struct rswitch_ext_desc
*tx_ring
;
945 struct rswitch_ext_ts_desc
*rx_ring
;
946 struct rswitch_ts_desc
*ts_ring
;
951 unsigned int ring_size
;
958 struct net_device
*ndev
; /* queue to ndev for irq */
963 struct sk_buff
**skbs
;
964 dma_addr_t
*unmap_addrs
;
969 struct sk_buff
*skb_fstart
;
975 struct rswitch_gwca_ts_info
{
977 struct list_head list
;
983 #define RSWITCH_NUM_IRQ_REGS (RSWITCH_MAX_NUM_QUEUES / BITS_PER_TYPE(u32))
984 struct rswitch_gwca
{
986 struct rswitch_desc
*linkfix_table
;
987 dma_addr_t linkfix_table_dma
;
988 u32 linkfix_table_size
;
989 struct rswitch_gwca_queue
*queues
;
991 struct rswitch_gwca_queue ts_queue
;
992 struct list_head ts_info_list
;
993 DECLARE_BITMAP(used
, RSWITCH_MAX_NUM_QUEUES
);
994 u32 tx_irq_bits
[RSWITCH_NUM_IRQ_REGS
];
995 u32 rx_irq_bits
[RSWITCH_NUM_IRQ_REGS
];
999 #define NUM_QUEUES_PER_NDEV 2
1000 struct rswitch_device
{
1001 struct rswitch_private
*priv
;
1002 struct net_device
*ndev
;
1003 struct napi_struct napi
;
1005 struct rswitch_gwca_queue
*tx_queue
;
1006 struct rswitch_gwca_queue
*rx_queue
;
1011 struct rswitch_etha
*etha
;
1012 struct device_node
*np_port
;
1016 struct rswitch_mfwd_mac_table_entry
{
1018 unsigned char addr
[MAX_ADDR_LEN
];
1021 struct rswitch_mfwd
{
1022 struct rswitch_mac_table_entry
*mac_table_entries
;
1023 int num_mac_table_entries
;
1026 struct rswitch_private
{
1027 struct platform_device
*pdev
;
1029 struct rcar_gen4_ptp_private
*ptp_priv
;
1031 struct rswitch_device
*rdev
[RSWITCH_NUM_PORTS
];
1032 DECLARE_BITMAP(opened_ports
, RSWITCH_NUM_PORTS
);
1034 struct rswitch_gwca gwca
;
1035 struct rswitch_etha etha
[RSWITCH_NUM_PORTS
];
1036 struct rswitch_mfwd mfwd
;
1038 spinlock_t lock
; /* lock interrupt registers' control */
1041 bool etha_no_runtime_change
;
1045 #endif /* #ifndef __RSWITCH_H__ */