drivers/net/ethernet/sfc/siena/nic.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /****************************************************************************
   3  * Driver for Solarflare network controllers and boards
   4  * Copyright 2005-2006 Fen Systems Ltd.
   5  * Copyright 2006-2013 Solarflare Communications Inc.
   6  */
   7
   8 #include <linux/bitops.h>
   9 #include <linux/delay.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/pci.h>
  12 #include <linux/module.h>
  13 #include <linux/seq_file.h>
  14 #include <linux/cpu_rmap.h>
  15 #include "net_driver.h"
  16 #include "bitfield.h"
  17 #include "efx.h"
  18 #include "nic.h"
  19 #include "farch_regs.h"
  20 #include "io.h"
  21 #include "workarounds.h"
  22 #include "mcdi_pcol.h"
  23
  24 /**************************************************************************
  25  *
  26  * Generic buffer handling
  27  * These buffers are used for interrupt status, MAC stats, etc.
  28  *
  29  **************************************************************************/
  30
  31 int efx_siena_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
  32                            unsigned int len, gfp_t gfp_flags)
  33 {
  34         buffer->addr = dma_alloc_coherent(&efx->pci_dev->dev, len,
  35                                           &buffer->dma_addr, gfp_flags);
  36         if (!buffer->addr)
  37                 return -ENOMEM;
  38         buffer->len = len;
  39         return 0;
  40 }
  41
  42 void efx_siena_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
  43 {
  44         if (buffer->addr) {
  45                 dma_free_coherent(&efx->pci_dev->dev, buffer->len,
  46                                   buffer->addr, buffer->dma_addr);
  47                 buffer->addr = NULL;
  48         }
  49 }
  50
  51 /* Check whether an event is present in the eventq at the current
  52  * read pointer.  Only useful for self-test.
  53  */
  54 bool efx_siena_event_present(struct efx_channel *channel)
  55 {
  56         return efx_event_present(efx_event(channel, channel->eventq_read_ptr));
  57 }
  58
  59 void efx_siena_event_test_start(struct efx_channel *channel)
  60 {
  61         channel->event_test_cpu = -1;
  62         smp_wmb();
  63         channel->efx->type->ev_test_generate(channel);
  64 }
  65
  66 int efx_siena_irq_test_start(struct efx_nic *efx)
  67 {
  68         efx->last_irq_cpu = -1;
  69         smp_wmb();
  70         return efx->type->irq_test_generate(efx);
  71 }
  72
  73 /* Hook interrupt handler(s)
  74  * Try MSI and then legacy interrupts.
  75  */
  76 int efx_siena_init_interrupt(struct efx_nic *efx)
  77 {
  78         struct efx_channel *channel;
  79         unsigned int n_irqs;
  80         int rc;
  81
  82         if (!EFX_INT_MODE_USE_MSI(efx)) {
  83                 rc = request_irq(efx->legacy_irq,
  84                                  efx->type->irq_handle_legacy, IRQF_SHARED,
  85                                  efx->name, efx);
  86                 if (rc) {
  87                         netif_err(efx, drv, efx->net_dev,
  88                                   "failed to hook legacy IRQ %d\n",
  89                                   efx->pci_dev->irq);
  90                         goto fail1;
  91                 }
  92                 efx->irqs_hooked = true;
  93                 return 0;
  94         }
  95
  96 #ifdef CONFIG_RFS_ACCEL
  97         if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
  98                 efx->net_dev->rx_cpu_rmap =
  99                         alloc_irq_cpu_rmap(efx->n_rx_channels);
 100                 if (!efx->net_dev->rx_cpu_rmap) {
 101                         rc = -ENOMEM;
 102                         goto fail1;
 103                 }
 104         }
 105 #endif
 106
 107         /* Hook MSI or MSI-X interrupt */
 108         n_irqs = 0;
 109         efx_for_each_channel(channel, efx) {
 110                 rc = request_irq(channel->irq, efx->type->irq_handle_msi,
 111                                  IRQF_PROBE_SHARED, /* Not shared */
 112                                  efx->msi_context[channel->channel].name,
 113                                  &efx->msi_context[channel->channel]);
 114                 if (rc) {
 115                         netif_err(efx, drv, efx->net_dev,
 116                                   "failed to hook IRQ %d\n", channel->irq);
 117                         goto fail2;
 118                 }
 119                 ++n_irqs;
 120
 121 #ifdef CONFIG_RFS_ACCEL
 122                 if (efx->interrupt_mode == EFX_INT_MODE_MSIX &&
 123                     channel->channel < efx->n_rx_channels) {
 124                         rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap,
 125                                               channel->irq);
 126                         if (rc)
 127                                 goto fail2;
 128                 }
 129 #endif
 130         }
 131
 132         efx->irqs_hooked = true;
 133         return 0;
 134
 135  fail2:
 136 #ifdef CONFIG_RFS_ACCEL
 137         free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
 138         efx->net_dev->rx_cpu_rmap = NULL;
 139 #endif
 140         efx_for_each_channel(channel, efx) {
 141                 if (n_irqs-- == 0)
 142                         break;
 143                 free_irq(channel->irq, &efx->msi_context[channel->channel]);
 144         }
 145  fail1:
 146         return rc;
 147 }
 148
 149 void efx_siena_fini_interrupt(struct efx_nic *efx)
 150 {
 151         struct efx_channel *channel;
 152
 153 #ifdef CONFIG_RFS_ACCEL
 154         free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
 155         efx->net_dev->rx_cpu_rmap = NULL;
 156 #endif
 157
 158         if (!efx->irqs_hooked)
 159                 return;
 160         if (EFX_INT_MODE_USE_MSI(efx)) {
 161                 /* Disable MSI/MSI-X interrupts */
 162                 efx_for_each_channel(channel, efx)
 163                         free_irq(channel->irq,
 164                                  &efx->msi_context[channel->channel]);
 165         } else {
 166                 /* Disable legacy interrupt */
 167                 free_irq(efx->legacy_irq, efx);
 168         }
 169         efx->irqs_hooked = false;
 170 }
 171
 172 /* Register dump */
 173
 174 #define REGISTER_REVISION_FA    1
 175 #define REGISTER_REVISION_FB    2
 176 #define REGISTER_REVISION_FC    3
 177 #define REGISTER_REVISION_FZ    3       /* last Falcon arch revision */
 178 #define REGISTER_REVISION_ED    4
 179 #define REGISTER_REVISION_EZ    4       /* latest EF10 revision */
 180
 181 struct efx_nic_reg {
 182         u32 offset:24;
 183         u32 min_revision:3, max_revision:3;
 184 };
 185
 186 #define REGISTER(name, arch, min_rev, max_rev) {                        \
 187         arch ## R_ ## min_rev ## max_rev ## _ ## name,                  \
 188         REGISTER_REVISION_ ## arch ## min_rev,                          \
 189         REGISTER_REVISION_ ## arch ## max_rev                           \
 190 }
 191 #define REGISTER_AA(name) REGISTER(name, F, A, A)
 192 #define REGISTER_AB(name) REGISTER(name, F, A, B)
 193 #define REGISTER_AZ(name) REGISTER(name, F, A, Z)
 194 #define REGISTER_BB(name) REGISTER(name, F, B, B)
 195 #define REGISTER_BZ(name) REGISTER(name, F, B, Z)
 196 #define REGISTER_CZ(name) REGISTER(name, F, C, Z)
 197
 198 static const struct efx_nic_reg efx_nic_regs[] = {
 199         REGISTER_AZ(ADR_REGION),
 200         REGISTER_AZ(INT_EN_KER),
 201         REGISTER_BZ(INT_EN_CHAR),
 202         REGISTER_AZ(INT_ADR_KER),
 203         REGISTER_BZ(INT_ADR_CHAR),
 204         /* INT_ACK_KER is WO */
 205         /* INT_ISR0 is RC */
 206         REGISTER_AZ(HW_INIT),
 207         REGISTER_CZ(USR_EV_CFG),
 208         REGISTER_AB(EE_SPI_HCMD),
 209         REGISTER_AB(EE_SPI_HADR),
 210         REGISTER_AB(EE_SPI_HDATA),
 211         REGISTER_AB(EE_BASE_PAGE),
 212         REGISTER_AB(EE_VPD_CFG0),
 213         /* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */
 214         /* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */
 215         /* PCIE_CORE_INDIRECT is indirect */
 216         REGISTER_AB(NIC_STAT),
 217         REGISTER_AB(GPIO_CTL),
 218         REGISTER_AB(GLB_CTL),
 219         /* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */
 220         REGISTER_BZ(DP_CTRL),
 221         REGISTER_AZ(MEM_STAT),
 222         REGISTER_AZ(CS_DEBUG),
 223         REGISTER_AZ(ALTERA_BUILD),
 224         REGISTER_AZ(CSR_SPARE),
 225         REGISTER_AB(PCIE_SD_CTL0123),
 226         REGISTER_AB(PCIE_SD_CTL45),
 227         REGISTER_AB(PCIE_PCS_CTL_STAT),
 228         /* DEBUG_DATA_OUT is not used */
 229         /* DRV_EV is WO */
 230         REGISTER_AZ(EVQ_CTL),
 231         REGISTER_AZ(EVQ_CNT1),
 232         REGISTER_AZ(EVQ_CNT2),
 233         REGISTER_AZ(BUF_TBL_CFG),
 234         REGISTER_AZ(SRM_RX_DC_CFG),
 235         REGISTER_AZ(SRM_TX_DC_CFG),
 236         REGISTER_AZ(SRM_CFG),
 237         /* BUF_TBL_UPD is WO */
 238         REGISTER_AZ(SRM_UPD_EVQ),
 239         REGISTER_AZ(SRAM_PARITY),
 240         REGISTER_AZ(RX_CFG),
 241         REGISTER_BZ(RX_FILTER_CTL),
 242         /* RX_FLUSH_DESCQ is WO */
 243         REGISTER_AZ(RX_DC_CFG),
 244         REGISTER_AZ(RX_DC_PF_WM),
 245         REGISTER_BZ(RX_RSS_TKEY),
 246         /* RX_NODESC_DROP is RC */
 247         REGISTER_AA(RX_SELF_RST),
 248         /* RX_DEBUG, RX_PUSH_DROP are not used */
 249         REGISTER_CZ(RX_RSS_IPV6_REG1),
 250         REGISTER_CZ(RX_RSS_IPV6_REG2),
 251         REGISTER_CZ(RX_RSS_IPV6_REG3),
 252         /* TX_FLUSH_DESCQ is WO */
 253         REGISTER_AZ(TX_DC_CFG),
 254         REGISTER_AA(TX_CHKSM_CFG),
 255         REGISTER_AZ(TX_CFG),
 256         /* TX_PUSH_DROP is not used */
 257         REGISTER_AZ(TX_RESERVED),
 258         REGISTER_BZ(TX_PACE),
 259         /* TX_PACE_DROP_QID is RC */
 260         REGISTER_BB(TX_VLAN),
 261         REGISTER_BZ(TX_IPFIL_PORTEN),
 262         REGISTER_AB(MD_TXD),
 263         REGISTER_AB(MD_RXD),
 264         REGISTER_AB(MD_CS),
 265         REGISTER_AB(MD_PHY_ADR),
 266         REGISTER_AB(MD_ID),
 267         /* MD_STAT is RC */
 268         REGISTER_AB(MAC_STAT_DMA),
 269         REGISTER_AB(MAC_CTRL),
 270         REGISTER_BB(GEN_MODE),
 271         REGISTER_AB(MAC_MC_HASH_REG0),
 272         REGISTER_AB(MAC_MC_HASH_REG1),
 273         REGISTER_AB(GM_CFG1),
 274         REGISTER_AB(GM_CFG2),
 275         /* GM_IPG and GM_HD are not used */
 276         REGISTER_AB(GM_MAX_FLEN),
 277         /* GM_TEST is not used */
 278         REGISTER_AB(GM_ADR1),
 279         REGISTER_AB(GM_ADR2),
 280         REGISTER_AB(GMF_CFG0),
 281         REGISTER_AB(GMF_CFG1),
 282         REGISTER_AB(GMF_CFG2),
 283         REGISTER_AB(GMF_CFG3),
 284         REGISTER_AB(GMF_CFG4),
 285         REGISTER_AB(GMF_CFG5),
 286         REGISTER_BB(TX_SRC_MAC_CTL),
 287         REGISTER_AB(XM_ADR_LO),
 288         REGISTER_AB(XM_ADR_HI),
 289         REGISTER_AB(XM_GLB_CFG),
 290         REGISTER_AB(XM_TX_CFG),
 291         REGISTER_AB(XM_RX_CFG),
 292         REGISTER_AB(XM_MGT_INT_MASK),
 293         REGISTER_AB(XM_FC),
 294         REGISTER_AB(XM_PAUSE_TIME),
 295         REGISTER_AB(XM_TX_PARAM),
 296         REGISTER_AB(XM_RX_PARAM),
 297         /* XM_MGT_INT_MSK (note no 'A') is RC */
 298         REGISTER_AB(XX_PWR_RST),
 299         REGISTER_AB(XX_SD_CTL),
 300         REGISTER_AB(XX_TXDRV_CTL),
 301         /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */
 302         /* XX_CORE_STAT is partly RC */
 303 };
 304
 305 struct efx_nic_reg_table {
 306         u32 offset:24;
 307         u32 min_revision:3, max_revision:3;
 308         u32 step:6, rows:21;
 309 };
 310
 311 #define REGISTER_TABLE_DIMENSIONS(_, offset, arch, min_rev, max_rev, step, rows) { \
 312         offset,                                                         \
 313         REGISTER_REVISION_ ## arch ## min_rev,                          \
 314         REGISTER_REVISION_ ## arch ## max_rev,                          \
 315         step, rows                                                      \
 316 }
 317 #define REGISTER_TABLE(name, arch, min_rev, max_rev)                    \
 318         REGISTER_TABLE_DIMENSIONS(                                      \
 319                 name, arch ## R_ ## min_rev ## max_rev ## _ ## name,    \
 320                 arch, min_rev, max_rev,                                 \
 321                 arch ## R_ ## min_rev ## max_rev ## _ ## name ## _STEP, \
 322                 arch ## R_ ## min_rev ## max_rev ## _ ## name ## _ROWS)
 323 #define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, F, A, A)
 324 #define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, F, A, Z)
 325 #define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, F, B, B)
 326 #define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, F, B, Z)
 327 #define REGISTER_TABLE_BB_CZ(name)                                      \
 328         REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, B, B,        \
 329                                   FR_BZ_ ## name ## _STEP,              \
 330                                   FR_BB_ ## name ## _ROWS),             \
 331         REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, C, Z,        \
 332                                   FR_BZ_ ## name ## _STEP,              \
 333                                   FR_CZ_ ## name ## _ROWS)
 334 #define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, F, C, Z)
 335
 336 static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
 337         /* DRIVER is not used */
 338         /* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */
 339         REGISTER_TABLE_BB(TX_IPFIL_TBL),
 340         REGISTER_TABLE_BB(TX_SRC_MAC_TBL),
 341         REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER),
 342         REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL),
 343         REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER),
 344         REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL),
 345         REGISTER_TABLE_AA(EVQ_PTR_TBL_KER),
 346         REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL),
 347         /* We can't reasonably read all of the buffer table (up to 8MB!).
 348          * However this driver will only use a few entries.  Reading
 349          * 1K entries allows for some expansion of queue count and
 350          * size before we need to change the version. */
 351         REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER,
 352                                   F, A, A, 8, 1024),
 353         REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL,
 354                                   F, B, Z, 8, 1024),
 355         REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0),
 356         REGISTER_TABLE_BB_CZ(TIMER_TBL),
 357         REGISTER_TABLE_BB_CZ(TX_PACE_TBL),
 358         REGISTER_TABLE_BZ(RX_INDIRECTION_TBL),
 359         /* TX_FILTER_TBL0 is huge and not used by this driver */
 360         REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0),
 361         REGISTER_TABLE_CZ(MC_TREG_SMEM),
 362         /* MSIX_PBA_TABLE is not mapped */
 363         /* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */
 364         REGISTER_TABLE_BZ(RX_FILTER_TBL0),
 365 };
 366
 367 size_t efx_siena_get_regs_len(struct efx_nic *efx)
 368 {
 369         const struct efx_nic_reg *reg;
 370         const struct efx_nic_reg_table *table;
 371         size_t len = 0;
 372
 373         for (reg = efx_nic_regs;
 374              reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
 375              reg++)
 376                 if (efx->type->revision >= reg->min_revision &&
 377                     efx->type->revision <= reg->max_revision)
 378                         len += sizeof(efx_oword_t);
 379
 380         for (table = efx_nic_reg_tables;
 381              table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
 382              table++)
 383                 if (efx->type->revision >= table->min_revision &&
 384                     efx->type->revision <= table->max_revision)
 385                         len += table->rows * min_t(size_t, table->step, 16);
 386
 387         return len;
 388 }
 389
 390 void efx_siena_get_regs(struct efx_nic *efx, void *buf)
 391 {
 392         const struct efx_nic_reg *reg;
 393         const struct efx_nic_reg_table *table;
 394
 395         for (reg = efx_nic_regs;
 396              reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
 397              reg++) {
 398                 if (efx->type->revision >= reg->min_revision &&
 399                     efx->type->revision <= reg->max_revision) {
 400                         efx_reado(efx, (efx_oword_t *)buf, reg->offset);
 401                         buf += sizeof(efx_oword_t);
 402                 }
 403         }
 404
 405         for (table = efx_nic_reg_tables;
 406              table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
 407              table++) {
 408                 size_t size, i;
 409
 410                 if (!(efx->type->revision >= table->min_revision &&
 411                       efx->type->revision <= table->max_revision))
 412                         continue;
 413
 414                 size = min_t(size_t, table->step, 16);
 415
 416                 for (i = 0; i < table->rows; i++) {
 417                         switch (table->step) {
 418                         case 4: /* 32-bit SRAM */
 419                                 efx_readd(efx, buf, table->offset + 4 * i);
 420                                 break;
 421                         case 8: /* 64-bit SRAM */
 422                                 efx_sram_readq(efx,
 423                                                efx->membase + table->offset,
 424                                                buf, i);
 425                                 break;
 426                         case 16: /* 128-bit-readable register */
 427                                 efx_reado_table(efx, buf, table->offset, i);
 428                                 break;
 429                         case 32: /* 128-bit register, interleaved */
 430                                 efx_reado_table(efx, buf, table->offset, 2 * i);
 431                                 break;
 432                         default:
 433                                 WARN_ON(1);
 434                                 return;
 435                         }
 436                         buf += size;
 437                 }
 438         }
 439 }
 440
 441 /**
 442  * efx_siena_describe_stats - Describe supported statistics for ethtool
 443  * @desc: Array of &struct efx_hw_stat_desc describing the statistics
 444  * @count: Length of the @desc array
 445  * @mask: Bitmask of which elements of @desc are enabled
 446  * @names: Buffer to copy names to, or %NULL.  The names are copied
 447  *      starting at intervals of %ETH_GSTRING_LEN bytes.
 448  *
 449  * Returns the number of visible statistics, i.e. the number of set
 450  * bits in the first @count bits of @mask for which a name is defined.
 451  */
 452 size_t efx_siena_describe_stats(const struct efx_hw_stat_desc *desc,
 453                                 size_t count, const unsigned long *mask,
 454                                 u8 **names)
 455 {
 456         size_t visible = 0;
 457         size_t index;
 458
 459         for_each_set_bit(index, mask, count) {
 460                 if (desc[index].name) {
 461                         ++visible;
 462                         if (!names)
 463                                 continue;
 464
 465                         ethtool_puts(names, desc[index].name);
 466                 }
 467         }
 468
 469         return visible;
 470 }
 471
 472 /**
 473  * efx_siena_update_stats - Convert statistics DMA buffer to array of u64
 474  * @desc: Array of &struct efx_hw_stat_desc describing the DMA buffer
 475  *      layout.  DMA widths of 0, 16, 32 and 64 are supported; where
 476  *      the width is specified as 0 the corresponding element of
 477  *      @stats is not updated.
 478  * @count: Length of the @desc array
 479  * @mask: Bitmask of which elements of @desc are enabled
 480  * @stats: Buffer to update with the converted statistics.  The length
 481  *      of this array must be at least @count.
 482  * @dma_buf: DMA buffer containing hardware statistics
 483  * @accumulate: If set, the converted values will be added rather than
 484  *      directly stored to the corresponding elements of @stats
 485  */
 486 void efx_siena_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
 487                             const unsigned long *mask,
 488                             u64 *stats, const void *dma_buf, bool accumulate)
 489 {
 490         size_t index;
 491
 492         for_each_set_bit(index, mask, count) {
 493                 if (desc[index].dma_width) {
 494                         const void *addr = dma_buf + desc[index].offset;
 495                         u64 val;
 496
 497                         switch (desc[index].dma_width) {
 498                         case 16:
 499                                 val = le16_to_cpup((__le16 *)addr);
 500                                 break;
 501                         case 32:
 502                                 val = le32_to_cpup((__le32 *)addr);
 503                                 break;
 504                         case 64:
 505                                 val = le64_to_cpup((__le64 *)addr);
 506                                 break;
 507                         default:
 508                                 WARN_ON(1);
 509                                 val = 0;
 510                                 break;
 511                         }
 512
 513                         if (accumulate)
 514                                 stats[index] += val;
 515                         else
 516                                 stats[index] = val;
 517                 }
 518         }
 519 }
 520
 521 void efx_siena_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *rx_nodesc_drops)
 522 {
 523         /* if down, or this is the first update after coming up */
 524         if (!(efx->net_dev->flags & IFF_UP) || !efx->rx_nodesc_drops_prev_state)
 525                 efx->rx_nodesc_drops_while_down +=
 526                         *rx_nodesc_drops - efx->rx_nodesc_drops_total;
 527         efx->rx_nodesc_drops_total = *rx_nodesc_drops;
 528         efx->rx_nodesc_drops_prev_state = !!(efx->net_dev->flags & IFF_UP);
 529         *rx_nodesc_drops -= efx->rx_nodesc_drops_while_down;
 530 }