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Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / net / ethernet / sun / cassini.c
blobb8948d5b779afa4a6d01302e9ddcebb5a54bb36d
1 // SPDX-License-Identifier: GPL-2.0+
2 /* cassini.c: Sun Microsystems Cassini(+) ethernet driver.
3 *
4 * Copyright (C) 2004 Sun Microsystems Inc.
5 * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com)
6 *
7 * This driver uses the sungem driver (c) David Miller
8 * (davem@redhat.com) as its basis.
9 *
10 * The cassini chip has a number of features that distinguish it from
11 * the gem chip:
12 * 4 transmit descriptor rings that are used for either QoS (VLAN) or
13 * load balancing (non-VLAN mode)
14 * batching of multiple packets
15 * multiple CPU dispatching
16 * page-based RX descriptor engine with separate completion rings
17 * Gigabit support (GMII and PCS interface)
18 * MIF link up/down detection works
19 *
20 * RX is handled by page sized buffers that are attached as fragments to
21 * the skb. here's what's done:
22 * -- driver allocates pages at a time and keeps reference counts
23 * on them.
24 * -- the upper protocol layers assume that the header is in the skb
25 * itself. as a result, cassini will copy a small amount (64 bytes)
26 * to make them happy.
27 * -- driver appends the rest of the data pages as frags to skbuffs
28 * and increments the reference count
29 * -- on page reclamation, the driver swaps the page with a spare page.
30 * if that page is still in use, it frees its reference to that page,
31 * and allocates a new page for use. otherwise, it just recycles the
32 * page.
33 *
34 * NOTE: cassini can parse the header. however, it's not worth it
35 * as long as the network stack requires a header copy.
36 *
37 * TX has 4 queues. currently these queues are used in a round-robin
38 * fashion for load balancing. They can also be used for QoS. for that
39 * to work, however, QoS information needs to be exposed down to the driver
40 * level so that subqueues get targeted to particular transmit rings.
41 * alternatively, the queues can be configured via use of the all-purpose
42 * ioctl.
43 *
44 * RX DATA: the rx completion ring has all the info, but the rx desc
45 * ring has all of the data. RX can conceivably come in under multiple
46 * interrupts, but the INT# assignment needs to be set up properly by
47 * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do
48 * that. also, the two descriptor rings are designed to distinguish between
49 * encrypted and non-encrypted packets, but we use them for buffering
50 * instead.
51 *
52 * by default, the selective clear mask is set up to process rx packets.
53 */
54
55 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
56
57 #include <linux/module.h>
58 #include <linux/kernel.h>
59 #include <linux/types.h>
60 #include <linux/compiler.h>
61 #include <linux/slab.h>
62 #include <linux/delay.h>
63 #include <linux/init.h>
64 #include <linux/interrupt.h>
65 #include <linux/vmalloc.h>
66 #include <linux/ioport.h>
67 #include <linux/pci.h>
68 #include <linux/mm.h>
69 #include <linux/highmem.h>
70 #include <linux/list.h>
71 #include <linux/dma-mapping.h>
72
73 #include <linux/netdevice.h>
74 #include <linux/etherdevice.h>
75 #include <linux/skbuff.h>
76 #include <linux/skbuff_ref.h>
77 #include <linux/ethtool.h>
78 #include <linux/crc32.h>
79 #include <linux/random.h>
80 #include <linux/mii.h>
81 #include <linux/ip.h>
82 #include <linux/tcp.h>
83 #include <linux/mutex.h>
84 #include <linux/firmware.h>
85
86 #include <net/checksum.h>
87
88 #include <linux/atomic.h>
89 #include <asm/io.h>
90 #include <asm/byteorder.h>
91 #include <linux/uaccess.h>
92 #include <linux/jiffies.h>
93
94 #define CAS_NCPUS num_online_cpus()
95
96 #define cas_skb_release(x) netif_rx(x)
97
98 /* select which firmware to use */
99 #define USE_HP_WORKAROUND
100 #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */
101 #define CAS_HP_ALT_FIRMWARE cas_prog_null /* alternate firmware */
102
103 #include "cassini.h"
104
105 #define USE_TX_COMPWB /* use completion writeback registers */
106 #define USE_CSMA_CD_PROTO /* standard CSMA/CD */
107 #define USE_RX_BLANK /* hw interrupt mitigation */
108 #undef USE_ENTROPY_DEV /* don't test for entropy device */
109
110 /* NOTE: these aren't useable unless PCI interrupts can be assigned.
111 * also, we need to make cp->lock finer-grained.
112 */
113 #undef USE_PCI_INTB
114 #undef USE_PCI_INTC
115 #undef USE_PCI_INTD
116 #undef USE_QOS
117
118 #undef USE_VPD_DEBUG /* debug vpd information if defined */
119
120 /* rx processing options */
121 #define USE_PAGE_ORDER /* specify to allocate large rx pages */
122 #define RX_DONT_BATCH 0 /* if 1, don't batch flows */
123 #define RX_COPY_ALWAYS 0 /* if 0, use frags */
124 #define RX_COPY_MIN 64 /* copy a little to make upper layers happy */
125 #undef RX_COUNT_BUFFERS /* define to calculate RX buffer stats */
126
127 #define DRV_MODULE_NAME "cassini"
128 #define DRV_MODULE_VERSION "1.6"
129 #define DRV_MODULE_RELDATE "21 May 2008"
130
131 #define CAS_DEF_MSG_ENABLE \
132 (NETIF_MSG_DRV | \
133 NETIF_MSG_PROBE | \
134 NETIF_MSG_LINK | \
135 NETIF_MSG_TIMER | \
136 NETIF_MSG_IFDOWN | \
137 NETIF_MSG_IFUP | \
138 NETIF_MSG_RX_ERR | \
139 NETIF_MSG_TX_ERR)
140
141 /* length of time before we decide the hardware is borked,
142 * and dev->tx_timeout() should be called to fix the problem
143 */
144 #define CAS_TX_TIMEOUT (HZ)
145 #define CAS_LINK_TIMEOUT (22*HZ/10)
146 #define CAS_LINK_FAST_TIMEOUT (1)
147
148 /* timeout values for state changing. these specify the number
149 * of 10us delays to be used before giving up.
150 */
151 #define STOP_TRIES_PHY 1000
152 #define STOP_TRIES 5000
153
154 /* specify a minimum frame size to deal with some fifo issues
155 * max mtu == 2 * page size - ethernet header - 64 - swivel =
156 * 2 * page_size - 0x50
157 */
158 #define CAS_MIN_FRAME 97
159 #define CAS_1000MB_MIN_FRAME 255
160 #define CAS_MIN_MTU 60
161 #define CAS_MAX_MTU min(((cp->page_size << 1) - 0x50), 9000)
162
163 #if 1
164 /*
165 * Eliminate these and use separate atomic counters for each, to
166 * avoid a race condition.
167 */
168 #else
169 #define CAS_RESET_MTU 1
170 #define CAS_RESET_ALL 2
171 #define CAS_RESET_SPARE 3
172 #endif
173
174 static char version[] =
175 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
176
177 static int cassini_debug = -1; /* -1 == use CAS_DEF_MSG_ENABLE as value */
178 static int link_mode;
179
180 MODULE_AUTHOR("Adrian Sun <asun@darksunrising.com>");
181 MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
182 MODULE_LICENSE("GPL");
183 MODULE_FIRMWARE("sun/cassini.bin");
184 module_param(cassini_debug, int, 0);
185 MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
186 module_param(link_mode, int, 0);
187 MODULE_PARM_DESC(link_mode, "default link mode");
188
189 /*
190 * Work around for a PCS bug in which the link goes down due to the chip
191 * being confused and never showing a link status of "up."
192 */
193 #define DEFAULT_LINKDOWN_TIMEOUT 5
194 /*
195 * Value in seconds, for user input.
196 */
197 static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
198 module_param(linkdown_timeout, int, 0);
199 MODULE_PARM_DESC(linkdown_timeout,
200 "min reset interval in sec. for PCS linkdown issue; disabled if not positive");
201
202 /*
203 * value in 'ticks' (units used by jiffies). Set when we init the
204 * module because 'HZ' in actually a function call on some flavors of
205 * Linux. This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ.
206 */
207 static int link_transition_timeout;
208
209
210
211 static u16 link_modes[] = {
212 BMCR_ANENABLE, /* 0 : autoneg */
213 0, /* 1 : 10bt half duplex */
214 BMCR_SPEED100, /* 2 : 100bt half duplex */
215 BMCR_FULLDPLX, /* 3 : 10bt full duplex */
216 BMCR_SPEED100|BMCR_FULLDPLX, /* 4 : 100bt full duplex */
217 CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */
218 };
219
220 static const struct pci_device_id cas_pci_tbl[] = {
221 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
223 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
225 { 0, }
226 };
227
228 MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
229
230 static void cas_set_link_modes(struct cas *cp);
231
232 static inline void cas_lock_tx(struct cas *cp)
233 {
234 int i;
235
236 for (i = 0; i < N_TX_RINGS; i++)
237 spin_lock_nested(&cp->tx_lock[i], i);
238 }
239
240 /* WTZ: QA was finding deadlock problems with the previous
241 * versions after long test runs with multiple cards per machine.
242 * See if replacing cas_lock_all with safer versions helps. The
243 * symptoms QA is reporting match those we'd expect if interrupts
244 * aren't being properly restored, and we fixed a previous deadlock
245 * with similar symptoms by using save/restore versions in other
246 * places.
247 */
248 #define cas_lock_all_save(cp, flags) \
249 do { \
250 struct cas *xxxcp = (cp); \
251 spin_lock_irqsave(&xxxcp->lock, flags); \
252 cas_lock_tx(xxxcp); \
253 } while (0)
254
255 static inline void cas_unlock_tx(struct cas *cp)
256 {
257 int i;
258
259 for (i = N_TX_RINGS; i > 0; i--)
260 spin_unlock(&cp->tx_lock[i - 1]);
261 }
262
263 #define cas_unlock_all_restore(cp, flags) \
264 do { \
265 struct cas *xxxcp = (cp); \
266 cas_unlock_tx(xxxcp); \
267 spin_unlock_irqrestore(&xxxcp->lock, flags); \
268 } while (0)
269
270 static void cas_disable_irq(struct cas *cp, const int ring)
271 {
272 /* Make sure we won't get any more interrupts */
273 if (ring == 0) {
274 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
275 return;
276 }
277
278 /* disable completion interrupts and selectively mask */
279 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
280 switch (ring) {
281 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
282 #ifdef USE_PCI_INTB
283 case 1:
284 #endif
285 #ifdef USE_PCI_INTC
286 case 2:
287 #endif
288 #ifdef USE_PCI_INTD
289 case 3:
290 #endif
291 writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,
292 cp->regs + REG_PLUS_INTRN_MASK(ring));
293 break;
294 #endif
295 default:
296 writel(INTRN_MASK_CLEAR_ALL, cp->regs +
297 REG_PLUS_INTRN_MASK(ring));
298 break;
299 }
300 }
301 }
302
303 static inline void cas_mask_intr(struct cas *cp)
304 {
305 int i;
306
307 for (i = 0; i < N_RX_COMP_RINGS; i++)
308 cas_disable_irq(cp, i);
309 }
310
311 static void cas_enable_irq(struct cas *cp, const int ring)
312 {
313 if (ring == 0) { /* all but TX_DONE */
314 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
315 return;
316 }
317
318 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
319 switch (ring) {
320 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
321 #ifdef USE_PCI_INTB
322 case 1:
323 #endif
324 #ifdef USE_PCI_INTC
325 case 2:
326 #endif
327 #ifdef USE_PCI_INTD
328 case 3:
329 #endif
330 writel(INTRN_MASK_RX_EN, cp->regs +
331 REG_PLUS_INTRN_MASK(ring));
332 break;
333 #endif
334 default:
335 break;
336 }
337 }
338 }
339
340 static inline void cas_unmask_intr(struct cas *cp)
341 {
342 int i;
343
344 for (i = 0; i < N_RX_COMP_RINGS; i++)
345 cas_enable_irq(cp, i);
346 }
347
348 static inline void cas_entropy_gather(struct cas *cp)
349 {
350 #ifdef USE_ENTROPY_DEV
351 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
352 return;
353
354 batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
355 readl(cp->regs + REG_ENTROPY_IV),
356 sizeof(uint64_t)*8);
357 #endif
358 }
359
360 static inline void cas_entropy_reset(struct cas *cp)
361 {
362 #ifdef USE_ENTROPY_DEV
363 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
364 return;
365
366 writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,
367 cp->regs + REG_BIM_LOCAL_DEV_EN);
368 writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
369 writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
370
371 /* if we read back 0x0, we don't have an entropy device */
372 if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
373 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
374 #endif
375 }
376
377 /* access to the phy. the following assumes that we've initialized the MIF to
378 * be in frame rather than bit-bang mode
379 */
380 static u16 cas_phy_read(struct cas *cp, int reg)
381 {
382 u32 cmd;
383 int limit = STOP_TRIES_PHY;
384
385 cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
386 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
387 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
388 cmd |= MIF_FRAME_TURN_AROUND_MSB;
389 writel(cmd, cp->regs + REG_MIF_FRAME);
390
391 /* poll for completion */
392 while (limit-- > 0) {
393 udelay(10);
394 cmd = readl(cp->regs + REG_MIF_FRAME);
395 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
396 return cmd & MIF_FRAME_DATA_MASK;
397 }
398 return 0xFFFF; /* -1 */
399 }
400
401 static int cas_phy_write(struct cas *cp, int reg, u16 val)
402 {
403 int limit = STOP_TRIES_PHY;
404 u32 cmd;
405
406 cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
407 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
408 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
409 cmd |= MIF_FRAME_TURN_AROUND_MSB;
410 cmd |= val & MIF_FRAME_DATA_MASK;
411 writel(cmd, cp->regs + REG_MIF_FRAME);
412
413 /* poll for completion */
414 while (limit-- > 0) {
415 udelay(10);
416 cmd = readl(cp->regs + REG_MIF_FRAME);
417 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
418 return 0;
419 }
420 return -1;
421 }
422
423 static void cas_phy_powerup(struct cas *cp)
424 {
425 u16 ctl = cas_phy_read(cp, MII_BMCR);
426
427 if ((ctl & BMCR_PDOWN) == 0)
428 return;
429 ctl &= ~BMCR_PDOWN;
430 cas_phy_write(cp, MII_BMCR, ctl);
431 }
432
433 static void cas_phy_powerdown(struct cas *cp)
434 {
435 u16 ctl = cas_phy_read(cp, MII_BMCR);
436
437 if (ctl & BMCR_PDOWN)
438 return;
439 ctl |= BMCR_PDOWN;
440 cas_phy_write(cp, MII_BMCR, ctl);
441 }
442
443 /* cp->lock held. note: the last put_page will free the buffer */
444 static int cas_page_free(struct cas *cp, cas_page_t *page)
445 {
446 dma_unmap_page(&cp->pdev->dev, page->dma_addr, cp->page_size,
447 DMA_FROM_DEVICE);
448 __free_pages(page->buffer, cp->page_order);
449 kfree(page);
450 return 0;
451 }
452
453 #ifdef RX_COUNT_BUFFERS
454 #define RX_USED_ADD(x, y) ((x)->used += (y))
455 #define RX_USED_SET(x, y) ((x)->used = (y))
456 #else
457 #define RX_USED_ADD(x, y) do { } while(0)
458 #define RX_USED_SET(x, y) do { } while(0)
459 #endif
460
461 /* local page allocation routines for the receive buffers. jumbo pages
462 * require at least 8K contiguous and 8K aligned buffers.
463 */
464 static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
465 {
466 cas_page_t *page;
467
468 page = kmalloc(sizeof(cas_page_t), flags);
469 if (!page)
470 return NULL;
471
472 INIT_LIST_HEAD(&page->list);
473 RX_USED_SET(page, 0);
474 page->buffer = alloc_pages(flags, cp->page_order);
475 if (!page->buffer)
476 goto page_err;
477 page->dma_addr = dma_map_page(&cp->pdev->dev, page->buffer, 0,
478 cp->page_size, DMA_FROM_DEVICE);
479 return page;
480
481 page_err:
482 kfree(page);
483 return NULL;
484 }
485
486 /* initialize spare pool of rx buffers, but allocate during the open */
487 static void cas_spare_init(struct cas *cp)
488 {
489 spin_lock(&cp->rx_inuse_lock);
490 INIT_LIST_HEAD(&cp->rx_inuse_list);
491 spin_unlock(&cp->rx_inuse_lock);
492
493 spin_lock(&cp->rx_spare_lock);
494 INIT_LIST_HEAD(&cp->rx_spare_list);
495 cp->rx_spares_needed = RX_SPARE_COUNT;
496 spin_unlock(&cp->rx_spare_lock);
497 }
498
499 /* used on close. free all the spare buffers. */
500 static void cas_spare_free(struct cas *cp)
501 {
502 struct list_head list, *elem, *tmp;
503
504 /* free spare buffers */
505 INIT_LIST_HEAD(&list);
506 spin_lock(&cp->rx_spare_lock);
507 list_splice_init(&cp->rx_spare_list, &list);
508 spin_unlock(&cp->rx_spare_lock);
509 list_for_each_safe(elem, tmp, &list) {
510 cas_page_free(cp, list_entry(elem, cas_page_t, list));
511 }
512
513 INIT_LIST_HEAD(&list);
514 #if 1
515 /*
516 * Looks like Adrian had protected this with a different
517 * lock than used everywhere else to manipulate this list.
518 */
519 spin_lock(&cp->rx_inuse_lock);
520 list_splice_init(&cp->rx_inuse_list, &list);
521 spin_unlock(&cp->rx_inuse_lock);
522 #else
523 spin_lock(&cp->rx_spare_lock);
524 list_splice_init(&cp->rx_inuse_list, &list);
525 spin_unlock(&cp->rx_spare_lock);
526 #endif
527 list_for_each_safe(elem, tmp, &list) {
528 cas_page_free(cp, list_entry(elem, cas_page_t, list));
529 }
530 }
531
532 /* replenish spares if needed */
533 static void cas_spare_recover(struct cas *cp, const gfp_t flags)
534 {
535 struct list_head list, *elem, *tmp;
536 int needed, i;
537
538 /* check inuse list. if we don't need any more free buffers,
539 * just free it
540 */
541
542 /* make a local copy of the list */
543 INIT_LIST_HEAD(&list);
544 spin_lock(&cp->rx_inuse_lock);
545 list_splice_init(&cp->rx_inuse_list, &list);
546 spin_unlock(&cp->rx_inuse_lock);
547
548 list_for_each_safe(elem, tmp, &list) {
549 cas_page_t *page = list_entry(elem, cas_page_t, list);
550
551 /*
552 * With the lockless pagecache, cassini buffering scheme gets
553 * slightly less accurate: we might find that a page has an
554 * elevated reference count here, due to a speculative ref,
555 * and skip it as in-use. Ideally we would be able to reclaim
556 * it. However this would be such a rare case, it doesn't
557 * matter too much as we should pick it up the next time round.
558 *
559 * Importantly, if we find that the page has a refcount of 1
560 * here (our refcount), then we know it is definitely not inuse
561 * so we can reuse it.
562 */
563 if (page_count(page->buffer) > 1)
564 continue;
565
566 list_del(elem);
567 spin_lock(&cp->rx_spare_lock);
568 if (cp->rx_spares_needed > 0) {
569 list_add(elem, &cp->rx_spare_list);
570 cp->rx_spares_needed--;
571 spin_unlock(&cp->rx_spare_lock);
572 } else {
573 spin_unlock(&cp->rx_spare_lock);
574 cas_page_free(cp, page);
575 }
576 }
577
578 /* put any inuse buffers back on the list */
579 if (!list_empty(&list)) {
580 spin_lock(&cp->rx_inuse_lock);
581 list_splice(&list, &cp->rx_inuse_list);
582 spin_unlock(&cp->rx_inuse_lock);
583 }
584
585 spin_lock(&cp->rx_spare_lock);
586 needed = cp->rx_spares_needed;
587 spin_unlock(&cp->rx_spare_lock);
588 if (!needed)
589 return;
590
591 /* we still need spares, so try to allocate some */
592 INIT_LIST_HEAD(&list);
593 i = 0;
594 while (i < needed) {
595 cas_page_t *spare = cas_page_alloc(cp, flags);
596 if (!spare)
597 break;
598 list_add(&spare->list, &list);
599 i++;
600 }
601
602 spin_lock(&cp->rx_spare_lock);
603 list_splice(&list, &cp->rx_spare_list);
604 cp->rx_spares_needed -= i;
605 spin_unlock(&cp->rx_spare_lock);
606 }
607
608 /* pull a page from the list. */
609 static cas_page_t *cas_page_dequeue(struct cas *cp)
610 {
611 struct list_head *entry;
612 int recover;
613
614 spin_lock(&cp->rx_spare_lock);
615 if (list_empty(&cp->rx_spare_list)) {
616 /* try to do a quick recovery */
617 spin_unlock(&cp->rx_spare_lock);
618 cas_spare_recover(cp, GFP_ATOMIC);
619 spin_lock(&cp->rx_spare_lock);
620 if (list_empty(&cp->rx_spare_list)) {
621 netif_err(cp, rx_err, cp->dev,
622 "no spare buffers available\n");
623 spin_unlock(&cp->rx_spare_lock);
624 return NULL;
625 }
626 }
627
628 entry = cp->rx_spare_list.next;
629 list_del(entry);
630 recover = ++cp->rx_spares_needed;
631 spin_unlock(&cp->rx_spare_lock);
632
633 /* trigger the timer to do the recovery */
634 if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
635 #if 1
636 atomic_inc(&cp->reset_task_pending);
637 atomic_inc(&cp->reset_task_pending_spare);
638 schedule_work(&cp->reset_task);
639 #else
640 atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
641 schedule_work(&cp->reset_task);
642 #endif
643 }
644 return list_entry(entry, cas_page_t, list);
645 }
646
647
648 static void cas_mif_poll(struct cas *cp, const int enable)
649 {
650 u32 cfg;
651
652 cfg = readl(cp->regs + REG_MIF_CFG);
653 cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
654
655 if (cp->phy_type & CAS_PHY_MII_MDIO1)
656 cfg |= MIF_CFG_PHY_SELECT;
657
658 /* poll and interrupt on link status change. */
659 if (enable) {
660 cfg |= MIF_CFG_POLL_EN;
661 cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
662 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
663 }
664 writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,
665 cp->regs + REG_MIF_MASK);
666 writel(cfg, cp->regs + REG_MIF_CFG);
667 }
668
669 /* Must be invoked under cp->lock */
670 static void cas_begin_auto_negotiation(struct cas *cp,
671 const struct ethtool_link_ksettings *ep)
672 {
673 u16 ctl;
674 #if 1
675 int lcntl;
676 int changed = 0;
677 int oldstate = cp->lstate;
678 int link_was_not_down = !(oldstate == link_down);
679 #endif
680 /* Setup link parameters */
681 if (!ep)
682 goto start_aneg;
683 lcntl = cp->link_cntl;
684 if (ep->base.autoneg == AUTONEG_ENABLE) {
685 cp->link_cntl = BMCR_ANENABLE;
686 } else {
687 u32 speed = ep->base.speed;
688 cp->link_cntl = 0;
689 if (speed == SPEED_100)
690 cp->link_cntl |= BMCR_SPEED100;
691 else if (speed == SPEED_1000)
692 cp->link_cntl |= CAS_BMCR_SPEED1000;
693 if (ep->base.duplex == DUPLEX_FULL)
694 cp->link_cntl |= BMCR_FULLDPLX;
695 }
696 #if 1
697 changed = (lcntl != cp->link_cntl);
698 #endif
699 start_aneg:
700 if (cp->lstate == link_up) {
701 netdev_info(cp->dev, "PCS link down\n");
702 } else {
703 if (changed) {
704 netdev_info(cp->dev, "link configuration changed\n");
705 }
706 }
707 cp->lstate = link_down;
708 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
709 if (!cp->hw_running)
710 return;
711 #if 1
712 /*
713 * WTZ: If the old state was link_up, we turn off the carrier
714 * to replicate everything we do elsewhere on a link-down
715 * event when we were already in a link-up state..
716 */
717 if (oldstate == link_up)
718 netif_carrier_off(cp->dev);
719 if (changed && link_was_not_down) {
720 /*
721 * WTZ: This branch will simply schedule a full reset after
722 * we explicitly changed link modes in an ioctl. See if this
723 * fixes the link-problems we were having for forced mode.
724 */
725 atomic_inc(&cp->reset_task_pending);
726 atomic_inc(&cp->reset_task_pending_all);
727 schedule_work(&cp->reset_task);
728 cp->timer_ticks = 0;
729 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
730 return;
731 }
732 #endif
733 if (cp->phy_type & CAS_PHY_SERDES) {
734 u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
735
736 if (cp->link_cntl & BMCR_ANENABLE) {
737 val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
738 cp->lstate = link_aneg;
739 } else {
740 if (cp->link_cntl & BMCR_FULLDPLX)
741 val |= PCS_MII_CTRL_DUPLEX;
742 val &= ~PCS_MII_AUTONEG_EN;
743 cp->lstate = link_force_ok;
744 }
745 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
746 writel(val, cp->regs + REG_PCS_MII_CTRL);
747
748 } else {
749 cas_mif_poll(cp, 0);
750 ctl = cas_phy_read(cp, MII_BMCR);
751 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
752 CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
753 ctl |= cp->link_cntl;
754 if (ctl & BMCR_ANENABLE) {
755 ctl |= BMCR_ANRESTART;
756 cp->lstate = link_aneg;
757 } else {
758 cp->lstate = link_force_ok;
759 }
760 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
761 cas_phy_write(cp, MII_BMCR, ctl);
762 cas_mif_poll(cp, 1);
763 }
764
765 cp->timer_ticks = 0;
766 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
767 }
768
769 /* Must be invoked under cp->lock. */
770 static int cas_reset_mii_phy(struct cas *cp)
771 {
772 int limit = STOP_TRIES_PHY;
773 u16 val;
774
775 cas_phy_write(cp, MII_BMCR, BMCR_RESET);
776 udelay(100);
777 while (--limit) {
778 val = cas_phy_read(cp, MII_BMCR);
779 if ((val & BMCR_RESET) == 0)
780 break;
781 udelay(10);
782 }
783 return limit <= 0;
784 }
785
786 static void cas_saturn_firmware_init(struct cas *cp)
787 {
788 const struct firmware *fw;
789 const char fw_name[] = "sun/cassini.bin";
790 int err;
791
792 if (PHY_NS_DP83065 != cp->phy_id)
793 return;
794
795 err = request_firmware(&fw, fw_name, &cp->pdev->dev);
796 if (err) {
797 pr_err("Failed to load firmware \"%s\"\n",
798 fw_name);
799 return;
800 }
801 if (fw->size < 2) {
802 pr_err("bogus length %zu in \"%s\"\n",
803 fw->size, fw_name);
804 goto out;
805 }
806 cp->fw_load_addr= fw->data[1] << 8 | fw->data[0];
807 cp->fw_size = fw->size - 2;
808 cp->fw_data = vmalloc(cp->fw_size);
809 if (!cp->fw_data)
810 goto out;
811 memcpy(cp->fw_data, &fw->data[2], cp->fw_size);
812 out:
813 release_firmware(fw);
814 }
815
816 static void cas_saturn_firmware_load(struct cas *cp)
817 {
818 int i;
819
820 if (!cp->fw_data)
821 return;
822
823 cas_phy_powerdown(cp);
824
825 /* expanded memory access mode */
826 cas_phy_write(cp, DP83065_MII_MEM, 0x0);
827
828 /* pointer configuration for new firmware */
829 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
830 cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
831 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
832 cas_phy_write(cp, DP83065_MII_REGD, 0x82);
833 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
834 cas_phy_write(cp, DP83065_MII_REGD, 0x0);
835 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
836 cas_phy_write(cp, DP83065_MII_REGD, 0x39);
837
838 /* download new firmware */
839 cas_phy_write(cp, DP83065_MII_MEM, 0x1);
840 cas_phy_write(cp, DP83065_MII_REGE, cp->fw_load_addr);
841 for (i = 0; i < cp->fw_size; i++)
842 cas_phy_write(cp, DP83065_MII_REGD, cp->fw_data[i]);
843
844 /* enable firmware */
845 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
846 cas_phy_write(cp, DP83065_MII_REGD, 0x1);
847 }
848
849
850 /* phy initialization */
851 static void cas_phy_init(struct cas *cp)
852 {
853 u16 val;
854
855 /* if we're in MII/GMII mode, set up phy */
856 if (CAS_PHY_MII(cp->phy_type)) {
857 writel(PCS_DATAPATH_MODE_MII,
858 cp->regs + REG_PCS_DATAPATH_MODE);
859
860 cas_mif_poll(cp, 0);
861 cas_reset_mii_phy(cp); /* take out of isolate mode */
862
863 if (PHY_LUCENT_B0 == cp->phy_id) {
864 /* workaround link up/down issue with lucent */
865 cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
866 cas_phy_write(cp, MII_BMCR, 0x00f1);
867 cas_phy_write(cp, LUCENT_MII_REG, 0x0);
868
869 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
870 /* workarounds for broadcom phy */
871 cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
872 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
873 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
874 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
875 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
876 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
877 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
878 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
879 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
880 cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
881 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
882
883 } else if (PHY_BROADCOM_5411 == cp->phy_id) {
884 val = cas_phy_read(cp, BROADCOM_MII_REG4);
885 val = cas_phy_read(cp, BROADCOM_MII_REG4);
886 if (val & 0x0080) {
887 /* link workaround */
888 cas_phy_write(cp, BROADCOM_MII_REG4,
889 val & ~0x0080);
890 }
891
892 } else if (cp->cas_flags & CAS_FLAG_SATURN) {
893 writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?
894 SATURN_PCFG_FSI : 0x0,
895 cp->regs + REG_SATURN_PCFG);
896
897 /* load firmware to address 10Mbps auto-negotiation
898 * issue. NOTE: this will need to be changed if the
899 * default firmware gets fixed.
900 */
901 if (PHY_NS_DP83065 == cp->phy_id) {
902 cas_saturn_firmware_load(cp);
903 }
904 cas_phy_powerup(cp);
905 }
906
907 /* advertise capabilities */
908 val = cas_phy_read(cp, MII_BMCR);
909 val &= ~BMCR_ANENABLE;
910 cas_phy_write(cp, MII_BMCR, val);
911 udelay(10);
912
913 cas_phy_write(cp, MII_ADVERTISE,
914 cas_phy_read(cp, MII_ADVERTISE) |
915 (ADVERTISE_10HALF | ADVERTISE_10FULL |
916 ADVERTISE_100HALF | ADVERTISE_100FULL |
917 CAS_ADVERTISE_PAUSE |
918 CAS_ADVERTISE_ASYM_PAUSE));
919
920 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
921 /* make sure that we don't advertise half
922 * duplex to avoid a chip issue
923 */
924 val = cas_phy_read(cp, CAS_MII_1000_CTRL);
925 val &= ~CAS_ADVERTISE_1000HALF;
926 val |= CAS_ADVERTISE_1000FULL;
927 cas_phy_write(cp, CAS_MII_1000_CTRL, val);
928 }
929
930 } else {
931 /* reset pcs for serdes */
932 u32 val;
933 int limit;
934
935 writel(PCS_DATAPATH_MODE_SERDES,
936 cp->regs + REG_PCS_DATAPATH_MODE);
937
938 /* enable serdes pins on saturn */
939 if (cp->cas_flags & CAS_FLAG_SATURN)
940 writel(0, cp->regs + REG_SATURN_PCFG);
941
942 /* Reset PCS unit. */
943 val = readl(cp->regs + REG_PCS_MII_CTRL);
944 val |= PCS_MII_RESET;
945 writel(val, cp->regs + REG_PCS_MII_CTRL);
946
947 limit = STOP_TRIES;
948 while (--limit > 0) {
949 udelay(10);
950 if ((readl(cp->regs + REG_PCS_MII_CTRL) &
951 PCS_MII_RESET) == 0)
952 break;
953 }
954 if (limit <= 0)
955 netdev_warn(cp->dev, "PCS reset bit would not clear [%08x]\n",
956 readl(cp->regs + REG_PCS_STATE_MACHINE));
957
958 /* Make sure PCS is disabled while changing advertisement
959 * configuration.
960 */
961 writel(0x0, cp->regs + REG_PCS_CFG);
962
963 /* Advertise all capabilities except half-duplex. */
964 val = readl(cp->regs + REG_PCS_MII_ADVERT);
965 val &= ~PCS_MII_ADVERT_HD;
966 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE |
967 PCS_MII_ADVERT_ASYM_PAUSE);
968 writel(val, cp->regs + REG_PCS_MII_ADVERT);
969
970 /* enable PCS */
971 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
972
973 /* pcs workaround: enable sync detect */
974 writel(PCS_SERDES_CTRL_SYNCD_EN,
975 cp->regs + REG_PCS_SERDES_CTRL);
976 }
977 }
978
979
980 static int cas_pcs_link_check(struct cas *cp)
981 {
982 u32 stat, state_machine;
983 int retval = 0;
984
985 /* The link status bit latches on zero, so you must
986 * read it twice in such a case to see a transition
987 * to the link being up.
988 */
989 stat = readl(cp->regs + REG_PCS_MII_STATUS);
990 if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
991 stat = readl(cp->regs + REG_PCS_MII_STATUS);
992
993 /* The remote-fault indication is only valid
994 * when autoneg has completed.
995 */
996 if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
997 PCS_MII_STATUS_REMOTE_FAULT)) ==
998 (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT))
999 netif_info(cp, link, cp->dev, "PCS RemoteFault\n");
1000
1001 /* work around link detection issue by querying the PCS state
1002 * machine directly.
1003 */
1004 state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
1005 if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
1006 stat &= ~PCS_MII_STATUS_LINK_STATUS;
1007 } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
1008 stat |= PCS_MII_STATUS_LINK_STATUS;
1009 }
1010
1011 if (stat & PCS_MII_STATUS_LINK_STATUS) {
1012 if (cp->lstate != link_up) {
1013 if (cp->opened) {
1014 cp->lstate = link_up;
1015 cp->link_transition = LINK_TRANSITION_LINK_UP;
1016
1017 cas_set_link_modes(cp);
1018 netif_carrier_on(cp->dev);
1019 }
1020 }
1021 } else if (cp->lstate == link_up) {
1022 cp->lstate = link_down;
1023 if (link_transition_timeout != 0 &&
1024 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1025 !cp->link_transition_jiffies_valid) {
1026 /*
1027 * force a reset, as a workaround for the
1028 * link-failure problem. May want to move this to a
1029 * point a bit earlier in the sequence. If we had
1030 * generated a reset a short time ago, we'll wait for
1031 * the link timer to check the status until a
1032 * timer expires (link_transistion_jiffies_valid is
1033 * true when the timer is running.) Instead of using
1034 * a system timer, we just do a check whenever the
1035 * link timer is running - this clears the flag after
1036 * a suitable delay.
1037 */
1038 retval = 1;
1039 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1040 cp->link_transition_jiffies = jiffies;
1041 cp->link_transition_jiffies_valid = 1;
1042 } else {
1043 cp->link_transition = LINK_TRANSITION_ON_FAILURE;
1044 }
1045 netif_carrier_off(cp->dev);
1046 if (cp->opened)
1047 netif_info(cp, link, cp->dev, "PCS link down\n");
1048
1049 /* Cassini only: if you force a mode, there can be
1050 * sync problems on link down. to fix that, the following
1051 * things need to be checked:
1052 * 1) read serialink state register
1053 * 2) read pcs status register to verify link down.
1054 * 3) if link down and serial link == 0x03, then you need
1055 * to global reset the chip.
1056 */
1057 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) {
1058 /* should check to see if we're in a forced mode */
1059 stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1060 if (stat == 0x03)
1061 return 1;
1062 }
1063 } else if (cp->lstate == link_down) {
1064 if (link_transition_timeout != 0 &&
1065 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1066 !cp->link_transition_jiffies_valid) {
1067 /* force a reset, as a workaround for the
1068 * link-failure problem. May want to move
1069 * this to a point a bit earlier in the
1070 * sequence.
1071 */
1072 retval = 1;
1073 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1074 cp->link_transition_jiffies = jiffies;
1075 cp->link_transition_jiffies_valid = 1;
1076 } else {
1077 cp->link_transition = LINK_TRANSITION_STILL_FAILED;
1078 }
1079 }
1080
1081 return retval;
1082 }
1083
1084 static int cas_pcs_interrupt(struct net_device *dev,
1085 struct cas *cp, u32 status)
1086 {
1087 u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1088
1089 if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
1090 return 0;
1091 return cas_pcs_link_check(cp);
1092 }
1093
1094 static int cas_txmac_interrupt(struct net_device *dev,
1095 struct cas *cp, u32 status)
1096 {
1097 u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS);
1098
1099 if (!txmac_stat)
1100 return 0;
1101
1102 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1103 "txmac interrupt, txmac_stat: 0x%x\n", txmac_stat);
1104
1105 /* Defer timer expiration is quite normal,
1106 * don't even log the event.
1107 */
1108 if ((txmac_stat & MAC_TX_DEFER_TIMER) &&
1109 !(txmac_stat & ~MAC_TX_DEFER_TIMER))
1110 return 0;
1111
1112 spin_lock(&cp->stat_lock[0]);
1113 if (txmac_stat & MAC_TX_UNDERRUN) {
1114 netdev_err(dev, "TX MAC xmit underrun\n");
1115 cp->net_stats[0].tx_fifo_errors++;
1116 }
1117
1118 if (txmac_stat & MAC_TX_MAX_PACKET_ERR) {
1119 netdev_err(dev, "TX MAC max packet size error\n");
1120 cp->net_stats[0].tx_errors++;
1121 }
1122
1123 /* The rest are all cases of one of the 16-bit TX
1124 * counters expiring.
1125 */
1126 if (txmac_stat & MAC_TX_COLL_NORMAL)
1127 cp->net_stats[0].collisions += 0x10000;
1128
1129 if (txmac_stat & MAC_TX_COLL_EXCESS) {
1130 cp->net_stats[0].tx_aborted_errors += 0x10000;
1131 cp->net_stats[0].collisions += 0x10000;
1132 }
1133
1134 if (txmac_stat & MAC_TX_COLL_LATE) {
1135 cp->net_stats[0].tx_aborted_errors += 0x10000;
1136 cp->net_stats[0].collisions += 0x10000;
1137 }
1138 spin_unlock(&cp->stat_lock[0]);
1139
1140 /* We do not keep track of MAC_TX_COLL_FIRST and
1141 * MAC_TX_PEAK_ATTEMPTS events.
1142 */
1143 return 0;
1144 }
1145
1146 static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware)
1147 {
1148 cas_hp_inst_t *inst;
1149 u32 val;
1150 int i;
1151
1152 i = 0;
1153 while ((inst = firmware) && inst->note) {
1154 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
1155
1156 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
1157 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
1158 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
1159
1160 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
1161 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
1162 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
1163 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
1164 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
1165 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
1166 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
1167 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
1168
1169 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
1170 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
1171 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
1172 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
1173 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
1174 ++firmware;
1175 ++i;
1176 }
1177 }
1178
1179 static void cas_init_rx_dma(struct cas *cp)
1180 {
1181 u64 desc_dma = cp->block_dvma;
1182 u32 val;
1183 int i, size;
1184
1185 /* rx free descriptors */
1186 val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);
1187 val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
1188 val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
1189 if ((N_RX_DESC_RINGS > 1) &&
1190 (cp->cas_flags & CAS_FLAG_REG_PLUS)) /* do desc 2 */
1191 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
1192 writel(val, cp->regs + REG_RX_CFG);
1193
1194 val = (unsigned long) cp->init_rxds[0] -
1195 (unsigned long) cp->init_block;
1196 writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
1197 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
1198 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
1199
1200 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1201 /* rx desc 2 is for IPSEC packets. however,
1202 * we don't it that for that purpose.
1203 */
1204 val = (unsigned long) cp->init_rxds[1] -
1205 (unsigned long) cp->init_block;
1206 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
1207 writel((desc_dma + val) & 0xffffffff, cp->regs +
1208 REG_PLUS_RX_DB1_LOW);
1209 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +
1210 REG_PLUS_RX_KICK1);
1211 }
1212
1213 /* rx completion registers */
1214 val = (unsigned long) cp->init_rxcs[0] -
1215 (unsigned long) cp->init_block;
1216 writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
1217 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
1218
1219 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1220 /* rx comp 2-4 */
1221 for (i = 1; i < MAX_RX_COMP_RINGS; i++) {
1222 val = (unsigned long) cp->init_rxcs[i] -
1223 (unsigned long) cp->init_block;
1224 writel((desc_dma + val) >> 32, cp->regs +
1225 REG_PLUS_RX_CBN_HI(i));
1226 writel((desc_dma + val) & 0xffffffff, cp->regs +
1227 REG_PLUS_RX_CBN_LOW(i));
1228 }
1229 }
1230
1231 /* read selective clear regs to prevent spurious interrupts
1232 * on reset because complete == kick.
1233 * selective clear set up to prevent interrupts on resets
1234 */
1235 readl(cp->regs + REG_INTR_STATUS_ALIAS);
1236 writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
1237
1238 /* set up pause thresholds */
1239 val = CAS_BASE(RX_PAUSE_THRESH_OFF,
1240 cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);
1241 val |= CAS_BASE(RX_PAUSE_THRESH_ON,
1242 cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);
1243 writel(val, cp->regs + REG_RX_PAUSE_THRESH);
1244
1245 /* zero out dma reassembly buffers */
1246 for (i = 0; i < 64; i++) {
1247 writel(i, cp->regs + REG_RX_TABLE_ADDR);
1248 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
1249 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
1250 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
1251 }
1252
1253 /* make sure address register is 0 for normal operation */
1254 writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
1255 writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
1256
1257 /* interrupt mitigation */
1258 #ifdef USE_RX_BLANK
1259 val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
1260 val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
1261 writel(val, cp->regs + REG_RX_BLANK);
1262 #else
1263 writel(0x0, cp->regs + REG_RX_BLANK);
1264 #endif
1265
1266 /* interrupt generation as a function of low water marks for
1267 * free desc and completion entries. these are used to trigger
1268 * housekeeping for rx descs. we don't use the free interrupt
1269 * as it's not very useful
1270 */
1271 /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */
1272 val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
1273 writel(val, cp->regs + REG_RX_AE_THRESH);
1274 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1275 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
1276 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
1277 }
1278
1279 /* Random early detect registers. useful for congestion avoidance.
1280 * this should be tunable.
1281 */
1282 writel(0x0, cp->regs + REG_RX_RED);
1283
1284 /* receive page sizes. default == 2K (0x800) */
1285 val = 0;
1286 if (cp->page_size == 0x1000)
1287 val = 0x1;
1288 else if (cp->page_size == 0x2000)
1289 val = 0x2;
1290 else if (cp->page_size == 0x4000)
1291 val = 0x3;
1292
1293 /* round mtu + offset. constrain to page size. */
1294 size = cp->dev->mtu + 64;
1295 if (size > cp->page_size)
1296 size = cp->page_size;
1297
1298 if (size <= 0x400)
1299 i = 0x0;
1300 else if (size <= 0x800)
1301 i = 0x1;
1302 else if (size <= 0x1000)
1303 i = 0x2;
1304 else
1305 i = 0x3;
1306
1307 cp->mtu_stride = 1 << (i + 10);
1308 val = CAS_BASE(RX_PAGE_SIZE, val);
1309 val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);
1310 val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
1311 val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
1312 writel(val, cp->regs + REG_RX_PAGE_SIZE);
1313
1314 /* enable the header parser if desired */
1315 if (&CAS_HP_FIRMWARE[0] == &cas_prog_null[0])
1316 return;
1317
1318 val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
1319 val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
1320 val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
1321 writel(val, cp->regs + REG_HP_CFG);
1322 }
1323
1324 static inline void cas_rxc_init(struct cas_rx_comp *rxc)
1325 {
1326 memset(rxc, 0, sizeof(*rxc));
1327 rxc->word4 = cpu_to_le64(RX_COMP4_ZERO);
1328 }
1329
1330 /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1]
1331 * flipping is protected by the fact that the chip will not
1332 * hand back the same page index while it's being processed.
1333 */
1334 static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
1335 {
1336 cas_page_t *page = cp->rx_pages[1][index];
1337 cas_page_t *new;
1338
1339 if (page_count(page->buffer) == 1)
1340 return page;
1341
1342 new = cas_page_dequeue(cp);
1343 if (new) {
1344 spin_lock(&cp->rx_inuse_lock);
1345 list_add(&page->list, &cp->rx_inuse_list);
1346 spin_unlock(&cp->rx_inuse_lock);
1347 }
1348 return new;
1349 }
1350
1351 /* this needs to be changed if we actually use the ENC RX DESC ring */
1352 static cas_page_t *cas_page_swap(struct cas *cp, const int ring,
1353 const int index)
1354 {
1355 cas_page_t **page0 = cp->rx_pages[0];
1356 cas_page_t **page1 = cp->rx_pages[1];
1357
1358 /* swap if buffer is in use */
1359 if (page_count(page0[index]->buffer) > 1) {
1360 cas_page_t *new = cas_page_spare(cp, index);
1361 if (new) {
1362 page1[index] = page0[index];
1363 page0[index] = new;
1364 }
1365 }
1366 RX_USED_SET(page0[index], 0);
1367 return page0[index];
1368 }
1369
1370 static void cas_clean_rxds(struct cas *cp)
1371 {
1372 /* only clean ring 0 as ring 1 is used for spare buffers */
1373 struct cas_rx_desc *rxd = cp->init_rxds[0];
1374 int i, size;
1375
1376 /* release all rx flows */
1377 for (i = 0; i < N_RX_FLOWS; i++) {
1378 struct sk_buff *skb;
1379 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) {
1380 cas_skb_release(skb);
1381 }
1382 }
1383
1384 /* initialize descriptors */
1385 size = RX_DESC_RINGN_SIZE(0);
1386 for (i = 0; i < size; i++) {
1387 cas_page_t *page = cas_page_swap(cp, 0, i);
1388 rxd[i].buffer = cpu_to_le64(page->dma_addr);
1389 rxd[i].index = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) |
1390 CAS_BASE(RX_INDEX_RING, 0));
1391 }
1392
1393 cp->rx_old[0] = RX_DESC_RINGN_SIZE(0) - 4;
1394 cp->rx_last[0] = 0;
1395 cp->cas_flags &= ~CAS_FLAG_RXD_POST(0);
1396 }
1397
1398 static void cas_clean_rxcs(struct cas *cp)
1399 {
1400 int i, j;
1401
1402 /* take ownership of rx comp descriptors */
1403 memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS);
1404 memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS);
1405 for (i = 0; i < N_RX_COMP_RINGS; i++) {
1406 struct cas_rx_comp *rxc = cp->init_rxcs[i];
1407 for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) {
1408 cas_rxc_init(rxc + j);
1409 }
1410 }
1411 }
1412
1413 #if 0
1414 /* When we get a RX fifo overflow, the RX unit is probably hung
1415 * so we do the following.
1416 *
1417 * If any part of the reset goes wrong, we return 1 and that causes the
1418 * whole chip to be reset.
1419 */
1420 static int cas_rxmac_reset(struct cas *cp)
1421 {
1422 struct net_device *dev = cp->dev;
1423 int limit;
1424 u32 val;
1425
1426 /* First, reset MAC RX. */
1427 writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1428 for (limit = 0; limit < STOP_TRIES; limit++) {
1429 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
1430 break;
1431 udelay(10);
1432 }
1433 if (limit == STOP_TRIES) {
1434 netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
1435 return 1;
1436 }
1437
1438 /* Second, disable RX DMA. */
1439 writel(0, cp->regs + REG_RX_CFG);
1440 for (limit = 0; limit < STOP_TRIES; limit++) {
1441 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
1442 break;
1443 udelay(10);
1444 }
1445 if (limit == STOP_TRIES) {
1446 netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
1447 return 1;
1448 }
1449
1450 mdelay(5);
1451
1452 /* Execute RX reset command. */
1453 writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1454 for (limit = 0; limit < STOP_TRIES; limit++) {
1455 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
1456 break;
1457 udelay(10);
1458 }
1459 if (limit == STOP_TRIES) {
1460 netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
1461 return 1;
1462 }
1463
1464 /* reset driver rx state */
1465 cas_clean_rxds(cp);
1466 cas_clean_rxcs(cp);
1467
1468 /* Now, reprogram the rest of RX unit. */
1469 cas_init_rx_dma(cp);
1470
1471 /* re-enable */
1472 val = readl(cp->regs + REG_RX_CFG);
1473 writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1474 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1475 val = readl(cp->regs + REG_MAC_RX_CFG);
1476 writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1477 return 0;
1478 }
1479 #endif
1480
1481 static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp,
1482 u32 status)
1483 {
1484 u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1485
1486 if (!stat)
1487 return 0;
1488
1489 netif_dbg(cp, intr, cp->dev, "rxmac interrupt, stat: 0x%x\n", stat);
1490
1491 /* these are all rollovers */
1492 spin_lock(&cp->stat_lock[0]);
1493 if (stat & MAC_RX_ALIGN_ERR)
1494 cp->net_stats[0].rx_frame_errors += 0x10000;
1495
1496 if (stat & MAC_RX_CRC_ERR)
1497 cp->net_stats[0].rx_crc_errors += 0x10000;
1498
1499 if (stat & MAC_RX_LEN_ERR)
1500 cp->net_stats[0].rx_length_errors += 0x10000;
1501
1502 if (stat & MAC_RX_OVERFLOW) {
1503 cp->net_stats[0].rx_over_errors++;
1504 cp->net_stats[0].rx_fifo_errors++;
1505 }
1506
1507 /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR
1508 * events.
1509 */
1510 spin_unlock(&cp->stat_lock[0]);
1511 return 0;
1512 }
1513
1514 static int cas_mac_interrupt(struct net_device *dev, struct cas *cp,
1515 u32 status)
1516 {
1517 u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1518
1519 if (!stat)
1520 return 0;
1521
1522 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1523 "mac interrupt, stat: 0x%x\n", stat);
1524
1525 /* This interrupt is just for pause frame and pause
1526 * tracking. It is useful for diagnostics and debug
1527 * but probably by default we will mask these events.
1528 */
1529 if (stat & MAC_CTRL_PAUSE_STATE)
1530 cp->pause_entered++;
1531
1532 if (stat & MAC_CTRL_PAUSE_RECEIVED)
1533 cp->pause_last_time_recvd = (stat >> 16);
1534
1535 return 0;
1536 }
1537
1538
1539 /* Must be invoked under cp->lock. */
1540 static inline int cas_mdio_link_not_up(struct cas *cp)
1541 {
1542 u16 val;
1543
1544 switch (cp->lstate) {
1545 case link_force_ret:
1546 netif_info(cp, link, cp->dev, "Autoneg failed again, keeping forced mode\n");
1547 cas_phy_write(cp, MII_BMCR, cp->link_fcntl);
1548 cp->timer_ticks = 5;
1549 cp->lstate = link_force_ok;
1550 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1551 break;
1552
1553 case link_aneg:
1554 val = cas_phy_read(cp, MII_BMCR);
1555
1556 /* Try forced modes. we try things in the following order:
1557 * 1000 full -> 100 full/half -> 10 half
1558 */
1559 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
1560 val |= BMCR_FULLDPLX;
1561 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
1562 CAS_BMCR_SPEED1000 : BMCR_SPEED100;
1563 cas_phy_write(cp, MII_BMCR, val);
1564 cp->timer_ticks = 5;
1565 cp->lstate = link_force_try;
1566 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1567 break;
1568
1569 case link_force_try:
1570 /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */
1571 val = cas_phy_read(cp, MII_BMCR);
1572 cp->timer_ticks = 5;
1573 if (val & CAS_BMCR_SPEED1000) { /* gigabit */
1574 val &= ~CAS_BMCR_SPEED1000;
1575 val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
1576 cas_phy_write(cp, MII_BMCR, val);
1577 break;
1578 }
1579
1580 if (val & BMCR_SPEED100) {
1581 if (val & BMCR_FULLDPLX) /* fd failed */
1582 val &= ~BMCR_FULLDPLX;
1583 else { /* 100Mbps failed */
1584 val &= ~BMCR_SPEED100;
1585 }
1586 cas_phy_write(cp, MII_BMCR, val);
1587 break;
1588 }
1589 break;
1590 default:
1591 break;
1592 }
1593 return 0;
1594 }
1595
1596
1597 /* must be invoked with cp->lock held */
1598 static int cas_mii_link_check(struct cas *cp, const u16 bmsr)
1599 {
1600 int restart;
1601
1602 if (bmsr & BMSR_LSTATUS) {
1603 /* Ok, here we got a link. If we had it due to a forced
1604 * fallback, and we were configured for autoneg, we
1605 * retry a short autoneg pass. If you know your hub is
1606 * broken, use ethtool ;)
1607 */
1608 if ((cp->lstate == link_force_try) &&
1609 (cp->link_cntl & BMCR_ANENABLE)) {
1610 cp->lstate = link_force_ret;
1611 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1612 cas_mif_poll(cp, 0);
1613 cp->link_fcntl = cas_phy_read(cp, MII_BMCR);
1614 cp->timer_ticks = 5;
1615 if (cp->opened)
1616 netif_info(cp, link, cp->dev,
1617 "Got link after fallback, retrying autoneg once...\n");
1618 cas_phy_write(cp, MII_BMCR,
1619 cp->link_fcntl | BMCR_ANENABLE |
1620 BMCR_ANRESTART);
1621 cas_mif_poll(cp, 1);
1622
1623 } else if (cp->lstate != link_up) {
1624 cp->lstate = link_up;
1625 cp->link_transition = LINK_TRANSITION_LINK_UP;
1626
1627 if (cp->opened) {
1628 cas_set_link_modes(cp);
1629 netif_carrier_on(cp->dev);
1630 }
1631 }
1632 return 0;
1633 }
1634
1635 /* link not up. if the link was previously up, we restart the
1636 * whole process
1637 */
1638 restart = 0;
1639 if (cp->lstate == link_up) {
1640 cp->lstate = link_down;
1641 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
1642
1643 netif_carrier_off(cp->dev);
1644 if (cp->opened)
1645 netif_info(cp, link, cp->dev, "Link down\n");
1646 restart = 1;
1647
1648 } else if (++cp->timer_ticks > 10)
1649 cas_mdio_link_not_up(cp);
1650
1651 return restart;
1652 }
1653
1654 static int cas_mif_interrupt(struct net_device *dev, struct cas *cp,
1655 u32 status)
1656 {
1657 u32 stat = readl(cp->regs + REG_MIF_STATUS);
1658 u16 bmsr;
1659
1660 /* check for a link change */
1661 if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1662 return 0;
1663
1664 bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1665 return cas_mii_link_check(cp, bmsr);
1666 }
1667
1668 static int cas_pci_interrupt(struct net_device *dev, struct cas *cp,
1669 u32 status)
1670 {
1671 u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1672
1673 if (!stat)
1674 return 0;
1675
1676 netdev_err(dev, "PCI error [%04x:%04x]",
1677 stat, readl(cp->regs + REG_BIM_DIAG));
1678
1679 /* cassini+ has this reserved */
1680 if ((stat & PCI_ERR_BADACK) &&
1681 ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0))
1682 pr_cont(" <No ACK64# during ABS64 cycle>");
1683
1684 if (stat & PCI_ERR_DTRTO)
1685 pr_cont(" <Delayed transaction timeout>");
1686 if (stat & PCI_ERR_OTHER)
1687 pr_cont(" <other>");
1688 if (stat & PCI_ERR_BIM_DMA_WRITE)
1689 pr_cont(" <BIM DMA 0 write req>");
1690 if (stat & PCI_ERR_BIM_DMA_READ)
1691 pr_cont(" <BIM DMA 0 read req>");
1692 pr_cont("\n");
1693
1694 if (stat & PCI_ERR_OTHER) {
1695 int pci_errs;
1696
1697 /* Interrogate PCI config space for the
1698 * true cause.
1699 */
1700 pci_errs = pci_status_get_and_clear_errors(cp->pdev);
1701
1702 netdev_err(dev, "PCI status errors[%04x]\n", pci_errs);
1703 if (pci_errs & PCI_STATUS_PARITY)
1704 netdev_err(dev, "PCI parity error detected\n");
1705 if (pci_errs & PCI_STATUS_SIG_TARGET_ABORT)
1706 netdev_err(dev, "PCI target abort\n");
1707 if (pci_errs & PCI_STATUS_REC_TARGET_ABORT)
1708 netdev_err(dev, "PCI master acks target abort\n");
1709 if (pci_errs & PCI_STATUS_REC_MASTER_ABORT)
1710 netdev_err(dev, "PCI master abort\n");
1711 if (pci_errs & PCI_STATUS_SIG_SYSTEM_ERROR)
1712 netdev_err(dev, "PCI system error SERR#\n");
1713 if (pci_errs & PCI_STATUS_DETECTED_PARITY)
1714 netdev_err(dev, "PCI parity error\n");
1715 }
1716
1717 /* For all PCI errors, we should reset the chip. */
1718 return 1;
1719 }
1720
1721 /* All non-normal interrupt conditions get serviced here.
1722 * Returns non-zero if we should just exit the interrupt
1723 * handler right now (ie. if we reset the card which invalidates
1724 * all of the other original irq status bits).
1725 */
1726 static int cas_abnormal_irq(struct net_device *dev, struct cas *cp,
1727 u32 status)
1728 {
1729 if (status & INTR_RX_TAG_ERROR) {
1730 /* corrupt RX tag framing */
1731 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
1732 "corrupt rx tag framing\n");
1733 spin_lock(&cp->stat_lock[0]);
1734 cp->net_stats[0].rx_errors++;
1735 spin_unlock(&cp->stat_lock[0]);
1736 goto do_reset;
1737 }
1738
1739 if (status & INTR_RX_LEN_MISMATCH) {
1740 /* length mismatch. */
1741 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
1742 "length mismatch for rx frame\n");
1743 spin_lock(&cp->stat_lock[0]);
1744 cp->net_stats[0].rx_errors++;
1745 spin_unlock(&cp->stat_lock[0]);
1746 goto do_reset;
1747 }
1748
1749 if (status & INTR_PCS_STATUS) {
1750 if (cas_pcs_interrupt(dev, cp, status))
1751 goto do_reset;
1752 }
1753
1754 if (status & INTR_TX_MAC_STATUS) {
1755 if (cas_txmac_interrupt(dev, cp, status))
1756 goto do_reset;
1757 }
1758
1759 if (status & INTR_RX_MAC_STATUS) {
1760 if (cas_rxmac_interrupt(dev, cp, status))
1761 goto do_reset;
1762 }
1763
1764 if (status & INTR_MAC_CTRL_STATUS) {
1765 if (cas_mac_interrupt(dev, cp, status))
1766 goto do_reset;
1767 }
1768
1769 if (status & INTR_MIF_STATUS) {
1770 if (cas_mif_interrupt(dev, cp, status))
1771 goto do_reset;
1772 }
1773
1774 if (status & INTR_PCI_ERROR_STATUS) {
1775 if (cas_pci_interrupt(dev, cp, status))
1776 goto do_reset;
1777 }
1778 return 0;
1779
1780 do_reset:
1781 #if 1
1782 atomic_inc(&cp->reset_task_pending);
1783 atomic_inc(&cp->reset_task_pending_all);
1784 netdev_err(dev, "reset called in cas_abnormal_irq [0x%x]\n", status);
1785 schedule_work(&cp->reset_task);
1786 #else
1787 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
1788 netdev_err(dev, "reset called in cas_abnormal_irq\n");
1789 schedule_work(&cp->reset_task);
1790 #endif
1791 return 1;
1792 }
1793
1794 /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when
1795 * determining whether to do a netif_stop/wakeup
1796 */
1797 #define CAS_TABORT(x) (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
1798 #define CAS_ROUND_PAGE(x) (((x) + PAGE_SIZE - 1) & PAGE_MASK)
1799 static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr,
1800 const int len)
1801 {
1802 unsigned long off = addr + len;
1803
1804 if (CAS_TABORT(cp) == 1)
1805 return 0;
1806 if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN)
1807 return 0;
1808 return TX_TARGET_ABORT_LEN;
1809 }
1810
1811 static inline void cas_tx_ringN(struct cas *cp, int ring, int limit)
1812 {
1813 struct cas_tx_desc *txds;
1814 struct sk_buff **skbs;
1815 struct net_device *dev = cp->dev;
1816 int entry, count;
1817
1818 spin_lock(&cp->tx_lock[ring]);
1819 txds = cp->init_txds[ring];
1820 skbs = cp->tx_skbs[ring];
1821 entry = cp->tx_old[ring];
1822
1823 count = TX_BUFF_COUNT(ring, entry, limit);
1824 while (entry != limit) {
1825 struct sk_buff *skb = skbs[entry];
1826 dma_addr_t daddr;
1827 u32 dlen;
1828 int frag;
1829
1830 if (!skb) {
1831 /* this should never occur */
1832 entry = TX_DESC_NEXT(ring, entry);
1833 continue;
1834 }
1835
1836 /* however, we might get only a partial skb release. */
1837 count -= skb_shinfo(skb)->nr_frags +
1838 + cp->tx_tiny_use[ring][entry].nbufs + 1;
1839 if (count < 0)
1840 break;
1841
1842 netif_printk(cp, tx_done, KERN_DEBUG, cp->dev,
1843 "tx[%d] done, slot %d\n", ring, entry);
1844
1845 skbs[entry] = NULL;
1846 cp->tx_tiny_use[ring][entry].nbufs = 0;
1847
1848 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1849 struct cas_tx_desc *txd = txds + entry;
1850
1851 daddr = le64_to_cpu(txd->buffer);
1852 dlen = CAS_VAL(TX_DESC_BUFLEN,
1853 le64_to_cpu(txd->control));
1854 dma_unmap_page(&cp->pdev->dev, daddr, dlen,
1855 DMA_TO_DEVICE);
1856 entry = TX_DESC_NEXT(ring, entry);
1857
1858 /* tiny buffer may follow */
1859 if (cp->tx_tiny_use[ring][entry].used) {
1860 cp->tx_tiny_use[ring][entry].used = 0;
1861 entry = TX_DESC_NEXT(ring, entry);
1862 }
1863 }
1864
1865 spin_lock(&cp->stat_lock[ring]);
1866 cp->net_stats[ring].tx_packets++;
1867 cp->net_stats[ring].tx_bytes += skb->len;
1868 spin_unlock(&cp->stat_lock[ring]);
1869 dev_consume_skb_irq(skb);
1870 }
1871 cp->tx_old[ring] = entry;
1872
1873 /* this is wrong for multiple tx rings. the net device needs
1874 * multiple queues for this to do the right thing. we wait
1875 * for 2*packets to be available when using tiny buffers
1876 */
1877 if (netif_queue_stopped(dev) &&
1878 (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)))
1879 netif_wake_queue(dev);
1880 spin_unlock(&cp->tx_lock[ring]);
1881 }
1882
1883 static void cas_tx(struct net_device *dev, struct cas *cp,
1884 u32 status)
1885 {
1886 int limit, ring;
1887 #ifdef USE_TX_COMPWB
1888 u64 compwb = le64_to_cpu(cp->init_block->tx_compwb);
1889 #endif
1890 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1891 "tx interrupt, status: 0x%x, %llx\n",
1892 status, (unsigned long long)compwb);
1893 /* process all the rings */
1894 for (ring = 0; ring < N_TX_RINGS; ring++) {
1895 #ifdef USE_TX_COMPWB
1896 /* use the completion writeback registers */
1897 limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) |
1898 CAS_VAL(TX_COMPWB_LSB, compwb);
1899 compwb = TX_COMPWB_NEXT(compwb);
1900 #else
1901 limit = readl(cp->regs + REG_TX_COMPN(ring));
1902 #endif
1903 if (cp->tx_old[ring] != limit)
1904 cas_tx_ringN(cp, ring, limit);
1905 }
1906 }
1907
1908
1909 static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
1910 int entry, const u64 *words,
1911 struct sk_buff **skbref)
1912 {
1913 int dlen, hlen, len, i, alloclen;
1914 int off, swivel = RX_SWIVEL_OFF_VAL;
1915 struct cas_page *page;
1916 struct sk_buff *skb;
1917 void *crcaddr;
1918 __sum16 csum;
1919 char *p;
1920
1921 hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
1922 dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]);
1923 len = hlen + dlen;
1924
1925 if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT))
1926 alloclen = len;
1927 else
1928 alloclen = max(hlen, RX_COPY_MIN);
1929
1930 skb = netdev_alloc_skb(cp->dev, alloclen + swivel + cp->crc_size);
1931 if (skb == NULL)
1932 return -1;
1933
1934 *skbref = skb;
1935 skb_reserve(skb, swivel);
1936
1937 p = skb->data;
1938 crcaddr = NULL;
1939 if (hlen) { /* always copy header pages */
1940 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
1941 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
1942 off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 +
1943 swivel;
1944
1945 i = hlen;
1946 if (!dlen) /* attach FCS */
1947 i += cp->crc_size;
1948 dma_sync_single_for_cpu(&cp->pdev->dev, page->dma_addr + off,
1949 i, DMA_FROM_DEVICE);
1950 memcpy(p, page_address(page->buffer) + off, i);
1951 dma_sync_single_for_device(&cp->pdev->dev,
1952 page->dma_addr + off, i,
1953 DMA_FROM_DEVICE);
1954 RX_USED_ADD(page, 0x100);
1955 p += hlen;
1956 swivel = 0;
1957 }
1958
1959
1960 if (alloclen < (hlen + dlen)) {
1961 skb_frag_t *frag = skb_shinfo(skb)->frags;
1962
1963 /* normal or jumbo packets. we use frags */
1964 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
1965 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
1966 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
1967
1968 hlen = min(cp->page_size - off, dlen);
1969 if (hlen < 0) {
1970 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
1971 "rx page overflow: %d\n", hlen);
1972 dev_kfree_skb_irq(skb);
1973 return -1;
1974 }
1975 i = hlen;
1976 if (i == dlen) /* attach FCS */
1977 i += cp->crc_size;
1978 dma_sync_single_for_cpu(&cp->pdev->dev, page->dma_addr + off,
1979 i, DMA_FROM_DEVICE);
1980
1981 /* make sure we always copy a header */
1982 swivel = 0;
1983 if (p == (char *) skb->data) { /* not split */
1984 memcpy(p, page_address(page->buffer) + off,
1985 RX_COPY_MIN);
1986 dma_sync_single_for_device(&cp->pdev->dev,
1987 page->dma_addr + off, i,
1988 DMA_FROM_DEVICE);
1989 off += RX_COPY_MIN;
1990 swivel = RX_COPY_MIN;
1991 RX_USED_ADD(page, cp->mtu_stride);
1992 } else {
1993 RX_USED_ADD(page, hlen);
1994 }
1995 skb_put(skb, alloclen);
1996
1997 skb_shinfo(skb)->nr_frags++;
1998 skb->data_len += hlen - swivel;
1999 skb->truesize += hlen - swivel;
2000 skb->len += hlen - swivel;
2001
2002 skb_frag_fill_page_desc(frag, page->buffer, off, hlen - swivel);
2003 __skb_frag_ref(frag);
2004
2005 /* any more data? */
2006 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2007 hlen = dlen;
2008 off = 0;
2009
2010 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2011 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2012 dma_sync_single_for_cpu(&cp->pdev->dev,
2013 page->dma_addr,
2014 hlen + cp->crc_size,
2015 DMA_FROM_DEVICE);
2016 dma_sync_single_for_device(&cp->pdev->dev,
2017 page->dma_addr,
2018 hlen + cp->crc_size,
2019 DMA_FROM_DEVICE);
2020
2021 skb_shinfo(skb)->nr_frags++;
2022 skb->data_len += hlen;
2023 skb->len += hlen;
2024 frag++;
2025
2026 skb_frag_fill_page_desc(frag, page->buffer, 0, hlen);
2027 __skb_frag_ref(frag);
2028 RX_USED_ADD(page, hlen + cp->crc_size);
2029 }
2030
2031 if (cp->crc_size)
2032 crcaddr = page_address(page->buffer) + off + hlen;
2033
2034 } else {
2035 /* copying packet */
2036 if (!dlen)
2037 goto end_copy_pkt;
2038
2039 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2040 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2041 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2042 hlen = min(cp->page_size - off, dlen);
2043 if (hlen < 0) {
2044 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
2045 "rx page overflow: %d\n", hlen);
2046 dev_kfree_skb_irq(skb);
2047 return -1;
2048 }
2049 i = hlen;
2050 if (i == dlen) /* attach FCS */
2051 i += cp->crc_size;
2052 dma_sync_single_for_cpu(&cp->pdev->dev, page->dma_addr + off,
2053 i, DMA_FROM_DEVICE);
2054 memcpy(p, page_address(page->buffer) + off, i);
2055 dma_sync_single_for_device(&cp->pdev->dev,
2056 page->dma_addr + off, i,
2057 DMA_FROM_DEVICE);
2058 if (p == (char *) skb->data) /* not split */
2059 RX_USED_ADD(page, cp->mtu_stride);
2060 else
2061 RX_USED_ADD(page, i);
2062
2063 /* any more data? */
2064 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2065 p += hlen;
2066 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2067 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2068 dma_sync_single_for_cpu(&cp->pdev->dev,
2069 page->dma_addr,
2070 dlen + cp->crc_size,
2071 DMA_FROM_DEVICE);
2072 memcpy(p, page_address(page->buffer), dlen + cp->crc_size);
2073 dma_sync_single_for_device(&cp->pdev->dev,
2074 page->dma_addr,
2075 dlen + cp->crc_size,
2076 DMA_FROM_DEVICE);
2077 RX_USED_ADD(page, dlen + cp->crc_size);
2078 }
2079 end_copy_pkt:
2080 if (cp->crc_size)
2081 crcaddr = skb->data + alloclen;
2082
2083 skb_put(skb, alloclen);
2084 }
2085
2086 csum = (__force __sum16)htons(CAS_VAL(RX_COMP4_TCP_CSUM, words[3]));
2087 if (cp->crc_size) {
2088 /* checksum includes FCS. strip it out. */
2089 csum = csum_fold(csum_partial(crcaddr, cp->crc_size,
2090 csum_unfold(csum)));
2091 }
2092 skb->protocol = eth_type_trans(skb, cp->dev);
2093 if (skb->protocol == htons(ETH_P_IP)) {
2094 skb->csum = csum_unfold(~csum);
2095 skb->ip_summed = CHECKSUM_COMPLETE;
2096 } else
2097 skb_checksum_none_assert(skb);
2098 return len;
2099 }
2100
2101
2102 /* we can handle up to 64 rx flows at a time. we do the same thing
2103 * as nonreassm except that we batch up the buffers.
2104 * NOTE: we currently just treat each flow as a bunch of packets that
2105 * we pass up. a better way would be to coalesce the packets
2106 * into a jumbo packet. to do that, we need to do the following:
2107 * 1) the first packet will have a clean split between header and
2108 * data. save both.
2109 * 2) each time the next flow packet comes in, extend the
2110 * data length and merge the checksums.
2111 * 3) on flow release, fix up the header.
2112 * 4) make sure the higher layer doesn't care.
2113 * because packets get coalesced, we shouldn't run into fragment count
2114 * issues.
2115 */
2116 static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words,
2117 struct sk_buff *skb)
2118 {
2119 int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1);
2120 struct sk_buff_head *flow = &cp->rx_flows[flowid];
2121
2122 /* this is protected at a higher layer, so no need to
2123 * do any additional locking here. stick the buffer
2124 * at the end.
2125 */
2126 __skb_queue_tail(flow, skb);
2127 if (words[0] & RX_COMP1_RELEASE_FLOW) {
2128 while ((skb = __skb_dequeue(flow))) {
2129 cas_skb_release(skb);
2130 }
2131 }
2132 }
2133
2134 /* put rx descriptor back on ring. if a buffer is in use by a higher
2135 * layer, this will need to put in a replacement.
2136 */
2137 static void cas_post_page(struct cas *cp, const int ring, const int index)
2138 {
2139 cas_page_t *new;
2140 int entry;
2141
2142 entry = cp->rx_old[ring];
2143
2144 new = cas_page_swap(cp, ring, index);
2145 cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr);
2146 cp->init_rxds[ring][entry].index =
2147 cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) |
2148 CAS_BASE(RX_INDEX_RING, ring));
2149
2150 entry = RX_DESC_ENTRY(ring, entry + 1);
2151 cp->rx_old[ring] = entry;
2152
2153 if (entry % 4)
2154 return;
2155
2156 if (ring == 0)
2157 writel(entry, cp->regs + REG_RX_KICK);
2158 else if ((N_RX_DESC_RINGS > 1) &&
2159 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2160 writel(entry, cp->regs + REG_PLUS_RX_KICK1);
2161 }
2162
2163
2164 /* only when things are bad */
2165 static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
2166 {
2167 unsigned int entry, last, count, released;
2168 int cluster;
2169 cas_page_t **page = cp->rx_pages[ring];
2170
2171 entry = cp->rx_old[ring];
2172
2173 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
2174 "rxd[%d] interrupt, done: %d\n", ring, entry);
2175
2176 cluster = -1;
2177 count = entry & 0x3;
2178 last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4);
2179 released = 0;
2180 while (entry != last) {
2181 /* make a new buffer if it's still in use */
2182 if (page_count(page[entry]->buffer) > 1) {
2183 cas_page_t *new = cas_page_dequeue(cp);
2184 if (!new) {
2185 /* let the timer know that we need to
2186 * do this again
2187 */
2188 cp->cas_flags |= CAS_FLAG_RXD_POST(ring);
2189 if (!timer_pending(&cp->link_timer))
2190 mod_timer(&cp->link_timer, jiffies +
2191 CAS_LINK_FAST_TIMEOUT);
2192 cp->rx_old[ring] = entry;
2193 cp->rx_last[ring] = num ? num - released : 0;
2194 return -ENOMEM;
2195 }
2196 spin_lock(&cp->rx_inuse_lock);
2197 list_add(&page[entry]->list, &cp->rx_inuse_list);
2198 spin_unlock(&cp->rx_inuse_lock);
2199 cp->init_rxds[ring][entry].buffer =
2200 cpu_to_le64(new->dma_addr);
2201 page[entry] = new;
2202
2203 }
2204
2205 if (++count == 4) {
2206 cluster = entry;
2207 count = 0;
2208 }
2209 released++;
2210 entry = RX_DESC_ENTRY(ring, entry + 1);
2211 }
2212 cp->rx_old[ring] = entry;
2213
2214 if (cluster < 0)
2215 return 0;
2216
2217 if (ring == 0)
2218 writel(cluster, cp->regs + REG_RX_KICK);
2219 else if ((N_RX_DESC_RINGS > 1) &&
2220 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2221 writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
2222 return 0;
2223 }
2224
2225
2226 /* process a completion ring. packets are set up in three basic ways:
2227 * small packets: should be copied header + data in single buffer.
2228 * large packets: header and data in a single buffer.
2229 * split packets: header in a separate buffer from data.
2230 * data may be in multiple pages. data may be > 256
2231 * bytes but in a single page.
2232 *
2233 * NOTE: RX page posting is done in this routine as well. while there's
2234 * the capability of using multiple RX completion rings, it isn't
2235 * really worthwhile due to the fact that the page posting will
2236 * force serialization on the single descriptor ring.
2237 */
2238 static int cas_rx_ringN(struct cas *cp, int ring, int budget)
2239 {
2240 struct cas_rx_comp *rxcs = cp->init_rxcs[ring];
2241 int entry, drops;
2242 int npackets = 0;
2243
2244 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
2245 "rx[%d] interrupt, done: %d/%d\n",
2246 ring,
2247 readl(cp->regs + REG_RX_COMP_HEAD), cp->rx_new[ring]);
2248
2249 entry = cp->rx_new[ring];
2250 drops = 0;
2251 while (1) {
2252 struct cas_rx_comp *rxc = rxcs + entry;
2253 struct sk_buff *skb;
2254 int type, len;
2255 u64 words[4];
2256 int i, dring;
2257
2258 words[0] = le64_to_cpu(rxc->word1);
2259 words[1] = le64_to_cpu(rxc->word2);
2260 words[2] = le64_to_cpu(rxc->word3);
2261 words[3] = le64_to_cpu(rxc->word4);
2262
2263 /* don't touch if still owned by hw */
2264 type = CAS_VAL(RX_COMP1_TYPE, words[0]);
2265 if (type == 0)
2266 break;
2267
2268 /* hw hasn't cleared the zero bit yet */
2269 if (words[3] & RX_COMP4_ZERO) {
2270 break;
2271 }
2272
2273 /* get info on the packet */
2274 if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) {
2275 spin_lock(&cp->stat_lock[ring]);
2276 cp->net_stats[ring].rx_errors++;
2277 if (words[3] & RX_COMP4_LEN_MISMATCH)
2278 cp->net_stats[ring].rx_length_errors++;
2279 if (words[3] & RX_COMP4_BAD)
2280 cp->net_stats[ring].rx_crc_errors++;
2281 spin_unlock(&cp->stat_lock[ring]);
2282
2283 /* We'll just return it to Cassini. */
2284 drop_it:
2285 spin_lock(&cp->stat_lock[ring]);
2286 ++cp->net_stats[ring].rx_dropped;
2287 spin_unlock(&cp->stat_lock[ring]);
2288 goto next;
2289 }
2290
2291 len = cas_rx_process_pkt(cp, rxc, entry, words, &skb);
2292 if (len < 0) {
2293 ++drops;
2294 goto drop_it;
2295 }
2296
2297 /* see if it's a flow re-assembly or not. the driver
2298 * itself handles release back up.
2299 */
2300 if (RX_DONT_BATCH || (type == 0x2)) {
2301 /* non-reassm: these always get released */
2302 cas_skb_release(skb);
2303 } else {
2304 cas_rx_flow_pkt(cp, words, skb);
2305 }
2306
2307 spin_lock(&cp->stat_lock[ring]);
2308 cp->net_stats[ring].rx_packets++;
2309 cp->net_stats[ring].rx_bytes += len;
2310 spin_unlock(&cp->stat_lock[ring]);
2311
2312 next:
2313 npackets++;
2314
2315 /* should it be released? */
2316 if (words[0] & RX_COMP1_RELEASE_HDR) {
2317 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2318 dring = CAS_VAL(RX_INDEX_RING, i);
2319 i = CAS_VAL(RX_INDEX_NUM, i);
2320 cas_post_page(cp, dring, i);
2321 }
2322
2323 if (words[0] & RX_COMP1_RELEASE_DATA) {
2324 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2325 dring = CAS_VAL(RX_INDEX_RING, i);
2326 i = CAS_VAL(RX_INDEX_NUM, i);
2327 cas_post_page(cp, dring, i);
2328 }
2329
2330 if (words[0] & RX_COMP1_RELEASE_NEXT) {
2331 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2332 dring = CAS_VAL(RX_INDEX_RING, i);
2333 i = CAS_VAL(RX_INDEX_NUM, i);
2334 cas_post_page(cp, dring, i);
2335 }
2336
2337 /* skip to the next entry */
2338 entry = RX_COMP_ENTRY(ring, entry + 1 +
2339 CAS_VAL(RX_COMP1_SKIP, words[0]));
2340 #ifdef USE_NAPI
2341 if (budget && (npackets >= budget))
2342 break;
2343 #endif
2344 }
2345 cp->rx_new[ring] = entry;
2346
2347 if (drops)
2348 netdev_info(cp->dev, "Memory squeeze, deferring packet\n");
2349 return npackets;
2350 }
2351
2352
2353 /* put completion entries back on the ring */
2354 static void cas_post_rxcs_ringN(struct net_device *dev,
2355 struct cas *cp, int ring)
2356 {
2357 struct cas_rx_comp *rxc = cp->init_rxcs[ring];
2358 int last, entry;
2359
2360 last = cp->rx_cur[ring];
2361 entry = cp->rx_new[ring];
2362 netif_printk(cp, intr, KERN_DEBUG, dev,
2363 "rxc[%d] interrupt, done: %d/%d\n",
2364 ring, readl(cp->regs + REG_RX_COMP_HEAD), entry);
2365
2366 /* zero and re-mark descriptors */
2367 while (last != entry) {
2368 cas_rxc_init(rxc + last);
2369 last = RX_COMP_ENTRY(ring, last + 1);
2370 }
2371 cp->rx_cur[ring] = last;
2372
2373 if (ring == 0)
2374 writel(last, cp->regs + REG_RX_COMP_TAIL);
2375 else if (cp->cas_flags & CAS_FLAG_REG_PLUS)
2376 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
2377 }
2378
2379
2380
2381 /* cassini can use all four PCI interrupts for the completion ring.
2382 * rings 3 and 4 are identical
2383 */
2384 #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
2385 static inline void cas_handle_irqN(struct net_device *dev,
2386 struct cas *cp, const u32 status,
2387 const int ring)
2388 {
2389 if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT))
2390 cas_post_rxcs_ringN(dev, cp, ring);
2391 }
2392
2393 static irqreturn_t cas_interruptN(int irq, void *dev_id)
2394 {
2395 struct net_device *dev = dev_id;
2396 struct cas *cp = netdev_priv(dev);
2397 unsigned long flags;
2398 int ring = (irq == cp->pci_irq_INTC) ? 2 : 3;
2399 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring));
2400
2401 /* check for shared irq */
2402 if (status == 0)
2403 return IRQ_NONE;
2404
2405 spin_lock_irqsave(&cp->lock, flags);
2406 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2407 #ifdef USE_NAPI
2408 cas_mask_intr(cp);
2409 napi_schedule(&cp->napi);
2410 #else
2411 cas_rx_ringN(cp, ring, 0);
2412 #endif
2413 status &= ~INTR_RX_DONE_ALT;
2414 }
2415
2416 if (status)
2417 cas_handle_irqN(dev, cp, status, ring);
2418 spin_unlock_irqrestore(&cp->lock, flags);
2419 return IRQ_HANDLED;
2420 }
2421 #endif
2422
2423 #ifdef USE_PCI_INTB
2424 /* everything but rx packets */
2425 static inline void cas_handle_irq1(struct cas *cp, const u32 status)
2426 {
2427 if (status & INTR_RX_BUF_UNAVAIL_1) {
2428 /* Frame arrived, no free RX buffers available.
2429 * NOTE: we can get this on a link transition. */
2430 cas_post_rxds_ringN(cp, 1, 0);
2431 spin_lock(&cp->stat_lock[1]);
2432 cp->net_stats[1].rx_dropped++;
2433 spin_unlock(&cp->stat_lock[1]);
2434 }
2435
2436 if (status & INTR_RX_BUF_AE_1)
2437 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) -
2438 RX_AE_FREEN_VAL(1));
2439
2440 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2441 cas_post_rxcs_ringN(cp, 1);
2442 }
2443
2444 /* ring 2 handles a few more events than 3 and 4 */
2445 static irqreturn_t cas_interrupt1(int irq, void *dev_id)
2446 {
2447 struct net_device *dev = dev_id;
2448 struct cas *cp = netdev_priv(dev);
2449 unsigned long flags;
2450 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2451
2452 /* check for shared interrupt */
2453 if (status == 0)
2454 return IRQ_NONE;
2455
2456 spin_lock_irqsave(&cp->lock, flags);
2457 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2458 #ifdef USE_NAPI
2459 cas_mask_intr(cp);
2460 napi_schedule(&cp->napi);
2461 #else
2462 cas_rx_ringN(cp, 1, 0);
2463 #endif
2464 status &= ~INTR_RX_DONE_ALT;
2465 }
2466 if (status)
2467 cas_handle_irq1(cp, status);
2468 spin_unlock_irqrestore(&cp->lock, flags);
2469 return IRQ_HANDLED;
2470 }
2471 #endif
2472
2473 static inline void cas_handle_irq(struct net_device *dev,
2474 struct cas *cp, const u32 status)
2475 {
2476 /* housekeeping interrupts */
2477 if (status & INTR_ERROR_MASK)
2478 cas_abnormal_irq(dev, cp, status);
2479
2480 if (status & INTR_RX_BUF_UNAVAIL) {
2481 /* Frame arrived, no free RX buffers available.
2482 * NOTE: we can get this on a link transition.
2483 */
2484 cas_post_rxds_ringN(cp, 0, 0);
2485 spin_lock(&cp->stat_lock[0]);
2486 cp->net_stats[0].rx_dropped++;
2487 spin_unlock(&cp->stat_lock[0]);
2488 } else if (status & INTR_RX_BUF_AE) {
2489 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) -
2490 RX_AE_FREEN_VAL(0));
2491 }
2492
2493 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2494 cas_post_rxcs_ringN(dev, cp, 0);
2495 }
2496
2497 static irqreturn_t cas_interrupt(int irq, void *dev_id)
2498 {
2499 struct net_device *dev = dev_id;
2500 struct cas *cp = netdev_priv(dev);
2501 unsigned long flags;
2502 u32 status = readl(cp->regs + REG_INTR_STATUS);
2503
2504 if (status == 0)
2505 return IRQ_NONE;
2506
2507 spin_lock_irqsave(&cp->lock, flags);
2508 if (status & (INTR_TX_ALL | INTR_TX_INTME)) {
2509 cas_tx(dev, cp, status);
2510 status &= ~(INTR_TX_ALL | INTR_TX_INTME);
2511 }
2512
2513 if (status & INTR_RX_DONE) {
2514 #ifdef USE_NAPI
2515 cas_mask_intr(cp);
2516 napi_schedule(&cp->napi);
2517 #else
2518 cas_rx_ringN(cp, 0, 0);
2519 #endif
2520 status &= ~INTR_RX_DONE;
2521 }
2522
2523 if (status)
2524 cas_handle_irq(dev, cp, status);
2525 spin_unlock_irqrestore(&cp->lock, flags);
2526 return IRQ_HANDLED;
2527 }
2528
2529
2530 #ifdef USE_NAPI
2531 static int cas_poll(struct napi_struct *napi, int budget)
2532 {
2533 struct cas *cp = container_of(napi, struct cas, napi);
2534 struct net_device *dev = cp->dev;
2535 int i, enable_intr, credits;
2536 u32 status = readl(cp->regs + REG_INTR_STATUS);
2537 unsigned long flags;
2538
2539 spin_lock_irqsave(&cp->lock, flags);
2540 cas_tx(dev, cp, status);
2541 spin_unlock_irqrestore(&cp->lock, flags);
2542
2543 /* NAPI rx packets. we spread the credits across all of the
2544 * rxc rings
2545 *
2546 * to make sure we're fair with the work we loop through each
2547 * ring N_RX_COMP_RING times with a request of
2548 * budget / N_RX_COMP_RINGS
2549 */
2550 enable_intr = 1;
2551 credits = 0;
2552 for (i = 0; i < N_RX_COMP_RINGS; i++) {
2553 int j;
2554 for (j = 0; j < N_RX_COMP_RINGS; j++) {
2555 credits += cas_rx_ringN(cp, j, budget / N_RX_COMP_RINGS);
2556 if (credits >= budget) {
2557 enable_intr = 0;
2558 goto rx_comp;
2559 }
2560 }
2561 }
2562
2563 rx_comp:
2564 /* final rx completion */
2565 spin_lock_irqsave(&cp->lock, flags);
2566 if (status)
2567 cas_handle_irq(dev, cp, status);
2568
2569 #ifdef USE_PCI_INTB
2570 if (N_RX_COMP_RINGS > 1) {
2571 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2572 if (status)
2573 cas_handle_irq1(dev, cp, status);
2574 }
2575 #endif
2576
2577 #ifdef USE_PCI_INTC
2578 if (N_RX_COMP_RINGS > 2) {
2579 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2));
2580 if (status)
2581 cas_handle_irqN(dev, cp, status, 2);
2582 }
2583 #endif
2584
2585 #ifdef USE_PCI_INTD
2586 if (N_RX_COMP_RINGS > 3) {
2587 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3));
2588 if (status)
2589 cas_handle_irqN(dev, cp, status, 3);
2590 }
2591 #endif
2592 spin_unlock_irqrestore(&cp->lock, flags);
2593 if (enable_intr) {
2594 napi_complete(napi);
2595 cas_unmask_intr(cp);
2596 }
2597 return credits;
2598 }
2599 #endif
2600
2601 #ifdef CONFIG_NET_POLL_CONTROLLER
2602 static void cas_netpoll(struct net_device *dev)
2603 {
2604 struct cas *cp = netdev_priv(dev);
2605
2606 cas_disable_irq(cp, 0);
2607 cas_interrupt(cp->pdev->irq, dev);
2608 cas_enable_irq(cp, 0);
2609
2610 #ifdef USE_PCI_INTB
2611 if (N_RX_COMP_RINGS > 1) {
2612 /* cas_interrupt1(); */
2613 }
2614 #endif
2615 #ifdef USE_PCI_INTC
2616 if (N_RX_COMP_RINGS > 2) {
2617 /* cas_interruptN(); */
2618 }
2619 #endif
2620 #ifdef USE_PCI_INTD
2621 if (N_RX_COMP_RINGS > 3) {
2622 /* cas_interruptN(); */
2623 }
2624 #endif
2625 }
2626 #endif
2627
2628 static void cas_tx_timeout(struct net_device *dev, unsigned int txqueue)
2629 {
2630 struct cas *cp = netdev_priv(dev);
2631
2632 netdev_err(dev, "transmit timed out, resetting\n");
2633 if (!cp->hw_running) {
2634 netdev_err(dev, "hrm.. hw not running!\n");
2635 return;
2636 }
2637
2638 netdev_err(dev, "MIF_STATE[%08x]\n",
2639 readl(cp->regs + REG_MIF_STATE_MACHINE));
2640
2641 netdev_err(dev, "MAC_STATE[%08x]\n",
2642 readl(cp->regs + REG_MAC_STATE_MACHINE));
2643
2644 netdev_err(dev, "TX_STATE[%08x:%08x:%08x] FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
2645 readl(cp->regs + REG_TX_CFG),
2646 readl(cp->regs + REG_MAC_TX_STATUS),
2647 readl(cp->regs + REG_MAC_TX_CFG),
2648 readl(cp->regs + REG_TX_FIFO_PKT_CNT),
2649 readl(cp->regs + REG_TX_FIFO_WRITE_PTR),
2650 readl(cp->regs + REG_TX_FIFO_READ_PTR),
2651 readl(cp->regs + REG_TX_SM_1),
2652 readl(cp->regs + REG_TX_SM_2));
2653
2654 netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
2655 readl(cp->regs + REG_RX_CFG),
2656 readl(cp->regs + REG_MAC_RX_STATUS),
2657 readl(cp->regs + REG_MAC_RX_CFG));
2658
2659 netdev_err(dev, "HP_STATE[%08x:%08x:%08x:%08x]\n",
2660 readl(cp->regs + REG_HP_STATE_MACHINE),
2661 readl(cp->regs + REG_HP_STATUS0),
2662 readl(cp->regs + REG_HP_STATUS1),
2663 readl(cp->regs + REG_HP_STATUS2));
2664
2665 #if 1
2666 atomic_inc(&cp->reset_task_pending);
2667 atomic_inc(&cp->reset_task_pending_all);
2668 schedule_work(&cp->reset_task);
2669 #else
2670 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
2671 schedule_work(&cp->reset_task);
2672 #endif
2673 }
2674
2675 static inline int cas_intme(int ring, int entry)
2676 {
2677 /* Algorithm: IRQ every 1/2 of descriptors. */
2678 if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1)))
2679 return 1;
2680 return 0;
2681 }
2682
2683
2684 static void cas_write_txd(struct cas *cp, int ring, int entry,
2685 dma_addr_t mapping, int len, u64 ctrl, int last)
2686 {
2687 struct cas_tx_desc *txd = cp->init_txds[ring] + entry;
2688
2689 ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
2690 if (cas_intme(ring, entry))
2691 ctrl |= TX_DESC_INTME;
2692 if (last)
2693 ctrl |= TX_DESC_EOF;
2694 txd->control = cpu_to_le64(ctrl);
2695 txd->buffer = cpu_to_le64(mapping);
2696 }
2697
2698 static inline void *tx_tiny_buf(struct cas *cp, const int ring,
2699 const int entry)
2700 {
2701 return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry;
2702 }
2703
2704 static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring,
2705 const int entry, const int tentry)
2706 {
2707 cp->tx_tiny_use[ring][tentry].nbufs++;
2708 cp->tx_tiny_use[ring][entry].used = 1;
2709 return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry;
2710 }
2711
2712 static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
2713 struct sk_buff *skb)
2714 {
2715 struct net_device *dev = cp->dev;
2716 int entry, nr_frags, frag, tabort, tentry;
2717 dma_addr_t mapping;
2718 unsigned long flags;
2719 u64 ctrl;
2720 u32 len;
2721
2722 spin_lock_irqsave(&cp->tx_lock[ring], flags);
2723
2724 /* This is a hard error, log it. */
2725 if (TX_BUFFS_AVAIL(cp, ring) <=
2726 CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) {
2727 netif_stop_queue(dev);
2728 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2729 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
2730 return 1;
2731 }
2732
2733 ctrl = 0;
2734 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2735 const u64 csum_start_off = skb_checksum_start_offset(skb);
2736 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
2737
2738 ctrl = TX_DESC_CSUM_EN |
2739 CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
2740 CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
2741 }
2742
2743 entry = cp->tx_new[ring];
2744 cp->tx_skbs[ring][entry] = skb;
2745
2746 nr_frags = skb_shinfo(skb)->nr_frags;
2747 len = skb_headlen(skb);
2748 mapping = dma_map_page(&cp->pdev->dev, virt_to_page(skb->data),
2749 offset_in_page(skb->data), len, DMA_TO_DEVICE);
2750
2751 tentry = entry;
2752 tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len);
2753 if (unlikely(tabort)) {
2754 /* NOTE: len is always > tabort */
2755 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2756 ctrl | TX_DESC_SOF, 0);
2757 entry = TX_DESC_NEXT(ring, entry);
2758
2759 skb_copy_from_linear_data_offset(skb, len - tabort,
2760 tx_tiny_buf(cp, ring, entry), tabort);
2761 mapping = tx_tiny_map(cp, ring, entry, tentry);
2762 cas_write_txd(cp, ring, entry, mapping, tabort, ctrl,
2763 (nr_frags == 0));
2764 } else {
2765 cas_write_txd(cp, ring, entry, mapping, len, ctrl |
2766 TX_DESC_SOF, (nr_frags == 0));
2767 }
2768 entry = TX_DESC_NEXT(ring, entry);
2769
2770 for (frag = 0; frag < nr_frags; frag++) {
2771 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
2772
2773 len = skb_frag_size(fragp);
2774 mapping = skb_frag_dma_map(&cp->pdev->dev, fragp, 0, len,
2775 DMA_TO_DEVICE);
2776
2777 tabort = cas_calc_tabort(cp, skb_frag_off(fragp), len);
2778 if (unlikely(tabort)) {
2779 /* NOTE: len is always > tabort */
2780 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2781 ctrl, 0);
2782 entry = TX_DESC_NEXT(ring, entry);
2783 memcpy_from_page(tx_tiny_buf(cp, ring, entry),
2784 skb_frag_page(fragp),
2785 skb_frag_off(fragp) + len - tabort,
2786 tabort);
2787 mapping = tx_tiny_map(cp, ring, entry, tentry);
2788 len = tabort;
2789 }
2790
2791 cas_write_txd(cp, ring, entry, mapping, len, ctrl,
2792 (frag + 1 == nr_frags));
2793 entry = TX_DESC_NEXT(ring, entry);
2794 }
2795
2796 cp->tx_new[ring] = entry;
2797 if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))
2798 netif_stop_queue(dev);
2799
2800 netif_printk(cp, tx_queued, KERN_DEBUG, dev,
2801 "tx[%d] queued, slot %d, skblen %d, avail %d\n",
2802 ring, entry, skb->len, TX_BUFFS_AVAIL(cp, ring));
2803 writel(entry, cp->regs + REG_TX_KICKN(ring));
2804 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2805 return 0;
2806 }
2807
2808 static netdev_tx_t cas_start_xmit(struct sk_buff *skb, struct net_device *dev)
2809 {
2810 struct cas *cp = netdev_priv(dev);
2811
2812 /* this is only used as a load-balancing hint, so it doesn't
2813 * need to be SMP safe
2814 */
2815 static int ring;
2816
2817 if (skb_padto(skb, cp->min_frame_size))
2818 return NETDEV_TX_OK;
2819
2820 /* XXX: we need some higher-level QoS hooks to steer packets to
2821 * individual queues.
2822 */
2823 if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb))
2824 return NETDEV_TX_BUSY;
2825 return NETDEV_TX_OK;
2826 }
2827
2828 static void cas_init_tx_dma(struct cas *cp)
2829 {
2830 u64 desc_dma = cp->block_dvma;
2831 unsigned long off;
2832 u32 val;
2833 int i;
2834
2835 /* set up tx completion writeback registers. must be 8-byte aligned */
2836 #ifdef USE_TX_COMPWB
2837 off = offsetof(struct cas_init_block, tx_compwb);
2838 writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
2839 writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
2840 #endif
2841
2842 /* enable completion writebacks, enable paced mode,
2843 * disable read pipe, and disable pre-interrupt compwbs
2844 */
2845 val = TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 |
2846 TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |
2847 TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE |
2848 TX_CFG_INTR_COMPWB_DIS;
2849
2850 /* write out tx ring info and tx desc bases */
2851 for (i = 0; i < MAX_TX_RINGS; i++) {
2852 off = (unsigned long) cp->init_txds[i] -
2853 (unsigned long) cp->init_block;
2854
2855 val |= CAS_TX_RINGN_BASE(i);
2856 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
2857 writel((desc_dma + off) & 0xffffffff, cp->regs +
2858 REG_TX_DBN_LOW(i));
2859 /* don't zero out the kick register here as the system
2860 * will wedge
2861 */
2862 }
2863 writel(val, cp->regs + REG_TX_CFG);
2864
2865 /* program max burst sizes. these numbers should be different
2866 * if doing QoS.
2867 */
2868 #ifdef USE_QOS
2869 writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2870 writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
2871 writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
2872 writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
2873 #else
2874 writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2875 writel(0x800, cp->regs + REG_TX_MAXBURST_1);
2876 writel(0x800, cp->regs + REG_TX_MAXBURST_2);
2877 writel(0x800, cp->regs + REG_TX_MAXBURST_3);
2878 #endif
2879 }
2880
2881 /* Must be invoked under cp->lock. */
2882 static inline void cas_init_dma(struct cas *cp)
2883 {
2884 cas_init_tx_dma(cp);
2885 cas_init_rx_dma(cp);
2886 }
2887
2888 static void cas_process_mc_list(struct cas *cp)
2889 {
2890 u16 hash_table[16];
2891 u32 crc;
2892 struct netdev_hw_addr *ha;
2893 int i = 1;
2894
2895 memset(hash_table, 0, sizeof(hash_table));
2896 netdev_for_each_mc_addr(ha, cp->dev) {
2897 if (i <= CAS_MC_EXACT_MATCH_SIZE) {
2898 /* use the alternate mac address registers for the
2899 * first 15 multicast addresses
2900 */
2901 writel((ha->addr[4] << 8) | ha->addr[5],
2902 cp->regs + REG_MAC_ADDRN(i*3 + 0));
2903 writel((ha->addr[2] << 8) | ha->addr[3],
2904 cp->regs + REG_MAC_ADDRN(i*3 + 1));
2905 writel((ha->addr[0] << 8) | ha->addr[1],
2906 cp->regs + REG_MAC_ADDRN(i*3 + 2));
2907 i++;
2908 }
2909 else {
2910 /* use hw hash table for the next series of
2911 * multicast addresses
2912 */
2913 crc = ether_crc_le(ETH_ALEN, ha->addr);
2914 crc >>= 24;
2915 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
2916 }
2917 }
2918 for (i = 0; i < 16; i++)
2919 writel(hash_table[i], cp->regs + REG_MAC_HASH_TABLEN(i));
2920 }
2921
2922 /* Must be invoked under cp->lock. */
2923 static u32 cas_setup_multicast(struct cas *cp)
2924 {
2925 u32 rxcfg = 0;
2926 int i;
2927
2928 if (cp->dev->flags & IFF_PROMISC) {
2929 rxcfg |= MAC_RX_CFG_PROMISC_EN;
2930
2931 } else if (cp->dev->flags & IFF_ALLMULTI) {
2932 for (i=0; i < 16; i++)
2933 writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
2934 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
2935
2936 } else {
2937 cas_process_mc_list(cp);
2938 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
2939 }
2940
2941 return rxcfg;
2942 }
2943
2944 /* must be invoked under cp->stat_lock[N_TX_RINGS] */
2945 static void cas_clear_mac_err(struct cas *cp)
2946 {
2947 writel(0, cp->regs + REG_MAC_COLL_NORMAL);
2948 writel(0, cp->regs + REG_MAC_COLL_FIRST);
2949 writel(0, cp->regs + REG_MAC_COLL_EXCESS);
2950 writel(0, cp->regs + REG_MAC_COLL_LATE);
2951 writel(0, cp->regs + REG_MAC_TIMER_DEFER);
2952 writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
2953 writel(0, cp->regs + REG_MAC_RECV_FRAME);
2954 writel(0, cp->regs + REG_MAC_LEN_ERR);
2955 writel(0, cp->regs + REG_MAC_ALIGN_ERR);
2956 writel(0, cp->regs + REG_MAC_FCS_ERR);
2957 writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
2958 }
2959
2960
2961 static void cas_mac_reset(struct cas *cp)
2962 {
2963 int i;
2964
2965 /* do both TX and RX reset */
2966 writel(0x1, cp->regs + REG_MAC_TX_RESET);
2967 writel(0x1, cp->regs + REG_MAC_RX_RESET);
2968
2969 /* wait for TX */
2970 i = STOP_TRIES;
2971 while (i-- > 0) {
2972 if (readl(cp->regs + REG_MAC_TX_RESET) == 0)
2973 break;
2974 udelay(10);
2975 }
2976
2977 /* wait for RX */
2978 i = STOP_TRIES;
2979 while (i-- > 0) {
2980 if (readl(cp->regs + REG_MAC_RX_RESET) == 0)
2981 break;
2982 udelay(10);
2983 }
2984
2985 if (readl(cp->regs + REG_MAC_TX_RESET) |
2986 readl(cp->regs + REG_MAC_RX_RESET))
2987 netdev_err(cp->dev, "mac tx[%d]/rx[%d] reset failed [%08x]\n",
2988 readl(cp->regs + REG_MAC_TX_RESET),
2989 readl(cp->regs + REG_MAC_RX_RESET),
2990 readl(cp->regs + REG_MAC_STATE_MACHINE));
2991 }
2992
2993
2994 /* Must be invoked under cp->lock. */
2995 static void cas_init_mac(struct cas *cp)
2996 {
2997 const unsigned char *e = &cp->dev->dev_addr[0];
2998 int i;
2999 cas_mac_reset(cp);
3000
3001 /* setup core arbitration weight register */
3002 writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
3003
3004 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
3005 /* set the infinite burst register for chips that don't have
3006 * pci issues.
3007 */
3008 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0)
3009 writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
3010 #endif
3011
3012 writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
3013
3014 writel(0x00, cp->regs + REG_MAC_IPG0);
3015 writel(0x08, cp->regs + REG_MAC_IPG1);
3016 writel(0x04, cp->regs + REG_MAC_IPG2);
3017
3018 /* change later for 802.3z */
3019 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3020
3021 /* min frame + FCS */
3022 writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
3023
3024 /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we
3025 * specify the maximum frame size to prevent RX tag errors on
3026 * oversized frames.
3027 */
3028 writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
3029 CAS_BASE(MAC_FRAMESIZE_MAX_FRAME,
3030 (CAS_MAX_MTU + ETH_HLEN + 4 + 4)),
3031 cp->regs + REG_MAC_FRAMESIZE_MAX);
3032
3033 /* NOTE: crc_size is used as a surrogate for half-duplex.
3034 * workaround saturn half-duplex issue by increasing preamble
3035 * size to 65 bytes.
3036 */
3037 if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size)
3038 writel(0x41, cp->regs + REG_MAC_PA_SIZE);
3039 else
3040 writel(0x07, cp->regs + REG_MAC_PA_SIZE);
3041 writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
3042 writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
3043 writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
3044
3045 writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
3046
3047 writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
3048 writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
3049 writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
3050 writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
3051 writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
3052
3053 /* setup mac address in perfect filter array */
3054 for (i = 0; i < 45; i++)
3055 writel(0x0, cp->regs + REG_MAC_ADDRN(i));
3056
3057 writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
3058 writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
3059 writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
3060
3061 writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
3062 writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
3063 writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
3064
3065 cp->mac_rx_cfg = cas_setup_multicast(cp);
3066
3067 spin_lock(&cp->stat_lock[N_TX_RINGS]);
3068 cas_clear_mac_err(cp);
3069 spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3070
3071 /* Setup MAC interrupts. We want to get all of the interesting
3072 * counter expiration events, but we do not want to hear about
3073 * normal rx/tx as the DMA engine tells us that.
3074 */
3075 writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
3076 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
3077
3078 /* Don't enable even the PAUSE interrupts for now, we
3079 * make no use of those events other than to record them.
3080 */
3081 writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
3082 }
3083
3084 /* Must be invoked under cp->lock. */
3085 static void cas_init_pause_thresholds(struct cas *cp)
3086 {
3087 /* Calculate pause thresholds. Setting the OFF threshold to the
3088 * full RX fifo size effectively disables PAUSE generation
3089 */
3090 if (cp->rx_fifo_size <= (2 * 1024)) {
3091 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size;
3092 } else {
3093 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
3094 if (max_frame * 3 > cp->rx_fifo_size) {
3095 cp->rx_pause_off = 7104;
3096 cp->rx_pause_on = 960;
3097 } else {
3098 int off = (cp->rx_fifo_size - (max_frame * 2));
3099 int on = off - max_frame;
3100 cp->rx_pause_off = off;
3101 cp->rx_pause_on = on;
3102 }
3103 }
3104 }
3105
3106 static int cas_vpd_match(const void __iomem *p, const char *str)
3107 {
3108 int len = strlen(str) + 1;
3109 int i;
3110
3111 for (i = 0; i < len; i++) {
3112 if (readb(p + i) != str[i])
3113 return 0;
3114 }
3115 return 1;
3116 }
3117
3118
3119 /* get the mac address by reading the vpd information in the rom.
3120 * also get the phy type and determine if there's an entropy generator.
3121 * NOTE: this is a bit convoluted for the following reasons:
3122 * 1) vpd info has order-dependent mac addresses for multinic cards
3123 * 2) the only way to determine the nic order is to use the slot
3124 * number.
3125 * 3) fiber cards don't have bridges, so their slot numbers don't
3126 * mean anything.
3127 * 4) we don't actually know we have a fiber card until after
3128 * the mac addresses are parsed.
3129 */
3130 static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
3131 const int offset)
3132 {
3133 void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START;
3134 void __iomem *base, *kstart;
3135 int i, len;
3136 int found = 0;
3137 #define VPD_FOUND_MAC 0x01
3138 #define VPD_FOUND_PHY 0x02
3139
3140 int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */
3141 int mac_off = 0;
3142
3143 #if defined(CONFIG_SPARC)
3144 const unsigned char *addr;
3145 #endif
3146
3147 /* give us access to the PROM */
3148 writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
3149 cp->regs + REG_BIM_LOCAL_DEV_EN);
3150
3151 /* check for an expansion rom */
3152 if (readb(p) != 0x55 || readb(p + 1) != 0xaa)
3153 goto use_random_mac_addr;
3154
3155 /* search for beginning of vpd */
3156 base = NULL;
3157 for (i = 2; i < EXPANSION_ROM_SIZE; i++) {
3158 /* check for PCIR */
3159 if ((readb(p + i + 0) == 0x50) &&
3160 (readb(p + i + 1) == 0x43) &&
3161 (readb(p + i + 2) == 0x49) &&
3162 (readb(p + i + 3) == 0x52)) {
3163 base = p + (readb(p + i + 8) |
3164 (readb(p + i + 9) << 8));
3165 break;
3166 }
3167 }
3168
3169 if (!base || (readb(base) != 0x82))
3170 goto use_random_mac_addr;
3171
3172 i = (readb(base + 1) | (readb(base + 2) << 8)) + 3;
3173 while (i < EXPANSION_ROM_SIZE) {
3174 if (readb(base + i) != 0x90) /* no vpd found */
3175 goto use_random_mac_addr;
3176
3177 /* found a vpd field */
3178 len = readb(base + i + 1) | (readb(base + i + 2) << 8);
3179
3180 /* extract keywords */
3181 kstart = base + i + 3;
3182 p = kstart;
3183 while ((p - kstart) < len) {
3184 int klen = readb(p + 2);
3185 int j;
3186 char type;
3187
3188 p += 3;
3189
3190 /* look for the following things:
3191 * -- correct length == 29
3192 * 3 (type) + 2 (size) +
3193 * 18 (strlen("local-mac-address") + 1) +
3194 * 6 (mac addr)
3195 * -- VPD Instance 'I'
3196 * -- VPD Type Bytes 'B'
3197 * -- VPD data length == 6
3198 * -- property string == local-mac-address
3199 *
3200 * -- correct length == 24
3201 * 3 (type) + 2 (size) +
3202 * 12 (strlen("entropy-dev") + 1) +
3203 * 7 (strlen("vms110") + 1)
3204 * -- VPD Instance 'I'
3205 * -- VPD Type String 'B'
3206 * -- VPD data length == 7
3207 * -- property string == entropy-dev
3208 *
3209 * -- correct length == 18
3210 * 3 (type) + 2 (size) +
3211 * 9 (strlen("phy-type") + 1) +
3212 * 4 (strlen("pcs") + 1)
3213 * -- VPD Instance 'I'
3214 * -- VPD Type String 'S'
3215 * -- VPD data length == 4
3216 * -- property string == phy-type
3217 *
3218 * -- correct length == 23
3219 * 3 (type) + 2 (size) +
3220 * 14 (strlen("phy-interface") + 1) +
3221 * 4 (strlen("pcs") + 1)
3222 * -- VPD Instance 'I'
3223 * -- VPD Type String 'S'
3224 * -- VPD data length == 4
3225 * -- property string == phy-interface
3226 */
3227 if (readb(p) != 'I')
3228 goto next;
3229
3230 /* finally, check string and length */
3231 type = readb(p + 3);
3232 if (type == 'B') {
3233 if ((klen == 29) && readb(p + 4) == 6 &&
3234 cas_vpd_match(p + 5,
3235 "local-mac-address")) {
3236 if (mac_off++ > offset)
3237 goto next;
3238
3239 /* set mac address */
3240 for (j = 0; j < 6; j++)
3241 dev_addr[j] =
3242 readb(p + 23 + j);
3243 goto found_mac;
3244 }
3245 }
3246
3247 if (type != 'S')
3248 goto next;
3249
3250 #ifdef USE_ENTROPY_DEV
3251 if ((klen == 24) &&
3252 cas_vpd_match(p + 5, "entropy-dev") &&
3253 cas_vpd_match(p + 17, "vms110")) {
3254 cp->cas_flags |= CAS_FLAG_ENTROPY_DEV;
3255 goto next;
3256 }
3257 #endif
3258
3259 if (found & VPD_FOUND_PHY)
3260 goto next;
3261
3262 if ((klen == 18) && readb(p + 4) == 4 &&
3263 cas_vpd_match(p + 5, "phy-type")) {
3264 if (cas_vpd_match(p + 14, "pcs")) {
3265 phy_type = CAS_PHY_SERDES;
3266 goto found_phy;
3267 }
3268 }
3269
3270 if ((klen == 23) && readb(p + 4) == 4 &&
3271 cas_vpd_match(p + 5, "phy-interface")) {
3272 if (cas_vpd_match(p + 19, "pcs")) {
3273 phy_type = CAS_PHY_SERDES;
3274 goto found_phy;
3275 }
3276 }
3277 found_mac:
3278 found |= VPD_FOUND_MAC;
3279 goto next;
3280
3281 found_phy:
3282 found |= VPD_FOUND_PHY;
3283
3284 next:
3285 p += klen;
3286 }
3287 i += len + 3;
3288 }
3289
3290 use_random_mac_addr:
3291 if (found & VPD_FOUND_MAC)
3292 goto done;
3293
3294 #if defined(CONFIG_SPARC)
3295 addr = of_get_property(cp->of_node, "local-mac-address", NULL);
3296 if (addr != NULL) {
3297 memcpy(dev_addr, addr, ETH_ALEN);
3298 goto done;
3299 }
3300 #endif
3301
3302 /* Sun MAC prefix then 3 random bytes. */
3303 pr_info("MAC address not found in ROM VPD\n");
3304 dev_addr[0] = 0x08;
3305 dev_addr[1] = 0x00;
3306 dev_addr[2] = 0x20;
3307 get_random_bytes(dev_addr + 3, 3);
3308
3309 done:
3310 writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3311 return phy_type;
3312 }
3313
3314 /* check pci invariants */
3315 static void cas_check_pci_invariants(struct cas *cp)
3316 {
3317 struct pci_dev *pdev = cp->pdev;
3318
3319 cp->cas_flags = 0;
3320 if ((pdev->vendor == PCI_VENDOR_ID_SUN) &&
3321 (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) {
3322 if (pdev->revision >= CAS_ID_REVPLUS)
3323 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3324 if (pdev->revision < CAS_ID_REVPLUS02u)
3325 cp->cas_flags |= CAS_FLAG_TARGET_ABORT;
3326
3327 /* Original Cassini supports HW CSUM, but it's not
3328 * enabled by default as it can trigger TX hangs.
3329 */
3330 if (pdev->revision < CAS_ID_REV2)
3331 cp->cas_flags |= CAS_FLAG_NO_HW_CSUM;
3332 } else {
3333 /* Only sun has original cassini chips. */
3334 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3335
3336 /* We use a flag because the same phy might be externally
3337 * connected.
3338 */
3339 if ((pdev->vendor == PCI_VENDOR_ID_NS) &&
3340 (pdev->device == PCI_DEVICE_ID_NS_SATURN))
3341 cp->cas_flags |= CAS_FLAG_SATURN;
3342 }
3343 }
3344
3345
3346 static int cas_check_invariants(struct cas *cp)
3347 {
3348 struct pci_dev *pdev = cp->pdev;
3349 u8 addr[ETH_ALEN];
3350 u32 cfg;
3351 int i;
3352
3353 /* get page size for rx buffers. */
3354 cp->page_order = 0;
3355 #ifdef USE_PAGE_ORDER
3356 if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) {
3357 /* see if we can allocate larger pages */
3358 struct page *page = alloc_pages(GFP_ATOMIC,
3359 CAS_JUMBO_PAGE_SHIFT -
3360 PAGE_SHIFT);
3361 if (page) {
3362 __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT);
3363 cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT;
3364 } else {
3365 printk("MTU limited to %d bytes\n", CAS_MAX_MTU);
3366 }
3367 }
3368 #endif
3369 cp->page_size = (PAGE_SIZE << cp->page_order);
3370
3371 /* Fetch the FIFO configurations. */
3372 cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64;
3373 cp->rx_fifo_size = RX_FIFO_SIZE;
3374
3375 /* finish phy determination. MDIO1 takes precedence over MDIO0 if
3376 * they're both connected.
3377 */
3378 cp->phy_type = cas_get_vpd_info(cp, addr, PCI_SLOT(pdev->devfn));
3379 eth_hw_addr_set(cp->dev, addr);
3380 if (cp->phy_type & CAS_PHY_SERDES) {
3381 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3382 return 0; /* no more checking needed */
3383 }
3384
3385 /* MII */
3386 cfg = readl(cp->regs + REG_MIF_CFG);
3387 if (cfg & MIF_CFG_MDIO_1) {
3388 cp->phy_type = CAS_PHY_MII_MDIO1;
3389 } else if (cfg & MIF_CFG_MDIO_0) {
3390 cp->phy_type = CAS_PHY_MII_MDIO0;
3391 }
3392
3393 cas_mif_poll(cp, 0);
3394 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3395
3396 for (i = 0; i < 32; i++) {
3397 u32 phy_id;
3398 int j;
3399
3400 for (j = 0; j < 3; j++) {
3401 cp->phy_addr = i;
3402 phy_id = cas_phy_read(cp, MII_PHYSID1) << 16;
3403 phy_id |= cas_phy_read(cp, MII_PHYSID2);
3404 if (phy_id && (phy_id != 0xFFFFFFFF)) {
3405 cp->phy_id = phy_id;
3406 goto done;
3407 }
3408 }
3409 }
3410 pr_err("MII phy did not respond [%08x]\n",
3411 readl(cp->regs + REG_MIF_STATE_MACHINE));
3412 return -1;
3413
3414 done:
3415 /* see if we can do gigabit */
3416 cfg = cas_phy_read(cp, MII_BMSR);
3417 if ((cfg & CAS_BMSR_1000_EXTEND) &&
3418 cas_phy_read(cp, CAS_MII_1000_EXTEND))
3419 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3420 return 0;
3421 }
3422
3423 /* Must be invoked under cp->lock. */
3424 static inline void cas_start_dma(struct cas *cp)
3425 {
3426 int i;
3427 u32 val;
3428 int txfailed = 0;
3429
3430 /* enable dma */
3431 val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN;
3432 writel(val, cp->regs + REG_TX_CFG);
3433 val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN;
3434 writel(val, cp->regs + REG_RX_CFG);
3435
3436 /* enable the mac */
3437 val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN;
3438 writel(val, cp->regs + REG_MAC_TX_CFG);
3439 val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN;
3440 writel(val, cp->regs + REG_MAC_RX_CFG);
3441
3442 i = STOP_TRIES;
3443 while (i-- > 0) {
3444 val = readl(cp->regs + REG_MAC_TX_CFG);
3445 if ((val & MAC_TX_CFG_EN))
3446 break;
3447 udelay(10);
3448 }
3449 if (i < 0) txfailed = 1;
3450 i = STOP_TRIES;
3451 while (i-- > 0) {
3452 val = readl(cp->regs + REG_MAC_RX_CFG);
3453 if ((val & MAC_RX_CFG_EN)) {
3454 if (txfailed) {
3455 netdev_err(cp->dev,
3456 "enabling mac failed [tx:%08x:%08x]\n",
3457 readl(cp->regs + REG_MIF_STATE_MACHINE),
3458 readl(cp->regs + REG_MAC_STATE_MACHINE));
3459 }
3460 goto enable_rx_done;
3461 }
3462 udelay(10);
3463 }
3464 netdev_err(cp->dev, "enabling mac failed [%s:%08x:%08x]\n",
3465 (txfailed ? "tx,rx" : "rx"),
3466 readl(cp->regs + REG_MIF_STATE_MACHINE),
3467 readl(cp->regs + REG_MAC_STATE_MACHINE));
3468
3469 enable_rx_done:
3470 cas_unmask_intr(cp); /* enable interrupts */
3471 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
3472 writel(0, cp->regs + REG_RX_COMP_TAIL);
3473
3474 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
3475 if (N_RX_DESC_RINGS > 1)
3476 writel(RX_DESC_RINGN_SIZE(1) - 4,
3477 cp->regs + REG_PLUS_RX_KICK1);
3478 }
3479 }
3480
3481 /* Must be invoked under cp->lock. */
3482 static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd,
3483 int *pause)
3484 {
3485 u32 val = readl(cp->regs + REG_PCS_MII_LPA);
3486 *fd = (val & PCS_MII_LPA_FD) ? 1 : 0;
3487 *pause = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00;
3488 if (val & PCS_MII_LPA_ASYM_PAUSE)
3489 *pause |= 0x10;
3490 *spd = 1000;
3491 }
3492
3493 /* Must be invoked under cp->lock. */
3494 static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd,
3495 int *pause)
3496 {
3497 u32 val;
3498
3499 *fd = 0;
3500 *spd = 10;
3501 *pause = 0;
3502
3503 /* use GMII registers */
3504 val = cas_phy_read(cp, MII_LPA);
3505 if (val & CAS_LPA_PAUSE)
3506 *pause = 0x01;
3507
3508 if (val & CAS_LPA_ASYM_PAUSE)
3509 *pause |= 0x10;
3510
3511 if (val & LPA_DUPLEX)
3512 *fd = 1;
3513 if (val & LPA_100)
3514 *spd = 100;
3515
3516 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
3517 val = cas_phy_read(cp, CAS_MII_1000_STATUS);
3518 if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF))
3519 *spd = 1000;
3520 if (val & CAS_LPA_1000FULL)
3521 *fd = 1;
3522 }
3523 }
3524
3525 /* A link-up condition has occurred, initialize and enable the
3526 * rest of the chip.
3527 *
3528 * Must be invoked under cp->lock.
3529 */
3530 static void cas_set_link_modes(struct cas *cp)
3531 {
3532 u32 val;
3533 int full_duplex, speed, pause;
3534
3535 full_duplex = 0;
3536 speed = 10;
3537 pause = 0;
3538
3539 if (CAS_PHY_MII(cp->phy_type)) {
3540 cas_mif_poll(cp, 0);
3541 val = cas_phy_read(cp, MII_BMCR);
3542 if (val & BMCR_ANENABLE) {
3543 cas_read_mii_link_mode(cp, &full_duplex, &speed,
3544 &pause);
3545 } else {
3546 if (val & BMCR_FULLDPLX)
3547 full_duplex = 1;
3548
3549 if (val & BMCR_SPEED100)
3550 speed = 100;
3551 else if (val & CAS_BMCR_SPEED1000)
3552 speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
3553 1000 : 100;
3554 }
3555 cas_mif_poll(cp, 1);
3556
3557 } else {
3558 val = readl(cp->regs + REG_PCS_MII_CTRL);
3559 cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause);
3560 if ((val & PCS_MII_AUTONEG_EN) == 0) {
3561 if (val & PCS_MII_CTRL_DUPLEX)
3562 full_duplex = 1;
3563 }
3564 }
3565
3566 netif_info(cp, link, cp->dev, "Link up at %d Mbps, %s-duplex\n",
3567 speed, full_duplex ? "full" : "half");
3568
3569 val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED;
3570 if (CAS_PHY_MII(cp->phy_type)) {
3571 val |= MAC_XIF_MII_BUFFER_OUTPUT_EN;
3572 if (!full_duplex)
3573 val |= MAC_XIF_DISABLE_ECHO;
3574 }
3575 if (full_duplex)
3576 val |= MAC_XIF_FDPLX_LED;
3577 if (speed == 1000)
3578 val |= MAC_XIF_GMII_MODE;
3579 writel(val, cp->regs + REG_MAC_XIF_CFG);
3580
3581 /* deal with carrier and collision detect. */
3582 val = MAC_TX_CFG_IPG_EN;
3583 if (full_duplex) {
3584 val |= MAC_TX_CFG_IGNORE_CARRIER;
3585 val |= MAC_TX_CFG_IGNORE_COLL;
3586 } else {
3587 #ifndef USE_CSMA_CD_PROTO
3588 val |= MAC_TX_CFG_NEVER_GIVE_UP_EN;
3589 val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM;
3590 #endif
3591 }
3592 /* val now set up for REG_MAC_TX_CFG */
3593
3594 /* If gigabit and half-duplex, enable carrier extension
3595 * mode. increase slot time to 512 bytes as well.
3596 * else, disable it and make sure slot time is 64 bytes.
3597 * also activate checksum bug workaround
3598 */
3599 if ((speed == 1000) && !full_duplex) {
3600 writel(val | MAC_TX_CFG_CARRIER_EXTEND,
3601 cp->regs + REG_MAC_TX_CFG);
3602
3603 val = readl(cp->regs + REG_MAC_RX_CFG);
3604 val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */
3605 writel(val | MAC_RX_CFG_CARRIER_EXTEND,
3606 cp->regs + REG_MAC_RX_CFG);
3607
3608 writel(0x200, cp->regs + REG_MAC_SLOT_TIME);
3609
3610 cp->crc_size = 4;
3611 /* minimum size gigabit frame at half duplex */
3612 cp->min_frame_size = CAS_1000MB_MIN_FRAME;
3613
3614 } else {
3615 writel(val, cp->regs + REG_MAC_TX_CFG);
3616
3617 /* checksum bug workaround. don't strip FCS when in
3618 * half-duplex mode
3619 */
3620 val = readl(cp->regs + REG_MAC_RX_CFG);
3621 if (full_duplex) {
3622 val |= MAC_RX_CFG_STRIP_FCS;
3623 cp->crc_size = 0;
3624 cp->min_frame_size = CAS_MIN_MTU;
3625 } else {
3626 val &= ~MAC_RX_CFG_STRIP_FCS;
3627 cp->crc_size = 4;
3628 cp->min_frame_size = CAS_MIN_FRAME;
3629 }
3630 writel(val & ~MAC_RX_CFG_CARRIER_EXTEND,
3631 cp->regs + REG_MAC_RX_CFG);
3632 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3633 }
3634
3635 if (netif_msg_link(cp)) {
3636 if (pause & 0x01) {
3637 netdev_info(cp->dev, "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
3638 cp->rx_fifo_size,
3639 cp->rx_pause_off,
3640 cp->rx_pause_on);
3641 } else if (pause & 0x10) {
3642 netdev_info(cp->dev, "TX pause enabled\n");
3643 } else {
3644 netdev_info(cp->dev, "Pause is disabled\n");
3645 }
3646 }
3647
3648 val = readl(cp->regs + REG_MAC_CTRL_CFG);
3649 val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN);
3650 if (pause) { /* symmetric or asymmetric pause */
3651 val |= MAC_CTRL_CFG_SEND_PAUSE_EN;
3652 if (pause & 0x01) { /* symmetric pause */
3653 val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
3654 }
3655 }
3656 writel(val, cp->regs + REG_MAC_CTRL_CFG);
3657 cas_start_dma(cp);
3658 }
3659
3660 /* Must be invoked under cp->lock. */
3661 static void cas_init_hw(struct cas *cp, int restart_link)
3662 {
3663 if (restart_link)
3664 cas_phy_init(cp);
3665
3666 cas_init_pause_thresholds(cp);
3667 cas_init_mac(cp);
3668 cas_init_dma(cp);
3669
3670 if (restart_link) {
3671 /* Default aneg parameters */
3672 cp->timer_ticks = 0;
3673 cas_begin_auto_negotiation(cp, NULL);
3674 } else if (cp->lstate == link_up) {
3675 cas_set_link_modes(cp);
3676 netif_carrier_on(cp->dev);
3677 }
3678 }
3679
3680 /* Must be invoked under cp->lock. on earlier cassini boards,
3681 * SOFT_0 is tied to PCI reset. we use this to force a pci reset,
3682 * let it settle out, and then restore pci state.
3683 */
3684 static void cas_hard_reset(struct cas *cp)
3685 {
3686 writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3687 udelay(20);
3688 pci_restore_state(cp->pdev);
3689 }
3690
3691
3692 static void cas_global_reset(struct cas *cp, int blkflag)
3693 {
3694 int limit;
3695
3696 /* issue a global reset. don't use RSTOUT. */
3697 if (blkflag && !CAS_PHY_MII(cp->phy_type)) {
3698 /* For PCS, when the blkflag is set, we should set the
3699 * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of
3700 * the last autonegotiation from being cleared. We'll
3701 * need some special handling if the chip is set into a
3702 * loopback mode.
3703 */
3704 writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK),
3705 cp->regs + REG_SW_RESET);
3706 } else {
3707 writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);
3708 }
3709
3710 /* need to wait at least 3ms before polling register */
3711 mdelay(3);
3712
3713 limit = STOP_TRIES;
3714 while (limit-- > 0) {
3715 u32 val = readl(cp->regs + REG_SW_RESET);
3716 if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0)
3717 goto done;
3718 udelay(10);
3719 }
3720 netdev_err(cp->dev, "sw reset failed\n");
3721
3722 done:
3723 /* enable various BIM interrupts */
3724 writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE |
3725 BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG);
3726
3727 /* clear out pci error status mask for handled errors.
3728 * we don't deal with DMA counter overflows as they happen
3729 * all the time.
3730 */
3731 writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO |
3732 PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE |
3733 PCI_ERR_BIM_DMA_READ), cp->regs +
3734 REG_PCI_ERR_STATUS_MASK);
3735
3736 /* set up for MII by default to address mac rx reset timeout
3737 * issue
3738 */
3739 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3740 }
3741
3742 static void cas_reset(struct cas *cp, int blkflag)
3743 {
3744 u32 val;
3745
3746 cas_mask_intr(cp);
3747 cas_global_reset(cp, blkflag);
3748 cas_mac_reset(cp);
3749 cas_entropy_reset(cp);
3750
3751 /* disable dma engines. */
3752 val = readl(cp->regs + REG_TX_CFG);
3753 val &= ~TX_CFG_DMA_EN;
3754 writel(val, cp->regs + REG_TX_CFG);
3755
3756 val = readl(cp->regs + REG_RX_CFG);
3757 val &= ~RX_CFG_DMA_EN;
3758 writel(val, cp->regs + REG_RX_CFG);
3759
3760 /* program header parser */
3761 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) ||
3762 (&CAS_HP_ALT_FIRMWARE[0] == &cas_prog_null[0])) {
3763 cas_load_firmware(cp, CAS_HP_FIRMWARE);
3764 } else {
3765 cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE);
3766 }
3767
3768 /* clear out error registers */
3769 spin_lock(&cp->stat_lock[N_TX_RINGS]);
3770 cas_clear_mac_err(cp);
3771 spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3772 }
3773
3774 /* Shut down the chip, must be called with pm_mutex held. */
3775 static void cas_shutdown(struct cas *cp)
3776 {
3777 unsigned long flags;
3778
3779 /* Make us not-running to avoid timers respawning */
3780 cp->hw_running = 0;
3781
3782 del_timer_sync(&cp->link_timer);
3783
3784 /* Stop the reset task */
3785 #if 0
3786 while (atomic_read(&cp->reset_task_pending_mtu) ||
3787 atomic_read(&cp->reset_task_pending_spare) ||
3788 atomic_read(&cp->reset_task_pending_all))
3789 schedule();
3790
3791 #else
3792 while (atomic_read(&cp->reset_task_pending))
3793 schedule();
3794 #endif
3795 /* Actually stop the chip */
3796 cas_lock_all_save(cp, flags);
3797 cas_reset(cp, 0);
3798 if (cp->cas_flags & CAS_FLAG_SATURN)
3799 cas_phy_powerdown(cp);
3800 cas_unlock_all_restore(cp, flags);
3801 }
3802
3803 static int cas_change_mtu(struct net_device *dev, int new_mtu)
3804 {
3805 struct cas *cp = netdev_priv(dev);
3806
3807 WRITE_ONCE(dev->mtu, new_mtu);
3808 if (!netif_running(dev) || !netif_device_present(dev))
3809 return 0;
3810
3811 /* let the reset task handle it */
3812 #if 1
3813 atomic_inc(&cp->reset_task_pending);
3814 if ((cp->phy_type & CAS_PHY_SERDES)) {
3815 atomic_inc(&cp->reset_task_pending_all);
3816 } else {
3817 atomic_inc(&cp->reset_task_pending_mtu);
3818 }
3819 schedule_work(&cp->reset_task);
3820 #else
3821 atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ?
3822 CAS_RESET_ALL : CAS_RESET_MTU);
3823 pr_err("reset called in cas_change_mtu\n");
3824 schedule_work(&cp->reset_task);
3825 #endif
3826
3827 flush_work(&cp->reset_task);
3828 return 0;
3829 }
3830
3831 static void cas_clean_txd(struct cas *cp, int ring)
3832 {
3833 struct cas_tx_desc *txd = cp->init_txds[ring];
3834 struct sk_buff *skb, **skbs = cp->tx_skbs[ring];
3835 u64 daddr, dlen;
3836 int i, size;
3837
3838 size = TX_DESC_RINGN_SIZE(ring);
3839 for (i = 0; i < size; i++) {
3840 int frag;
3841
3842 if (skbs[i] == NULL)
3843 continue;
3844
3845 skb = skbs[i];
3846 skbs[i] = NULL;
3847
3848 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
3849 int ent = i & (size - 1);
3850
3851 /* first buffer is never a tiny buffer and so
3852 * needs to be unmapped.
3853 */
3854 daddr = le64_to_cpu(txd[ent].buffer);
3855 dlen = CAS_VAL(TX_DESC_BUFLEN,
3856 le64_to_cpu(txd[ent].control));
3857 dma_unmap_page(&cp->pdev->dev, daddr, dlen,
3858 DMA_TO_DEVICE);
3859
3860 if (frag != skb_shinfo(skb)->nr_frags) {
3861 i++;
3862
3863 /* next buffer might by a tiny buffer.
3864 * skip past it.
3865 */
3866 ent = i & (size - 1);
3867 if (cp->tx_tiny_use[ring][ent].used)
3868 i++;
3869 }
3870 }
3871 dev_kfree_skb_any(skb);
3872 }
3873
3874 /* zero out tiny buf usage */
3875 memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring]));
3876 }
3877
3878 /* freed on close */
3879 static inline void cas_free_rx_desc(struct cas *cp, int ring)
3880 {
3881 cas_page_t **page = cp->rx_pages[ring];
3882 int i, size;
3883
3884 size = RX_DESC_RINGN_SIZE(ring);
3885 for (i = 0; i < size; i++) {
3886 if (page[i]) {
3887 cas_page_free(cp, page[i]);
3888 page[i] = NULL;
3889 }
3890 }
3891 }
3892
3893 static void cas_free_rxds(struct cas *cp)
3894 {
3895 int i;
3896
3897 for (i = 0; i < N_RX_DESC_RINGS; i++)
3898 cas_free_rx_desc(cp, i);
3899 }
3900
3901 /* Must be invoked under cp->lock. */
3902 static void cas_clean_rings(struct cas *cp)
3903 {
3904 int i;
3905
3906 /* need to clean all tx rings */
3907 memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS);
3908 memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS);
3909 for (i = 0; i < N_TX_RINGS; i++)
3910 cas_clean_txd(cp, i);
3911
3912 /* zero out init block */
3913 memset(cp->init_block, 0, sizeof(struct cas_init_block));
3914 cas_clean_rxds(cp);
3915 cas_clean_rxcs(cp);
3916 }
3917
3918 /* allocated on open */
3919 static inline int cas_alloc_rx_desc(struct cas *cp, int ring)
3920 {
3921 cas_page_t **page = cp->rx_pages[ring];
3922 int size, i = 0;
3923
3924 size = RX_DESC_RINGN_SIZE(ring);
3925 for (i = 0; i < size; i++) {
3926 if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL)
3927 return -1;
3928 }
3929 return 0;
3930 }
3931
3932 static int cas_alloc_rxds(struct cas *cp)
3933 {
3934 int i;
3935
3936 for (i = 0; i < N_RX_DESC_RINGS; i++) {
3937 if (cas_alloc_rx_desc(cp, i) < 0) {
3938 cas_free_rxds(cp);
3939 return -1;
3940 }
3941 }
3942 return 0;
3943 }
3944
3945 static void cas_reset_task(struct work_struct *work)
3946 {
3947 struct cas *cp = container_of(work, struct cas, reset_task);
3948 #if 0
3949 int pending = atomic_read(&cp->reset_task_pending);
3950 #else
3951 int pending_all = atomic_read(&cp->reset_task_pending_all);
3952 int pending_spare = atomic_read(&cp->reset_task_pending_spare);
3953 int pending_mtu = atomic_read(&cp->reset_task_pending_mtu);
3954
3955 if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) {
3956 /* We can have more tasks scheduled than actually
3957 * needed.
3958 */
3959 atomic_dec(&cp->reset_task_pending);
3960 return;
3961 }
3962 #endif
3963 /* The link went down, we reset the ring, but keep
3964 * DMA stopped. Use this function for reset
3965 * on error as well.
3966 */
3967 if (cp->hw_running) {
3968 unsigned long flags;
3969
3970 /* Make sure we don't get interrupts or tx packets */
3971 netif_device_detach(cp->dev);
3972 cas_lock_all_save(cp, flags);
3973
3974 if (cp->opened) {
3975 /* We call cas_spare_recover when we call cas_open.
3976 * but we do not initialize the lists cas_spare_recover
3977 * uses until cas_open is called.
3978 */
3979 cas_spare_recover(cp, GFP_ATOMIC);
3980 }
3981 #if 1
3982 /* test => only pending_spare set */
3983 if (!pending_all && !pending_mtu)
3984 goto done;
3985 #else
3986 if (pending == CAS_RESET_SPARE)
3987 goto done;
3988 #endif
3989 /* when pending == CAS_RESET_ALL, the following
3990 * call to cas_init_hw will restart auto negotiation.
3991 * Setting the second argument of cas_reset to
3992 * !(pending == CAS_RESET_ALL) will set this argument
3993 * to 1 (avoiding reinitializing the PHY for the normal
3994 * PCS case) when auto negotiation is not restarted.
3995 */
3996 #if 1
3997 cas_reset(cp, !(pending_all > 0));
3998 if (cp->opened)
3999 cas_clean_rings(cp);
4000 cas_init_hw(cp, (pending_all > 0));
4001 #else
4002 cas_reset(cp, !(pending == CAS_RESET_ALL));
4003 if (cp->opened)
4004 cas_clean_rings(cp);
4005 cas_init_hw(cp, pending == CAS_RESET_ALL);
4006 #endif
4007
4008 done:
4009 cas_unlock_all_restore(cp, flags);
4010 netif_device_attach(cp->dev);
4011 }
4012 #if 1
4013 atomic_sub(pending_all, &cp->reset_task_pending_all);
4014 atomic_sub(pending_spare, &cp->reset_task_pending_spare);
4015 atomic_sub(pending_mtu, &cp->reset_task_pending_mtu);
4016 atomic_dec(&cp->reset_task_pending);
4017 #else
4018 atomic_set(&cp->reset_task_pending, 0);
4019 #endif
4020 }
4021
4022 static void cas_link_timer(struct timer_list *t)
4023 {
4024 struct cas *cp = from_timer(cp, t, link_timer);
4025 int mask, pending = 0, reset = 0;
4026 unsigned long flags;
4027
4028 if (link_transition_timeout != 0 &&
4029 cp->link_transition_jiffies_valid &&
4030 time_is_before_jiffies(cp->link_transition_jiffies +
4031 link_transition_timeout)) {
4032 /* One-second counter so link-down workaround doesn't
4033 * cause resets to occur so fast as to fool the switch
4034 * into thinking the link is down.
4035 */
4036 cp->link_transition_jiffies_valid = 0;
4037 }
4038
4039 if (!cp->hw_running)
4040 return;
4041
4042 spin_lock_irqsave(&cp->lock, flags);
4043 cas_lock_tx(cp);
4044 cas_entropy_gather(cp);
4045
4046 /* If the link task is still pending, we just
4047 * reschedule the link timer
4048 */
4049 #if 1
4050 if (atomic_read(&cp->reset_task_pending_all) ||
4051 atomic_read(&cp->reset_task_pending_spare) ||
4052 atomic_read(&cp->reset_task_pending_mtu))
4053 goto done;
4054 #else
4055 if (atomic_read(&cp->reset_task_pending))
4056 goto done;
4057 #endif
4058
4059 /* check for rx cleaning */
4060 if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) {
4061 int i, rmask;
4062
4063 for (i = 0; i < MAX_RX_DESC_RINGS; i++) {
4064 rmask = CAS_FLAG_RXD_POST(i);
4065 if ((mask & rmask) == 0)
4066 continue;
4067
4068 /* post_rxds will do a mod_timer */
4069 if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) {
4070 pending = 1;
4071 continue;
4072 }
4073 cp->cas_flags &= ~rmask;
4074 }
4075 }
4076
4077 if (CAS_PHY_MII(cp->phy_type)) {
4078 u16 bmsr;
4079 cas_mif_poll(cp, 0);
4080 bmsr = cas_phy_read(cp, MII_BMSR);
4081 /* WTZ: Solaris driver reads this twice, but that
4082 * may be due to the PCS case and the use of a
4083 * common implementation. Read it twice here to be
4084 * safe.
4085 */
4086 bmsr = cas_phy_read(cp, MII_BMSR);
4087 cas_mif_poll(cp, 1);
4088 readl(cp->regs + REG_MIF_STATUS); /* avoid dups */
4089 reset = cas_mii_link_check(cp, bmsr);
4090 } else {
4091 reset = cas_pcs_link_check(cp);
4092 }
4093
4094 if (reset)
4095 goto done;
4096
4097 /* check for tx state machine confusion */
4098 if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) {
4099 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE);
4100 u32 wptr, rptr;
4101 int tlm = CAS_VAL(MAC_SM_TLM, val);
4102
4103 if (((tlm == 0x5) || (tlm == 0x3)) &&
4104 (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) {
4105 netif_printk(cp, tx_err, KERN_DEBUG, cp->dev,
4106 "tx err: MAC_STATE[%08x]\n", val);
4107 reset = 1;
4108 goto done;
4109 }
4110
4111 val = readl(cp->regs + REG_TX_FIFO_PKT_CNT);
4112 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR);
4113 rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR);
4114 if ((val == 0) && (wptr != rptr)) {
4115 netif_printk(cp, tx_err, KERN_DEBUG, cp->dev,
4116 "tx err: TX_FIFO[%08x:%08x:%08x]\n",
4117 val, wptr, rptr);
4118 reset = 1;
4119 }
4120
4121 if (reset)
4122 cas_hard_reset(cp);
4123 }
4124
4125 done:
4126 if (reset) {
4127 #if 1
4128 atomic_inc(&cp->reset_task_pending);
4129 atomic_inc(&cp->reset_task_pending_all);
4130 schedule_work(&cp->reset_task);
4131 #else
4132 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
4133 pr_err("reset called in cas_link_timer\n");
4134 schedule_work(&cp->reset_task);
4135 #endif
4136 }
4137
4138 if (!pending)
4139 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
4140 cas_unlock_tx(cp);
4141 spin_unlock_irqrestore(&cp->lock, flags);
4142 }
4143
4144 /* tiny buffers are used to avoid target abort issues with
4145 * older cassini's
4146 */
4147 static void cas_tx_tiny_free(struct cas *cp)
4148 {
4149 struct pci_dev *pdev = cp->pdev;
4150 int i;
4151
4152 for (i = 0; i < N_TX_RINGS; i++) {
4153 if (!cp->tx_tiny_bufs[i])
4154 continue;
4155
4156 dma_free_coherent(&pdev->dev, TX_TINY_BUF_BLOCK,
4157 cp->tx_tiny_bufs[i], cp->tx_tiny_dvma[i]);
4158 cp->tx_tiny_bufs[i] = NULL;
4159 }
4160 }
4161
4162 static int cas_tx_tiny_alloc(struct cas *cp)
4163 {
4164 struct pci_dev *pdev = cp->pdev;
4165 int i;
4166
4167 for (i = 0; i < N_TX_RINGS; i++) {
4168 cp->tx_tiny_bufs[i] =
4169 dma_alloc_coherent(&pdev->dev, TX_TINY_BUF_BLOCK,
4170 &cp->tx_tiny_dvma[i], GFP_KERNEL);
4171 if (!cp->tx_tiny_bufs[i]) {
4172 cas_tx_tiny_free(cp);
4173 return -1;
4174 }
4175 }
4176 return 0;
4177 }
4178
4179
4180 static int cas_open(struct net_device *dev)
4181 {
4182 struct cas *cp = netdev_priv(dev);
4183 int hw_was_up, err;
4184 unsigned long flags;
4185
4186 mutex_lock(&cp->pm_mutex);
4187
4188 hw_was_up = cp->hw_running;
4189
4190 /* The power-management mutex protects the hw_running
4191 * etc. state so it is safe to do this bit without cp->lock
4192 */
4193 if (!cp->hw_running) {
4194 /* Reset the chip */
4195 cas_lock_all_save(cp, flags);
4196 /* We set the second arg to cas_reset to zero
4197 * because cas_init_hw below will have its second
4198 * argument set to non-zero, which will force
4199 * autonegotiation to start.
4200 */
4201 cas_reset(cp, 0);
4202 cp->hw_running = 1;
4203 cas_unlock_all_restore(cp, flags);
4204 }
4205
4206 err = -ENOMEM;
4207 if (cas_tx_tiny_alloc(cp) < 0)
4208 goto err_unlock;
4209
4210 /* alloc rx descriptors */
4211 if (cas_alloc_rxds(cp) < 0)
4212 goto err_tx_tiny;
4213
4214 /* allocate spares */
4215 cas_spare_init(cp);
4216 cas_spare_recover(cp, GFP_KERNEL);
4217
4218 /* We can now request the interrupt as we know it's masked
4219 * on the controller. cassini+ has up to 4 interrupts
4220 * that can be used, but you need to do explicit pci interrupt
4221 * mapping to expose them
4222 */
4223 if (request_irq(cp->pdev->irq, cas_interrupt,
4224 IRQF_SHARED, dev->name, (void *) dev)) {
4225 netdev_err(cp->dev, "failed to request irq !\n");
4226 err = -EAGAIN;
4227 goto err_spare;
4228 }
4229
4230 #ifdef USE_NAPI
4231 napi_enable(&cp->napi);
4232 #endif
4233 /* init hw */
4234 cas_lock_all_save(cp, flags);
4235 cas_clean_rings(cp);
4236 cas_init_hw(cp, !hw_was_up);
4237 cp->opened = 1;
4238 cas_unlock_all_restore(cp, flags);
4239
4240 netif_start_queue(dev);
4241 mutex_unlock(&cp->pm_mutex);
4242 return 0;
4243
4244 err_spare:
4245 cas_spare_free(cp);
4246 cas_free_rxds(cp);
4247 err_tx_tiny:
4248 cas_tx_tiny_free(cp);
4249 err_unlock:
4250 mutex_unlock(&cp->pm_mutex);
4251 return err;
4252 }
4253
4254 static int cas_close(struct net_device *dev)
4255 {
4256 unsigned long flags;
4257 struct cas *cp = netdev_priv(dev);
4258
4259 #ifdef USE_NAPI
4260 napi_disable(&cp->napi);
4261 #endif
4262 /* Make sure we don't get distracted by suspend/resume */
4263 mutex_lock(&cp->pm_mutex);
4264
4265 netif_stop_queue(dev);
4266
4267 /* Stop traffic, mark us closed */
4268 cas_lock_all_save(cp, flags);
4269 cp->opened = 0;
4270 cas_reset(cp, 0);
4271 cas_phy_init(cp);
4272 cas_begin_auto_negotiation(cp, NULL);
4273 cas_clean_rings(cp);
4274 cas_unlock_all_restore(cp, flags);
4275
4276 free_irq(cp->pdev->irq, (void *) dev);
4277 cas_spare_free(cp);
4278 cas_free_rxds(cp);
4279 cas_tx_tiny_free(cp);
4280 mutex_unlock(&cp->pm_mutex);
4281 return 0;
4282 }
4283
4284 static struct {
4285 const char name[ETH_GSTRING_LEN];
4286 } ethtool_cassini_statnames[] = {
4287 {"collisions"},
4288 {"rx_bytes"},
4289 {"rx_crc_errors"},
4290 {"rx_dropped"},
4291 {"rx_errors"},
4292 {"rx_fifo_errors"},
4293 {"rx_frame_errors"},
4294 {"rx_length_errors"},
4295 {"rx_over_errors"},
4296 {"rx_packets"},
4297 {"tx_aborted_errors"},
4298 {"tx_bytes"},
4299 {"tx_dropped"},
4300 {"tx_errors"},
4301 {"tx_fifo_errors"},
4302 {"tx_packets"}
4303 };
4304 #define CAS_NUM_STAT_KEYS ARRAY_SIZE(ethtool_cassini_statnames)
4305
4306 static struct {
4307 const int offsets; /* neg. values for 2nd arg to cas_read_phy */
4308 } ethtool_register_table[] = {
4309 {-MII_BMSR},
4310 {-MII_BMCR},
4311 {REG_CAWR},
4312 {REG_INF_BURST},
4313 {REG_BIM_CFG},
4314 {REG_RX_CFG},
4315 {REG_HP_CFG},
4316 {REG_MAC_TX_CFG},
4317 {REG_MAC_RX_CFG},
4318 {REG_MAC_CTRL_CFG},
4319 {REG_MAC_XIF_CFG},
4320 {REG_MIF_CFG},
4321 {REG_PCS_CFG},
4322 {REG_SATURN_PCFG},
4323 {REG_PCS_MII_STATUS},
4324 {REG_PCS_STATE_MACHINE},
4325 {REG_MAC_COLL_EXCESS},
4326 {REG_MAC_COLL_LATE}
4327 };
4328 #define CAS_REG_LEN ARRAY_SIZE(ethtool_register_table)
4329 #define CAS_MAX_REGS (sizeof (u32)*CAS_REG_LEN)
4330
4331 static void cas_read_regs(struct cas *cp, u8 *ptr, int len)
4332 {
4333 u8 *p;
4334 int i;
4335 unsigned long flags;
4336
4337 spin_lock_irqsave(&cp->lock, flags);
4338 for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) {
4339 u16 hval;
4340 u32 val;
4341 if (ethtool_register_table[i].offsets < 0) {
4342 hval = cas_phy_read(cp,
4343 -ethtool_register_table[i].offsets);
4344 val = hval;
4345 } else {
4346 val= readl(cp->regs+ethtool_register_table[i].offsets);
4347 }
4348 memcpy(p, (u8 *)&val, sizeof(u32));
4349 }
4350 spin_unlock_irqrestore(&cp->lock, flags);
4351 }
4352
4353 static struct net_device_stats *cas_get_stats(struct net_device *dev)
4354 {
4355 struct cas *cp = netdev_priv(dev);
4356 struct net_device_stats *stats = cp->net_stats;
4357 unsigned long flags;
4358 int i;
4359 unsigned long tmp;
4360
4361 /* we collate all of the stats into net_stats[N_TX_RING] */
4362 if (!cp->hw_running)
4363 return stats + N_TX_RINGS;
4364
4365 /* collect outstanding stats */
4366 /* WTZ: the Cassini spec gives these as 16 bit counters but
4367 * stored in 32-bit words. Added a mask of 0xffff to be safe,
4368 * in case the chip somehow puts any garbage in the other bits.
4369 * Also, counter usage didn't seem to mach what Adrian did
4370 * in the parts of the code that set these quantities. Made
4371 * that consistent.
4372 */
4373 spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags);
4374 stats[N_TX_RINGS].rx_crc_errors +=
4375 readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff;
4376 stats[N_TX_RINGS].rx_frame_errors +=
4377 readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff;
4378 stats[N_TX_RINGS].rx_length_errors +=
4379 readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff;
4380 #if 1
4381 tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) +
4382 (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff);
4383 stats[N_TX_RINGS].tx_aborted_errors += tmp;
4384 stats[N_TX_RINGS].collisions +=
4385 tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff);
4386 #else
4387 stats[N_TX_RINGS].tx_aborted_errors +=
4388 readl(cp->regs + REG_MAC_COLL_EXCESS);
4389 stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) +
4390 readl(cp->regs + REG_MAC_COLL_LATE);
4391 #endif
4392 cas_clear_mac_err(cp);
4393
4394 /* saved bits that are unique to ring 0 */
4395 spin_lock(&cp->stat_lock[0]);
4396 stats[N_TX_RINGS].collisions += stats[0].collisions;
4397 stats[N_TX_RINGS].rx_over_errors += stats[0].rx_over_errors;
4398 stats[N_TX_RINGS].rx_frame_errors += stats[0].rx_frame_errors;
4399 stats[N_TX_RINGS].rx_fifo_errors += stats[0].rx_fifo_errors;
4400 stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors;
4401 stats[N_TX_RINGS].tx_fifo_errors += stats[0].tx_fifo_errors;
4402 spin_unlock(&cp->stat_lock[0]);
4403
4404 for (i = 0; i < N_TX_RINGS; i++) {
4405 spin_lock(&cp->stat_lock[i]);
4406 stats[N_TX_RINGS].rx_length_errors +=
4407 stats[i].rx_length_errors;
4408 stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors;
4409 stats[N_TX_RINGS].rx_packets += stats[i].rx_packets;
4410 stats[N_TX_RINGS].tx_packets += stats[i].tx_packets;
4411 stats[N_TX_RINGS].rx_bytes += stats[i].rx_bytes;
4412 stats[N_TX_RINGS].tx_bytes += stats[i].tx_bytes;
4413 stats[N_TX_RINGS].rx_errors += stats[i].rx_errors;
4414 stats[N_TX_RINGS].tx_errors += stats[i].tx_errors;
4415 stats[N_TX_RINGS].rx_dropped += stats[i].rx_dropped;
4416 stats[N_TX_RINGS].tx_dropped += stats[i].tx_dropped;
4417 memset(stats + i, 0, sizeof(struct net_device_stats));
4418 spin_unlock(&cp->stat_lock[i]);
4419 }
4420 spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags);
4421 return stats + N_TX_RINGS;
4422 }
4423
4424
4425 static void cas_set_multicast(struct net_device *dev)
4426 {
4427 struct cas *cp = netdev_priv(dev);
4428 u32 rxcfg, rxcfg_new;
4429 unsigned long flags;
4430 int limit = STOP_TRIES;
4431
4432 if (!cp->hw_running)
4433 return;
4434
4435 spin_lock_irqsave(&cp->lock, flags);
4436 rxcfg = readl(cp->regs + REG_MAC_RX_CFG);
4437
4438 /* disable RX MAC and wait for completion */
4439 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4440 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) {
4441 if (!limit--)
4442 break;
4443 udelay(10);
4444 }
4445
4446 /* disable hash filter and wait for completion */
4447 limit = STOP_TRIES;
4448 rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN);
4449 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4450 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) {
4451 if (!limit--)
4452 break;
4453 udelay(10);
4454 }
4455
4456 /* program hash filters */
4457 cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp);
4458 rxcfg |= rxcfg_new;
4459 writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
4460 spin_unlock_irqrestore(&cp->lock, flags);
4461 }
4462
4463 static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4464 {
4465 struct cas *cp = netdev_priv(dev);
4466 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
4467 strscpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
4468 strscpy(info->bus_info, pci_name(cp->pdev), sizeof(info->bus_info));
4469 }
4470
4471 static int cas_get_link_ksettings(struct net_device *dev,
4472 struct ethtool_link_ksettings *cmd)
4473 {
4474 struct cas *cp = netdev_priv(dev);
4475 u16 bmcr;
4476 int full_duplex, speed, pause;
4477 unsigned long flags;
4478 enum link_state linkstate = link_up;
4479 u32 supported, advertising;
4480
4481 advertising = 0;
4482 supported = SUPPORTED_Autoneg;
4483 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
4484 supported |= SUPPORTED_1000baseT_Full;
4485 advertising |= ADVERTISED_1000baseT_Full;
4486 }
4487
4488 /* Record PHY settings if HW is on. */
4489 spin_lock_irqsave(&cp->lock, flags);
4490 bmcr = 0;
4491 linkstate = cp->lstate;
4492 if (CAS_PHY_MII(cp->phy_type)) {
4493 cmd->base.port = PORT_MII;
4494 cmd->base.phy_address = cp->phy_addr;
4495 advertising |= ADVERTISED_TP | ADVERTISED_MII |
4496 ADVERTISED_10baseT_Half |
4497 ADVERTISED_10baseT_Full |
4498 ADVERTISED_100baseT_Half |
4499 ADVERTISED_100baseT_Full;
4500
4501 supported |=
4502 (SUPPORTED_10baseT_Half |
4503 SUPPORTED_10baseT_Full |
4504 SUPPORTED_100baseT_Half |
4505 SUPPORTED_100baseT_Full |
4506 SUPPORTED_TP | SUPPORTED_MII);
4507
4508 if (cp->hw_running) {
4509 cas_mif_poll(cp, 0);
4510 bmcr = cas_phy_read(cp, MII_BMCR);
4511 cas_read_mii_link_mode(cp, &full_duplex,
4512 &speed, &pause);
4513 cas_mif_poll(cp, 1);
4514 }
4515
4516 } else {
4517 cmd->base.port = PORT_FIBRE;
4518 cmd->base.phy_address = 0;
4519 supported |= SUPPORTED_FIBRE;
4520 advertising |= ADVERTISED_FIBRE;
4521
4522 if (cp->hw_running) {
4523 /* pcs uses the same bits as mii */
4524 bmcr = readl(cp->regs + REG_PCS_MII_CTRL);
4525 cas_read_pcs_link_mode(cp, &full_duplex,
4526 &speed, &pause);
4527 }
4528 }
4529 spin_unlock_irqrestore(&cp->lock, flags);
4530
4531 if (bmcr & BMCR_ANENABLE) {
4532 advertising |= ADVERTISED_Autoneg;
4533 cmd->base.autoneg = AUTONEG_ENABLE;
4534 cmd->base.speed = ((speed == 10) ?
4535 SPEED_10 :
4536 ((speed == 1000) ?
4537 SPEED_1000 : SPEED_100));
4538 cmd->base.duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
4539 } else {
4540 cmd->base.autoneg = AUTONEG_DISABLE;
4541 cmd->base.speed = ((bmcr & CAS_BMCR_SPEED1000) ?
4542 SPEED_1000 :
4543 ((bmcr & BMCR_SPEED100) ?
4544 SPEED_100 : SPEED_10));
4545 cmd->base.duplex = (bmcr & BMCR_FULLDPLX) ?
4546 DUPLEX_FULL : DUPLEX_HALF;
4547 }
4548 if (linkstate != link_up) {
4549 /* Force these to "unknown" if the link is not up and
4550 * autonogotiation in enabled. We can set the link
4551 * speed to 0, but not cmd->duplex,
4552 * because its legal values are 0 and 1. Ethtool will
4553 * print the value reported in parentheses after the
4554 * word "Unknown" for unrecognized values.
4555 *
4556 * If in forced mode, we report the speed and duplex
4557 * settings that we configured.
4558 */
4559 if (cp->link_cntl & BMCR_ANENABLE) {
4560 cmd->base.speed = 0;
4561 cmd->base.duplex = 0xff;
4562 } else {
4563 cmd->base.speed = SPEED_10;
4564 if (cp->link_cntl & BMCR_SPEED100) {
4565 cmd->base.speed = SPEED_100;
4566 } else if (cp->link_cntl & CAS_BMCR_SPEED1000) {
4567 cmd->base.speed = SPEED_1000;
4568 }
4569 cmd->base.duplex = (cp->link_cntl & BMCR_FULLDPLX) ?
4570 DUPLEX_FULL : DUPLEX_HALF;
4571 }
4572 }
4573
4574 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
4575 supported);
4576 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
4577 advertising);
4578
4579 return 0;
4580 }
4581
4582 static int cas_set_link_ksettings(struct net_device *dev,
4583 const struct ethtool_link_ksettings *cmd)
4584 {
4585 struct cas *cp = netdev_priv(dev);
4586 unsigned long flags;
4587 u32 speed = cmd->base.speed;
4588
4589 /* Verify the settings we care about. */
4590 if (cmd->base.autoneg != AUTONEG_ENABLE &&
4591 cmd->base.autoneg != AUTONEG_DISABLE)
4592 return -EINVAL;
4593
4594 if (cmd->base.autoneg == AUTONEG_DISABLE &&
4595 ((speed != SPEED_1000 &&
4596 speed != SPEED_100 &&
4597 speed != SPEED_10) ||
4598 (cmd->base.duplex != DUPLEX_HALF &&
4599 cmd->base.duplex != DUPLEX_FULL)))
4600 return -EINVAL;
4601
4602 /* Apply settings and restart link process. */
4603 spin_lock_irqsave(&cp->lock, flags);
4604 cas_begin_auto_negotiation(cp, cmd);
4605 spin_unlock_irqrestore(&cp->lock, flags);
4606 return 0;
4607 }
4608
4609 static int cas_nway_reset(struct net_device *dev)
4610 {
4611 struct cas *cp = netdev_priv(dev);
4612 unsigned long flags;
4613
4614 if ((cp->link_cntl & BMCR_ANENABLE) == 0)
4615 return -EINVAL;
4616
4617 /* Restart link process. */
4618 spin_lock_irqsave(&cp->lock, flags);
4619 cas_begin_auto_negotiation(cp, NULL);
4620 spin_unlock_irqrestore(&cp->lock, flags);
4621
4622 return 0;
4623 }
4624
4625 static u32 cas_get_link(struct net_device *dev)
4626 {
4627 struct cas *cp = netdev_priv(dev);
4628 return cp->lstate == link_up;
4629 }
4630
4631 static u32 cas_get_msglevel(struct net_device *dev)
4632 {
4633 struct cas *cp = netdev_priv(dev);
4634 return cp->msg_enable;
4635 }
4636
4637 static void cas_set_msglevel(struct net_device *dev, u32 value)
4638 {
4639 struct cas *cp = netdev_priv(dev);
4640 cp->msg_enable = value;
4641 }
4642
4643 static int cas_get_regs_len(struct net_device *dev)
4644 {
4645 struct cas *cp = netdev_priv(dev);
4646 return min_t(int, cp->casreg_len, CAS_MAX_REGS);
4647 }
4648
4649 static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4650 void *p)
4651 {
4652 struct cas *cp = netdev_priv(dev);
4653 regs->version = 0;
4654 /* cas_read_regs handles locks (cp->lock). */
4655 cas_read_regs(cp, p, regs->len / sizeof(u32));
4656 }
4657
4658 static int cas_get_sset_count(struct net_device *dev, int sset)
4659 {
4660 switch (sset) {
4661 case ETH_SS_STATS:
4662 return CAS_NUM_STAT_KEYS;
4663 default:
4664 return -EOPNOTSUPP;
4665 }
4666 }
4667
4668 static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4669 {
4670 memcpy(data, &ethtool_cassini_statnames,
4671 CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN);
4672 }
4673
4674 static void cas_get_ethtool_stats(struct net_device *dev,
4675 struct ethtool_stats *estats, u64 *data)
4676 {
4677 struct cas *cp = netdev_priv(dev);
4678 struct net_device_stats *stats = cas_get_stats(cp->dev);
4679 int i = 0;
4680 data[i++] = stats->collisions;
4681 data[i++] = stats->rx_bytes;
4682 data[i++] = stats->rx_crc_errors;
4683 data[i++] = stats->rx_dropped;
4684 data[i++] = stats->rx_errors;
4685 data[i++] = stats->rx_fifo_errors;
4686 data[i++] = stats->rx_frame_errors;
4687 data[i++] = stats->rx_length_errors;
4688 data[i++] = stats->rx_over_errors;
4689 data[i++] = stats->rx_packets;
4690 data[i++] = stats->tx_aborted_errors;
4691 data[i++] = stats->tx_bytes;
4692 data[i++] = stats->tx_dropped;
4693 data[i++] = stats->tx_errors;
4694 data[i++] = stats->tx_fifo_errors;
4695 data[i++] = stats->tx_packets;
4696 BUG_ON(i != CAS_NUM_STAT_KEYS);
4697 }
4698
4699 static const struct ethtool_ops cas_ethtool_ops = {
4700 .get_drvinfo = cas_get_drvinfo,
4701 .nway_reset = cas_nway_reset,
4702 .get_link = cas_get_link,
4703 .get_msglevel = cas_get_msglevel,
4704 .set_msglevel = cas_set_msglevel,
4705 .get_regs_len = cas_get_regs_len,
4706 .get_regs = cas_get_regs,
4707 .get_sset_count = cas_get_sset_count,
4708 .get_strings = cas_get_strings,
4709 .get_ethtool_stats = cas_get_ethtool_stats,
4710 .get_link_ksettings = cas_get_link_ksettings,
4711 .set_link_ksettings = cas_set_link_ksettings,
4712 };
4713
4714 static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4715 {
4716 struct cas *cp = netdev_priv(dev);
4717 struct mii_ioctl_data *data = if_mii(ifr);
4718 unsigned long flags;
4719 int rc = -EOPNOTSUPP;
4720
4721 /* Hold the PM mutex while doing ioctl's or we may collide
4722 * with open/close and power management and oops.
4723 */
4724 mutex_lock(&cp->pm_mutex);
4725 switch (cmd) {
4726 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
4727 data->phy_id = cp->phy_addr;
4728 fallthrough;
4729
4730 case SIOCGMIIREG: /* Read MII PHY register. */
4731 spin_lock_irqsave(&cp->lock, flags);
4732 cas_mif_poll(cp, 0);
4733 data->val_out = cas_phy_read(cp, data->reg_num & 0x1f);
4734 cas_mif_poll(cp, 1);
4735 spin_unlock_irqrestore(&cp->lock, flags);
4736 rc = 0;
4737 break;
4738
4739 case SIOCSMIIREG: /* Write MII PHY register. */
4740 spin_lock_irqsave(&cp->lock, flags);
4741 cas_mif_poll(cp, 0);
4742 rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in);
4743 cas_mif_poll(cp, 1);
4744 spin_unlock_irqrestore(&cp->lock, flags);
4745 break;
4746 default:
4747 break;
4748 }
4749
4750 mutex_unlock(&cp->pm_mutex);
4751 return rc;
4752 }
4753
4754 /* When this chip sits underneath an Intel 31154 bridge, it is the
4755 * only subordinate device and we can tweak the bridge settings to
4756 * reflect that fact.
4757 */
4758 static void cas_program_bridge(struct pci_dev *cas_pdev)
4759 {
4760 struct pci_dev *pdev = cas_pdev->bus->self;
4761 u32 val;
4762
4763 if (!pdev)
4764 return;
4765
4766 if (pdev->vendor != 0x8086 || pdev->device != 0x537c)
4767 return;
4768
4769 /* Clear bit 10 (Bus Parking Control) in the Secondary
4770 * Arbiter Control/Status Register which lives at offset
4771 * 0x41. Using a 32-bit word read/modify/write at 0x40
4772 * is much simpler so that's how we do this.
4773 */
4774 pci_read_config_dword(pdev, 0x40, &val);
4775 val &= ~0x00040000;
4776 pci_write_config_dword(pdev, 0x40, val);
4777
4778 /* Max out the Multi-Transaction Timer settings since
4779 * Cassini is the only device present.
4780 *
4781 * The register is 16-bit and lives at 0x50. When the
4782 * settings are enabled, it extends the GRANT# signal
4783 * for a requestor after a transaction is complete. This
4784 * allows the next request to run without first needing
4785 * to negotiate the GRANT# signal back.
4786 *
4787 * Bits 12:10 define the grant duration:
4788 *
4789 * 1 -- 16 clocks
4790 * 2 -- 32 clocks
4791 * 3 -- 64 clocks
4792 * 4 -- 128 clocks
4793 * 5 -- 256 clocks
4794 *
4795 * All other values are illegal.
4796 *
4797 * Bits 09:00 define which REQ/GNT signal pairs get the
4798 * GRANT# signal treatment. We set them all.
4799 */
4800 pci_write_config_word(pdev, 0x50, (5 << 10) | 0x3ff);
4801
4802 /* The Read Prefecth Policy register is 16-bit and sits at
4803 * offset 0x52. It enables a "smart" pre-fetch policy. We
4804 * enable it and max out all of the settings since only one
4805 * device is sitting underneath and thus bandwidth sharing is
4806 * not an issue.
4807 *
4808 * The register has several 3 bit fields, which indicates a
4809 * multiplier applied to the base amount of prefetching the
4810 * chip would do. These fields are at:
4811 *
4812 * 15:13 --- ReRead Primary Bus
4813 * 12:10 --- FirstRead Primary Bus
4814 * 09:07 --- ReRead Secondary Bus
4815 * 06:04 --- FirstRead Secondary Bus
4816 *
4817 * Bits 03:00 control which REQ/GNT pairs the prefetch settings
4818 * get enabled on. Bit 3 is a grouped enabler which controls
4819 * all of the REQ/GNT pairs from [8:3]. Bits 2 to 0 control
4820 * the individual REQ/GNT pairs [2:0].
4821 */
4822 pci_write_config_word(pdev, 0x52,
4823 (0x7 << 13) |
4824 (0x7 << 10) |
4825 (0x7 << 7) |
4826 (0x7 << 4) |
4827 (0xf << 0));
4828
4829 /* Force cacheline size to 0x8 */
4830 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4831
4832 /* Force latency timer to maximum setting so Cassini can
4833 * sit on the bus as long as it likes.
4834 */
4835 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xff);
4836 }
4837
4838 static const struct net_device_ops cas_netdev_ops = {
4839 .ndo_open = cas_open,
4840 .ndo_stop = cas_close,
4841 .ndo_start_xmit = cas_start_xmit,
4842 .ndo_get_stats = cas_get_stats,
4843 .ndo_set_rx_mode = cas_set_multicast,
4844 .ndo_eth_ioctl = cas_ioctl,
4845 .ndo_tx_timeout = cas_tx_timeout,
4846 .ndo_change_mtu = cas_change_mtu,
4847 .ndo_set_mac_address = eth_mac_addr,
4848 .ndo_validate_addr = eth_validate_addr,
4849 #ifdef CONFIG_NET_POLL_CONTROLLER
4850 .ndo_poll_controller = cas_netpoll,
4851 #endif
4852 };
4853
4854 static int cas_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4855 {
4856 static int cas_version_printed = 0;
4857 unsigned long casreg_len;
4858 struct net_device *dev;
4859 struct cas *cp;
4860 u16 pci_cmd;
4861 int i, err;
4862 u8 orig_cacheline_size = 0, cas_cacheline_size = 0;
4863
4864 if (cas_version_printed++ == 0)
4865 pr_info("%s", version);
4866
4867 err = pci_enable_device(pdev);
4868 if (err) {
4869 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
4870 return err;
4871 }
4872
4873 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4874 dev_err(&pdev->dev, "Cannot find proper PCI device "
4875 "base address, aborting\n");
4876 err = -ENODEV;
4877 goto err_out_disable_pdev;
4878 }
4879
4880 dev = alloc_etherdev(sizeof(*cp));
4881 if (!dev) {
4882 err = -ENOMEM;
4883 goto err_out_disable_pdev;
4884 }
4885 SET_NETDEV_DEV(dev, &pdev->dev);
4886
4887 err = pci_request_regions(pdev, dev->name);
4888 if (err) {
4889 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
4890 goto err_out_free_netdev;
4891 }
4892 pci_set_master(pdev);
4893
4894 /* we must always turn on parity response or else parity
4895 * doesn't get generated properly. disable SERR/PERR as well.
4896 * in addition, we want to turn MWI on.
4897 */
4898 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4899 pci_cmd &= ~PCI_COMMAND_SERR;
4900 pci_cmd |= PCI_COMMAND_PARITY;
4901 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4902 if (pci_try_set_mwi(pdev))
4903 pr_warn("Could not enable MWI for %s\n", pci_name(pdev));
4904
4905 cas_program_bridge(pdev);
4906
4907 /*
4908 * On some architectures, the default cache line size set
4909 * by pci_try_set_mwi reduces perforamnce. We have to increase
4910 * it for this case. To start, we'll print some configuration
4911 * data.
4912 */
4913 #if 1
4914 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
4915 &orig_cacheline_size);
4916 if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) {
4917 cas_cacheline_size =
4918 (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ?
4919 CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES;
4920 if (pci_write_config_byte(pdev,
4921 PCI_CACHE_LINE_SIZE,
4922 cas_cacheline_size)) {
4923 dev_err(&pdev->dev, "Could not set PCI cache "
4924 "line size\n");
4925 goto err_out_free_res;
4926 }
4927 }
4928 #endif
4929
4930
4931 /* Configure DMA attributes. */
4932 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4933 if (err) {
4934 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
4935 goto err_out_free_res;
4936 }
4937
4938 casreg_len = pci_resource_len(pdev, 0);
4939
4940 cp = netdev_priv(dev);
4941 cp->pdev = pdev;
4942 #if 1
4943 /* A value of 0 indicates we never explicitly set it */
4944 cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0;
4945 #endif
4946 cp->dev = dev;
4947 cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE :
4948 cassini_debug;
4949
4950 #if defined(CONFIG_SPARC)
4951 cp->of_node = pci_device_to_OF_node(pdev);
4952 #endif
4953
4954 cp->link_transition = LINK_TRANSITION_UNKNOWN;
4955 cp->link_transition_jiffies_valid = 0;
4956
4957 spin_lock_init(&cp->lock);
4958 spin_lock_init(&cp->rx_inuse_lock);
4959 spin_lock_init(&cp->rx_spare_lock);
4960 for (i = 0; i < N_TX_RINGS; i++) {
4961 spin_lock_init(&cp->stat_lock[i]);
4962 spin_lock_init(&cp->tx_lock[i]);
4963 }
4964 spin_lock_init(&cp->stat_lock[N_TX_RINGS]);
4965 mutex_init(&cp->pm_mutex);
4966
4967 timer_setup(&cp->link_timer, cas_link_timer, 0);
4968
4969 #if 1
4970 /* Just in case the implementation of atomic operations
4971 * change so that an explicit initialization is necessary.
4972 */
4973 atomic_set(&cp->reset_task_pending, 0);
4974 atomic_set(&cp->reset_task_pending_all, 0);
4975 atomic_set(&cp->reset_task_pending_spare, 0);
4976 atomic_set(&cp->reset_task_pending_mtu, 0);
4977 #endif
4978 INIT_WORK(&cp->reset_task, cas_reset_task);
4979
4980 /* Default link parameters */
4981 if (link_mode >= 0 && link_mode < 6)
4982 cp->link_cntl = link_modes[link_mode];
4983 else
4984 cp->link_cntl = BMCR_ANENABLE;
4985 cp->lstate = link_down;
4986 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
4987 netif_carrier_off(cp->dev);
4988 cp->timer_ticks = 0;
4989
4990 /* give us access to cassini registers */
4991 cp->regs = pci_iomap(pdev, 0, casreg_len);
4992 if (!cp->regs) {
4993 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
4994 goto err_out_free_res;
4995 }
4996 cp->casreg_len = casreg_len;
4997
4998 pci_save_state(pdev);
4999 cas_check_pci_invariants(cp);
5000 cas_hard_reset(cp);
5001 cas_reset(cp, 0);
5002 if (cas_check_invariants(cp))
5003 goto err_out_iounmap;
5004 if (cp->cas_flags & CAS_FLAG_SATURN)
5005 cas_saturn_firmware_init(cp);
5006
5007 cp->init_block =
5008 dma_alloc_coherent(&pdev->dev, sizeof(struct cas_init_block),
5009 &cp->block_dvma, GFP_KERNEL);
5010 if (!cp->init_block) {
5011 dev_err(&pdev->dev, "Cannot allocate init block, aborting\n");
5012 goto err_out_iounmap;
5013 }
5014
5015 for (i = 0; i < N_TX_RINGS; i++)
5016 cp->init_txds[i] = cp->init_block->txds[i];
5017
5018 for (i = 0; i < N_RX_DESC_RINGS; i++)
5019 cp->init_rxds[i] = cp->init_block->rxds[i];
5020
5021 for (i = 0; i < N_RX_COMP_RINGS; i++)
5022 cp->init_rxcs[i] = cp->init_block->rxcs[i];
5023
5024 for (i = 0; i < N_RX_FLOWS; i++)
5025 skb_queue_head_init(&cp->rx_flows[i]);
5026
5027 dev->netdev_ops = &cas_netdev_ops;
5028 dev->ethtool_ops = &cas_ethtool_ops;
5029 dev->watchdog_timeo = CAS_TX_TIMEOUT;
5030
5031 #ifdef USE_NAPI
5032 netif_napi_add(dev, &cp->napi, cas_poll);
5033 #endif
5034 dev->irq = pdev->irq;
5035 dev->dma = 0;
5036
5037 /* Cassini features. */
5038 if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0)
5039 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5040
5041 dev->features |= NETIF_F_HIGHDMA;
5042
5043 /* MTU range: 60 - varies or 9000 */
5044 dev->min_mtu = CAS_MIN_MTU;
5045 dev->max_mtu = CAS_MAX_MTU;
5046
5047 if (register_netdev(dev)) {
5048 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
5049 goto err_out_free_consistent;
5050 }
5051
5052 i = readl(cp->regs + REG_BIM_CFG);
5053 netdev_info(dev, "Sun Cassini%s (%sbit/%sMHz PCI/%s) Ethernet[%d] %pM\n",
5054 (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "",
5055 (i & BIM_CFG_32BIT) ? "32" : "64",
5056 (i & BIM_CFG_66MHZ) ? "66" : "33",
5057 (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq,
5058 dev->dev_addr);
5059
5060 pci_set_drvdata(pdev, dev);
5061 cp->hw_running = 1;
5062 cas_entropy_reset(cp);
5063 cas_phy_init(cp);
5064 cas_begin_auto_negotiation(cp, NULL);
5065 return 0;
5066
5067 err_out_free_consistent:
5068 dma_free_coherent(&pdev->dev, sizeof(struct cas_init_block),
5069 cp->init_block, cp->block_dvma);
5070
5071 err_out_iounmap:
5072 mutex_lock(&cp->pm_mutex);
5073 if (cp->hw_running)
5074 cas_shutdown(cp);
5075 mutex_unlock(&cp->pm_mutex);
5076
5077 vfree(cp->fw_data);
5078
5079 pci_iounmap(pdev, cp->regs);
5080
5081
5082 err_out_free_res:
5083 pci_release_regions(pdev);
5084
5085 /* Try to restore it in case the error occurred after we
5086 * set it.
5087 */
5088 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);
5089
5090 err_out_free_netdev:
5091 free_netdev(dev);
5092
5093 err_out_disable_pdev:
5094 pci_disable_device(pdev);
5095 return -ENODEV;
5096 }
5097
5098 static void cas_remove_one(struct pci_dev *pdev)
5099 {
5100 struct net_device *dev = pci_get_drvdata(pdev);
5101 struct cas *cp;
5102 if (!dev)
5103 return;
5104
5105 cp = netdev_priv(dev);
5106 unregister_netdev(dev);
5107
5108 vfree(cp->fw_data);
5109
5110 mutex_lock(&cp->pm_mutex);
5111 cancel_work_sync(&cp->reset_task);
5112 if (cp->hw_running)
5113 cas_shutdown(cp);
5114 mutex_unlock(&cp->pm_mutex);
5115
5116 #if 1
5117 if (cp->orig_cacheline_size) {
5118 /* Restore the cache line size if we had modified
5119 * it.
5120 */
5121 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
5122 cp->orig_cacheline_size);
5123 }
5124 #endif
5125 dma_free_coherent(&pdev->dev, sizeof(struct cas_init_block),
5126 cp->init_block, cp->block_dvma);
5127 pci_iounmap(pdev, cp->regs);
5128 free_netdev(dev);
5129 pci_release_regions(pdev);
5130 pci_disable_device(pdev);
5131 }
5132
5133 static int __maybe_unused cas_suspend(struct device *dev_d)
5134 {
5135 struct net_device *dev = dev_get_drvdata(dev_d);
5136 struct cas *cp = netdev_priv(dev);
5137 unsigned long flags;
5138
5139 mutex_lock(&cp->pm_mutex);
5140
5141 /* If the driver is opened, we stop the DMA */
5142 if (cp->opened) {
5143 netif_device_detach(dev);
5144
5145 cas_lock_all_save(cp, flags);
5146
5147 /* We can set the second arg of cas_reset to 0
5148 * because on resume, we'll call cas_init_hw with
5149 * its second arg set so that autonegotiation is
5150 * restarted.
5151 */
5152 cas_reset(cp, 0);
5153 cas_clean_rings(cp);
5154 cas_unlock_all_restore(cp, flags);
5155 }
5156
5157 if (cp->hw_running)
5158 cas_shutdown(cp);
5159 mutex_unlock(&cp->pm_mutex);
5160
5161 return 0;
5162 }
5163
5164 static int __maybe_unused cas_resume(struct device *dev_d)
5165 {
5166 struct net_device *dev = dev_get_drvdata(dev_d);
5167 struct cas *cp = netdev_priv(dev);
5168
5169 netdev_info(dev, "resuming\n");
5170
5171 mutex_lock(&cp->pm_mutex);
5172 cas_hard_reset(cp);
5173 if (cp->opened) {
5174 unsigned long flags;
5175 cas_lock_all_save(cp, flags);
5176 cas_reset(cp, 0);
5177 cp->hw_running = 1;
5178 cas_clean_rings(cp);
5179 cas_init_hw(cp, 1);
5180 cas_unlock_all_restore(cp, flags);
5181
5182 netif_device_attach(dev);
5183 }
5184 mutex_unlock(&cp->pm_mutex);
5185 return 0;
5186 }
5187
5188 static SIMPLE_DEV_PM_OPS(cas_pm_ops, cas_suspend, cas_resume);
5189
5190 static struct pci_driver cas_driver = {
5191 .name = DRV_MODULE_NAME,
5192 .id_table = cas_pci_tbl,
5193 .probe = cas_init_one,
5194 .remove = cas_remove_one,
5195 .driver.pm = &cas_pm_ops,
5196 };
5197
5198 static int __init cas_init(void)
5199 {
5200 if (linkdown_timeout > 0)
5201 link_transition_timeout = linkdown_timeout * HZ;
5202 else
5203 link_transition_timeout = 0;
5204
5205 return pci_register_driver(&cas_driver);
5206 }
5207
5208 static void __exit cas_cleanup(void)
5209 {
5210 pci_unregister_driver(&cas_driver);
5211 }
5212
5213 module_init(cas_init);
5214 module_exit(cas_cleanup);
Kernel DRM miscellaneous fixes and cross-tree changes