drivers/net/wireless/intel/iwlwifi/iwl-context-info-gen3.h

   1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2 /*
   3  * Copyright (C) 2018, 2020-2024 Intel Corporation
   4  */
   5 #ifndef __iwl_context_info_file_gen3_h__
   6 #define __iwl_context_info_file_gen3_h__
   7
   8 #include "iwl-context-info.h"
   9
  10 #define CSR_CTXT_INFO_BOOT_CTRL         0x0
  11 #define CSR_CTXT_INFO_ADDR              0x118
  12 #define CSR_IML_DATA_ADDR               0x120
  13 #define CSR_IML_SIZE_ADDR               0x128
  14 #define CSR_IML_RESP_ADDR               0x12c
  15
  16 #define UNFRAGMENTED_PNVM_PAYLOADS_NUMBER 2
  17
  18 /* Set bit for enabling automatic function boot */
  19 #define CSR_AUTO_FUNC_BOOT_ENA          BIT(1)
  20 /* Set bit for initiating function boot */
  21 #define CSR_AUTO_FUNC_INIT              BIT(7)
  22
  23 /**
  24  * enum iwl_prph_scratch_mtr_format - tfd size configuration
  25  * @IWL_PRPH_MTR_FORMAT_16B: 16 bit tfd
  26  * @IWL_PRPH_MTR_FORMAT_32B: 32 bit tfd
  27  * @IWL_PRPH_MTR_FORMAT_64B: 64 bit tfd
  28  * @IWL_PRPH_MTR_FORMAT_256B: 256 bit tfd
  29  */
  30 enum iwl_prph_scratch_mtr_format {
  31         IWL_PRPH_MTR_FORMAT_16B = 0x0,
  32         IWL_PRPH_MTR_FORMAT_32B = 0x40000,
  33         IWL_PRPH_MTR_FORMAT_64B = 0x80000,
  34         IWL_PRPH_MTR_FORMAT_256B = 0xC0000,
  35 };
  36
  37 /**
  38  * enum iwl_prph_scratch_flags - PRPH scratch control flags
  39  * @IWL_PRPH_SCRATCH_IMR_DEBUG_EN: IMR support for debug
  40  * @IWL_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf
  41  * @IWL_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated
  42  *      in hwm config.
  43  * @IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL: use buffer on SRAM
  44  * @IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER: use st arbiter, mainly for
  45  *      multicomm.
  46  * @IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF: route debug data to SoC HW
  47  * @IWL_PRPH_SCRATCH_RB_SIZE_4K: Use 4K RB size (the default is 2K)
  48  * @IWL_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for
  49  *      completion descriptor, 1 for responses (legacy)
  50  * @IWL_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd.
  51  *      There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit,
  52  *      3: 256 bit.
  53  * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK: RB size full information, ignored
  54  *      by older firmware versions, so set IWL_PRPH_SCRATCH_RB_SIZE_4K
  55  *      appropriately; use the below values for this.
  56  * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size
  57  * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size
  58  * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K: 16kB RB size
  59  * @IWL_PRPH_SCRATCH_SCU_FORCE_ACTIVE: Indicate fw to set SCU_FORCE_ACTIVE
  60  *      upon reset.
  61  */
  62 enum iwl_prph_scratch_flags {
  63         IWL_PRPH_SCRATCH_IMR_DEBUG_EN           = BIT(1),
  64         IWL_PRPH_SCRATCH_EARLY_DEBUG_EN         = BIT(4),
  65         IWL_PRPH_SCRATCH_EDBG_DEST_DRAM         = BIT(8),
  66         IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL     = BIT(9),
  67         IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER   = BIT(10),
  68         IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF      = BIT(11),
  69         IWL_PRPH_SCRATCH_RB_SIZE_4K             = BIT(16),
  70         IWL_PRPH_SCRATCH_MTR_MODE               = BIT(17),
  71         IWL_PRPH_SCRATCH_MTR_FORMAT             = BIT(18) | BIT(19),
  72         IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK       = 0xf << 20,
  73         IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K         = 8 << 20,
  74         IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K        = 9 << 20,
  75         IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K        = 10 << 20,
  76         IWL_PRPH_SCRATCH_SCU_FORCE_ACTIVE       = BIT(29),
  77 };
  78
  79 /*
  80  * struct iwl_prph_scratch_version - version structure
  81  * @mac_id: SKU and revision id
  82  * @version: prph scratch information version id
  83  * @size: the size of the context information in DWs
  84  * @reserved: reserved
  85  */
  86 struct iwl_prph_scratch_version {
  87         __le16 mac_id;
  88         __le16 version;
  89         __le16 size;
  90         __le16 reserved;
  91 } __packed; /* PERIPH_SCRATCH_VERSION_S */
  92
  93 /*
  94  * struct iwl_prph_scratch_control - control structure
  95  * @control_flags: context information flags see &enum iwl_prph_scratch_flags
  96  * @reserved: reserved
  97  */
  98 struct iwl_prph_scratch_control {
  99         __le32 control_flags;
 100         __le32 reserved;
 101 } __packed; /* PERIPH_SCRATCH_CONTROL_S */
 102
 103 /*
 104  * struct iwl_prph_scratch_pnvm_cfg - PNVM scratch
 105  * @pnvm_base_addr: PNVM start address
 106  * @pnvm_size: the size of the PNVM image in bytes
 107  * @reserved: reserved
 108  */
 109 struct iwl_prph_scratch_pnvm_cfg {
 110         __le64 pnvm_base_addr;
 111         __le32 pnvm_size;
 112         __le32 reserved;
 113 } __packed; /* PERIPH_SCRATCH_PNVM_CFG_S */
 114
 115 /**
 116  * struct iwl_prph_scrath_mem_desc_addr_array
 117  * @mem_descs: array of dram addresses.
 118  * Each address is the beggining of a pnvm payload.
 119  */
 120 struct iwl_prph_scrath_mem_desc_addr_array {
 121         __le64 mem_descs[IPC_DRAM_MAP_ENTRY_NUM_MAX];
 122 } __packed; /* PERIPH_SCRATCH_MEM_DESC_ADDR_ARRAY_S_VER_1 */
 123 /*
 124  * struct iwl_prph_scratch_hwm_cfg - hwm config
 125  * @hwm_base_addr: hwm start address
 126  * @hwm_size: hwm size in DWs
 127  * @debug_token_config: debug preset
 128  */
 129 struct iwl_prph_scratch_hwm_cfg {
 130         __le64 hwm_base_addr;
 131         __le32 hwm_size;
 132         __le32 debug_token_config;
 133 } __packed; /* PERIPH_SCRATCH_HWM_CFG_S */
 134
 135 /*
 136  * struct iwl_prph_scratch_rbd_cfg - RBDs configuration
 137  * @free_rbd_addr: default queue free RB CB base address
 138  * @reserved: reserved
 139  */
 140 struct iwl_prph_scratch_rbd_cfg {
 141         __le64 free_rbd_addr;
 142         __le32 reserved;
 143 } __packed; /* PERIPH_SCRATCH_RBD_CFG_S */
 144
 145 /*
 146  * struct iwl_prph_scratch_uefi_cfg - prph scratch reduce power table
 147  * @base_addr: reduce power table address
 148  * @size: the size of the entire power table image
 149  */
 150 struct iwl_prph_scratch_uefi_cfg {
 151         __le64 base_addr;
 152         __le32 size;
 153         __le32 reserved;
 154 } __packed; /* PERIPH_SCRATCH_UEFI_CFG_S */
 155
 156 /*
 157  * struct iwl_prph_scratch_step_cfg - prph scratch step configuration
 158  * @mbx_addr_0: [0:7] revision,
 159  *              [8:15] cnvi_to_cnvr length,
 160  *              [16:23] cnvr_to_cnvi channel length,
 161  *              [24:31] radio1 reserved
 162  * @mbx_addr_1: [0:7] radio2 reserved
 163  */
 164
 165 struct iwl_prph_scratch_step_cfg {
 166         __le32 mbx_addr_0;
 167         __le32 mbx_addr_1;
 168 } __packed;
 169
 170 /*
 171  * struct iwl_prph_scratch_ctrl_cfg - prph scratch ctrl and config
 172  * @version: version information of context info and HW
 173  * @control: control flags of FH configurations
 174  * @pnvm_cfg: ror configuration
 175  * @hwm_cfg: hwm configuration
 176  * @rbd_cfg: default RX queue configuration
 177  * @step_cfg: step configuration
 178  */
 179 struct iwl_prph_scratch_ctrl_cfg {
 180         struct iwl_prph_scratch_version version;
 181         struct iwl_prph_scratch_control control;
 182         struct iwl_prph_scratch_pnvm_cfg pnvm_cfg;
 183         struct iwl_prph_scratch_hwm_cfg hwm_cfg;
 184         struct iwl_prph_scratch_rbd_cfg rbd_cfg;
 185         struct iwl_prph_scratch_uefi_cfg reduce_power_cfg;
 186         struct iwl_prph_scratch_step_cfg step_cfg;
 187 } __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */
 188
 189 /*
 190  * struct iwl_prph_scratch - peripheral scratch mapping
 191  * @ctrl_cfg: control and configuration of prph scratch
 192  * @dram: firmware images addresses in DRAM
 193  * @fseq_override: FSEQ override parameters
 194  * @step_analog_params: STEP analog calibration values
 195  * @reserved: reserved
 196  */
 197 struct iwl_prph_scratch {
 198         struct iwl_prph_scratch_ctrl_cfg ctrl_cfg;
 199         __le32 fseq_override;
 200         __le32 step_analog_params;
 201         __le32 reserved[8];
 202         struct iwl_context_info_dram dram;
 203 } __packed; /* PERIPH_SCRATCH_S */
 204
 205 /*
 206  * struct iwl_prph_info - peripheral information
 207  * @boot_stage_mirror: reflects the value in the Boot Stage CSR register
 208  * @ipc_status_mirror: reflects the value in the IPC Status CSR register
 209  * @sleep_notif: indicates the peripheral sleep status
 210  * @reserved: reserved
 211  */
 212 struct iwl_prph_info {
 213         __le32 boot_stage_mirror;
 214         __le32 ipc_status_mirror;
 215         __le32 sleep_notif;
 216         __le32 reserved;
 217 } __packed; /* PERIPH_INFO_S */
 218
 219 /*
 220  * struct iwl_context_info_gen3 - device INIT configuration
 221  * @version: version of the context information
 222  * @size: size of context information in DWs
 223  * @config: context in which the peripheral would execute - a subset of
 224  *      capability csr register published by the peripheral
 225  * @prph_info_base_addr: the peripheral information structure start address
 226  * @cr_head_idx_arr_base_addr: the completion ring head index array
 227  *      start address
 228  * @tr_tail_idx_arr_base_addr: the transfer ring tail index array
 229  *      start address
 230  * @cr_tail_idx_arr_base_addr: the completion ring tail index array
 231  *      start address
 232  * @tr_head_idx_arr_base_addr: the transfer ring head index array
 233  *      start address
 234  * @cr_idx_arr_size: number of entries in the completion ring index array
 235  * @tr_idx_arr_size: number of entries in the transfer ring index array
 236  * @mtr_base_addr: the message transfer ring start address
 237  * @mcr_base_addr: the message completion ring start address
 238  * @mtr_size: number of entries which the message transfer ring can hold
 239  * @mcr_size: number of entries which the message completion ring can hold
 240  * @mtr_doorbell_vec: the doorbell vector associated with the message
 241  *      transfer ring
 242  * @mcr_doorbell_vec: the doorbell vector associated with the message
 243  *      completion ring
 244  * @mtr_msi_vec: the MSI which shall be generated by the peripheral after
 245  *      completing a transfer descriptor in the message transfer ring
 246  * @mcr_msi_vec: the MSI which shall be generated by the peripheral after
 247  *      completing a completion descriptor in the message completion ring
 248  * @mtr_opt_header_size: the size of the optional header in the transfer
 249  *      descriptor associated with the message transfer ring in DWs
 250  * @mtr_opt_footer_size: the size of the optional footer in the transfer
 251  *      descriptor associated with the message transfer ring in DWs
 252  * @mcr_opt_header_size: the size of the optional header in the completion
 253  *      descriptor associated with the message completion ring in DWs
 254  * @mcr_opt_footer_size: the size of the optional footer in the completion
 255  *      descriptor associated with the message completion ring in DWs
 256  * @msg_rings_ctrl_flags: message rings control flags
 257  * @prph_info_msi_vec: the MSI which shall be generated by the peripheral
 258  *      after updating the Peripheral Information structure
 259  * @prph_scratch_base_addr: the peripheral scratch structure start address
 260  * @prph_scratch_size: the size of the peripheral scratch structure in DWs
 261  * @reserved: reserved
 262  */
 263 struct iwl_context_info_gen3 {
 264         __le16 version;
 265         __le16 size;
 266         __le32 config;
 267         __le64 prph_info_base_addr;
 268         __le64 cr_head_idx_arr_base_addr;
 269         __le64 tr_tail_idx_arr_base_addr;
 270         __le64 cr_tail_idx_arr_base_addr;
 271         __le64 tr_head_idx_arr_base_addr;
 272         __le16 cr_idx_arr_size;
 273         __le16 tr_idx_arr_size;
 274         __le64 mtr_base_addr;
 275         __le64 mcr_base_addr;
 276         __le16 mtr_size;
 277         __le16 mcr_size;
 278         __le16 mtr_doorbell_vec;
 279         __le16 mcr_doorbell_vec;
 280         __le16 mtr_msi_vec;
 281         __le16 mcr_msi_vec;
 282         u8 mtr_opt_header_size;
 283         u8 mtr_opt_footer_size;
 284         u8 mcr_opt_header_size;
 285         u8 mcr_opt_footer_size;
 286         __le16 msg_rings_ctrl_flags;
 287         __le16 prph_info_msi_vec;
 288         __le64 prph_scratch_base_addr;
 289         __le32 prph_scratch_size;
 290         __le32 reserved;
 291 } __packed; /* IPC_CONTEXT_INFO_S */
 292
 293 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
 294                                  const struct fw_img *fw);
 295 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans, bool alive);
 296
 297 int iwl_trans_pcie_ctx_info_gen3_load_pnvm(struct iwl_trans *trans,
 298                                            const struct iwl_pnvm_image *pnvm_payloads,
 299                                            const struct iwl_ucode_capabilities *capa);
 300 void iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans,
 301                                            const struct iwl_ucode_capabilities *capa);
 302 int
 303 iwl_trans_pcie_ctx_info_gen3_load_reduce_power(struct iwl_trans *trans,
 304                                                const struct iwl_pnvm_image *payloads,
 305                                                const struct iwl_ucode_capabilities *capa);
 306 void
 307 iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans,
 308                                               const struct iwl_ucode_capabilities *capa);
 309 int iwl_trans_pcie_ctx_info_gen3_set_step(struct iwl_trans *trans,
 310                                           u32 mbx_addr_0_step, u32 mbx_addr_1_step);
 311 #endif /* __iwl_context_info_file_gen3_h__ */