drivers/net/wireless/microchip/wilc1000/wlan.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
   4  * All rights reserved.
   5  */
   6
   7 #ifndef WILC_WLAN_H
   8 #define WILC_WLAN_H
   9
  10 #include <linux/types.h>
  11 #include <linux/bitfield.h>
  12
  13 /********************************************
  14  *
  15  *      Mac eth header length
  16  *
  17  ********************************************/
  18 #define MAX_MAC_HDR_LEN                 26 /* QOS_MAC_HDR_LEN */
  19 #define SUB_MSDU_HEADER_LENGTH          14
  20 #define SNAP_HDR_LEN                    8
  21 #define ETHERNET_HDR_LEN                14
  22 #define WORD_ALIGNMENT_PAD              0
  23
  24 #define ETH_ETHERNET_HDR_OFFSET         (MAX_MAC_HDR_LEN + \
  25                                          SUB_MSDU_HEADER_LENGTH + \
  26                                          SNAP_HDR_LEN - \
  27                                          ETHERNET_HDR_LEN + \
  28                                          WORD_ALIGNMENT_PAD)
  29
  30 #define HOST_HDR_OFFSET                 4
  31 #define ETHERNET_HDR_LEN                14
  32 #define IP_HDR_LEN                      20
  33 #define IP_HDR_OFFSET                   ETHERNET_HDR_LEN
  34 #define UDP_HDR_OFFSET                  (IP_HDR_LEN + IP_HDR_OFFSET)
  35 #define UDP_HDR_LEN                     8
  36 #define UDP_DATA_OFFSET                 (UDP_HDR_OFFSET + UDP_HDR_LEN)
  37 #define ETH_CONFIG_PKT_HDR_LEN          UDP_DATA_OFFSET
  38
  39 #define ETH_CONFIG_PKT_HDR_OFFSET       (ETH_ETHERNET_HDR_OFFSET + \
  40                                          ETH_CONFIG_PKT_HDR_LEN)
  41
  42 /********************************************
  43  *
  44  *      Register Defines
  45  *
  46  ********************************************/
  47 #define WILC_PERIPH_REG_BASE            0x1000
  48 #define WILC_CHANGING_VIR_IF            0x108c
  49 #define WILC_CHIPID                     WILC_PERIPH_REG_BASE
  50 #define WILC_GLB_RESET_0                (WILC_PERIPH_REG_BASE + 0x400)
  51 #define WILC_PIN_MUX_0                  (WILC_PERIPH_REG_BASE + 0x408)
  52 #define WILC_HOST_TX_CTRL               (WILC_PERIPH_REG_BASE + 0x6c)
  53 #define WILC_HOST_RX_CTRL_0             (WILC_PERIPH_REG_BASE + 0x70)
  54 #define WILC_HOST_RX_CTRL_1             (WILC_PERIPH_REG_BASE + 0x74)
  55 #define WILC_HOST_VMM_CTL               (WILC_PERIPH_REG_BASE + 0x78)
  56 #define WILC_HOST_RX_CTRL               (WILC_PERIPH_REG_BASE + 0x80)
  57 #define WILC_HOST_RX_EXTRA_SIZE         (WILC_PERIPH_REG_BASE + 0x84)
  58 #define WILC_HOST_TX_CTRL_1             (WILC_PERIPH_REG_BASE + 0x88)
  59 #define WILC_INTR_REG_BASE              (WILC_PERIPH_REG_BASE + 0xa00)
  60 #define WILC_INTR_ENABLE                WILC_INTR_REG_BASE
  61 #define WILC_INTR2_ENABLE               (WILC_INTR_REG_BASE + 4)
  62
  63 #define WILC_INTR_POLARITY              (WILC_INTR_REG_BASE + 0x10)
  64 #define WILC_INTR_TYPE                  (WILC_INTR_REG_BASE + 0x20)
  65 #define WILC_INTR_CLEAR                 (WILC_INTR_REG_BASE + 0x30)
  66 #define WILC_INTR_STATUS                (WILC_INTR_REG_BASE + 0x40)
  67
  68 #define WILC_RF_REVISION_ID             0x13f4
  69
  70 #define WILC_VMM_TBL_SIZE               64
  71 #define WILC_VMM_TX_TBL_BASE            0x150400
  72 #define WILC_VMM_RX_TBL_BASE            0x150500
  73
  74 #define WILC_VMM_BASE                   0x150000
  75 #define WILC_VMM_CORE_CTL               WILC_VMM_BASE
  76 #define WILC_VMM_TBL_CTL                (WILC_VMM_BASE + 0x4)
  77 #define WILC_VMM_TBL_ENTRY              (WILC_VMM_BASE + 0x8)
  78 #define WILC_VMM_TBL0_SIZE              (WILC_VMM_BASE + 0xc)
  79 #define WILC_VMM_TO_HOST_SIZE           (WILC_VMM_BASE + 0x10)
  80 #define WILC_VMM_CORE_CFG               (WILC_VMM_BASE + 0x14)
  81 #define WILC_VMM_TBL_ACTIVE             (WILC_VMM_BASE + 040)
  82 #define WILC_VMM_TBL_STATUS             (WILC_VMM_BASE + 0x44)
  83
  84 #define WILC_SPI_REG_BASE               0xe800
  85 #define WILC_SPI_CTL                    WILC_SPI_REG_BASE
  86 #define WILC_SPI_MASTER_DMA_ADDR        (WILC_SPI_REG_BASE + 0x4)
  87 #define WILC_SPI_MASTER_DMA_COUNT       (WILC_SPI_REG_BASE + 0x8)
  88 #define WILC_SPI_SLAVE_DMA_ADDR         (WILC_SPI_REG_BASE + 0xc)
  89 #define WILC_SPI_SLAVE_DMA_COUNT        (WILC_SPI_REG_BASE + 0x10)
  90 #define WILC_SPI_TX_MODE                (WILC_SPI_REG_BASE + 0x20)
  91 #define WILC_SPI_PROTOCOL_CONFIG        (WILC_SPI_REG_BASE + 0x24)
  92 #define WILC_SPI_INTR_CTL               (WILC_SPI_REG_BASE + 0x2c)
  93 #define WILC_SPI_INT_STATUS             (WILC_SPI_REG_BASE + 0x40)
  94 #define WILC_SPI_INT_CLEAR              (WILC_SPI_REG_BASE + 0x44)
  95
  96 #define WILC_SPI_WAKEUP_REG             0x1
  97 #define WILC_SPI_WAKEUP_BIT             BIT(1)
  98
  99 /* WILC1000 specific */
 100 #define WILC1000_SPI_CLK_STATUS_REG     0x0f
 101 #define WILC1000_SPI_CLK_STATUS_BIT     BIT(2)
 102
 103 /* WILC3000 specific */
 104 #define WILC3000_SPI_CLK_STATUS_REG     0x13
 105 #define WILC3000_SPI_CLK_STATUS_BIT     BIT(2)
 106
 107 #define WILC_SPI_HOST_TO_FW_REG         0x0b
 108 #define WILC_SPI_HOST_TO_FW_BIT         BIT(0)
 109
 110 #define WILC_SPI_FW_TO_HOST_REG         0x10
 111 #define WILC_SPI_FW_TO_HOST_BIT         BIT(0)
 112
 113 #define WILC_SPI_PROTOCOL_OFFSET        (WILC_SPI_PROTOCOL_CONFIG - \
 114                                          WILC_SPI_REG_BASE)
 115
 116 #define WILC_SPI_CLOCKLESS_ADDR_LIMIT   0x30
 117
 118 /* Functions IO enables bits */
 119 #define WILC_SDIO_CCCR_IO_EN_FUNC1      BIT(1)
 120
 121 /* Function/Interrupt enables bits */
 122 #define WILC_SDIO_CCCR_IEN_MASTER       BIT(0)
 123 #define WILC_SDIO_CCCR_IEN_FUNC1        BIT(1)
 124
 125 /* Abort CCCR register bits */
 126 #define WILC_SDIO_CCCR_ABORT_RESET      BIT(3)
 127
 128 /* Vendor specific CCCR registers */
 129 #define WILC_SDIO_WAKEUP_REG            0xf0
 130 #define WILC_SDIO_WAKEUP_BIT            BIT(0)
 131
 132 /* WILC1000 */
 133 #define WILC1000_SDIO_CLK_STATUS_REG    0xf1
 134 #define WILC1000_SDIO_CLK_STATUS_BIT    BIT(0)
 135
 136 #define WILC1000_SDIO_IRQ_FLAG_REG      0xf7
 137 #define WILC1000_SDIO_IRQ_CLEAR_FLAG_REG        0xf8
 138
 139 /* WILC3000 specific */
 140 #define WILC3000_SDIO_CLK_STATUS_REG    0xf0 /* clk & wakeup are on same reg */
 141 #define WILC3000_SDIO_CLK_STATUS_BIT    BIT(4)
 142
 143 #define WILC3000_SDIO_VMM_TBL_CTRL_REG  0xf1
 144 #define WILC3000_SDIO_IRQ_FLAG_REG      0xfe
 145
 146 /* Common vendor specific CCCR register */
 147 #define WILC_SDIO_INTERRUPT_DATA_SZ_REG 0xf2 /* Read size (2 bytes) */
 148
 149 #define WILC_SDIO_VMM_TBL_CTRL_REG      0xf6
 150
 151 #define WILC_SDIO_HOST_TO_FW_REG        0xfa
 152 #define WILC_SDIO_HOST_TO_FW_BIT        BIT(0)
 153
 154 #define WILC_SDIO_FW_TO_HOST_REG        0xfc
 155 #define WILC_SDIO_FW_TO_HOST_BIT        BIT(0)
 156
 157 /* Function 1 specific FBR register */
 158 #define WILC_SDIO_FBR_CSA_REG           0x10C /* CSA pointer (3 bytes) */
 159 #define WILC_SDIO_FBR_DATA_REG          0x10F
 160
 161 #define WILC_SDIO_F1_DATA_REG           0x0
 162 #define WILC_SDIO_EXT_IRQ_FLAG_REG      0x4
 163
 164 #define WILC_AHB_DATA_MEM_BASE          0x30000
 165 #define WILC_AHB_SHARE_MEM_BASE         0xd0000
 166
 167 #define WILC_VMM_TBL_RX_SHADOW_BASE     WILC_AHB_SHARE_MEM_BASE
 168 #define WILC_VMM_TBL_RX_SHADOW_SIZE     256
 169
 170 #define WILC_FW_HOST_COMM               0x13c0
 171 #define WILC_GP_REG_0                   0x149c
 172 #define WILC_GP_REG_1                   0x14a0
 173
 174 #define GLOBAL_MODE_CONTROL             0x1614
 175 #define PWR_SEQ_MISC_CTRL               0x3008
 176
 177 #define WILC_GLOBAL_MODE_ENABLE_WIFI    BIT(0)
 178 #define WILC_PWR_SEQ_ENABLE_WIFI_SLEEP  BIT(28)
 179
 180 #define WILC_HAVE_SDIO_IRQ_GPIO         BIT(0)
 181 #define WILC_HAVE_USE_PMU               BIT(1)
 182 #define WILC_HAVE_SLEEP_CLK_SRC_RTC     BIT(2)
 183 #define WILC_HAVE_SLEEP_CLK_SRC_XO      BIT(3)
 184 #define WILC_HAVE_EXT_PA_INV_TX_RX      BIT(4)
 185 #define WILC_HAVE_LEGACY_RF_SETTINGS    BIT(5)
 186 #define WILC_HAVE_XTAL_24               BIT(6)
 187 #define WILC_HAVE_DISABLE_WILC_UART     BIT(7)
 188 #define WILC_HAVE_USE_IRQ_AS_HOST_WAKE  BIT(8)
 189
 190 #define WILC_CORTUS_INTERRUPT_BASE      0x10A8
 191 #define WILC1000_CORTUS_INTERRUPT_1     (WILC_CORTUS_INTERRUPT_BASE + 0x4)
 192 #define WILC3000_CORTUS_INTERRUPT_1     (WILC_CORTUS_INTERRUPT_BASE + 0x14)
 193
 194 #define WILC1000_CORTUS_INTERRUPT_2     (WILC_CORTUS_INTERRUPT_BASE + 0x8)
 195 #define WILC3000_CORTUS_INTERRUPT_2     (WILC_CORTUS_INTERRUPT_BASE + 0x18)
 196
 197 /* tx control register 1 to 4 for RX */
 198 #define WILC_REG_4_TO_1_RX              0x1e1c
 199
 200 /* tx control register 1 to 4 for TX Bank_0 */
 201 #define WILC_REG_4_TO_1_TX_BANK0        0x1e9c
 202
 203 #define WILC_CORTUS_RESET_MUX_SEL       0x1118
 204 #define WILC_CORTUS_BOOT_REGISTER       0xc0000
 205 #define WILC3000_BOOTROM_STATUS         0x207ac
 206 #define WILC3000_CORTUS_BOOT_REGISTER_2 0x4f0000
 207 #define WILC3000_CHIP_ID                0x3b0000
 208
 209 #define WILC_CORTUS_BOOT_FROM_IRAM      0x71
 210
 211 #define WILC_1000_BASE_ID               0x100000
 212
 213 #define WILC_1000_BASE_ID_2A            0x1002A0
 214 #define WILC_1000_BASE_ID_2A_REV1       (WILC_1000_BASE_ID_2A + 1)
 215
 216 #define WILC_1000_BASE_ID_2B            0x1002B0
 217 #define WILC_1000_BASE_ID_2B_REV1       (WILC_1000_BASE_ID_2B + 1)
 218 #define WILC_1000_BASE_ID_2B_REV2       (WILC_1000_BASE_ID_2B + 2)
 219
 220 #define WILC_3000_BASE_ID               0x300000
 221
 222 #define WILC_CHIP_REV_FIELD             GENMASK(11, 0)
 223
 224 /********************************************
 225  *
 226  *      Wlan Defines
 227  *
 228  ********************************************/
 229 #define WILC_CFG_PKT            1
 230 #define WILC_NET_PKT            0
 231 #define WILC_MGMT_PKT           2
 232
 233 #define WILC_CFG_SET            1
 234 #define WILC_CFG_QUERY          0
 235
 236 #define WILC_CFG_RSP            1
 237 #define WILC_CFG_RSP_STATUS     2
 238 #define WILC_CFG_RSP_SCAN       3
 239
 240 #define WILC_ABORT_REQ_BIT              BIT(31)
 241
 242 #define WILC_RX_BUFF_SIZE       (96 * 1024)
 243 #define WILC_TX_BUFF_SIZE       (64 * 1024)
 244
 245 #define NQUEUES                 4
 246 #define AC_BUFFER_SIZE          1000
 247
 248 #define VO_AC_COUNT_FIELD               GENMASK(31, 25)
 249 #define VO_AC_ACM_STAT_FIELD            BIT(24)
 250 #define VI_AC_COUNT_FIELD               GENMASK(23, 17)
 251 #define VI_AC_ACM_STAT_FIELD            BIT(16)
 252 #define BE_AC_COUNT_FIELD               GENMASK(15, 9)
 253 #define BE_AC_ACM_STAT_FIELD            BIT(8)
 254 #define BK_AC_COUNT_FIELD               GENMASK(7, 3)
 255 #define BK_AC_ACM_STAT_FIELD            BIT(1)
 256
 257 #define WILC_PKT_HDR_CONFIG_FIELD       BIT(31)
 258 #define WILC_PKT_HDR_OFFSET_FIELD       GENMASK(30, 22)
 259 #define WILC_PKT_HDR_TOTAL_LEN_FIELD    GENMASK(21, 11)
 260 #define WILC_PKT_HDR_LEN_FIELD          GENMASK(10, 0)
 261
 262 #define WILC_INTERRUPT_DATA_SIZE        GENMASK(14, 0)
 263
 264 #define WILC_VMM_BUFFER_SIZE            GENMASK(9, 0)
 265
 266 #define WILC_VMM_HDR_TYPE               BIT(31)
 267 #define WILC_VMM_HDR_MGMT_FIELD         BIT(30)
 268 #define WILC_VMM_HDR_PKT_SIZE           GENMASK(29, 15)
 269 #define WILC_VMM_HDR_BUFF_SIZE          GENMASK(14, 0)
 270
 271 #define WILC_VMM_ENTRY_COUNT            GENMASK(8, 3)
 272 #define WILC_VMM_ENTRY_AVAILABLE        BIT(2)
 273 /*******************************************/
 274 /*        E0 and later Interrupt flags.    */
 275 /*******************************************/
 276 /*******************************************/
 277 /*        E0 and later Interrupt flags.    */
 278 /*           IRQ Status word               */
 279 /* 15:0 = DMA count in words.              */
 280 /* 16: INT0 flag                           */
 281 /* 17: INT1 flag                           */
 282 /* 18: INT2 flag                           */
 283 /* 19: INT3 flag                           */
 284 /* 20: INT4 flag                           */
 285 /* 21: INT5 flag                           */
 286 /*******************************************/
 287 #define IRG_FLAGS_OFFSET        16
 288 #define IRQ_DMA_WD_CNT_MASK     GENMASK(IRG_FLAGS_OFFSET - 1, 0)
 289 #define INT_0                   BIT(IRG_FLAGS_OFFSET)
 290 #define INT_1                   BIT(IRG_FLAGS_OFFSET + 1)
 291 #define INT_2                   BIT(IRG_FLAGS_OFFSET + 2)
 292 #define INT_3                   BIT(IRG_FLAGS_OFFSET + 3)
 293 #define INT_4                   BIT(IRG_FLAGS_OFFSET + 4)
 294 #define INT_5                   BIT(IRG_FLAGS_OFFSET + 5)
 295 #define MAX_NUM_INT             5
 296 #define IRG_FLAGS_MASK          GENMASK(IRG_FLAGS_OFFSET + MAX_NUM_INT, \
 297                                         IRG_FLAGS_OFFSET)
 298
 299 /*******************************************/
 300 /*        E0 and later Interrupt flags.    */
 301 /*           IRQ Clear word                */
 302 /* 0: Clear INT0                           */
 303 /* 1: Clear INT1                           */
 304 /* 2: Clear INT2                           */
 305 /* 3: Clear INT3                           */
 306 /* 4: Clear INT4                           */
 307 /* 5: Clear INT5                           */
 308 /* 6: Select VMM table 1                   */
 309 /* 7: Select VMM table 2                   */
 310 /* 8: Enable VMM                           */
 311 /*******************************************/
 312 #define CLR_INT0                BIT(0)
 313 #define CLR_INT1                BIT(1)
 314 #define CLR_INT2                BIT(2)
 315 #define CLR_INT3                BIT(3)
 316 #define CLR_INT4                BIT(4)
 317 #define CLR_INT5                BIT(5)
 318 #define SEL_VMM_TBL0            BIT(6)
 319 #define SEL_VMM_TBL1            BIT(7)
 320 #define EN_VMM                  BIT(8)
 321
 322 #define DATA_INT_EXT            INT_0
 323 #define ALL_INT_EXT             DATA_INT_EXT
 324 #define NUM_INT_EXT             1
 325 #define UNHANDLED_IRQ_MASK      GENMASK(MAX_NUM_INT - 1, NUM_INT_EXT)
 326
 327 #define DATA_INT_CLR            CLR_INT0
 328
 329 #define ENABLE_RX_VMM           (SEL_VMM_TBL1 | EN_VMM)
 330 #define ENABLE_TX_VMM           (SEL_VMM_TBL0 | EN_VMM)
 331 /* time for expiring the completion of cfg packets */
 332 #define WILC_CFG_PKTS_TIMEOUT   msecs_to_jiffies(3000)
 333
 334 #define IS_MANAGMEMENT          0x100
 335 #define IS_MANAGMEMENT_CALLBACK 0x080
 336 #define IS_MGMT_STATUS_SUCCES   0x040
 337 #define IS_MGMT_AUTH_PKT       0x010
 338
 339 #define WILC_WID_TYPE           GENMASK(15, 12)
 340 #define WILC_VMM_ENTRY_FULL_RETRY       1
 341 /********************************************
 342  *
 343  *      Tx/Rx Queue Structure
 344  *
 345  ********************************************/
 346 enum ip_pkt_priority {
 347         AC_VO_Q = 0,
 348         AC_VI_Q = 1,
 349         AC_BE_Q = 2,
 350         AC_BK_Q = 3
 351 };
 352
 353 struct txq_entry_t {
 354         struct list_head list;
 355         int type;
 356         u8 q_num;
 357         int ack_idx;
 358         u8 *buffer;
 359         int buffer_size;
 360         void *priv;
 361         int status;
 362         struct wilc_vif *vif;
 363         void (*tx_complete_func)(void *priv, int status);
 364 };
 365
 366 struct txq_fw_recv_queue_stat {
 367         u8 acm;
 368         u8 count;
 369 };
 370
 371 struct txq_handle {
 372         struct txq_entry_t txq_head;
 373         u16 count;
 374         struct txq_fw_recv_queue_stat fw;
 375 };
 376
 377 struct rxq_entry_t {
 378         struct list_head list;
 379         u8 *buffer;
 380         int buffer_size;
 381 };
 382
 383 /********************************************
 384  *
 385  *      Host IF Structure
 386  *
 387  ********************************************/
 388 struct wilc;
 389 struct wilc_hif_func {
 390         int (*hif_init)(struct wilc *wilc, bool resume);
 391         int (*hif_deinit)(struct wilc *wilc);
 392         int (*hif_read_reg)(struct wilc *wilc, u32 addr, u32 *data);
 393         int (*hif_write_reg)(struct wilc *wilc, u32 addr, u32 data);
 394         int (*hif_block_rx)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
 395         int (*hif_block_tx)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
 396         int (*hif_read_int)(struct wilc *wilc, u32 *int_status);
 397         int (*hif_clear_int_ext)(struct wilc *wilc, u32 val);
 398         int (*hif_read_size)(struct wilc *wilc, u32 *size);
 399         int (*hif_block_tx_ext)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
 400         int (*hif_block_rx_ext)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
 401         int (*hif_sync_ext)(struct wilc *wilc, int nint);
 402         int (*enable_interrupt)(struct wilc *nic);
 403         void (*disable_interrupt)(struct wilc *nic);
 404         int (*hif_reset)(struct wilc *wilc);
 405         bool (*hif_is_init)(struct wilc *wilc);
 406 };
 407
 408 #define WILC_MAX_CFG_FRAME_SIZE         1468
 409
 410 struct tx_complete_data {
 411         int size;
 412         void *buff;
 413         struct sk_buff *skb;
 414 };
 415
 416 struct wilc_cfg_cmd_hdr {
 417         u8 cmd_type;
 418         u8 seq_no;
 419         __le16 total_len;
 420         __le32 driver_handler;
 421 };
 422
 423 struct wilc_cfg_frame {
 424         struct wilc_cfg_cmd_hdr hdr;
 425         u8 frame[WILC_MAX_CFG_FRAME_SIZE];
 426 };
 427
 428 struct wilc_cfg_rsp {
 429         u8 type;
 430         u8 seq_no;
 431 };
 432
 433 struct wilc_vif;
 434
 435 static inline bool is_wilc1000(u32 id)
 436 {
 437         return (id & (~WILC_CHIP_REV_FIELD)) == WILC_1000_BASE_ID;
 438 }
 439
 440 static inline bool is_wilc3000(u32 id)
 441 {
 442         return (id & (~WILC_CHIP_REV_FIELD)) == WILC_3000_BASE_ID;
 443 }
 444
 445 int wilc_wlan_firmware_download(struct wilc *wilc, const u8 *buffer,
 446                                 u32 buffer_size);
 447 int wilc_wlan_start(struct wilc *wilc);
 448 int wilc_wlan_stop(struct wilc *wilc, struct wilc_vif *vif);
 449 int wilc_wlan_txq_add_net_pkt(struct net_device *dev,
 450                               struct tx_complete_data *tx_data, u8 *buffer,
 451                               u32 buffer_size,
 452                               void (*tx_complete_fn)(void *, int));
 453 int wilc_wlan_handle_txq(struct wilc *wl, u32 *txq_count);
 454 void wilc_handle_isr(struct wilc *wilc);
 455 void wilc_wlan_cleanup(struct net_device *dev);
 456 int wilc_wlan_cfg_set(struct wilc_vif *vif, int start, u16 wid, u8 *buffer,
 457                       u32 buffer_size, int commit, u32 drv_handler);
 458 int wilc_wlan_cfg_get(struct wilc_vif *vif, int start, u16 wid, int commit,
 459                       u32 drv_handler);
 460 int wilc_wlan_txq_add_mgmt_pkt(struct net_device *dev, void *priv, u8 *buffer,
 461                                u32 buffer_size, void (*func)(void *, int));
 462 void wilc_enable_tcp_ack_filter(struct wilc_vif *vif, bool value);
 463 int wilc_wlan_get_num_conn_ifcs(struct wilc *wilc);
 464 netdev_tx_t wilc_mac_xmit(struct sk_buff *skb, struct net_device *dev);
 465
 466 void wilc_wfi_p2p_rx(struct wilc_vif *vif, u8 *buff, u32 size);
 467 bool wilc_wfi_mgmt_frame_rx(struct wilc_vif *vif, u8 *buff, u32 size);
 468 int host_wakeup_notify(struct wilc *wilc);
 469 int host_sleep_notify(struct wilc *wilc);
 470 int wilc_send_config_pkt(struct wilc_vif *vif, u8 mode, struct wid *wids,
 471                          u32 count);
 472 int wilc_wlan_init(struct net_device *dev);
 473 int wilc_get_chipid(struct wilc *wilc);
 474 int wilc_load_mac_from_nv(struct wilc *wilc);
 475 #endif