drivers/nvmem/qfprom.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/device.h>
   8 #include <linux/io.h>
   9 #include <linux/iopoll.h>
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/mod_devicetable.h>
  13 #include <linux/nvmem-provider.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pm_domain.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/property.h>
  18 #include <linux/regulator/consumer.h>
  19
  20 /* Blow timer clock frequency in Mhz */
  21 #define QFPROM_BLOW_TIMER_OFFSET 0x03c
  22
  23 /* Amount of time required to hold charge to blow fuse in micro-seconds */
  24 #define QFPROM_FUSE_BLOW_POLL_US        100
  25 #define QFPROM_FUSE_BLOW_TIMEOUT_US     10000
  26
  27 #define QFPROM_BLOW_STATUS_OFFSET       0x048
  28 #define QFPROM_BLOW_STATUS_BUSY         0x1
  29 #define QFPROM_BLOW_STATUS_READY        0x0
  30
  31 #define QFPROM_ACCEL_OFFSET             0x044
  32
  33 #define QFPROM_VERSION_OFFSET           0x0
  34 #define QFPROM_MAJOR_VERSION_SHIFT      28
  35 #define QFPROM_MAJOR_VERSION_MASK       GENMASK(31, QFPROM_MAJOR_VERSION_SHIFT)
  36 #define QFPROM_MINOR_VERSION_SHIFT      16
  37 #define QFPROM_MINOR_VERSION_MASK       GENMASK(27, QFPROM_MINOR_VERSION_SHIFT)
  38
  39 static bool read_raw_data;
  40 module_param(read_raw_data, bool, 0644);
  41 MODULE_PARM_DESC(read_raw_data, "Read raw instead of corrected data");
  42
  43 /**
  44  * struct qfprom_soc_data - config that varies from SoC to SoC.
  45  *
  46  * @accel_value:             Should contain qfprom accel value.
  47  * @qfprom_blow_timer_value: The timer value of qfprom when doing efuse blow.
  48  * @qfprom_blow_set_freq:    The frequency required to set when we start the
  49  *                           fuse blowing.
  50  * @qfprom_blow_uV:          LDO voltage to be set when doing efuse blow
  51  */
  52 struct qfprom_soc_data {
  53         u32 accel_value;
  54         u32 qfprom_blow_timer_value;
  55         u32 qfprom_blow_set_freq;
  56         int qfprom_blow_uV;
  57 };
  58
  59 /**
  60  * struct qfprom_priv - structure holding qfprom attributes
  61  *
  62  * @qfpraw:       iomapped memory space for qfprom-efuse raw address space.
  63  * @qfpconf:      iomapped memory space for qfprom-efuse configuration address
  64  *                space.
  65  * @qfpcorrected: iomapped memory space for qfprom corrected address space.
  66  * @qfpsecurity:  iomapped memory space for qfprom security control space.
  67  * @dev:          qfprom device structure.
  68  * @secclk:       Clock supply.
  69  * @vcc:          Regulator supply.
  70  * @soc_data:     Data that for things that varies from SoC to SoC.
  71  */
  72 struct qfprom_priv {
  73         void __iomem *qfpraw;
  74         void __iomem *qfpconf;
  75         void __iomem *qfpcorrected;
  76         void __iomem *qfpsecurity;
  77         struct device *dev;
  78         struct clk *secclk;
  79         struct regulator *vcc;
  80         const struct qfprom_soc_data *soc_data;
  81 };
  82
  83 /**
  84  * struct qfprom_touched_values - saved values to restore after blowing
  85  *
  86  * @clk_rate: The rate the clock was at before blowing.
  87  * @accel_val: The value of the accel reg before blowing.
  88  * @timer_val: The value of the timer before blowing.
  89  */
  90 struct qfprom_touched_values {
  91         unsigned long clk_rate;
  92         u32 accel_val;
  93         u32 timer_val;
  94 };
  95
  96 /**
  97  * struct qfprom_soc_compatible_data - Data matched against the SoC
  98  * compatible string.
  99  *
 100  * @keepout: Array of keepout regions for this SoC.
 101  * @nkeepout: Number of elements in the keepout array.
 102  */
 103 struct qfprom_soc_compatible_data {
 104         const struct nvmem_keepout *keepout;
 105         unsigned int nkeepout;
 106 };
 107
 108 static const struct nvmem_keepout sc7180_qfprom_keepout[] = {
 109         {.start = 0x128, .end = 0x148},
 110         {.start = 0x220, .end = 0x228}
 111 };
 112
 113 static const struct qfprom_soc_compatible_data sc7180_qfprom = {
 114         .keepout = sc7180_qfprom_keepout,
 115         .nkeepout = ARRAY_SIZE(sc7180_qfprom_keepout)
 116 };
 117
 118 static const struct nvmem_keepout sc7280_qfprom_keepout[] = {
 119         {.start = 0x128, .end = 0x148},
 120         {.start = 0x238, .end = 0x248}
 121 };
 122
 123 static const struct qfprom_soc_compatible_data sc7280_qfprom = {
 124         .keepout = sc7280_qfprom_keepout,
 125         .nkeepout = ARRAY_SIZE(sc7280_qfprom_keepout)
 126 };
 127
 128 /**
 129  * qfprom_disable_fuse_blowing() - Undo enabling of fuse blowing.
 130  * @priv: Our driver data.
 131  * @old:  The data that was stashed from before fuse blowing.
 132  *
 133  * Resets the value of the blow timer, accel register and the clock
 134  * and voltage settings.
 135  *
 136  * Prints messages if there are errors but doesn't return an error code
 137  * since there's not much we can do upon failure.
 138  */
 139 static void qfprom_disable_fuse_blowing(const struct qfprom_priv *priv,
 140                                         const struct qfprom_touched_values *old)
 141 {
 142         int ret;
 143
 144         writel(old->timer_val, priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
 145         writel(old->accel_val, priv->qfpconf + QFPROM_ACCEL_OFFSET);
 146
 147         dev_pm_genpd_set_performance_state(priv->dev, 0);
 148         pm_runtime_put(priv->dev);
 149
 150         /*
 151          * This may be a shared rail and may be able to run at a lower rate
 152          * when we're not blowing fuses.  At the moment, the regulator framework
 153          * applies voltage constraints even on disabled rails, so remove our
 154          * constraints and allow the rail to be adjusted by other users.
 155          */
 156         ret = regulator_set_voltage(priv->vcc, 0, INT_MAX);
 157         if (ret)
 158                 dev_warn(priv->dev, "Failed to set 0 voltage (ignoring)\n");
 159
 160         ret = regulator_disable(priv->vcc);
 161         if (ret)
 162                 dev_warn(priv->dev, "Failed to disable regulator (ignoring)\n");
 163
 164         ret = clk_set_rate(priv->secclk, old->clk_rate);
 165         if (ret)
 166                 dev_warn(priv->dev,
 167                          "Failed to set clock rate for disable (ignoring)\n");
 168
 169         clk_disable_unprepare(priv->secclk);
 170 }
 171
 172 /**
 173  * qfprom_enable_fuse_blowing() - Enable fuse blowing.
 174  * @priv: Our driver data.
 175  * @old:  We'll stash stuff here to use when disabling.
 176  *
 177  * Sets the value of the blow timer, accel register and the clock
 178  * and voltage settings.
 179  *
 180  * Prints messages if there are errors so caller doesn't need to.
 181  *
 182  * Return: 0 or -err.
 183  */
 184 static int qfprom_enable_fuse_blowing(const struct qfprom_priv *priv,
 185                                       struct qfprom_touched_values *old)
 186 {
 187         int ret;
 188         int qfprom_blow_uV = priv->soc_data->qfprom_blow_uV;
 189
 190         ret = clk_prepare_enable(priv->secclk);
 191         if (ret) {
 192                 dev_err(priv->dev, "Failed to enable clock\n");
 193                 return ret;
 194         }
 195
 196         old->clk_rate = clk_get_rate(priv->secclk);
 197         ret = clk_set_rate(priv->secclk, priv->soc_data->qfprom_blow_set_freq);
 198         if (ret) {
 199                 dev_err(priv->dev, "Failed to set clock rate for enable\n");
 200                 goto err_clk_prepared;
 201         }
 202
 203         /*
 204          * Hardware requires a minimum voltage for fuse blowing.
 205          * This may be a shared rail so don't specify a maximum.
 206          * Regulator constraints will cap to the actual maximum.
 207          */
 208         ret = regulator_set_voltage(priv->vcc, qfprom_blow_uV, INT_MAX);
 209         if (ret) {
 210                 dev_err(priv->dev, "Failed to set %duV\n", qfprom_blow_uV);
 211                 goto err_clk_rate_set;
 212         }
 213
 214         ret = regulator_enable(priv->vcc);
 215         if (ret) {
 216                 dev_err(priv->dev, "Failed to enable regulator\n");
 217                 goto err_clk_rate_set;
 218         }
 219
 220         ret = pm_runtime_resume_and_get(priv->dev);
 221         if (ret < 0) {
 222                 dev_err(priv->dev, "Failed to enable power-domain\n");
 223                 goto err_reg_enable;
 224         }
 225         dev_pm_genpd_set_performance_state(priv->dev, INT_MAX);
 226
 227         old->timer_val = readl(priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
 228         old->accel_val = readl(priv->qfpconf + QFPROM_ACCEL_OFFSET);
 229         writel(priv->soc_data->qfprom_blow_timer_value,
 230                priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
 231         writel(priv->soc_data->accel_value,
 232                priv->qfpconf + QFPROM_ACCEL_OFFSET);
 233
 234         return 0;
 235
 236 err_reg_enable:
 237         regulator_disable(priv->vcc);
 238 err_clk_rate_set:
 239         clk_set_rate(priv->secclk, old->clk_rate);
 240 err_clk_prepared:
 241         clk_disable_unprepare(priv->secclk);
 242         return ret;
 243 }
 244
 245 /**
 246  * qfprom_reg_write() - Write to fuses.
 247  * @context: Our driver data.
 248  * @reg:     The offset to write at.
 249  * @_val:    Pointer to data to write.
 250  * @bytes:   The number of bytes to write.
 251  *
 252  * Writes to fuses.  WARNING: THIS IS PERMANENT.
 253  *
 254  * Return: 0 or -err.
 255  */
 256 static int qfprom_reg_write(void *context, unsigned int reg, void *_val,
 257                             size_t bytes)
 258 {
 259         struct qfprom_priv *priv = context;
 260         struct qfprom_touched_values old;
 261         int words = bytes / 4;
 262         u32 *value = _val;
 263         u32 blow_status;
 264         int ret;
 265         int i;
 266
 267         dev_dbg(priv->dev,
 268                 "Writing to raw qfprom region : %#010x of size: %zu\n",
 269                 reg, bytes);
 270
 271         /*
 272          * The hardware only allows us to write word at a time, but we can
 273          * read byte at a time.  Until the nvmem framework allows a separate
 274          * word_size and stride for reading vs. writing, we'll enforce here.
 275          */
 276         if (bytes % 4) {
 277                 dev_err(priv->dev,
 278                         "%zu is not an integral number of words\n", bytes);
 279                 return -EINVAL;
 280         }
 281         if (reg % 4) {
 282                 dev_err(priv->dev,
 283                         "Invalid offset: %#x.  Must be word aligned\n", reg);
 284                 return -EINVAL;
 285         }
 286
 287         ret = qfprom_enable_fuse_blowing(priv, &old);
 288         if (ret)
 289                 return ret;
 290
 291         ret = readl_relaxed_poll_timeout(
 292                 priv->qfpconf + QFPROM_BLOW_STATUS_OFFSET,
 293                 blow_status, blow_status == QFPROM_BLOW_STATUS_READY,
 294                 QFPROM_FUSE_BLOW_POLL_US, QFPROM_FUSE_BLOW_TIMEOUT_US);
 295
 296         if (ret) {
 297                 dev_err(priv->dev,
 298                         "Timeout waiting for initial ready; aborting.\n");
 299                 goto exit_enabled_fuse_blowing;
 300         }
 301
 302         for (i = 0; i < words; i++)
 303                 writel(value[i], priv->qfpraw + reg + (i * 4));
 304
 305         ret = readl_relaxed_poll_timeout(
 306                 priv->qfpconf + QFPROM_BLOW_STATUS_OFFSET,
 307                 blow_status, blow_status == QFPROM_BLOW_STATUS_READY,
 308                 QFPROM_FUSE_BLOW_POLL_US, QFPROM_FUSE_BLOW_TIMEOUT_US);
 309
 310         /* Give an error, but not much we can do in this case */
 311         if (ret)
 312                 dev_err(priv->dev, "Timeout waiting for finish.\n");
 313
 314 exit_enabled_fuse_blowing:
 315         qfprom_disable_fuse_blowing(priv, &old);
 316
 317         return ret;
 318 }
 319
 320 static int qfprom_reg_read(void *context,
 321                         unsigned int reg, void *_val, size_t bytes)
 322 {
 323         struct qfprom_priv *priv = context;
 324         u8 *val = _val;
 325         int i = 0, words = bytes;
 326         void __iomem *base = priv->qfpcorrected;
 327
 328         if (read_raw_data && priv->qfpraw)
 329                 base = priv->qfpraw;
 330
 331         while (words--)
 332                 *val++ = readb(base + reg + i++);
 333
 334         return 0;
 335 }
 336
 337 static void qfprom_runtime_disable(void *data)
 338 {
 339         pm_runtime_disable(data);
 340 }
 341
 342 static const struct qfprom_soc_data qfprom_7_8_data = {
 343         .accel_value = 0xD10,
 344         .qfprom_blow_timer_value = 25,
 345         .qfprom_blow_set_freq = 4800000,
 346         .qfprom_blow_uV = 1800000,
 347 };
 348
 349 static const struct qfprom_soc_data qfprom_7_15_data = {
 350         .accel_value = 0xD08,
 351         .qfprom_blow_timer_value = 24,
 352         .qfprom_blow_set_freq = 4800000,
 353         .qfprom_blow_uV = 1900000,
 354 };
 355
 356 static int qfprom_probe(struct platform_device *pdev)
 357 {
 358         struct nvmem_config econfig = {
 359                 .name = "qfprom",
 360                 .add_legacy_fixed_of_cells = true,
 361                 .stride = 1,
 362                 .word_size = 1,
 363                 .id = NVMEM_DEVID_AUTO,
 364                 .reg_read = qfprom_reg_read,
 365         };
 366         struct device *dev = &pdev->dev;
 367         struct resource *res;
 368         struct nvmem_device *nvmem;
 369         const struct qfprom_soc_compatible_data *soc_data;
 370         struct qfprom_priv *priv;
 371         int ret;
 372
 373         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 374         if (!priv)
 375                 return -ENOMEM;
 376
 377         /* The corrected section is always provided */
 378         priv->qfpcorrected = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 379         if (IS_ERR(priv->qfpcorrected))
 380                 return PTR_ERR(priv->qfpcorrected);
 381
 382         econfig.size = resource_size(res);
 383         econfig.dev = dev;
 384         econfig.priv = priv;
 385
 386         priv->dev = dev;
 387         soc_data = device_get_match_data(dev);
 388         if (soc_data) {
 389                 econfig.keepout = soc_data->keepout;
 390                 econfig.nkeepout = soc_data->nkeepout;
 391         }
 392
 393         /*
 394          * If more than one region is provided then the OS has the ability
 395          * to write.
 396          */
 397         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 398         if (res) {
 399                 u32 version;
 400                 int major_version, minor_version;
 401
 402                 priv->qfpraw = devm_ioremap_resource(dev, res);
 403                 if (IS_ERR(priv->qfpraw))
 404                         return PTR_ERR(priv->qfpraw);
 405                 priv->qfpconf = devm_platform_ioremap_resource(pdev, 2);
 406                 if (IS_ERR(priv->qfpconf))
 407                         return PTR_ERR(priv->qfpconf);
 408                 priv->qfpsecurity = devm_platform_ioremap_resource(pdev, 3);
 409                 if (IS_ERR(priv->qfpsecurity))
 410                         return PTR_ERR(priv->qfpsecurity);
 411
 412                 version = readl(priv->qfpsecurity + QFPROM_VERSION_OFFSET);
 413                 major_version = (version & QFPROM_MAJOR_VERSION_MASK) >>
 414                                 QFPROM_MAJOR_VERSION_SHIFT;
 415                 minor_version = (version & QFPROM_MINOR_VERSION_MASK) >>
 416                                 QFPROM_MINOR_VERSION_SHIFT;
 417
 418                 if (major_version == 7 && minor_version == 8)
 419                         priv->soc_data = &qfprom_7_8_data;
 420                 else if (major_version == 7 && minor_version == 15)
 421                         priv->soc_data = &qfprom_7_15_data;
 422
 423                 priv->vcc = devm_regulator_get(&pdev->dev, "vcc");
 424                 if (IS_ERR(priv->vcc))
 425                         return PTR_ERR(priv->vcc);
 426
 427                 priv->secclk = devm_clk_get_optional(dev, "core");
 428                 if (IS_ERR(priv->secclk))
 429                         return dev_err_probe(dev, PTR_ERR(priv->secclk), "Error getting clock\n");
 430
 431                 /* Only enable writing if we have SoC data and a valid clock */
 432                 if (priv->soc_data && priv->secclk)
 433                         econfig.reg_write = qfprom_reg_write;
 434         }
 435
 436         pm_runtime_enable(dev);
 437         ret = devm_add_action_or_reset(dev, qfprom_runtime_disable, dev);
 438         if (ret)
 439                 return ret;
 440
 441         nvmem = devm_nvmem_register(dev, &econfig);
 442
 443         return PTR_ERR_OR_ZERO(nvmem);
 444 }
 445
 446 static const struct of_device_id qfprom_of_match[] = {
 447         { .compatible = "qcom,qfprom",},
 448         { .compatible = "qcom,sc7180-qfprom", .data = &sc7180_qfprom},
 449         { .compatible = "qcom,sc7280-qfprom", .data = &sc7280_qfprom},
 450         {/* sentinel */},
 451 };
 452 MODULE_DEVICE_TABLE(of, qfprom_of_match);
 453
 454 static struct platform_driver qfprom_driver = {
 455         .probe = qfprom_probe,
 456         .driver = {
 457                 .name = "qcom,qfprom",
 458                 .of_match_table = qfprom_of_match,
 459         },
 460 };
 461 module_platform_driver(qfprom_driver);
 462 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
 463 MODULE_DESCRIPTION("Qualcomm QFPROM driver");
 464 MODULE_LICENSE("GPL v2");