drivers/pci/controller/pcie-rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Rockchip AXI PCIe host controller driver
   4  *
   5  * Copyright (c) 2016 Rockchip, Inc.
   6  *
   7  * Author: Shawn Lin <shawn.lin@rock-chips.com>
   8  *         Wenrui Li <wenrui.li@rock-chips.com>
   9  *
  10  * Bits taken from Synopsys DesignWare Host controller driver and
  11  * ARM PCI Host generic driver.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/gpio/consumer.h>
  17 #include <linux/iopoll.h>
  18 #include <linux/of.h>
  19 #include <linux/of_pci.h>
  20 #include <linux/phy/phy.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/reset.h>
  23
  24 #include "../pci.h"
  25 #include "pcie-rockchip.h"
  26
  27 int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
  28 {
  29         struct device *dev = rockchip->dev;
  30         struct platform_device *pdev = to_platform_device(dev);
  31         struct device_node *node = dev->of_node;
  32         struct resource *regs;
  33         int err;
  34
  35         if (rockchip->is_rc) {
  36                 regs = platform_get_resource_byname(pdev,
  37                                                     IORESOURCE_MEM,
  38                                                     "axi-base");
  39                 rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs);
  40                 if (IS_ERR(rockchip->reg_base))
  41                         return PTR_ERR(rockchip->reg_base);
  42         } else {
  43                 rockchip->mem_res =
  44                         platform_get_resource_byname(pdev, IORESOURCE_MEM,
  45                                                      "mem-base");
  46                 if (!rockchip->mem_res)
  47                         return -EINVAL;
  48         }
  49
  50         rockchip->apb_base =
  51                 devm_platform_ioremap_resource_byname(pdev, "apb-base");
  52         if (IS_ERR(rockchip->apb_base))
  53                 return PTR_ERR(rockchip->apb_base);
  54
  55         err = rockchip_pcie_get_phys(rockchip);
  56         if (err)
  57                 return err;
  58
  59         rockchip->lanes = 1;
  60         err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
  61         if (!err && (rockchip->lanes == 0 ||
  62                      rockchip->lanes == 3 ||
  63                      rockchip->lanes > 4)) {
  64                 dev_warn(dev, "invalid num-lanes, default to use one lane\n");
  65                 rockchip->lanes = 1;
  66         }
  67
  68         rockchip->link_gen = of_pci_get_max_link_speed(node);
  69         if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
  70                 rockchip->link_gen = 2;
  71
  72         rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core");
  73         if (IS_ERR(rockchip->core_rst)) {
  74                 if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
  75                         dev_err(dev, "missing core reset property in node\n");
  76                 return PTR_ERR(rockchip->core_rst);
  77         }
  78
  79         rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt");
  80         if (IS_ERR(rockchip->mgmt_rst)) {
  81                 if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
  82                         dev_err(dev, "missing mgmt reset property in node\n");
  83                 return PTR_ERR(rockchip->mgmt_rst);
  84         }
  85
  86         rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev,
  87                                                                 "mgmt-sticky");
  88         if (IS_ERR(rockchip->mgmt_sticky_rst)) {
  89                 if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
  90                         dev_err(dev, "missing mgmt-sticky reset property in node\n");
  91                 return PTR_ERR(rockchip->mgmt_sticky_rst);
  92         }
  93
  94         rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe");
  95         if (IS_ERR(rockchip->pipe_rst)) {
  96                 if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
  97                         dev_err(dev, "missing pipe reset property in node\n");
  98                 return PTR_ERR(rockchip->pipe_rst);
  99         }
 100
 101         rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm");
 102         if (IS_ERR(rockchip->pm_rst)) {
 103                 if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)
 104                         dev_err(dev, "missing pm reset property in node\n");
 105                 return PTR_ERR(rockchip->pm_rst);
 106         }
 107
 108         rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk");
 109         if (IS_ERR(rockchip->pclk_rst)) {
 110                 if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)
 111                         dev_err(dev, "missing pclk reset property in node\n");
 112                 return PTR_ERR(rockchip->pclk_rst);
 113         }
 114
 115         rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk");
 116         if (IS_ERR(rockchip->aclk_rst)) {
 117                 if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)
 118                         dev_err(dev, "missing aclk reset property in node\n");
 119                 return PTR_ERR(rockchip->aclk_rst);
 120         }
 121
 122         if (rockchip->is_rc)
 123                 rockchip->perst_gpio = devm_gpiod_get_optional(dev, "ep",
 124                                                                GPIOD_OUT_LOW);
 125         else
 126                 rockchip->perst_gpio = devm_gpiod_get_optional(dev, "reset",
 127                                                                GPIOD_IN);
 128         if (IS_ERR(rockchip->perst_gpio))
 129                 return dev_err_probe(dev, PTR_ERR(rockchip->perst_gpio),
 130                                      "failed to get PERST# GPIO\n");
 131
 132         rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
 133         if (IS_ERR(rockchip->aclk_pcie)) {
 134                 dev_err(dev, "aclk clock not found\n");
 135                 return PTR_ERR(rockchip->aclk_pcie);
 136         }
 137
 138         rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
 139         if (IS_ERR(rockchip->aclk_perf_pcie)) {
 140                 dev_err(dev, "aclk_perf clock not found\n");
 141                 return PTR_ERR(rockchip->aclk_perf_pcie);
 142         }
 143
 144         rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
 145         if (IS_ERR(rockchip->hclk_pcie)) {
 146                 dev_err(dev, "hclk clock not found\n");
 147                 return PTR_ERR(rockchip->hclk_pcie);
 148         }
 149
 150         rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
 151         if (IS_ERR(rockchip->clk_pcie_pm)) {
 152                 dev_err(dev, "pm clock not found\n");
 153                 return PTR_ERR(rockchip->clk_pcie_pm);
 154         }
 155
 156         return 0;
 157 }
 158 EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt);
 159
 160 #define rockchip_pcie_read_addr(addr) rockchip_pcie_read(rockchip, addr)
 161 /* 100 ms max wait time for PHY PLLs to lock */
 162 #define RK_PHY_PLL_LOCK_TIMEOUT_US 100000
 163 /* Sleep should be less than 20ms */
 164 #define RK_PHY_PLL_LOCK_SLEEP_US 1000
 165
 166 int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 167 {
 168         struct device *dev = rockchip->dev;
 169         int err, i;
 170         u32 regs;
 171
 172         err = reset_control_assert(rockchip->aclk_rst);
 173         if (err) {
 174                 dev_err(dev, "assert aclk_rst err %d\n", err);
 175                 return err;
 176         }
 177
 178         err = reset_control_assert(rockchip->pclk_rst);
 179         if (err) {
 180                 dev_err(dev, "assert pclk_rst err %d\n", err);
 181                 return err;
 182         }
 183
 184         err = reset_control_assert(rockchip->pm_rst);
 185         if (err) {
 186                 dev_err(dev, "assert pm_rst err %d\n", err);
 187                 return err;
 188         }
 189
 190         for (i = 0; i < MAX_LANE_NUM; i++) {
 191                 err = phy_init(rockchip->phys[i]);
 192                 if (err) {
 193                         dev_err(dev, "init phy%d err %d\n", i, err);
 194                         goto err_exit_phy;
 195                 }
 196         }
 197
 198         err = reset_control_assert(rockchip->core_rst);
 199         if (err) {
 200                 dev_err(dev, "assert core_rst err %d\n", err);
 201                 goto err_exit_phy;
 202         }
 203
 204         err = reset_control_assert(rockchip->mgmt_rst);
 205         if (err) {
 206                 dev_err(dev, "assert mgmt_rst err %d\n", err);
 207                 goto err_exit_phy;
 208         }
 209
 210         err = reset_control_assert(rockchip->mgmt_sticky_rst);
 211         if (err) {
 212                 dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
 213                 goto err_exit_phy;
 214         }
 215
 216         err = reset_control_assert(rockchip->pipe_rst);
 217         if (err) {
 218                 dev_err(dev, "assert pipe_rst err %d\n", err);
 219                 goto err_exit_phy;
 220         }
 221
 222         udelay(10);
 223
 224         err = reset_control_deassert(rockchip->pm_rst);
 225         if (err) {
 226                 dev_err(dev, "deassert pm_rst err %d\n", err);
 227                 goto err_exit_phy;
 228         }
 229
 230         err = reset_control_deassert(rockchip->aclk_rst);
 231         if (err) {
 232                 dev_err(dev, "deassert aclk_rst err %d\n", err);
 233                 goto err_exit_phy;
 234         }
 235
 236         err = reset_control_deassert(rockchip->pclk_rst);
 237         if (err) {
 238                 dev_err(dev, "deassert pclk_rst err %d\n", err);
 239                 goto err_exit_phy;
 240         }
 241
 242         if (rockchip->link_gen == 2)
 243                 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2,
 244                                     PCIE_CLIENT_CONFIG);
 245         else
 246                 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1,
 247                                     PCIE_CLIENT_CONFIG);
 248
 249         regs = PCIE_CLIENT_ARI_ENABLE |
 250                PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes);
 251
 252         if (rockchip->is_rc)
 253                 regs |= PCIE_CLIENT_LINK_TRAIN_ENABLE |
 254                         PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
 255         else
 256                 regs |= PCIE_CLIENT_CONF_DISABLE | PCIE_CLIENT_MODE_EP;
 257
 258         rockchip_pcie_write(rockchip, regs, PCIE_CLIENT_CONFIG);
 259
 260         for (i = 0; i < MAX_LANE_NUM; i++) {
 261                 err = phy_power_on(rockchip->phys[i]);
 262                 if (err) {
 263                         dev_err(dev, "power on phy%d err %d\n", i, err);
 264                         goto err_power_off_phy;
 265                 }
 266         }
 267
 268         err = readx_poll_timeout(rockchip_pcie_read_addr,
 269                                  PCIE_CLIENT_SIDE_BAND_STATUS,
 270                                  regs, !(regs & PCIE_CLIENT_PHY_ST),
 271                                  RK_PHY_PLL_LOCK_SLEEP_US,
 272                                  RK_PHY_PLL_LOCK_TIMEOUT_US);
 273         if (err) {
 274                 dev_err(dev, "PHY PLLs could not lock, %d\n", err);
 275                 goto err_power_off_phy;
 276         }
 277
 278         /*
 279          * Please don't reorder the deassert sequence of the following
 280          * four reset pins.
 281          */
 282         err = reset_control_deassert(rockchip->mgmt_sticky_rst);
 283         if (err) {
 284                 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
 285                 goto err_power_off_phy;
 286         }
 287
 288         err = reset_control_deassert(rockchip->core_rst);
 289         if (err) {
 290                 dev_err(dev, "deassert core_rst err %d\n", err);
 291                 goto err_power_off_phy;
 292         }
 293
 294         err = reset_control_deassert(rockchip->mgmt_rst);
 295         if (err) {
 296                 dev_err(dev, "deassert mgmt_rst err %d\n", err);
 297                 goto err_power_off_phy;
 298         }
 299
 300         err = reset_control_deassert(rockchip->pipe_rst);
 301         if (err) {
 302                 dev_err(dev, "deassert pipe_rst err %d\n", err);
 303                 goto err_power_off_phy;
 304         }
 305
 306         return 0;
 307 err_power_off_phy:
 308         while (i--)
 309                 phy_power_off(rockchip->phys[i]);
 310         i = MAX_LANE_NUM;
 311 err_exit_phy:
 312         while (i--)
 313                 phy_exit(rockchip->phys[i]);
 314         return err;
 315 }
 316 EXPORT_SYMBOL_GPL(rockchip_pcie_init_port);
 317
 318 int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip)
 319 {
 320         struct device *dev = rockchip->dev;
 321         struct phy *phy;
 322         char *name;
 323         u32 i;
 324
 325         phy = devm_phy_get(dev, "pcie-phy");
 326         if (!IS_ERR(phy)) {
 327                 rockchip->legacy_phy = true;
 328                 rockchip->phys[0] = phy;
 329                 dev_warn(dev, "legacy phy model is deprecated!\n");
 330                 return 0;
 331         }
 332
 333         if (PTR_ERR(phy) == -EPROBE_DEFER)
 334                 return PTR_ERR(phy);
 335
 336         dev_dbg(dev, "missing legacy phy; search for per-lane PHY\n");
 337
 338         for (i = 0; i < MAX_LANE_NUM; i++) {
 339                 name = kasprintf(GFP_KERNEL, "pcie-phy-%u", i);
 340                 if (!name)
 341                         return -ENOMEM;
 342
 343                 phy = devm_of_phy_get(dev, dev->of_node, name);
 344                 kfree(name);
 345
 346                 if (IS_ERR(phy)) {
 347                         if (PTR_ERR(phy) != -EPROBE_DEFER)
 348                                 dev_err(dev, "missing phy for lane %d: %ld\n",
 349                                         i, PTR_ERR(phy));
 350                         return PTR_ERR(phy);
 351                 }
 352
 353                 rockchip->phys[i] = phy;
 354         }
 355
 356         return 0;
 357 }
 358 EXPORT_SYMBOL_GPL(rockchip_pcie_get_phys);
 359
 360 void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip)
 361 {
 362         int i;
 363
 364         for (i = 0; i < MAX_LANE_NUM; i++) {
 365                 /* inactive lanes are already powered off */
 366                 if (rockchip->lanes_map & BIT(i))
 367                         phy_power_off(rockchip->phys[i]);
 368                 phy_exit(rockchip->phys[i]);
 369         }
 370 }
 371 EXPORT_SYMBOL_GPL(rockchip_pcie_deinit_phys);
 372
 373 int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip)
 374 {
 375         struct device *dev = rockchip->dev;
 376         int err;
 377
 378         err = clk_prepare_enable(rockchip->aclk_pcie);
 379         if (err) {
 380                 dev_err(dev, "unable to enable aclk_pcie clock\n");
 381                 return err;
 382         }
 383
 384         err = clk_prepare_enable(rockchip->aclk_perf_pcie);
 385         if (err) {
 386                 dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
 387                 goto err_aclk_perf_pcie;
 388         }
 389
 390         err = clk_prepare_enable(rockchip->hclk_pcie);
 391         if (err) {
 392                 dev_err(dev, "unable to enable hclk_pcie clock\n");
 393                 goto err_hclk_pcie;
 394         }
 395
 396         err = clk_prepare_enable(rockchip->clk_pcie_pm);
 397         if (err) {
 398                 dev_err(dev, "unable to enable clk_pcie_pm clock\n");
 399                 goto err_clk_pcie_pm;
 400         }
 401
 402         return 0;
 403
 404 err_clk_pcie_pm:
 405         clk_disable_unprepare(rockchip->hclk_pcie);
 406 err_hclk_pcie:
 407         clk_disable_unprepare(rockchip->aclk_perf_pcie);
 408 err_aclk_perf_pcie:
 409         clk_disable_unprepare(rockchip->aclk_pcie);
 410         return err;
 411 }
 412 EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks);
 413
 414 void rockchip_pcie_disable_clocks(void *data)
 415 {
 416         struct rockchip_pcie *rockchip = data;
 417
 418         clk_disable_unprepare(rockchip->clk_pcie_pm);
 419         clk_disable_unprepare(rockchip->hclk_pcie);
 420         clk_disable_unprepare(rockchip->aclk_perf_pcie);
 421         clk_disable_unprepare(rockchip->aclk_pcie);
 422 }
 423 EXPORT_SYMBOL_GPL(rockchip_pcie_disable_clocks);
 424
 425 void rockchip_pcie_cfg_configuration_accesses(
 426                 struct rockchip_pcie *rockchip, u32 type)
 427 {
 428         u32 ob_desc_0;
 429
 430         /* Configuration Accesses for region 0 */
 431         rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
 432
 433         rockchip_pcie_write(rockchip,
 434                             (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
 435                             PCIE_CORE_OB_REGION_ADDR0);
 436         rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
 437                             PCIE_CORE_OB_REGION_ADDR1);
 438         ob_desc_0 = rockchip_pcie_read(rockchip, PCIE_CORE_OB_REGION_DESC0);
 439         ob_desc_0 &= ~(RC_REGION_0_TYPE_MASK);
 440         ob_desc_0 |= (type | (0x1 << 23));
 441         rockchip_pcie_write(rockchip, ob_desc_0, PCIE_CORE_OB_REGION_DESC0);
 442         rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
 443 }
 444 EXPORT_SYMBOL_GPL(rockchip_pcie_cfg_configuration_accesses);