drivers/perf/thunderx2_pmu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * CAVIUM THUNDERX2 SoC PMU UNCORE
   4  * Copyright (C) 2018 Cavium Inc.
   5  * Author: Ganapatrao Kulkarni <gkulkarni@cavium.com>
   6  */
   7
   8 #include <linux/acpi.h>
   9 #include <linux/cpuhotplug.h>
  10 #include <linux/perf_event.h>
  11 #include <linux/platform_device.h>
  12
  13 /* Each ThunderX2(TX2) Socket has a L3C and DMC UNCORE PMU device.
  14  * Each UNCORE PMU device consists of 4 independent programmable counters.
  15  * Counters are 32 bit and do not support overflow interrupt,
  16  * they need to be sampled before overflow(i.e, at every 2 seconds).
  17  */
  18
  19 #define TX2_PMU_DMC_L3C_MAX_COUNTERS    4
  20 #define TX2_PMU_CCPI2_MAX_COUNTERS      8
  21 #define TX2_PMU_MAX_COUNTERS            TX2_PMU_CCPI2_MAX_COUNTERS
  22
  23
  24 #define TX2_PMU_DMC_CHANNELS            8
  25 #define TX2_PMU_L3_TILES                16
  26
  27 #define TX2_PMU_HRTIMER_INTERVAL        (2 * NSEC_PER_SEC)
  28 #define GET_EVENTID(ev, mask)           ((ev->hw.config) & mask)
  29 #define GET_COUNTERID(ev, mask)         ((ev->hw.idx) & mask)
  30  /* 1 byte per counter(4 counters).
  31   * Event id is encoded in bits [5:1] of a byte,
  32   */
  33 #define DMC_EVENT_CFG(idx, val)         ((val) << (((idx) * 8) + 1))
  34
  35 /* bits[3:0] to select counters, are indexed from 8 to 15. */
  36 #define CCPI2_COUNTER_OFFSET            8
  37
  38 #define L3C_COUNTER_CTL                 0xA8
  39 #define L3C_COUNTER_DATA                0xAC
  40 #define DMC_COUNTER_CTL                 0x234
  41 #define DMC_COUNTER_DATA                0x240
  42
  43 #define CCPI2_PERF_CTL                  0x108
  44 #define CCPI2_COUNTER_CTL               0x10C
  45 #define CCPI2_COUNTER_SEL               0x12c
  46 #define CCPI2_COUNTER_DATA_L            0x130
  47 #define CCPI2_COUNTER_DATA_H            0x134
  48
  49 /* L3C event IDs */
  50 #define L3_EVENT_READ_REQ               0xD
  51 #define L3_EVENT_WRITEBACK_REQ          0xE
  52 #define L3_EVENT_INV_N_WRITE_REQ        0xF
  53 #define L3_EVENT_INV_REQ                0x10
  54 #define L3_EVENT_EVICT_REQ              0x13
  55 #define L3_EVENT_INV_N_WRITE_HIT        0x14
  56 #define L3_EVENT_INV_HIT                0x15
  57 #define L3_EVENT_READ_HIT               0x17
  58 #define L3_EVENT_MAX                    0x18
  59
  60 /* DMC event IDs */
  61 #define DMC_EVENT_COUNT_CYCLES          0x1
  62 #define DMC_EVENT_WRITE_TXNS            0xB
  63 #define DMC_EVENT_DATA_TRANSFERS        0xD
  64 #define DMC_EVENT_READ_TXNS             0xF
  65 #define DMC_EVENT_MAX                   0x10
  66
  67 #define CCPI2_EVENT_REQ_PKT_SENT        0x3D
  68 #define CCPI2_EVENT_SNOOP_PKT_SENT      0x65
  69 #define CCPI2_EVENT_DATA_PKT_SENT       0x105
  70 #define CCPI2_EVENT_GIC_PKT_SENT        0x12D
  71 #define CCPI2_EVENT_MAX                 0x200
  72
  73 #define CCPI2_PERF_CTL_ENABLE           BIT(0)
  74 #define CCPI2_PERF_CTL_START            BIT(1)
  75 #define CCPI2_PERF_CTL_RESET            BIT(4)
  76 #define CCPI2_EVENT_LEVEL_RISING_EDGE   BIT(10)
  77 #define CCPI2_EVENT_TYPE_EDGE_SENSITIVE BIT(11)
  78
  79 enum tx2_uncore_type {
  80         PMU_TYPE_L3C,
  81         PMU_TYPE_DMC,
  82         PMU_TYPE_CCPI2,
  83         PMU_TYPE_INVALID,
  84 };
  85
  86 /*
  87  * Each socket has 3 uncore devices associated with a PMU. The DMC and
  88  * L3C have 4 32-bit counters and the CCPI2 has 8 64-bit counters.
  89  */
  90 struct tx2_uncore_pmu {
  91         struct hlist_node hpnode;
  92         struct list_head  entry;
  93         struct pmu pmu;
  94         char *name;
  95         int node;
  96         int cpu;
  97         u32 max_counters;
  98         u32 counters_mask;
  99         u32 prorate_factor;
 100         u32 max_events;
 101         u32 events_mask;
 102         u64 hrtimer_interval;
 103         void __iomem *base;
 104         DECLARE_BITMAP(active_counters, TX2_PMU_MAX_COUNTERS);
 105         struct perf_event *events[TX2_PMU_MAX_COUNTERS];
 106         struct device *dev;
 107         struct hrtimer hrtimer;
 108         const struct attribute_group **attr_groups;
 109         enum tx2_uncore_type type;
 110         enum hrtimer_restart (*hrtimer_callback)(struct hrtimer *cb);
 111         void (*init_cntr_base)(struct perf_event *event,
 112                         struct tx2_uncore_pmu *tx2_pmu);
 113         void (*stop_event)(struct perf_event *event);
 114         void (*start_event)(struct perf_event *event, int flags);
 115 };
 116
 117 static LIST_HEAD(tx2_pmus);
 118
 119 static inline struct tx2_uncore_pmu *pmu_to_tx2_pmu(struct pmu *pmu)
 120 {
 121         return container_of(pmu, struct tx2_uncore_pmu, pmu);
 122 }
 123
 124 #define TX2_PMU_FORMAT_ATTR(_var, _name, _format)                       \
 125 static ssize_t                                                          \
 126 __tx2_pmu_##_var##_show(struct device *dev,                             \
 127                                struct device_attribute *attr,           \
 128                                char *page)                              \
 129 {                                                                       \
 130         BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE);                     \
 131         return sysfs_emit(page, _format "\n");                          \
 132 }                                                                       \
 133                                                                         \
 134 static struct device_attribute format_attr_##_var =                     \
 135         __ATTR(_name, 0444, __tx2_pmu_##_var##_show, NULL)
 136
 137 TX2_PMU_FORMAT_ATTR(event, event, "config:0-4");
 138 TX2_PMU_FORMAT_ATTR(event_ccpi2, event, "config:0-9");
 139
 140 static struct attribute *l3c_pmu_format_attrs[] = {
 141         &format_attr_event.attr,
 142         NULL,
 143 };
 144
 145 static struct attribute *dmc_pmu_format_attrs[] = {
 146         &format_attr_event.attr,
 147         NULL,
 148 };
 149
 150 static struct attribute *ccpi2_pmu_format_attrs[] = {
 151         &format_attr_event_ccpi2.attr,
 152         NULL,
 153 };
 154
 155 static const struct attribute_group l3c_pmu_format_attr_group = {
 156         .name = "format",
 157         .attrs = l3c_pmu_format_attrs,
 158 };
 159
 160 static const struct attribute_group dmc_pmu_format_attr_group = {
 161         .name = "format",
 162         .attrs = dmc_pmu_format_attrs,
 163 };
 164
 165 static const struct attribute_group ccpi2_pmu_format_attr_group = {
 166         .name = "format",
 167         .attrs = ccpi2_pmu_format_attrs,
 168 };
 169
 170 /*
 171  * sysfs event attributes
 172  */
 173 static ssize_t tx2_pmu_event_show(struct device *dev,
 174                                     struct device_attribute *attr, char *buf)
 175 {
 176         struct dev_ext_attribute *eattr;
 177
 178         eattr = container_of(attr, struct dev_ext_attribute, attr);
 179         return sysfs_emit(buf, "event=0x%lx\n", (unsigned long) eattr->var);
 180 }
 181
 182 #define TX2_EVENT_ATTR(name, config) \
 183         PMU_EVENT_ATTR(name, tx2_pmu_event_attr_##name, \
 184                         config, tx2_pmu_event_show)
 185
 186 TX2_EVENT_ATTR(read_request, L3_EVENT_READ_REQ);
 187 TX2_EVENT_ATTR(writeback_request, L3_EVENT_WRITEBACK_REQ);
 188 TX2_EVENT_ATTR(inv_nwrite_request, L3_EVENT_INV_N_WRITE_REQ);
 189 TX2_EVENT_ATTR(inv_request, L3_EVENT_INV_REQ);
 190 TX2_EVENT_ATTR(evict_request, L3_EVENT_EVICT_REQ);
 191 TX2_EVENT_ATTR(inv_nwrite_hit, L3_EVENT_INV_N_WRITE_HIT);
 192 TX2_EVENT_ATTR(inv_hit, L3_EVENT_INV_HIT);
 193 TX2_EVENT_ATTR(read_hit, L3_EVENT_READ_HIT);
 194
 195 static struct attribute *l3c_pmu_events_attrs[] = {
 196         &tx2_pmu_event_attr_read_request.attr.attr,
 197         &tx2_pmu_event_attr_writeback_request.attr.attr,
 198         &tx2_pmu_event_attr_inv_nwrite_request.attr.attr,
 199         &tx2_pmu_event_attr_inv_request.attr.attr,
 200         &tx2_pmu_event_attr_evict_request.attr.attr,
 201         &tx2_pmu_event_attr_inv_nwrite_hit.attr.attr,
 202         &tx2_pmu_event_attr_inv_hit.attr.attr,
 203         &tx2_pmu_event_attr_read_hit.attr.attr,
 204         NULL,
 205 };
 206
 207 TX2_EVENT_ATTR(cnt_cycles, DMC_EVENT_COUNT_CYCLES);
 208 TX2_EVENT_ATTR(write_txns, DMC_EVENT_WRITE_TXNS);
 209 TX2_EVENT_ATTR(data_transfers, DMC_EVENT_DATA_TRANSFERS);
 210 TX2_EVENT_ATTR(read_txns, DMC_EVENT_READ_TXNS);
 211
 212 static struct attribute *dmc_pmu_events_attrs[] = {
 213         &tx2_pmu_event_attr_cnt_cycles.attr.attr,
 214         &tx2_pmu_event_attr_write_txns.attr.attr,
 215         &tx2_pmu_event_attr_data_transfers.attr.attr,
 216         &tx2_pmu_event_attr_read_txns.attr.attr,
 217         NULL,
 218 };
 219
 220 TX2_EVENT_ATTR(req_pktsent, CCPI2_EVENT_REQ_PKT_SENT);
 221 TX2_EVENT_ATTR(snoop_pktsent, CCPI2_EVENT_SNOOP_PKT_SENT);
 222 TX2_EVENT_ATTR(data_pktsent, CCPI2_EVENT_DATA_PKT_SENT);
 223 TX2_EVENT_ATTR(gic_pktsent, CCPI2_EVENT_GIC_PKT_SENT);
 224
 225 static struct attribute *ccpi2_pmu_events_attrs[] = {
 226         &tx2_pmu_event_attr_req_pktsent.attr.attr,
 227         &tx2_pmu_event_attr_snoop_pktsent.attr.attr,
 228         &tx2_pmu_event_attr_data_pktsent.attr.attr,
 229         &tx2_pmu_event_attr_gic_pktsent.attr.attr,
 230         NULL,
 231 };
 232
 233 static const struct attribute_group l3c_pmu_events_attr_group = {
 234         .name = "events",
 235         .attrs = l3c_pmu_events_attrs,
 236 };
 237
 238 static const struct attribute_group dmc_pmu_events_attr_group = {
 239         .name = "events",
 240         .attrs = dmc_pmu_events_attrs,
 241 };
 242
 243 static const struct attribute_group ccpi2_pmu_events_attr_group = {
 244         .name = "events",
 245         .attrs = ccpi2_pmu_events_attrs,
 246 };
 247
 248 /*
 249  * sysfs cpumask attributes
 250  */
 251 static ssize_t cpumask_show(struct device *dev, struct device_attribute *attr,
 252                 char *buf)
 253 {
 254         struct tx2_uncore_pmu *tx2_pmu;
 255
 256         tx2_pmu = pmu_to_tx2_pmu(dev_get_drvdata(dev));
 257         return cpumap_print_to_pagebuf(true, buf, cpumask_of(tx2_pmu->cpu));
 258 }
 259 static DEVICE_ATTR_RO(cpumask);
 260
 261 static struct attribute *tx2_pmu_cpumask_attrs[] = {
 262         &dev_attr_cpumask.attr,
 263         NULL,
 264 };
 265
 266 static const struct attribute_group pmu_cpumask_attr_group = {
 267         .attrs = tx2_pmu_cpumask_attrs,
 268 };
 269
 270 /*
 271  * Per PMU device attribute groups
 272  */
 273 static const struct attribute_group *l3c_pmu_attr_groups[] = {
 274         &l3c_pmu_format_attr_group,
 275         &pmu_cpumask_attr_group,
 276         &l3c_pmu_events_attr_group,
 277         NULL
 278 };
 279
 280 static const struct attribute_group *dmc_pmu_attr_groups[] = {
 281         &dmc_pmu_format_attr_group,
 282         &pmu_cpumask_attr_group,
 283         &dmc_pmu_events_attr_group,
 284         NULL
 285 };
 286
 287 static const struct attribute_group *ccpi2_pmu_attr_groups[] = {
 288         &ccpi2_pmu_format_attr_group,
 289         &pmu_cpumask_attr_group,
 290         &ccpi2_pmu_events_attr_group,
 291         NULL
 292 };
 293
 294 static inline u32 reg_readl(unsigned long addr)
 295 {
 296         return readl((void __iomem *)addr);
 297 }
 298
 299 static inline void reg_writel(u32 val, unsigned long addr)
 300 {
 301         writel(val, (void __iomem *)addr);
 302 }
 303
 304 static int alloc_counter(struct tx2_uncore_pmu *tx2_pmu)
 305 {
 306         int counter;
 307
 308         counter = find_first_zero_bit(tx2_pmu->active_counters,
 309                                 tx2_pmu->max_counters);
 310         if (counter == tx2_pmu->max_counters)
 311                 return -ENOSPC;
 312
 313         set_bit(counter, tx2_pmu->active_counters);
 314         return counter;
 315 }
 316
 317 static inline void free_counter(struct tx2_uncore_pmu *tx2_pmu, int counter)
 318 {
 319         clear_bit(counter, tx2_pmu->active_counters);
 320 }
 321
 322 static void init_cntr_base_l3c(struct perf_event *event,
 323                 struct tx2_uncore_pmu *tx2_pmu)
 324 {
 325         struct hw_perf_event *hwc = &event->hw;
 326         u32 cmask;
 327
 328         tx2_pmu = pmu_to_tx2_pmu(event->pmu);
 329         cmask = tx2_pmu->counters_mask;
 330
 331         /* counter ctrl/data reg offset at 8 */
 332         hwc->config_base = (unsigned long)tx2_pmu->base
 333                 + L3C_COUNTER_CTL + (8 * GET_COUNTERID(event, cmask));
 334         hwc->event_base =  (unsigned long)tx2_pmu->base
 335                 + L3C_COUNTER_DATA + (8 * GET_COUNTERID(event, cmask));
 336 }
 337
 338 static void init_cntr_base_dmc(struct perf_event *event,
 339                 struct tx2_uncore_pmu *tx2_pmu)
 340 {
 341         struct hw_perf_event *hwc = &event->hw;
 342         u32 cmask;
 343
 344         tx2_pmu = pmu_to_tx2_pmu(event->pmu);
 345         cmask = tx2_pmu->counters_mask;
 346
 347         hwc->config_base = (unsigned long)tx2_pmu->base
 348                 + DMC_COUNTER_CTL;
 349         /* counter data reg offset at 0xc */
 350         hwc->event_base = (unsigned long)tx2_pmu->base
 351                 + DMC_COUNTER_DATA + (0xc * GET_COUNTERID(event, cmask));
 352 }
 353
 354 static void init_cntr_base_ccpi2(struct perf_event *event,
 355                 struct tx2_uncore_pmu *tx2_pmu)
 356 {
 357         struct hw_perf_event *hwc = &event->hw;
 358         u32 cmask;
 359
 360         cmask = tx2_pmu->counters_mask;
 361
 362         hwc->config_base = (unsigned long)tx2_pmu->base
 363                 + CCPI2_COUNTER_CTL + (4 * GET_COUNTERID(event, cmask));
 364         hwc->event_base =  (unsigned long)tx2_pmu->base;
 365 }
 366
 367 static void uncore_start_event_l3c(struct perf_event *event, int flags)
 368 {
 369         u32 val, emask;
 370         struct hw_perf_event *hwc = &event->hw;
 371         struct tx2_uncore_pmu *tx2_pmu;
 372
 373         tx2_pmu = pmu_to_tx2_pmu(event->pmu);
 374         emask = tx2_pmu->events_mask;
 375
 376         /* event id encoded in bits [07:03] */
 377         val = GET_EVENTID(event, emask) << 3;
 378         reg_writel(val, hwc->config_base);
 379         local64_set(&hwc->prev_count, 0);
 380         reg_writel(0, hwc->event_base);
 381 }
 382
 383 static inline void uncore_stop_event_l3c(struct perf_event *event)
 384 {
 385         reg_writel(0, event->hw.config_base);
 386 }
 387
 388 static void uncore_start_event_dmc(struct perf_event *event, int flags)
 389 {
 390         u32 val, cmask, emask;
 391         struct hw_perf_event *hwc = &event->hw;
 392         struct tx2_uncore_pmu *tx2_pmu;
 393         int idx, event_id;
 394
 395         tx2_pmu = pmu_to_tx2_pmu(event->pmu);
 396         cmask = tx2_pmu->counters_mask;
 397         emask = tx2_pmu->events_mask;
 398
 399         idx = GET_COUNTERID(event, cmask);
 400         event_id = GET_EVENTID(event, emask);
 401
 402         /* enable and start counters.
 403          * 8 bits for each counter, bits[05:01] of a counter to set event type.
 404          */
 405         val = reg_readl(hwc->config_base);
 406         val &= ~DMC_EVENT_CFG(idx, 0x1f);
 407         val |= DMC_EVENT_CFG(idx, event_id);
 408         reg_writel(val, hwc->config_base);
 409         local64_set(&hwc->prev_count, 0);
 410         reg_writel(0, hwc->event_base);
 411 }
 412
 413 static void uncore_stop_event_dmc(struct perf_event *event)
 414 {
 415         u32 val, cmask;
 416         struct hw_perf_event *hwc = &event->hw;
 417         struct tx2_uncore_pmu *tx2_pmu;
 418         int idx;
 419
 420         tx2_pmu = pmu_to_tx2_pmu(event->pmu);
 421         cmask = tx2_pmu->counters_mask;
 422         idx = GET_COUNTERID(event, cmask);
 423
 424         /* clear event type(bits[05:01]) to stop counter */
 425         val = reg_readl(hwc->config_base);
 426         val &= ~DMC_EVENT_CFG(idx, 0x1f);
 427         reg_writel(val, hwc->config_base);
 428 }
 429
 430 static void uncore_start_event_ccpi2(struct perf_event *event, int flags)
 431 {
 432         u32 emask;
 433         struct hw_perf_event *hwc = &event->hw;
 434         struct tx2_uncore_pmu *tx2_pmu;
 435
 436         tx2_pmu = pmu_to_tx2_pmu(event->pmu);
 437         emask = tx2_pmu->events_mask;
 438
 439         /* Bit [09:00] to set event id.
 440          * Bits [10], set level to rising edge.
 441          * Bits [11], set type to edge sensitive.
 442          */
 443         reg_writel((CCPI2_EVENT_TYPE_EDGE_SENSITIVE |
 444                         CCPI2_EVENT_LEVEL_RISING_EDGE |
 445                         GET_EVENTID(event, emask)), hwc->config_base);
 446
 447         /* reset[4], enable[0] and start[1] counters */
 448         reg_writel(CCPI2_PERF_CTL_RESET |
 449                         CCPI2_PERF_CTL_START |
 450                         CCPI2_PERF_CTL_ENABLE,
 451                         hwc->event_base + CCPI2_PERF_CTL);
 452         local64_set(&event->hw.prev_count, 0ULL);
 453 }
 454
 455 static void uncore_stop_event_ccpi2(struct perf_event *event)
 456 {
 457         struct hw_perf_event *hwc = &event->hw;
 458
 459         /* disable and stop counter */
 460         reg_writel(0, hwc->event_base + CCPI2_PERF_CTL);
 461 }
 462
 463 static void tx2_uncore_event_update(struct perf_event *event)
 464 {
 465         u64 prev, delta, new = 0;
 466         struct hw_perf_event *hwc = &event->hw;
 467         struct tx2_uncore_pmu *tx2_pmu;
 468         enum tx2_uncore_type type;
 469         u32 prorate_factor;
 470         u32 cmask, emask;
 471
 472         tx2_pmu = pmu_to_tx2_pmu(event->pmu);
 473         type = tx2_pmu->type;
 474         cmask = tx2_pmu->counters_mask;
 475         emask = tx2_pmu->events_mask;
 476         prorate_factor = tx2_pmu->prorate_factor;
 477         if (type == PMU_TYPE_CCPI2) {
 478                 reg_writel(CCPI2_COUNTER_OFFSET +
 479                                 GET_COUNTERID(event, cmask),
 480                                 hwc->event_base + CCPI2_COUNTER_SEL);
 481                 new = reg_readl(hwc->event_base + CCPI2_COUNTER_DATA_H);
 482                 new = (new << 32) +
 483                         reg_readl(hwc->event_base + CCPI2_COUNTER_DATA_L);
 484                 prev = local64_xchg(&hwc->prev_count, new);
 485                 delta = new - prev;
 486         } else {
 487                 new = reg_readl(hwc->event_base);
 488                 prev = local64_xchg(&hwc->prev_count, new);
 489                 /* handles rollover of 32 bit counter */
 490                 delta = (u32)(((1ULL << 32) - prev) + new);
 491         }
 492
 493         /* DMC event data_transfers granularity is 16 Bytes, convert it to 64 */
 494         if (type == PMU_TYPE_DMC &&
 495                         GET_EVENTID(event, emask) == DMC_EVENT_DATA_TRANSFERS)
 496                 delta = delta/4;
 497
 498         /* L3C and DMC has 16 and 8 interleave channels respectively.
 499          * The sampled value is for channel 0 and multiplied with
 500          * prorate_factor to get the count for a device.
 501          */
 502         local64_add(delta * prorate_factor, &event->count);
 503 }
 504
 505 static enum tx2_uncore_type get_tx2_pmu_type(struct acpi_device *adev)
 506 {
 507         struct acpi_device_id devices[] = {
 508                 {"CAV901D", PMU_TYPE_L3C},
 509                 {"CAV901F", PMU_TYPE_DMC},
 510                 {"CAV901E", PMU_TYPE_CCPI2},
 511                 {}
 512         };
 513         const struct acpi_device_id *id;
 514
 515         id = acpi_match_acpi_device(devices, adev);
 516         if (!id)
 517                 return PMU_TYPE_INVALID;
 518
 519         return (enum tx2_uncore_type)id->driver_data;
 520 }
 521
 522 static bool tx2_uncore_validate_event(struct pmu *pmu,
 523                                   struct perf_event *event, int *counters)
 524 {
 525         if (is_software_event(event))
 526                 return true;
 527         /* Reject groups spanning multiple HW PMUs. */
 528         if (event->pmu != pmu)
 529                 return false;
 530
 531         *counters = *counters + 1;
 532         return true;
 533 }
 534
 535 /*
 536  * Make sure the group of events can be scheduled at once
 537  * on the PMU.
 538  */
 539 static bool tx2_uncore_validate_event_group(struct perf_event *event,
 540                 int max_counters)
 541 {
 542         struct perf_event *sibling, *leader = event->group_leader;
 543         int counters = 0;
 544
 545         if (event->group_leader == event)
 546                 return true;
 547
 548         if (!tx2_uncore_validate_event(event->pmu, leader, &counters))
 549                 return false;
 550
 551         for_each_sibling_event(sibling, leader) {
 552                 if (!tx2_uncore_validate_event(event->pmu, sibling, &counters))
 553                         return false;
 554         }
 555
 556         if (!tx2_uncore_validate_event(event->pmu, event, &counters))
 557                 return false;
 558
 559         /*
 560          * If the group requires more counters than the HW has,
 561          * it cannot ever be scheduled.
 562          */
 563         return counters <= max_counters;
 564 }
 565
 566
 567 static int tx2_uncore_event_init(struct perf_event *event)
 568 {
 569         struct hw_perf_event *hwc = &event->hw;
 570         struct tx2_uncore_pmu *tx2_pmu;
 571
 572         /* Test the event attr type check for PMU enumeration */
 573         if (event->attr.type != event->pmu->type)
 574                 return -ENOENT;
 575
 576         /*
 577          * SOC PMU counters are shared across all cores.
 578          * Therefore, it does not support per-process mode.
 579          * Also, it does not support event sampling mode.
 580          */
 581         if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
 582                 return -EINVAL;
 583
 584         if (event->cpu < 0)
 585                 return -EINVAL;
 586
 587         tx2_pmu = pmu_to_tx2_pmu(event->pmu);
 588         if (tx2_pmu->cpu >= nr_cpu_ids)
 589                 return -EINVAL;
 590         event->cpu = tx2_pmu->cpu;
 591
 592         if (event->attr.config >= tx2_pmu->max_events)
 593                 return -EINVAL;
 594
 595         /* store event id */
 596         hwc->config = event->attr.config;
 597
 598         /* Validate the group */
 599         if (!tx2_uncore_validate_event_group(event, tx2_pmu->max_counters))
 600                 return -EINVAL;
 601
 602         return 0;
 603 }
 604
 605 static void tx2_uncore_event_start(struct perf_event *event, int flags)
 606 {
 607         struct hw_perf_event *hwc = &event->hw;
 608         struct tx2_uncore_pmu *tx2_pmu;
 609
 610         hwc->state = 0;
 611         tx2_pmu = pmu_to_tx2_pmu(event->pmu);
 612
 613         tx2_pmu->start_event(event, flags);
 614         perf_event_update_userpage(event);
 615
 616         /* No hrtimer needed for CCPI2, 64-bit counters */
 617         if (!tx2_pmu->hrtimer_callback)
 618                 return;
 619
 620         /* Start timer for first event */
 621         if (bitmap_weight(tx2_pmu->active_counters,
 622                                 tx2_pmu->max_counters) == 1) {
 623                 hrtimer_start(&tx2_pmu->hrtimer,
 624                         ns_to_ktime(tx2_pmu->hrtimer_interval),
 625                         HRTIMER_MODE_REL_PINNED);
 626         }
 627 }
 628
 629 static void tx2_uncore_event_stop(struct perf_event *event, int flags)
 630 {
 631         struct hw_perf_event *hwc = &event->hw;
 632         struct tx2_uncore_pmu *tx2_pmu;
 633
 634         if (hwc->state & PERF_HES_UPTODATE)
 635                 return;
 636
 637         tx2_pmu = pmu_to_tx2_pmu(event->pmu);
 638         tx2_pmu->stop_event(event);
 639         WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
 640         hwc->state |= PERF_HES_STOPPED;
 641         if (flags & PERF_EF_UPDATE) {
 642                 tx2_uncore_event_update(event);
 643                 hwc->state |= PERF_HES_UPTODATE;
 644         }
 645 }
 646
 647 static int tx2_uncore_event_add(struct perf_event *event, int flags)
 648 {
 649         struct hw_perf_event *hwc = &event->hw;
 650         struct tx2_uncore_pmu *tx2_pmu;
 651
 652         tx2_pmu = pmu_to_tx2_pmu(event->pmu);
 653
 654         /* Allocate a free counter */
 655         hwc->idx  = alloc_counter(tx2_pmu);
 656         if (hwc->idx < 0)
 657                 return -EAGAIN;
 658
 659         tx2_pmu->events[hwc->idx] = event;
 660         /* set counter control and data registers base address */
 661         tx2_pmu->init_cntr_base(event, tx2_pmu);
 662
 663         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
 664         if (flags & PERF_EF_START)
 665                 tx2_uncore_event_start(event, flags);
 666
 667         return 0;
 668 }
 669
 670 static void tx2_uncore_event_del(struct perf_event *event, int flags)
 671 {
 672         struct tx2_uncore_pmu *tx2_pmu = pmu_to_tx2_pmu(event->pmu);
 673         struct hw_perf_event *hwc = &event->hw;
 674         u32 cmask;
 675
 676         cmask = tx2_pmu->counters_mask;
 677         tx2_uncore_event_stop(event, PERF_EF_UPDATE);
 678
 679         /* clear the assigned counter */
 680         free_counter(tx2_pmu, GET_COUNTERID(event, cmask));
 681
 682         perf_event_update_userpage(event);
 683         tx2_pmu->events[hwc->idx] = NULL;
 684         hwc->idx = -1;
 685
 686         if (!tx2_pmu->hrtimer_callback)
 687                 return;
 688
 689         if (bitmap_empty(tx2_pmu->active_counters, tx2_pmu->max_counters))
 690                 hrtimer_cancel(&tx2_pmu->hrtimer);
 691 }
 692
 693 static void tx2_uncore_event_read(struct perf_event *event)
 694 {
 695         tx2_uncore_event_update(event);
 696 }
 697
 698 static enum hrtimer_restart tx2_hrtimer_callback(struct hrtimer *timer)
 699 {
 700         struct tx2_uncore_pmu *tx2_pmu;
 701         int max_counters, idx;
 702
 703         tx2_pmu = container_of(timer, struct tx2_uncore_pmu, hrtimer);
 704         max_counters = tx2_pmu->max_counters;
 705
 706         if (bitmap_empty(tx2_pmu->active_counters, max_counters))
 707                 return HRTIMER_NORESTART;
 708
 709         for_each_set_bit(idx, tx2_pmu->active_counters, max_counters) {
 710                 struct perf_event *event = tx2_pmu->events[idx];
 711
 712                 tx2_uncore_event_update(event);
 713         }
 714         hrtimer_forward_now(timer, ns_to_ktime(tx2_pmu->hrtimer_interval));
 715         return HRTIMER_RESTART;
 716 }
 717
 718 static int tx2_uncore_pmu_register(
 719                 struct tx2_uncore_pmu *tx2_pmu)
 720 {
 721         struct device *dev = tx2_pmu->dev;
 722         char *name = tx2_pmu->name;
 723
 724         /* Perf event registration */
 725         tx2_pmu->pmu = (struct pmu) {
 726                 .module         = THIS_MODULE,
 727                 .parent         = tx2_pmu->dev,
 728                 .attr_groups    = tx2_pmu->attr_groups,
 729                 .task_ctx_nr    = perf_invalid_context,
 730                 .event_init     = tx2_uncore_event_init,
 731                 .add            = tx2_uncore_event_add,
 732                 .del            = tx2_uncore_event_del,
 733                 .start          = tx2_uncore_event_start,
 734                 .stop           = tx2_uncore_event_stop,
 735                 .read           = tx2_uncore_event_read,
 736                 .capabilities   = PERF_PMU_CAP_NO_EXCLUDE,
 737         };
 738
 739         tx2_pmu->pmu.name = devm_kasprintf(dev, GFP_KERNEL,
 740                         "%s", name);
 741
 742         return perf_pmu_register(&tx2_pmu->pmu, tx2_pmu->pmu.name, -1);
 743 }
 744
 745 static int tx2_uncore_pmu_add_dev(struct tx2_uncore_pmu *tx2_pmu)
 746 {
 747         int ret, cpu;
 748
 749         cpu = cpumask_any_and(cpumask_of_node(tx2_pmu->node),
 750                         cpu_online_mask);
 751
 752         tx2_pmu->cpu = cpu;
 753
 754         if (tx2_pmu->hrtimer_callback) {
 755                 hrtimer_init(&tx2_pmu->hrtimer,
 756                                 CLOCK_MONOTONIC, HRTIMER_MODE_REL);
 757                 tx2_pmu->hrtimer.function = tx2_pmu->hrtimer_callback;
 758         }
 759
 760         ret = tx2_uncore_pmu_register(tx2_pmu);
 761         if (ret) {
 762                 dev_err(tx2_pmu->dev, "%s PMU: Failed to init driver\n",
 763                                 tx2_pmu->name);
 764                 return -ENODEV;
 765         }
 766
 767         /* register hotplug callback for the pmu */
 768         ret = cpuhp_state_add_instance(
 769                         CPUHP_AP_PERF_ARM_CAVIUM_TX2_UNCORE_ONLINE,
 770                         &tx2_pmu->hpnode);
 771         if (ret) {
 772                 dev_err(tx2_pmu->dev, "Error %d registering hotplug", ret);
 773                 return ret;
 774         }
 775
 776         /* Add to list */
 777         list_add(&tx2_pmu->entry, &tx2_pmus);
 778
 779         dev_dbg(tx2_pmu->dev, "%s PMU UNCORE registered\n",
 780                         tx2_pmu->pmu.name);
 781         return ret;
 782 }
 783
 784 static struct tx2_uncore_pmu *tx2_uncore_pmu_init_dev(struct device *dev,
 785                 acpi_handle handle, struct acpi_device *adev, u32 type)
 786 {
 787         struct tx2_uncore_pmu *tx2_pmu;
 788         void __iomem *base;
 789         struct resource res;
 790         struct resource_entry *rentry;
 791         struct list_head list;
 792         int ret;
 793
 794         INIT_LIST_HEAD(&list);
 795         ret = acpi_dev_get_resources(adev, &list, NULL, NULL);
 796         if (ret <= 0) {
 797                 dev_err(dev, "failed to parse _CRS method, error %d\n", ret);
 798                 return NULL;
 799         }
 800
 801         list_for_each_entry(rentry, &list, node) {
 802                 if (resource_type(rentry->res) == IORESOURCE_MEM) {
 803                         res = *rentry->res;
 804                         rentry = NULL;
 805                         break;
 806                 }
 807         }
 808         acpi_dev_free_resource_list(&list);
 809
 810         if (rentry) {
 811                 dev_err(dev, "PMU type %d: Fail to find resource\n", type);
 812                 return NULL;
 813         }
 814
 815         base = devm_ioremap_resource(dev, &res);
 816         if (IS_ERR(base))
 817                 return NULL;
 818
 819         tx2_pmu = devm_kzalloc(dev, sizeof(*tx2_pmu), GFP_KERNEL);
 820         if (!tx2_pmu)
 821                 return NULL;
 822
 823         tx2_pmu->dev = dev;
 824         tx2_pmu->type = type;
 825         tx2_pmu->base = base;
 826         tx2_pmu->node = dev_to_node(dev);
 827         INIT_LIST_HEAD(&tx2_pmu->entry);
 828
 829         switch (tx2_pmu->type) {
 830         case PMU_TYPE_L3C:
 831                 tx2_pmu->max_counters = TX2_PMU_DMC_L3C_MAX_COUNTERS;
 832                 tx2_pmu->counters_mask = 0x3;
 833                 tx2_pmu->prorate_factor = TX2_PMU_L3_TILES;
 834                 tx2_pmu->max_events = L3_EVENT_MAX;
 835                 tx2_pmu->events_mask = 0x1f;
 836                 tx2_pmu->hrtimer_interval = TX2_PMU_HRTIMER_INTERVAL;
 837                 tx2_pmu->hrtimer_callback = tx2_hrtimer_callback;
 838                 tx2_pmu->attr_groups = l3c_pmu_attr_groups;
 839                 tx2_pmu->name = devm_kasprintf(dev, GFP_KERNEL,
 840                                 "uncore_l3c_%d", tx2_pmu->node);
 841                 tx2_pmu->init_cntr_base = init_cntr_base_l3c;
 842                 tx2_pmu->start_event = uncore_start_event_l3c;
 843                 tx2_pmu->stop_event = uncore_stop_event_l3c;
 844                 break;
 845         case PMU_TYPE_DMC:
 846                 tx2_pmu->max_counters = TX2_PMU_DMC_L3C_MAX_COUNTERS;
 847                 tx2_pmu->counters_mask = 0x3;
 848                 tx2_pmu->prorate_factor = TX2_PMU_DMC_CHANNELS;
 849                 tx2_pmu->max_events = DMC_EVENT_MAX;
 850                 tx2_pmu->events_mask = 0x1f;
 851                 tx2_pmu->hrtimer_interval = TX2_PMU_HRTIMER_INTERVAL;
 852                 tx2_pmu->hrtimer_callback = tx2_hrtimer_callback;
 853                 tx2_pmu->attr_groups = dmc_pmu_attr_groups;
 854                 tx2_pmu->name = devm_kasprintf(dev, GFP_KERNEL,
 855                                 "uncore_dmc_%d", tx2_pmu->node);
 856                 tx2_pmu->init_cntr_base = init_cntr_base_dmc;
 857                 tx2_pmu->start_event = uncore_start_event_dmc;
 858                 tx2_pmu->stop_event = uncore_stop_event_dmc;
 859                 break;
 860         case PMU_TYPE_CCPI2:
 861                 /* CCPI2 has 8 counters */
 862                 tx2_pmu->max_counters = TX2_PMU_CCPI2_MAX_COUNTERS;
 863                 tx2_pmu->counters_mask = 0x7;
 864                 tx2_pmu->prorate_factor = 1;
 865                 tx2_pmu->max_events = CCPI2_EVENT_MAX;
 866                 tx2_pmu->events_mask = 0x1ff;
 867                 tx2_pmu->attr_groups = ccpi2_pmu_attr_groups;
 868                 tx2_pmu->name = devm_kasprintf(dev, GFP_KERNEL,
 869                                 "uncore_ccpi2_%d", tx2_pmu->node);
 870                 tx2_pmu->init_cntr_base = init_cntr_base_ccpi2;
 871                 tx2_pmu->start_event = uncore_start_event_ccpi2;
 872                 tx2_pmu->stop_event = uncore_stop_event_ccpi2;
 873                 tx2_pmu->hrtimer_callback = NULL;
 874                 break;
 875         case PMU_TYPE_INVALID:
 876                 devm_kfree(dev, tx2_pmu);
 877                 return NULL;
 878         }
 879
 880         return tx2_pmu;
 881 }
 882
 883 static acpi_status tx2_uncore_pmu_add(acpi_handle handle, u32 level,
 884                                     void *data, void **return_value)
 885 {
 886         struct acpi_device *adev = acpi_fetch_acpi_dev(handle);
 887         struct tx2_uncore_pmu *tx2_pmu;
 888         enum tx2_uncore_type type;
 889
 890         if (!adev || acpi_bus_get_status(adev) || !adev->status.present)
 891                 return AE_OK;
 892
 893         type = get_tx2_pmu_type(adev);
 894         if (type == PMU_TYPE_INVALID)
 895                 return AE_OK;
 896
 897         tx2_pmu = tx2_uncore_pmu_init_dev((struct device *)data,
 898                         handle, adev, type);
 899
 900         if (!tx2_pmu)
 901                 return AE_ERROR;
 902
 903         if (tx2_uncore_pmu_add_dev(tx2_pmu)) {
 904                 /* Can't add the PMU device, abort */
 905                 return AE_ERROR;
 906         }
 907         return AE_OK;
 908 }
 909
 910 static int tx2_uncore_pmu_online_cpu(unsigned int cpu,
 911                 struct hlist_node *hpnode)
 912 {
 913         struct tx2_uncore_pmu *tx2_pmu;
 914
 915         tx2_pmu = hlist_entry_safe(hpnode,
 916                         struct tx2_uncore_pmu, hpnode);
 917
 918         /* Pick this CPU, If there is no CPU/PMU association and both are
 919          * from same node.
 920          */
 921         if ((tx2_pmu->cpu >= nr_cpu_ids) &&
 922                 (tx2_pmu->node == cpu_to_node(cpu)))
 923                 tx2_pmu->cpu = cpu;
 924
 925         return 0;
 926 }
 927
 928 static int tx2_uncore_pmu_offline_cpu(unsigned int cpu,
 929                 struct hlist_node *hpnode)
 930 {
 931         struct tx2_uncore_pmu *tx2_pmu;
 932         unsigned int new_cpu;
 933
 934         tx2_pmu = hlist_entry_safe(hpnode,
 935                         struct tx2_uncore_pmu, hpnode);
 936
 937         if (cpu != tx2_pmu->cpu)
 938                 return 0;
 939
 940         if (tx2_pmu->hrtimer_callback)
 941                 hrtimer_cancel(&tx2_pmu->hrtimer);
 942
 943         new_cpu = cpumask_any_and_but(cpumask_of_node(tx2_pmu->node),
 944                                       cpu_online_mask, cpu);
 945
 946         tx2_pmu->cpu = new_cpu;
 947         if (new_cpu >= nr_cpu_ids)
 948                 return 0;
 949         perf_pmu_migrate_context(&tx2_pmu->pmu, cpu, new_cpu);
 950
 951         return 0;
 952 }
 953
 954 static const struct acpi_device_id tx2_uncore_acpi_match[] = {
 955         {"CAV901C", 0},
 956         {},
 957 };
 958 MODULE_DEVICE_TABLE(acpi, tx2_uncore_acpi_match);
 959
 960 static int tx2_uncore_probe(struct platform_device *pdev)
 961 {
 962         struct device *dev = &pdev->dev;
 963         acpi_handle handle;
 964         acpi_status status;
 965
 966         set_dev_node(dev, acpi_get_node(ACPI_HANDLE(dev)));
 967
 968         if (!has_acpi_companion(dev))
 969                 return -ENODEV;
 970
 971         handle = ACPI_HANDLE(dev);
 972         if (!handle)
 973                 return -EINVAL;
 974
 975         /* Walk through the tree for all PMU UNCORE devices */
 976         status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
 977                                      tx2_uncore_pmu_add,
 978                                      NULL, dev, NULL);
 979         if (ACPI_FAILURE(status)) {
 980                 dev_err(dev, "failed to probe PMU devices\n");
 981                 return_ACPI_STATUS(status);
 982         }
 983
 984         dev_info(dev, "node%d: pmu uncore registered\n", dev_to_node(dev));
 985         return 0;
 986 }
 987
 988 static void tx2_uncore_remove(struct platform_device *pdev)
 989 {
 990         struct tx2_uncore_pmu *tx2_pmu, *temp;
 991         struct device *dev = &pdev->dev;
 992
 993         if (!list_empty(&tx2_pmus)) {
 994                 list_for_each_entry_safe(tx2_pmu, temp, &tx2_pmus, entry) {
 995                         if (tx2_pmu->node == dev_to_node(dev)) {
 996                                 cpuhp_state_remove_instance_nocalls(
 997                                         CPUHP_AP_PERF_ARM_CAVIUM_TX2_UNCORE_ONLINE,
 998                                         &tx2_pmu->hpnode);
 999                                 perf_pmu_unregister(&tx2_pmu->pmu);
1000                                 list_del(&tx2_pmu->entry);
1001                         }
1002                 }
1003         }
1004 }
1005
1006 static struct platform_driver tx2_uncore_driver = {
1007         .driver = {
1008                 .name           = "tx2-uncore-pmu",
1009                 .acpi_match_table = ACPI_PTR(tx2_uncore_acpi_match),
1010                 .suppress_bind_attrs = true,
1011         },
1012         .probe = tx2_uncore_probe,
1013         .remove = tx2_uncore_remove,
1014 };
1015
1016 static int __init tx2_uncore_driver_init(void)
1017 {
1018         int ret;
1019
1020         ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_CAVIUM_TX2_UNCORE_ONLINE,
1021                                       "perf/tx2/uncore:online",
1022                                       tx2_uncore_pmu_online_cpu,
1023                                       tx2_uncore_pmu_offline_cpu);
1024         if (ret) {
1025                 pr_err("TX2 PMU: setup hotplug failed(%d)\n", ret);
1026                 return ret;
1027         }
1028         ret = platform_driver_register(&tx2_uncore_driver);
1029         if (ret)
1030                 cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CAVIUM_TX2_UNCORE_ONLINE);
1031
1032         return ret;
1033 }
1034 module_init(tx2_uncore_driver_init);
1035
1036 static void __exit tx2_uncore_driver_exit(void)
1037 {
1038         platform_driver_unregister(&tx2_uncore_driver);
1039         cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CAVIUM_TX2_UNCORE_ONLINE);
1040 }
1041 module_exit(tx2_uncore_driver_exit);
1042
1043 MODULE_DESCRIPTION("ThunderX2 UNCORE PMU driver");
1044 MODULE_LICENSE("GPL v2");
1045 MODULE_AUTHOR("Ganapatrao Kulkarni <gkulkarni@cavium.com>");