drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014 MediaTek Inc.
   4  * Author: Jie Qiu <jie.qiu@mediatek.com>
   5  */
   6
   7 #include "phy-mtk-hdmi.h"
   8 #include "phy-mtk-io.h"
   9
  10 #define HDMI_CON0               0x00
  11 #define RG_HDMITX_PLL_EN                BIT(31)
  12 #define RG_HDMITX_PLL_FBKDIV            GENMASK(30, 24)
  13 #define RG_HDMITX_PLL_FBKSEL            GENMASK(23, 22)
  14 #define RG_HDMITX_PLL_PREDIV            GENMASK(21, 20)
  15 #define RG_HDMITX_PLL_POSDIV            GENMASK(19, 18)
  16 #define RG_HDMITX_PLL_RST_DLY           GENMASK(17, 16)
  17 #define RG_HDMITX_PLL_IR                GENMASK(15, 12)
  18 #define RG_HDMITX_PLL_IC                GENMASK(11, 8)
  19 #define RG_HDMITX_PLL_BP                GENMASK(7, 4)
  20 #define RG_HDMITX_PLL_BR                GENMASK(3, 2)
  21 #define RG_HDMITX_PLL_BC                GENMASK(1, 0)
  22 #define HDMI_CON1               0x04
  23 #define RG_HDMITX_PLL_DIVEN             GENMASK(31, 29)
  24 #define RG_HDMITX_PLL_AUTOK_EN          BIT(28)
  25 #define RG_HDMITX_PLL_AUTOK_KF          GENMASK(27, 26)
  26 #define RG_HDMITX_PLL_AUTOK_KS          GENMASK(25, 24)
  27 #define RG_HDMITX_PLL_AUTOK_LOAD        BIT(23)
  28 #define RG_HDMITX_PLL_BAND              GENMASK(21, 16)
  29 #define RG_HDMITX_PLL_REF_SEL           BIT(15)
  30 #define RG_HDMITX_PLL_BIAS_EN           BIT(14)
  31 #define RG_HDMITX_PLL_BIAS_LPF_EN       BIT(13)
  32 #define RG_HDMITX_PLL_TXDIV_EN          BIT(12)
  33 #define RG_HDMITX_PLL_TXDIV             GENMASK(11, 10)
  34 #define RG_HDMITX_PLL_LVROD_EN          BIT(9)
  35 #define RG_HDMITX_PLL_MONVC_EN          BIT(8)
  36 #define RG_HDMITX_PLL_MONCK_EN          BIT(7)
  37 #define RG_HDMITX_PLL_MONREF_EN         BIT(6)
  38 #define RG_HDMITX_PLL_TST_EN            BIT(5)
  39 #define RG_HDMITX_PLL_TST_CK_EN         BIT(4)
  40 #define RG_HDMITX_PLL_TST_SEL           GENMASK(3, 0)
  41 #define HDMI_CON2               0x08
  42 #define RGS_HDMITX_PLL_AUTOK_BAND       GENMASK(14, 8)
  43 #define RGS_HDMITX_PLL_AUTOK_FAIL       BIT(1)
  44 #define RG_HDMITX_EN_TX_CKLDO           BIT(0)
  45 #define HDMI_CON3               0x0c
  46 #define RG_HDMITX_SER_EN                GENMASK(31, 28)
  47 #define RG_HDMITX_PRD_EN                GENMASK(27, 24)
  48 #define RG_HDMITX_PRD_IMP_EN            GENMASK(23, 20)
  49 #define RG_HDMITX_DRV_EN                GENMASK(19, 16)
  50 #define RG_HDMITX_DRV_IMP_EN            GENMASK(15, 12)
  51 #define RG_HDMITX_MHLCK_FORCE           BIT(10)
  52 #define RG_HDMITX_MHLCK_PPIX_EN         BIT(9)
  53 #define RG_HDMITX_MHLCK_EN              BIT(8)
  54 #define RG_HDMITX_SER_DIN_SEL           GENMASK(7, 4)
  55 #define RG_HDMITX_SER_5T1_BIST_EN       BIT(3)
  56 #define RG_HDMITX_SER_BIST_TOG          BIT(2)
  57 #define RG_HDMITX_SER_DIN_TOG           BIT(1)
  58 #define RG_HDMITX_SER_CLKDIG_INV        BIT(0)
  59 #define HDMI_CON4               0x10
  60 #define RG_HDMITX_PRD_IBIAS_CLK         GENMASK(27, 24)
  61 #define RG_HDMITX_PRD_IBIAS_D2          GENMASK(19, 16)
  62 #define RG_HDMITX_PRD_IBIAS_D1          GENMASK(11, 8)
  63 #define RG_HDMITX_PRD_IBIAS_D0          GENMASK(3, 0)
  64 #define HDMI_CON5               0x14
  65 #define RG_HDMITX_DRV_IBIAS_CLK         GENMASK(29, 24)
  66 #define RG_HDMITX_DRV_IBIAS_D2          GENMASK(21, 16)
  67 #define RG_HDMITX_DRV_IBIAS_D1          GENMASK(13, 8)
  68 #define RG_HDMITX_DRV_IBIAS_D0          GENMASK(5, 0)
  69 #define HDMI_CON6               0x18
  70 #define RG_HDMITX_DRV_IMP_CLK           GENMASK(29, 24)
  71 #define RG_HDMITX_DRV_IMP_D2            GENMASK(21, 16)
  72 #define RG_HDMITX_DRV_IMP_D1            GENMASK(13, 8)
  73 #define RG_HDMITX_DRV_IMP_D0            GENMASK(5, 0)
  74 #define HDMI_CON7               0x1c
  75 #define RG_HDMITX_MHLCK_DRV_IBIAS       GENMASK(31, 27)
  76 #define RG_HDMITX_SER_DIN               GENMASK(25, 16)
  77 #define RG_HDMITX_CHLDC_TST             GENMASK(15, 12)
  78 #define RG_HDMITX_CHLCK_TST             GENMASK(11, 8)
  79 #define RG_HDMITX_RESERVE               GENMASK(7, 0)
  80 #define HDMI_CON8               0x20
  81 #define RGS_HDMITX_2T1_LEV              GENMASK(19, 16)
  82 #define RGS_HDMITX_2T1_EDG              GENMASK(15, 12)
  83 #define RGS_HDMITX_5T1_LEV              GENMASK(11, 8)
  84 #define RGS_HDMITX_5T1_EDG              GENMASK(7, 4)
  85 #define RGS_HDMITX_PLUG_TST             BIT(0)
  86
  87 static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
  88 {
  89         struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
  90         void __iomem *base = hdmi_phy->regs;
  91
  92         mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
  93         mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV);
  94         mtk_phy_clear_bits(base + HDMI_CON3, RG_HDMITX_MHLCK_EN);
  95         mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
  96         usleep_range(100, 150);
  97         mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_EN);
  98         usleep_range(100, 150);
  99         mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
 100         mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
 101
 102         return 0;
 103 }
 104
 105 static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
 106 {
 107         struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
 108         void __iomem *base = hdmi_phy->regs;
 109
 110         mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
 111         mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
 112         usleep_range(100, 150);
 113         mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_PLL_EN);
 114         usleep_range(100, 150);
 115         mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
 116         mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV);
 117         mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
 118         usleep_range(100, 150);
 119 }
 120
 121 static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 122                                     unsigned long *parent_rate)
 123 {
 124         struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
 125
 126         hdmi_phy->pll_rate = rate;
 127         if (rate <= 74250000)
 128                 *parent_rate = rate;
 129         else
 130                 *parent_rate = rate / 2;
 131
 132         return rate;
 133 }
 134
 135 static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 136                                  unsigned long parent_rate)
 137 {
 138         struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
 139         void __iomem *base = hdmi_phy->regs;
 140         unsigned int pre_div;
 141         unsigned int div;
 142         unsigned int pre_ibias;
 143         unsigned int hdmi_ibias;
 144         unsigned int imp_en;
 145
 146         dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__,
 147                 rate, parent_rate);
 148
 149         if (rate <= 27000000) {
 150                 pre_div = 0;
 151                 div = 3;
 152         } else if (rate <= 74250000) {
 153                 pre_div = 1;
 154                 div = 2;
 155         } else {
 156                 pre_div = 1;
 157                 div = 1;
 158         }
 159
 160         mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_PLL_PREDIV, pre_div);
 161         mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV);
 162         mtk_phy_update_bits(base + HDMI_CON0,
 163                             RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR,
 164                             FIELD_PREP(RG_HDMITX_PLL_IC, 0x1) |
 165                             FIELD_PREP(RG_HDMITX_PLL_IR, 0x1));
 166         mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV, div);
 167         mtk_phy_update_bits(base + HDMI_CON0,
 168                             RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV,
 169                             FIELD_PREP(RG_HDMITX_PLL_FBKSEL, 0x1) |
 170                             FIELD_PREP(RG_HDMITX_PLL_FBKDIV, 19));
 171         mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PLL_DIVEN, 0x2);
 172         mtk_phy_update_bits(base + HDMI_CON0,
 173                             RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
 174                             RG_HDMITX_PLL_BR,
 175                             FIELD_PREP(RG_HDMITX_PLL_BP, 0xc) |
 176                             FIELD_PREP(RG_HDMITX_PLL_BC, 0x2) |
 177                             FIELD_PREP(RG_HDMITX_PLL_BR, 0x1));
 178         if (rate < 165000000) {
 179                 mtk_phy_clear_bits(base + HDMI_CON3, RG_HDMITX_PRD_IMP_EN);
 180                 pre_ibias = 0x3;
 181                 imp_en = 0x0;
 182                 hdmi_ibias = hdmi_phy->ibias;
 183         } else {
 184                 mtk_phy_set_bits(base + HDMI_CON3, RG_HDMITX_PRD_IMP_EN);
 185                 pre_ibias = 0x6;
 186                 imp_en = 0xf;
 187                 hdmi_ibias = hdmi_phy->ibias_up;
 188         }
 189         mtk_phy_update_bits(base + HDMI_CON4,
 190                             RG_HDMITX_PRD_IBIAS_CLK | RG_HDMITX_PRD_IBIAS_D2 |
 191                             RG_HDMITX_PRD_IBIAS_D1 | RG_HDMITX_PRD_IBIAS_D0,
 192                             FIELD_PREP(RG_HDMITX_PRD_IBIAS_CLK, pre_ibias) |
 193                             FIELD_PREP(RG_HDMITX_PRD_IBIAS_D2, pre_ibias) |
 194                             FIELD_PREP(RG_HDMITX_PRD_IBIAS_D1, pre_ibias) |
 195                             FIELD_PREP(RG_HDMITX_PRD_IBIAS_D0, pre_ibias));
 196         mtk_phy_update_field(base + HDMI_CON3, RG_HDMITX_DRV_IMP_EN, imp_en);
 197         mtk_phy_update_bits(base + HDMI_CON6,
 198                             RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
 199                             RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0,
 200                             FIELD_PREP(RG_HDMITX_DRV_IMP_CLK, hdmi_phy->drv_imp_clk) |
 201                             FIELD_PREP(RG_HDMITX_DRV_IMP_D2, hdmi_phy->drv_imp_d2) |
 202                             FIELD_PREP(RG_HDMITX_DRV_IMP_D1, hdmi_phy->drv_imp_d1) |
 203                             FIELD_PREP(RG_HDMITX_DRV_IMP_D0, hdmi_phy->drv_imp_d0));
 204         mtk_phy_update_bits(base + HDMI_CON5,
 205                             RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 |
 206                             RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0,
 207                             FIELD_PREP(RG_HDMITX_DRV_IBIAS_CLK, hdmi_ibias) |
 208                             FIELD_PREP(RG_HDMITX_DRV_IBIAS_D2, hdmi_ibias) |
 209                             FIELD_PREP(RG_HDMITX_DRV_IBIAS_D1, hdmi_ibias) |
 210                             FIELD_PREP(RG_HDMITX_DRV_IBIAS_D0, hdmi_ibias));
 211         return 0;
 212 }
 213
 214 static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
 215                                               unsigned long parent_rate)
 216 {
 217         struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
 218
 219         return hdmi_phy->pll_rate;
 220 }
 221
 222 static const struct clk_ops mtk_hdmi_phy_pll_ops = {
 223         .prepare = mtk_hdmi_pll_prepare,
 224         .unprepare = mtk_hdmi_pll_unprepare,
 225         .set_rate = mtk_hdmi_pll_set_rate,
 226         .round_rate = mtk_hdmi_pll_round_rate,
 227         .recalc_rate = mtk_hdmi_pll_recalc_rate,
 228 };
 229
 230 static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
 231 {
 232         mtk_phy_set_bits(hdmi_phy->regs + HDMI_CON3,
 233                          RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN |
 234                          RG_HDMITX_DRV_EN);
 235         usleep_range(100, 150);
 236 }
 237
 238 static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
 239 {
 240         mtk_phy_clear_bits(hdmi_phy->regs + HDMI_CON3,
 241                            RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN |
 242                            RG_HDMITX_SER_EN);
 243 }
 244
 245 struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {
 246         .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
 247         .hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
 248         .hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds,
 249         .hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds,
 250 };
 251
 252 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
 253 MODULE_DESCRIPTION("MediaTek MT8173 HDMI PHY Driver");
 254 MODULE_LICENSE("GPL v2");