drivers/phy/microchip/sparx5_serdes_regs.h

   1 /* SPDX-License-Identifier: GPL-2.0+
   2  * Microchip Sparx5 SerDes driver
   3  *
   4  * Copyright (c) 2024 Microchip Technology Inc.
   5  */
   6
   7 /* This file is autogenerated by cml-utils 2023-04-13 15:02:00 +0200.
   8  * Commit ID: 5ac560288d46048f872ecdb8add53717f1efc0e1
   9  */
  10
  11 #ifndef _SPARX5_SERDES_REGS_H_
  12 #define _SPARX5_SERDES_REGS_H_
  13
  14 #include <linux/bitfield.h>
  15 #include <linux/types.h>
  16 #include <linux/bug.h>
  17
  18 enum sparx5_serdes_target {
  19         TARGET_SD10G_LANE = 200,
  20         TARGET_SD25G_LANE = 212,
  21         TARGET_SD6G_LANE = 233,
  22         TARGET_SD_CMU = 248,
  23         TARGET_SD_CMU_CFG = 262,
  24         TARGET_SD_LANE = 276,
  25         TARGET_SD_LANE_25G = 301,
  26         NUM_TARGETS = 332
  27 };
  28
  29 enum sparx5_serdes_tsize_enum {
  30         TC_SD10G_LANE,
  31         TC_SD_CMU,
  32         TC_SD_CMU_CFG,
  33         TC_SD_LANE,
  34         TSIZE_LAST,
  35 };
  36
  37 /* sparx5_serdes.c */
  38 extern const unsigned int *tsize;
  39
  40 #define TSIZE(o) tsize[o]
  41
  42 #define __REG(...)    __VA_ARGS__
  43
  44 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_01 */
  45 #define SD10G_LANE_LANE_01(t)                                                  \
  46         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 4, 0,  \
  47               1, 4)
  48
  49 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0)
  50 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\
  51         FIELD_PREP(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
  52 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\
  53         FIELD_GET(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
  54
  55 #define SD10G_LANE_LANE_01_CFG_RXDET_EN          BIT(4)
  56 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_SET(x)\
  57         FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
  58 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_GET(x)\
  59         FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
  60
  61 #define SD10G_LANE_LANE_01_CFG_RXDET_STR         BIT(5)
  62 #define SD10G_LANE_LANE_01_CFG_RXDET_STR_SET(x)\
  63         FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)
  64 #define SD10G_LANE_LANE_01_CFG_RXDET_STR_GET(x)\
  65         FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)
  66
  67 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_02 */
  68 #define SD10G_LANE_LANE_02(t)                                                  \
  69         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 8, 0,  \
  70               1, 4)
  71
  72 #define SD10G_LANE_LANE_02_CFG_EN_ADV            BIT(0)
  73 #define SD10G_LANE_LANE_02_CFG_EN_ADV_SET(x)\
  74         FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_ADV, x)
  75 #define SD10G_LANE_LANE_02_CFG_EN_ADV_GET(x)\
  76         FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_ADV, x)
  77
  78 #define SD10G_LANE_LANE_02_CFG_EN_MAIN           BIT(1)
  79 #define SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(x)\
  80         FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)
  81 #define SD10G_LANE_LANE_02_CFG_EN_MAIN_GET(x)\
  82         FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)
  83
  84 #define SD10G_LANE_LANE_02_CFG_EN_DLY            BIT(2)
  85 #define SD10G_LANE_LANE_02_CFG_EN_DLY_SET(x)\
  86         FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY, x)
  87 #define SD10G_LANE_LANE_02_CFG_EN_DLY_GET(x)\
  88         FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY, x)
  89
  90 #define SD10G_LANE_LANE_02_CFG_EN_DLY2           BIT(3)
  91 #define SD10G_LANE_LANE_02_CFG_EN_DLY2_SET(x)\
  92         FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)
  93 #define SD10G_LANE_LANE_02_CFG_EN_DLY2_GET(x)\
  94         FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)
  95
  96 #define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0       GENMASK(7, 4)
  97 #define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_SET(x)\
  98         FIELD_PREP(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)
  99 #define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_GET(x)\
 100         FIELD_GET(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)
 101
 102 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_03 */
 103 #define SD10G_LANE_LANE_03(t)                                                  \
 104         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 12, 0, \
 105               1, 4)
 106
 107 #define SD10G_LANE_LANE_03_CFG_TAP_MAIN          BIT(0)
 108 #define SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(x)\
 109         FIELD_PREP(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x)
 110 #define SD10G_LANE_LANE_03_CFG_TAP_MAIN_GET(x)\
 111         FIELD_GET(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x)
 112
 113 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_04 */
 114 #define SD10G_LANE_LANE_04(t)                                                  \
 115         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 16, 0, \
 116               1, 4)
 117
 118 #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0       GENMASK(4, 0)
 119 #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET(x)\
 120         FIELD_PREP(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x)
 121 #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_GET(x)\
 122         FIELD_GET(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x)
 123
 124 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_06 */
 125 #define SD10G_LANE_LANE_06(t)                                                  \
 126         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 24, 0, \
 127               1, 4)
 128
 129 #define SD10G_LANE_LANE_06_CFG_PD_DRIVER         BIT(0)
 130 #define SD10G_LANE_LANE_06_CFG_PD_DRIVER_SET(x)\
 131         FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_DRIVER, x)
 132 #define SD10G_LANE_LANE_06_CFG_PD_DRIVER_GET(x)\
 133         FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_DRIVER, x)
 134
 135 #define SD10G_LANE_LANE_06_CFG_PD_CLK            BIT(1)
 136 #define SD10G_LANE_LANE_06_CFG_PD_CLK_SET(x)\
 137         FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_CLK, x)
 138 #define SD10G_LANE_LANE_06_CFG_PD_CLK_GET(x)\
 139         FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_CLK, x)
 140
 141 #define SD10G_LANE_LANE_06_CFG_PD_CML            BIT(2)
 142 #define SD10G_LANE_LANE_06_CFG_PD_CML_SET(x)\
 143         FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_CML, x)
 144 #define SD10G_LANE_LANE_06_CFG_PD_CML_GET(x)\
 145         FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_CML, x)
 146
 147 #define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN       BIT(3)
 148 #define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_SET(x)\
 149         FIELD_PREP(SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, x)
 150 #define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_GET(x)\
 151         FIELD_GET(SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, x)
 152
 153 #define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN       BIT(4)
 154 #define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_SET(x)\
 155         FIELD_PREP(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN, x)
 156 #define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_GET(x)\
 157         FIELD_GET(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN, x)
 158
 159 #define SD10G_LANE_LANE_06_CFG_EN_PREEMPH        BIT(5)
 160 #define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_SET(x)\
 161         FIELD_PREP(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x)
 162 #define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_GET(x)\
 163         FIELD_GET(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x)
 164
 165 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0B */
 166 #define SD10G_LANE_LANE_0B(t)                                                  \
 167         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 44, 0, \
 168               1, 4)
 169
 170 #define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0        GENMASK(3, 0)
 171 #define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET(x)\
 172         FIELD_PREP(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, x)
 173 #define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_GET(x)\
 174         FIELD_GET(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, x)
 175
 176 #define SD10G_LANE_LANE_0B_CFG_PD_CTLE           BIT(4)
 177 #define SD10G_LANE_LANE_0B_CFG_PD_CTLE_SET(x)\
 178         FIELD_PREP(SD10G_LANE_LANE_0B_CFG_PD_CTLE, x)
 179 #define SD10G_LANE_LANE_0B_CFG_PD_CTLE_GET(x)\
 180         FIELD_GET(SD10G_LANE_LANE_0B_CFG_PD_CTLE, x)
 181
 182 #define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN        BIT(5)
 183 #define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_SET(x)\
 184         FIELD_PREP(SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN, x)
 185 #define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_GET(x)\
 186         FIELD_GET(SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN, x)
 187
 188 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE  BIT(6)
 189 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET(x)\
 190         FIELD_PREP(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, x)
 191 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_GET(x)\
 192         FIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, x)
 193
 194 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ   BIT(7)
 195 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_SET(x)\
 196         FIELD_PREP(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x)
 197 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_GET(x)\
 198         FIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x)
 199
 200 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0C */
 201 #define SD10G_LANE_LANE_0C(t)                                                  \
 202         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 48, 0, \
 203               1, 4)
 204
 205 #define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE         BIT(0)
 206 #define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET(x)\
 207         FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE, x)
 208 #define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_GET(x)\
 209         FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE, x)
 210
 211 #define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ          BIT(1)
 212 #define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_SET(x)\
 213         FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSCAL_SQ, x)
 214 #define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_GET(x)\
 215         FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSCAL_SQ, x)
 216
 217 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE      BIT(2)
 218 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_SET(x)\
 219         FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE, x)
 220 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_GET(x)\
 221         FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE, x)
 222
 223 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ       BIT(3)
 224 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_SET(x)\
 225         FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ, x)
 226 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_GET(x)\
 227         FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ, x)
 228
 229 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE      BIT(4)
 230 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_SET(x)\
 231         FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, x)
 232 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_GET(x)\
 233         FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, x)
 234
 235 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ       BIT(5)
 236 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_SET(x)\
 237         FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ, x)
 238 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_GET(x)\
 239         FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ, x)
 240
 241 #define SD10G_LANE_LANE_0C_CFG_PD_RX_LS          BIT(6)
 242 #define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_SET(x)\
 243         FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_RX_LS, x)
 244 #define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_GET(x)\
 245         FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_RX_LS, x)
 246
 247 #define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12     BIT(7)
 248 #define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_SET(x)\
 249         FIELD_PREP(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x)
 250 #define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_GET(x)\
 251         FIELD_GET(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x)
 252
 253 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0D */
 254 #define SD10G_LANE_LANE_0D(t)                                                  \
 255         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 52, 0, \
 256               1, 4)
 257
 258 #define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0    GENMASK(1, 0)
 259 #define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_SET(x)\
 260         FIELD_PREP(SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0, x)
 261 #define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_GET(x)\
 262         FIELD_GET(SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0, x)
 263
 264 #define SD10G_LANE_LANE_0D_CFG_EQR_BYP           BIT(4)
 265 #define SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(x)\
 266         FIELD_PREP(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x)
 267 #define SD10G_LANE_LANE_0D_CFG_EQR_BYP_GET(x)\
 268         FIELD_GET(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x)
 269
 270 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0E */
 271 #define SD10G_LANE_LANE_0E(t)                                                  \
 272         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 56, 0, \
 273               1, 4)
 274
 275 #define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0     GENMASK(3, 0)
 276 #define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET(x)\
 277         FIELD_PREP(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0, x)
 278 #define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_GET(x)\
 279         FIELD_GET(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0, x)
 280
 281 #define SD10G_LANE_LANE_0E_CFG_RXLB_EN           BIT(4)
 282 #define SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(x)\
 283         FIELD_PREP(SD10G_LANE_LANE_0E_CFG_RXLB_EN, x)
 284 #define SD10G_LANE_LANE_0E_CFG_RXLB_EN_GET(x)\
 285         FIELD_GET(SD10G_LANE_LANE_0E_CFG_RXLB_EN, x)
 286
 287 #define SD10G_LANE_LANE_0E_CFG_TXLB_EN           BIT(5)
 288 #define SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(x)\
 289         FIELD_PREP(SD10G_LANE_LANE_0E_CFG_TXLB_EN, x)
 290 #define SD10G_LANE_LANE_0E_CFG_TXLB_EN_GET(x)\
 291         FIELD_GET(SD10G_LANE_LANE_0E_CFG_TXLB_EN, x)
 292
 293 #define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN      BIT(6)
 294 #define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_SET(x)\
 295         FIELD_PREP(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x)
 296 #define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_GET(x)\
 297         FIELD_GET(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x)
 298
 299 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0F */
 300 #define SD10G_LANE_LANE_0F(t)                                                  \
 301         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 60, 0, \
 302               1, 4)
 303
 304 #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0      GENMASK(7, 0)
 305 #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET(x)\
 306         FIELD_PREP(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x)
 307 #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_GET(x)\
 308         FIELD_GET(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x)
 309
 310 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_13 */
 311 #define SD10G_LANE_LANE_13(t)                                                  \
 312         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 76, 0, \
 313               1, 4)
 314
 315 #define SD10G_LANE_LANE_13_CFG_DCDR_PD           BIT(0)
 316 #define SD10G_LANE_LANE_13_CFG_DCDR_PD_SET(x)\
 317         FIELD_PREP(SD10G_LANE_LANE_13_CFG_DCDR_PD, x)
 318 #define SD10G_LANE_LANE_13_CFG_DCDR_PD_GET(x)\
 319         FIELD_GET(SD10G_LANE_LANE_13_CFG_DCDR_PD, x)
 320
 321 #define SD10G_LANE_LANE_13_CFG_PHID_1T           BIT(1)
 322 #define SD10G_LANE_LANE_13_CFG_PHID_1T_SET(x)\
 323         FIELD_PREP(SD10G_LANE_LANE_13_CFG_PHID_1T, x)
 324 #define SD10G_LANE_LANE_13_CFG_PHID_1T_GET(x)\
 325         FIELD_GET(SD10G_LANE_LANE_13_CFG_PHID_1T, x)
 326
 327 #define SD10G_LANE_LANE_13_CFG_CDRCK_EN          BIT(2)
 328 #define SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(x)\
 329         FIELD_PREP(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x)
 330 #define SD10G_LANE_LANE_13_CFG_CDRCK_EN_GET(x)\
 331         FIELD_GET(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x)
 332
 333 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_14 */
 334 #define SD10G_LANE_LANE_14(t)                                                  \
 335         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 80, 0, \
 336               1, 4)
 337
 338 #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0    GENMASK(7, 0)
 339 #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET(x)\
 340         FIELD_PREP(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x)
 341 #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_GET(x)\
 342         FIELD_GET(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x)
 343
 344 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_15 */
 345 #define SD10G_LANE_LANE_15(t)                                                  \
 346         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 84, 0, \
 347               1, 4)
 348
 349 #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8   GENMASK(7, 0)
 350 #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET(x)\
 351         FIELD_PREP(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x)
 352 #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_GET(x)\
 353         FIELD_GET(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x)
 354
 355 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_16 */
 356 #define SD10G_LANE_LANE_16(t)                                                  \
 357         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 88, 0, \
 358               1, 4)
 359
 360 #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16  GENMASK(7, 0)
 361 #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET(x)\
 362         FIELD_PREP(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x)
 363 #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_GET(x)\
 364         FIELD_GET(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x)
 365
 366 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_1A */
 367 #define SD10G_LANE_LANE_1A(t)                                                  \
 368         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 104, 0,\
 369               1, 4)
 370
 371 #define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN      BIT(0)
 372 #define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_SET(x)\
 373         FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN, x)
 374 #define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_GET(x)\
 375         FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN, x)
 376
 377 #define SD10G_LANE_LANE_1A_CFG_PI_EN             BIT(1)
 378 #define SD10G_LANE_LANE_1A_CFG_PI_EN_SET(x)\
 379         FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_EN, x)
 380 #define SD10G_LANE_LANE_1A_CFG_PI_EN_GET(x)\
 381         FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_EN, x)
 382
 383 #define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN         BIT(2)
 384 #define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_SET(x)\
 385         FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, x)
 386 #define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_GET(x)\
 387         FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, x)
 388
 389 #define SD10G_LANE_LANE_1A_CFG_PI_STEPS          BIT(3)
 390 #define SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(x)\
 391         FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_STEPS, x)
 392 #define SD10G_LANE_LANE_1A_CFG_PI_STEPS_GET(x)\
 393         FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_STEPS, x)
 394
 395 #define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0 GENMASK(5, 4)
 396 #define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_SET(x)\
 397         FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x)
 398 #define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_GET(x)\
 399         FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x)
 400
 401 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_22 */
 402 #define SD10G_LANE_LANE_22(t)                                                  \
 403         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 136, 0,\
 404               1, 4)
 405
 406 #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1     GENMASK(4, 0)
 407 #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET(x)\
 408         FIELD_PREP(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x)
 409 #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_GET(x)\
 410         FIELD_GET(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x)
 411
 412 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_23 */
 413 #define SD10G_LANE_LANE_23(t)                                                  \
 414         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 140, 0,\
 415               1, 4)
 416
 417 #define SD10G_LANE_LANE_23_CFG_DFE_PD            BIT(0)
 418 #define SD10G_LANE_LANE_23_CFG_DFE_PD_SET(x)\
 419         FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFE_PD, x)
 420 #define SD10G_LANE_LANE_23_CFG_DFE_PD_GET(x)\
 421         FIELD_GET(SD10G_LANE_LANE_23_CFG_DFE_PD, x)
 422
 423 #define SD10G_LANE_LANE_23_CFG_EN_DFEDIG         BIT(1)
 424 #define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_SET(x)\
 425         FIELD_PREP(SD10G_LANE_LANE_23_CFG_EN_DFEDIG, x)
 426 #define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_GET(x)\
 427         FIELD_GET(SD10G_LANE_LANE_23_CFG_EN_DFEDIG, x)
 428
 429 #define SD10G_LANE_LANE_23_CFG_DFECK_EN          BIT(2)
 430 #define SD10G_LANE_LANE_23_CFG_DFECK_EN_SET(x)\
 431         FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFECK_EN, x)
 432 #define SD10G_LANE_LANE_23_CFG_DFECK_EN_GET(x)\
 433         FIELD_GET(SD10G_LANE_LANE_23_CFG_DFECK_EN, x)
 434
 435 #define SD10G_LANE_LANE_23_CFG_ERRAMP_PD         BIT(3)
 436 #define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_SET(x)\
 437         FIELD_PREP(SD10G_LANE_LANE_23_CFG_ERRAMP_PD, x)
 438 #define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_GET(x)\
 439         FIELD_GET(SD10G_LANE_LANE_23_CFG_ERRAMP_PD, x)
 440
 441 #define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0      GENMASK(6, 4)
 442 #define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_SET(x)\
 443         FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x)
 444 #define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_GET(x)\
 445         FIELD_GET(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x)
 446
 447 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_24 */
 448 #define SD10G_LANE_LANE_24(t)                                                  \
 449         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 144, 0,\
 450               1, 4)
 451
 452 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0    GENMASK(3, 0)
 453 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET(x)\
 454         FIELD_PREP(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, x)
 455 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_GET(x)\
 456         FIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, x)
 457
 458 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0    GENMASK(7, 4)
 459 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_SET(x)\
 460         FIELD_PREP(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x)
 461 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_GET(x)\
 462         FIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x)
 463
 464 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_26 */
 465 #define SD10G_LANE_LANE_26(t)                                                  \
 466         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 152, 0,\
 467               1, 4)
 468
 469 #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0 GENMASK(7, 0)
 470 #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET(x)\
 471         FIELD_PREP(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x)
 472 #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_GET(x)\
 473         FIELD_GET(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x)
 474
 475 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_2F */
 476 #define SD10G_LANE_LANE_2F(t)                                                  \
 477         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 188, 0,\
 478               1, 4)
 479
 480 #define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0        GENMASK(2, 0)
 481 #define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET(x)\
 482         FIELD_PREP(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, x)
 483 #define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_GET(x)\
 484         FIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, x)
 485
 486 #define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0      GENMASK(7, 4)
 487 #define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_SET(x)\
 488         FIELD_PREP(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x)
 489 #define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_GET(x)\
 490         FIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x)
 491
 492 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_30 */
 493 #define SD10G_LANE_LANE_30(t)                                                  \
 494         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 192, 0,\
 495               1, 4)
 496
 497 #define SD10G_LANE_LANE_30_CFG_SUMMER_EN         BIT(0)
 498 #define SD10G_LANE_LANE_30_CFG_SUMMER_EN_SET(x)\
 499         FIELD_PREP(SD10G_LANE_LANE_30_CFG_SUMMER_EN, x)
 500 #define SD10G_LANE_LANE_30_CFG_SUMMER_EN_GET(x)\
 501         FIELD_GET(SD10G_LANE_LANE_30_CFG_SUMMER_EN, x)
 502
 503 #define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0     GENMASK(6, 4)
 504 #define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_SET(x)\
 505         FIELD_PREP(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x)
 506 #define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_GET(x)\
 507         FIELD_GET(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x)
 508
 509 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_31 */
 510 #define SD10G_LANE_LANE_31(t)                                                  \
 511         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 196, 0,\
 512               1, 4)
 513
 514 #define SD10G_LANE_LANE_31_CFG_PI_RSTN           BIT(0)
 515 #define SD10G_LANE_LANE_31_CFG_PI_RSTN_SET(x)\
 516         FIELD_PREP(SD10G_LANE_LANE_31_CFG_PI_RSTN, x)
 517 #define SD10G_LANE_LANE_31_CFG_PI_RSTN_GET(x)\
 518         FIELD_GET(SD10G_LANE_LANE_31_CFG_PI_RSTN, x)
 519
 520 #define SD10G_LANE_LANE_31_CFG_CDR_RSTN          BIT(1)
 521 #define SD10G_LANE_LANE_31_CFG_CDR_RSTN_SET(x)\
 522         FIELD_PREP(SD10G_LANE_LANE_31_CFG_CDR_RSTN, x)
 523 #define SD10G_LANE_LANE_31_CFG_CDR_RSTN_GET(x)\
 524         FIELD_GET(SD10G_LANE_LANE_31_CFG_CDR_RSTN, x)
 525
 526 #define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG       BIT(2)
 527 #define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_SET(x)\
 528         FIELD_PREP(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, x)
 529 #define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_GET(x)\
 530         FIELD_GET(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, x)
 531
 532 #define SD10G_LANE_LANE_31_CFG_CTLE_RSTN         BIT(3)
 533 #define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_SET(x)\
 534         FIELD_PREP(SD10G_LANE_LANE_31_CFG_CTLE_RSTN, x)
 535 #define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_GET(x)\
 536         FIELD_GET(SD10G_LANE_LANE_31_CFG_CTLE_RSTN, x)
 537
 538 #define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8       BIT(4)
 539 #define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_SET(x)\
 540         FIELD_PREP(SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8, x)
 541 #define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_GET(x)\
 542         FIELD_GET(SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8, x)
 543
 544 #define SD10G_LANE_LANE_31_CFG_R50_EN            BIT(5)
 545 #define SD10G_LANE_LANE_31_CFG_R50_EN_SET(x)\
 546         FIELD_PREP(SD10G_LANE_LANE_31_CFG_R50_EN, x)
 547 #define SD10G_LANE_LANE_31_CFG_R50_EN_GET(x)\
 548         FIELD_GET(SD10G_LANE_LANE_31_CFG_R50_EN, x)
 549
 550 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_32 */
 551 #define SD10G_LANE_LANE_32(t)                                                  \
 552         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 200, 0,\
 553               1, 4)
 554
 555 #define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0 GENMASK(1, 0)
 556 #define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_SET(x)\
 557         FIELD_PREP(SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0, x)
 558 #define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_GET(x)\
 559         FIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0, x)
 560
 561 #define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0 GENMASK(5, 4)
 562 #define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_SET(x)\
 563         FIELD_PREP(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x)
 564 #define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_GET(x)\
 565         FIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x)
 566
 567 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_33 */
 568 #define SD10G_LANE_LANE_33(t)                                                  \
 569         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 204, 0,\
 570               1, 4)
 571
 572 #define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0)
 573 #define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\
 574         FIELD_PREP(SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, x)
 575 #define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\
 576         FIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, x)
 577
 578 #define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0 GENMASK(5, 4)
 579 #define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_SET(x)\
 580         FIELD_PREP(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x)
 581 #define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_GET(x)\
 582         FIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x)
 583
 584 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_35 */
 585 #define SD10G_LANE_LANE_35(t)                                                  \
 586         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 212, 0,\
 587               1, 4)
 588
 589 #define SD10G_LANE_LANE_35_CFG_TXRATE_1_0        GENMASK(1, 0)
 590 #define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET(x)\
 591         FIELD_PREP(SD10G_LANE_LANE_35_CFG_TXRATE_1_0, x)
 592 #define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_GET(x)\
 593         FIELD_GET(SD10G_LANE_LANE_35_CFG_TXRATE_1_0, x)
 594
 595 #define SD10G_LANE_LANE_35_CFG_RXRATE_1_0        GENMASK(5, 4)
 596 #define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_SET(x)\
 597         FIELD_PREP(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x)
 598 #define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_GET(x)\
 599         FIELD_GET(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x)
 600
 601 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_36 */
 602 #define SD10G_LANE_LANE_36(t)                                                  \
 603         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 216, 0,\
 604               1, 4)
 605
 606 #define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0 GENMASK(1, 0)
 607 #define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET(x)\
 608         FIELD_PREP(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, x)
 609 #define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_GET(x)\
 610         FIELD_GET(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, x)
 611
 612 #define SD10G_LANE_LANE_36_CFG_EID_LP            BIT(4)
 613 #define SD10G_LANE_LANE_36_CFG_EID_LP_SET(x)\
 614         FIELD_PREP(SD10G_LANE_LANE_36_CFG_EID_LP, x)
 615 #define SD10G_LANE_LANE_36_CFG_EID_LP_GET(x)\
 616         FIELD_GET(SD10G_LANE_LANE_36_CFG_EID_LP, x)
 617
 618 #define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH    BIT(5)
 619 #define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_SET(x)\
 620         FIELD_PREP(SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH, x)
 621 #define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_GET(x)\
 622         FIELD_GET(SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH, x)
 623
 624 #define SD10G_LANE_LANE_36_CFG_PRBS_SEL          BIT(6)
 625 #define SD10G_LANE_LANE_36_CFG_PRBS_SEL_SET(x)\
 626         FIELD_PREP(SD10G_LANE_LANE_36_CFG_PRBS_SEL, x)
 627 #define SD10G_LANE_LANE_36_CFG_PRBS_SEL_GET(x)\
 628         FIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SEL, x)
 629
 630 #define SD10G_LANE_LANE_36_CFG_PRBS_SETB         BIT(7)
 631 #define SD10G_LANE_LANE_36_CFG_PRBS_SETB_SET(x)\
 632         FIELD_PREP(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x)
 633 #define SD10G_LANE_LANE_36_CFG_PRBS_SETB_GET(x)\
 634         FIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x)
 635
 636 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_37 */
 637 #define SD10G_LANE_LANE_37(t)                                                  \
 638         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 220, 0,\
 639               1, 4)
 640
 641 #define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD     BIT(0)
 642 #define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_SET(x)\
 643         FIELD_PREP(SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD, x)
 644 #define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_GET(x)\
 645         FIELD_GET(SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD, x)
 646
 647 #define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE      BIT(1)
 648 #define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_SET(x)\
 649         FIELD_PREP(SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE, x)
 650 #define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_GET(x)\
 651         FIELD_GET(SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE, x)
 652
 653 #define SD10G_LANE_LANE_37_CFG_TXSWING_HALF      BIT(2)
 654 #define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_SET(x)\
 655         FIELD_PREP(SD10G_LANE_LANE_37_CFG_TXSWING_HALF, x)
 656 #define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_GET(x)\
 657         FIELD_GET(SD10G_LANE_LANE_37_CFG_TXSWING_HALF, x)
 658
 659 #define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0   GENMASK(5, 4)
 660 #define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_SET(x)\
 661         FIELD_PREP(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x)
 662 #define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_GET(x)\
 663         FIELD_GET(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x)
 664
 665 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_39 */
 666 #define SD10G_LANE_LANE_39(t)                                                  \
 667         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 228, 0,\
 668               1, 4)
 669
 670 #define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0      GENMASK(2, 0)
 671 #define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_SET(x)\
 672         FIELD_PREP(SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0, x)
 673 #define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_GET(x)\
 674         FIELD_GET(SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0, x)
 675
 676 #define SD10G_LANE_LANE_39_CFG_RX_SSC_LH         BIT(4)
 677 #define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_SET(x)\
 678         FIELD_PREP(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x)
 679 #define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_GET(x)\
 680         FIELD_GET(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x)
 681
 682 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3A */
 683 #define SD10G_LANE_LANE_3A(t)                                                  \
 684         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 232, 0,\
 685               1, 4)
 686
 687 #define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0        GENMASK(3, 0)
 688 #define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_SET(x)\
 689         FIELD_PREP(SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0, x)
 690 #define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_GET(x)\
 691         FIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0, x)
 692
 693 #define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0        GENMASK(7, 4)
 694 #define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_SET(x)\
 695         FIELD_PREP(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x)
 696 #define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_GET(x)\
 697         FIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x)
 698
 699 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3C */
 700 #define SD10G_LANE_LANE_3C(t)                                                  \
 701         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 240, 0,\
 702               1, 4)
 703
 704 #define SD10G_LANE_LANE_3C_CFG_DIS_ACC           BIT(0)
 705 #define SD10G_LANE_LANE_3C_CFG_DIS_ACC_SET(x)\
 706         FIELD_PREP(SD10G_LANE_LANE_3C_CFG_DIS_ACC, x)
 707 #define SD10G_LANE_LANE_3C_CFG_DIS_ACC_GET(x)\
 708         FIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_ACC, x)
 709
 710 #define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER      BIT(1)
 711 #define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_SET(x)\
 712         FIELD_PREP(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x)
 713 #define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_GET(x)\
 714         FIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x)
 715
 716 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_40 */
 717 #define SD10G_LANE_LANE_40(t)                                                  \
 718         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 256, 0,\
 719               1, 4)
 720
 721 #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0  GENMASK(7, 0)
 722 #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET(x)\
 723         FIELD_PREP(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x)
 724 #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_GET(x)\
 725         FIELD_GET(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x)
 726
 727 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_41 */
 728 #define SD10G_LANE_LANE_41(t)                                                  \
 729         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 260, 0,\
 730               1, 4)
 731
 732 #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8 GENMASK(7, 0)
 733 #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET(x)\
 734         FIELD_PREP(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x)
 735 #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_GET(x)\
 736         FIELD_GET(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x)
 737
 738 /* SD10G_LANE_TARGET:LANE_GRP_0:LANE_42 */
 739 #define SD10G_LANE_LANE_42(t)                                                  \
 740         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 264, 0,\
 741               1, 4)
 742
 743 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0   GENMASK(2, 0)
 744 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET(x)\
 745         FIELD_PREP(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, x)
 746 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_GET(x)\
 747         FIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, x)
 748
 749 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0   GENMASK(6, 4)
 750 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_SET(x)\
 751         FIELD_PREP(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x)
 752 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_GET(x)\
 753         FIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x)
 754
 755 /* SD10G_LANE_TARGET:LANE_GRP_1:LANE_48 */
 756 #define SD10G_LANE_LANE_48(t)                                                  \
 757         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 288, 0, 1, 40, 0, 0, \
 758               1, 4)
 759
 760 #define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0      GENMASK(3, 0)
 761 #define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET(x)\
 762         FIELD_PREP(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, x)
 763 #define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_GET(x)\
 764         FIELD_GET(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, x)
 765
 766 #define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL      BIT(4)
 767 #define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_SET(x)\
 768         FIELD_PREP(SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL, x)
 769 #define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_GET(x)\
 770         FIELD_GET(SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL, x)
 771
 772 #define SD10G_LANE_LANE_48_CFG_CLK_ENQ           BIT(5)
 773 #define SD10G_LANE_LANE_48_CFG_CLK_ENQ_SET(x)\
 774         FIELD_PREP(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x)
 775 #define SD10G_LANE_LANE_48_CFG_CLK_ENQ_GET(x)\
 776         FIELD_GET(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x)
 777
 778 /* SD10G_LANE_TARGET:LANE_GRP_1:LANE_50 */
 779 #define SD10G_LANE_LANE_50(t)                                                  \
 780         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 288, 0, 1, 40, 32, 0,\
 781               1, 4)
 782
 783 #define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0   GENMASK(1, 0)
 784 #define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_SET(x)\
 785         FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0, x)
 786 #define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_GET(x)\
 787         FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0, x)
 788
 789 #define SD10G_LANE_LANE_50_CFG_SSC_RESETB        BIT(4)
 790 #define SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(x)\
 791         FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_RESETB, x)
 792 #define SD10G_LANE_LANE_50_CFG_SSC_RESETB_GET(x)\
 793         FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_RESETB, x)
 794
 795 #define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL   BIT(5)
 796 #define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_SET(x)\
 797         FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, x)
 798 #define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_GET(x)\
 799         FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, x)
 800
 801 #define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL      BIT(6)
 802 #define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_SET(x)\
 803         FIELD_PREP(SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL, x)
 804 #define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_GET(x)\
 805         FIELD_GET(SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL, x)
 806
 807 #define SD10G_LANE_LANE_50_CFG_JT_EN             BIT(7)
 808 #define SD10G_LANE_LANE_50_CFG_JT_EN_SET(x)\
 809         FIELD_PREP(SD10G_LANE_LANE_50_CFG_JT_EN, x)
 810 #define SD10G_LANE_LANE_50_CFG_JT_EN_GET(x)\
 811         FIELD_GET(SD10G_LANE_LANE_50_CFG_JT_EN, x)
 812
 813 /* SD10G_LANE_TARGET:LANE_GRP_2:LANE_52 */
 814 #define SD10G_LANE_LANE_52(t)                                                  \
 815         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 328, 0, 1, 24, 0, 0, \
 816               1, 4)
 817
 818 #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0 GENMASK(5, 0)
 819 #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET(x)\
 820         FIELD_PREP(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x)
 821 #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_GET(x)\
 822         FIELD_GET(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x)
 823
 824 /* SD10G_LANE_TARGET:LANE_GRP_4:LANE_83 */
 825 #define SD10G_LANE_LANE_83(t)                                                  \
 826         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 464, 0, 1, 112, 60,  \
 827               0, 1, 4)
 828
 829 #define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE      BIT(0)
 830 #define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_SET(x)\
 831         FIELD_PREP(SD10G_LANE_LANE_83_R_TX_BIT_REVERSE, x)
 832 #define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_GET(x)\
 833         FIELD_GET(SD10G_LANE_LANE_83_R_TX_BIT_REVERSE, x)
 834
 835 #define SD10G_LANE_LANE_83_R_TX_POL_INV          BIT(1)
 836 #define SD10G_LANE_LANE_83_R_TX_POL_INV_SET(x)\
 837         FIELD_PREP(SD10G_LANE_LANE_83_R_TX_POL_INV, x)
 838 #define SD10G_LANE_LANE_83_R_TX_POL_INV_GET(x)\
 839         FIELD_GET(SD10G_LANE_LANE_83_R_TX_POL_INV, x)
 840
 841 #define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE      BIT(2)
 842 #define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_SET(x)\
 843         FIELD_PREP(SD10G_LANE_LANE_83_R_RX_BIT_REVERSE, x)
 844 #define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_GET(x)\
 845         FIELD_GET(SD10G_LANE_LANE_83_R_RX_BIT_REVERSE, x)
 846
 847 #define SD10G_LANE_LANE_83_R_RX_POL_INV          BIT(3)
 848 #define SD10G_LANE_LANE_83_R_RX_POL_INV_SET(x)\
 849         FIELD_PREP(SD10G_LANE_LANE_83_R_RX_POL_INV, x)
 850 #define SD10G_LANE_LANE_83_R_RX_POL_INV_GET(x)\
 851         FIELD_GET(SD10G_LANE_LANE_83_R_RX_POL_INV, x)
 852
 853 #define SD10G_LANE_LANE_83_R_DFE_RSTN            BIT(4)
 854 #define SD10G_LANE_LANE_83_R_DFE_RSTN_SET(x)\
 855         FIELD_PREP(SD10G_LANE_LANE_83_R_DFE_RSTN, x)
 856 #define SD10G_LANE_LANE_83_R_DFE_RSTN_GET(x)\
 857         FIELD_GET(SD10G_LANE_LANE_83_R_DFE_RSTN, x)
 858
 859 #define SD10G_LANE_LANE_83_R_CDR_RSTN            BIT(5)
 860 #define SD10G_LANE_LANE_83_R_CDR_RSTN_SET(x)\
 861         FIELD_PREP(SD10G_LANE_LANE_83_R_CDR_RSTN, x)
 862 #define SD10G_LANE_LANE_83_R_CDR_RSTN_GET(x)\
 863         FIELD_GET(SD10G_LANE_LANE_83_R_CDR_RSTN, x)
 864
 865 #define SD10G_LANE_LANE_83_R_CTLE_RSTN           BIT(6)
 866 #define SD10G_LANE_LANE_83_R_CTLE_RSTN_SET(x)\
 867         FIELD_PREP(SD10G_LANE_LANE_83_R_CTLE_RSTN, x)
 868 #define SD10G_LANE_LANE_83_R_CTLE_RSTN_GET(x)\
 869         FIELD_GET(SD10G_LANE_LANE_83_R_CTLE_RSTN, x)
 870
 871 /* SD10G_LANE_TARGET:LANE_GRP_5:LANE_93 */
 872 #define SD10G_LANE_LANE_93(t)                                                  \
 873         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 576, 0, 1, 64, 12, 0,\
 874               1, 4)
 875
 876 #define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN    BIT(0)
 877 #define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_SET(x)\
 878         FIELD_PREP(SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN, x)
 879 #define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_GET(x)\
 880         FIELD_GET(SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN, x)
 881
 882 #define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT BIT(1)
 883 #define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(x)\
 884         FIELD_PREP(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT, x)
 885 #define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_GET(x)\
 886         FIELD_GET(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT, x)
 887
 888 #define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE     BIT(2)
 889 #define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_SET(x)\
 890         FIELD_PREP(SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE, x)
 891 #define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_GET(x)\
 892         FIELD_GET(SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE, x)
 893
 894 #define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL     BIT(3)
 895 #define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(x)\
 896         FIELD_PREP(SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, x)
 897 #define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_GET(x)\
 898         FIELD_GET(SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, x)
 899
 900 #define SD10G_LANE_LANE_93_R_REG_MANUAL          BIT(4)
 901 #define SD10G_LANE_LANE_93_R_REG_MANUAL_SET(x)\
 902         FIELD_PREP(SD10G_LANE_LANE_93_R_REG_MANUAL, x)
 903 #define SD10G_LANE_LANE_93_R_REG_MANUAL_GET(x)\
 904         FIELD_GET(SD10G_LANE_LANE_93_R_REG_MANUAL, x)
 905
 906 #define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT   BIT(5)
 907 #define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(x)\
 908         FIELD_PREP(SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT, x)
 909 #define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_GET(x)\
 910         FIELD_GET(SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT, x)
 911
 912 #define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT    BIT(6)
 913 #define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(x)\
 914         FIELD_PREP(SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT, x)
 915 #define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_GET(x)\
 916         FIELD_GET(SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT, x)
 917
 918 #define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT BIT(7)
 919 #define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_SET(x)\
 920         FIELD_PREP(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x)
 921 #define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_GET(x)\
 922         FIELD_GET(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x)
 923
 924 /* SD10G_LANE_TARGET:LANE_GRP_5:LANE_94 */
 925 #define SD10G_LANE_LANE_94(t)                                                  \
 926         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 576, 0, 1, 64, 16, 0,\
 927               1, 4)
 928
 929 #define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0      GENMASK(2, 0)
 930 #define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET(x)\
 931         FIELD_PREP(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, x)
 932 #define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_GET(x)\
 933         FIELD_GET(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, x)
 934
 935 #define SD10G_LANE_LANE_94_R_ISCAN_REG           BIT(4)
 936 #define SD10G_LANE_LANE_94_R_ISCAN_REG_SET(x)\
 937         FIELD_PREP(SD10G_LANE_LANE_94_R_ISCAN_REG, x)
 938 #define SD10G_LANE_LANE_94_R_ISCAN_REG_GET(x)\
 939         FIELD_GET(SD10G_LANE_LANE_94_R_ISCAN_REG, x)
 940
 941 #define SD10G_LANE_LANE_94_R_TXEQ_REG            BIT(5)
 942 #define SD10G_LANE_LANE_94_R_TXEQ_REG_SET(x)\
 943         FIELD_PREP(SD10G_LANE_LANE_94_R_TXEQ_REG, x)
 944 #define SD10G_LANE_LANE_94_R_TXEQ_REG_GET(x)\
 945         FIELD_GET(SD10G_LANE_LANE_94_R_TXEQ_REG, x)
 946
 947 #define SD10G_LANE_LANE_94_R_MISC_REG            BIT(6)
 948 #define SD10G_LANE_LANE_94_R_MISC_REG_SET(x)\
 949         FIELD_PREP(SD10G_LANE_LANE_94_R_MISC_REG, x)
 950 #define SD10G_LANE_LANE_94_R_MISC_REG_GET(x)\
 951         FIELD_GET(SD10G_LANE_LANE_94_R_MISC_REG, x)
 952
 953 #define SD10G_LANE_LANE_94_R_SWING_REG           BIT(7)
 954 #define SD10G_LANE_LANE_94_R_SWING_REG_SET(x)\
 955         FIELD_PREP(SD10G_LANE_LANE_94_R_SWING_REG, x)
 956 #define SD10G_LANE_LANE_94_R_SWING_REG_GET(x)\
 957         FIELD_GET(SD10G_LANE_LANE_94_R_SWING_REG, x)
 958
 959 /* SD10G_LANE_TARGET:LANE_GRP_5:LANE_9E */
 960 #define SD10G_LANE_LANE_9E(t)                                                  \
 961         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 576, 0, 1, 64, 56, 0,\
 962               1, 4)
 963
 964 #define SD10G_LANE_LANE_9E_R_RXEQ_REG            BIT(0)
 965 #define SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(x)\
 966         FIELD_PREP(SD10G_LANE_LANE_9E_R_RXEQ_REG, x)
 967 #define SD10G_LANE_LANE_9E_R_RXEQ_REG_GET(x)\
 968         FIELD_GET(SD10G_LANE_LANE_9E_R_RXEQ_REG, x)
 969
 970 #define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN BIT(1)
 971 #define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_SET(x)\
 972         FIELD_PREP(SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN, x)
 973 #define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_GET(x)\
 974         FIELD_GET(SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN, x)
 975
 976 #define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN    BIT(2)
 977 #define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_SET(x)\
 978         FIELD_PREP(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x)
 979 #define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_GET(x)\
 980         FIELD_GET(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x)
 981
 982 /* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A1 */
 983 #define SD10G_LANE_LANE_A1(t)                                                  \
 984         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 640, 0, 1, 128, 4, 0,\
 985               1, 4)
 986
 987 #define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0 GENMASK(1, 0)
 988 #define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_SET(x)\
 989         FIELD_PREP(SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0, x)
 990 #define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_GET(x)\
 991         FIELD_GET(SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0, x)
 992
 993 #define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT        BIT(4)
 994 #define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(x)\
 995         FIELD_PREP(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT, x)
 996 #define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_GET(x)\
 997         FIELD_GET(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT, x)
 998
 999 #define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT        BIT(5)
1000 #define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(x)\
1001         FIELD_PREP(SD10G_LANE_LANE_A1_R_CDR_FROM_HWT, x)
1002 #define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_GET(x)\
1003         FIELD_GET(SD10G_LANE_LANE_A1_R_CDR_FROM_HWT, x)
1004
1005 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT BIT(6)
1006 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(x)\
1007         FIELD_PREP(SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, x)
1008 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_GET(x)\
1009         FIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, x)
1010
1011 #define SD10G_LANE_LANE_A1_R_PCLK_GATING         BIT(7)
1012 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_SET(x)\
1013         FIELD_PREP(SD10G_LANE_LANE_A1_R_PCLK_GATING, x)
1014 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_GET(x)\
1015         FIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING, x)
1016
1017 /* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A2 */
1018 #define SD10G_LANE_LANE_A2(t)                                                  \
1019         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 640, 0, 1, 128, 8, 0,\
1020               1, 4)
1021
1022 #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0)
1023 #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET(x)\
1024         FIELD_PREP(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x)
1025 #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_GET(x)\
1026         FIELD_GET(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x)
1027
1028 /* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */
1029 #define SD10G_LANE_LANE_DF(t)                                                  \
1030         __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 832, 0, 1, 84, 60, 0,\
1031               1, 4)
1032
1033 #define SD10G_LANE_LANE_DF_LOL_UDL               BIT(0)
1034 #define SD10G_LANE_LANE_DF_LOL_UDL_SET(x)\
1035         FIELD_PREP(SD10G_LANE_LANE_DF_LOL_UDL, x)
1036 #define SD10G_LANE_LANE_DF_LOL_UDL_GET(x)\
1037         FIELD_GET(SD10G_LANE_LANE_DF_LOL_UDL, x)
1038
1039 #define SD10G_LANE_LANE_DF_LOL                   BIT(1)
1040 #define SD10G_LANE_LANE_DF_LOL_SET(x)\
1041         FIELD_PREP(SD10G_LANE_LANE_DF_LOL, x)
1042 #define SD10G_LANE_LANE_DF_LOL_GET(x)\
1043         FIELD_GET(SD10G_LANE_LANE_DF_LOL, x)
1044
1045 #define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED BIT(2)
1046 #define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\
1047         FIELD_PREP(SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
1048 #define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\
1049         FIELD_GET(SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
1050
1051 #define SD10G_LANE_LANE_DF_SQUELCH               BIT(3)
1052 #define SD10G_LANE_LANE_DF_SQUELCH_SET(x)\
1053         FIELD_PREP(SD10G_LANE_LANE_DF_SQUELCH, x)
1054 #define SD10G_LANE_LANE_DF_SQUELCH_GET(x)\
1055         FIELD_GET(SD10G_LANE_LANE_DF_SQUELCH, x)
1056
1057 /* SPARX5 ONLY */
1058 /* SD25G_TARGET:CMU_GRP_0:CMU_09 */
1059 #define SD25G_LANE_CMU_09(t)                                                   \
1060         __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 36, 0, 1, 4)
1061
1062 #define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN      BIT(0)
1063 #define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_SET(x)\
1064         FIELD_PREP(SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN, x)
1065 #define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_GET(x)\
1066         FIELD_GET(SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN, x)
1067
1068 #define SD25G_LANE_CMU_09_CFG_EN_DUMMY           BIT(1)
1069 #define SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(x)\
1070         FIELD_PREP(SD25G_LANE_CMU_09_CFG_EN_DUMMY, x)
1071 #define SD25G_LANE_CMU_09_CFG_EN_DUMMY_GET(x)\
1072         FIELD_GET(SD25G_LANE_CMU_09_CFG_EN_DUMMY, x)
1073
1074 #define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET        BIT(2)
1075 #define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_SET(x)\
1076         FIELD_PREP(SD25G_LANE_CMU_09_CFG_PLL_LOS_SET, x)
1077 #define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_GET(x)\
1078         FIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_LOS_SET, x)
1079
1080 #define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD      BIT(3)
1081 #define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_SET(x)\
1082         FIELD_PREP(SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD, x)
1083 #define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_GET(x)\
1084         FIELD_GET(SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD, x)
1085
1086 #define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0     GENMASK(5, 4)
1087 #define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_SET(x)\
1088         FIELD_PREP(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x)
1089 #define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_GET(x)\
1090         FIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x)
1091
1092 /* SPARX5 ONLY */
1093 /* SD25G_TARGET:CMU_GRP_0:CMU_0B */
1094 #define SD25G_LANE_CMU_0B(t)                                                   \
1095         __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 44, 0, 1, 4)
1096
1097 #define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT      BIT(0)
1098 #define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_SET(x)\
1099         FIELD_PREP(SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT, x)
1100 #define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_GET(x)\
1101         FIELD_GET(SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT, x)
1102
1103 #define SD25G_LANE_CMU_0B_CFG_DISLOL             BIT(1)
1104 #define SD25G_LANE_CMU_0B_CFG_DISLOL_SET(x)\
1105         FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DISLOL, x)
1106 #define SD25G_LANE_CMU_0B_CFG_DISLOL_GET(x)\
1107         FIELD_GET(SD25G_LANE_CMU_0B_CFG_DISLOL, x)
1108
1109 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN BIT(2)
1110 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_SET(x)\
1111         FIELD_PREP(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN, x)
1112 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_GET(x)\
1113         FIELD_GET(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN, x)
1114
1115 #define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN     BIT(3)
1116 #define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(x)\
1117         FIELD_PREP(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, x)
1118 #define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_GET(x)\
1119         FIELD_GET(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, x)
1120
1121 #define SD25G_LANE_CMU_0B_CFG_VFILT2PAD          BIT(4)
1122 #define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_SET(x)\
1123         FIELD_PREP(SD25G_LANE_CMU_0B_CFG_VFILT2PAD, x)
1124 #define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_GET(x)\
1125         FIELD_GET(SD25G_LANE_CMU_0B_CFG_VFILT2PAD, x)
1126
1127 #define SD25G_LANE_CMU_0B_CFG_DISLOS             BIT(5)
1128 #define SD25G_LANE_CMU_0B_CFG_DISLOS_SET(x)\
1129         FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DISLOS, x)
1130 #define SD25G_LANE_CMU_0B_CFG_DISLOS_GET(x)\
1131         FIELD_GET(SD25G_LANE_CMU_0B_CFG_DISLOS, x)
1132
1133 #define SD25G_LANE_CMU_0B_CFG_DCLOL              BIT(6)
1134 #define SD25G_LANE_CMU_0B_CFG_DCLOL_SET(x)\
1135         FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DCLOL, x)
1136 #define SD25G_LANE_CMU_0B_CFG_DCLOL_GET(x)\
1137         FIELD_GET(SD25G_LANE_CMU_0B_CFG_DCLOL, x)
1138
1139 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN    BIT(7)
1140 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_SET(x)\
1141         FIELD_PREP(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN, x)
1142 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_GET(x)\
1143         FIELD_GET(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN, x)
1144
1145 /* SPARX5 ONLY */
1146 /* SD25G_TARGET:CMU_GRP_0:CMU_0C */
1147 #define SD25G_LANE_CMU_0C(t)                                                   \
1148         __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 48, 0, 1, 4)
1149
1150 #define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET        BIT(0)
1151 #define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(x)\
1152         FIELD_PREP(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET, x)
1153 #define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_GET(x)\
1154         FIELD_GET(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET, x)
1155
1156 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN        BIT(1)
1157 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_SET(x)\
1158         FIELD_PREP(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN, x)
1159 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_GET(x)\
1160         FIELD_GET(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN, x)
1161
1162 #define SD25G_LANE_CMU_0C_CFG_VCO_PD             BIT(2)
1163 #define SD25G_LANE_CMU_0C_CFG_VCO_PD_SET(x)\
1164         FIELD_PREP(SD25G_LANE_CMU_0C_CFG_VCO_PD, x)
1165 #define SD25G_LANE_CMU_0C_CFG_VCO_PD_GET(x)\
1166         FIELD_GET(SD25G_LANE_CMU_0C_CFG_VCO_PD, x)
1167
1168 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP        BIT(3)
1169 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_SET(x)\
1170         FIELD_PREP(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP, x)
1171 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_GET(x)\
1172         FIELD_GET(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP, x)
1173
1174 #define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0   GENMASK(5, 4)
1175 #define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_SET(x)\
1176         FIELD_PREP(SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, x)
1177 #define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_GET(x)\
1178         FIELD_GET(SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, x)
1179
1180 /* SPARX5 ONLY */
1181 /* SD25G_TARGET:CMU_GRP_0:CMU_0D */
1182 #define SD25G_LANE_CMU_0D(t)                                                   \
1183         __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 52, 0, 1, 4)
1184
1185 #define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD         BIT(0)
1186 #define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_SET(x)\
1187         FIELD_PREP(SD25G_LANE_CMU_0D_CFG_CK_TREE_PD, x)
1188 #define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_GET(x)\
1189         FIELD_GET(SD25G_LANE_CMU_0D_CFG_CK_TREE_PD, x)
1190
1191 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN        BIT(1)
1192 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_SET(x)\
1193         FIELD_PREP(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN, x)
1194 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_GET(x)\
1195         FIELD_GET(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN, x)
1196
1197 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP        BIT(2)
1198 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_SET(x)\
1199         FIELD_PREP(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP, x)
1200 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_GET(x)\
1201         FIELD_GET(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP, x)
1202
1203 #define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP        BIT(3)
1204 #define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_SET(x)\
1205         FIELD_PREP(SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP, x)
1206 #define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_GET(x)\
1207         FIELD_GET(SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP, x)
1208
1209 #define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0     GENMASK(5, 4)
1210 #define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_SET(x)\
1211         FIELD_PREP(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, x)
1212 #define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_GET(x)\
1213         FIELD_GET(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, x)
1214
1215 /* SPARX5 ONLY */
1216 /* SD25G_TARGET:CMU_GRP_0:CMU_0E */
1217 #define SD25G_LANE_CMU_0E(t)                                                   \
1218         __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 56, 0, 1, 4)
1219
1220 #define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0        GENMASK(3, 0)
1221 #define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(x)\
1222         FIELD_PREP(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0, x)
1223 #define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_GET(x)\
1224         FIELD_GET(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0, x)
1225
1226 #define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD   BIT(4)
1227 #define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_SET(x)\
1228         FIELD_PREP(SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD, x)
1229 #define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_GET(x)\
1230         FIELD_GET(SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD, x)
1231
1232 /* SPARX5 ONLY */
1233 /* SD25G_TARGET:CMU_GRP_0:CMU_13 */
1234 #define SD25G_LANE_CMU_13(t)                                                   \
1235         __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 76, 0, 1, 4)
1236
1237 #define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0    GENMASK(3, 0)
1238 #define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET(x)\
1239         FIELD_PREP(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0, x)
1240 #define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_GET(x)\
1241         FIELD_GET(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0, x)
1242
1243 #define SD25G_LANE_CMU_13_CFG_JT_EN              BIT(4)
1244 #define SD25G_LANE_CMU_13_CFG_JT_EN_SET(x)\
1245         FIELD_PREP(SD25G_LANE_CMU_13_CFG_JT_EN, x)
1246 #define SD25G_LANE_CMU_13_CFG_JT_EN_GET(x)\
1247         FIELD_GET(SD25G_LANE_CMU_13_CFG_JT_EN, x)
1248
1249 /* SPARX5 ONLY */
1250 /* SD25G_TARGET:CMU_GRP_0:CMU_18 */
1251 #define SD25G_LANE_CMU_18(t)                                                   \
1252         __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 96, 0, 1, 4)
1253
1254 #define SD25G_LANE_CMU_18_R_PLL_RSTN             BIT(0)
1255 #define SD25G_LANE_CMU_18_R_PLL_RSTN_SET(x)\
1256         FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_RSTN, x)
1257 #define SD25G_LANE_CMU_18_R_PLL_RSTN_GET(x)\
1258         FIELD_GET(SD25G_LANE_CMU_18_R_PLL_RSTN, x)
1259
1260 #define SD25G_LANE_CMU_18_R_PLL_LOL_SET          BIT(1)
1261 #define SD25G_LANE_CMU_18_R_PLL_LOL_SET_SET(x)\
1262         FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_LOL_SET, x)
1263 #define SD25G_LANE_CMU_18_R_PLL_LOL_SET_GET(x)\
1264         FIELD_GET(SD25G_LANE_CMU_18_R_PLL_LOL_SET, x)
1265
1266 #define SD25G_LANE_CMU_18_R_PLL_LOS_SET          BIT(2)
1267 #define SD25G_LANE_CMU_18_R_PLL_LOS_SET_SET(x)\
1268         FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_LOS_SET, x)
1269 #define SD25G_LANE_CMU_18_R_PLL_LOS_SET_GET(x)\
1270         FIELD_GET(SD25G_LANE_CMU_18_R_PLL_LOS_SET, x)
1271
1272 #define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0       GENMASK(5, 4)
1273 #define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_SET(x)\
1274         FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0, x)
1275 #define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_GET(x)\
1276         FIELD_GET(SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0, x)
1277
1278 /* SPARX5 ONLY */
1279 /* SD25G_TARGET:CMU_GRP_0:CMU_19 */
1280 #define SD25G_LANE_CMU_19(t)                                                   \
1281         __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 100, 0, 1, 4)
1282
1283 #define SD25G_LANE_CMU_19_R_CK_RESETB            BIT(0)
1284 #define SD25G_LANE_CMU_19_R_CK_RESETB_SET(x)\
1285         FIELD_PREP(SD25G_LANE_CMU_19_R_CK_RESETB, x)
1286 #define SD25G_LANE_CMU_19_R_CK_RESETB_GET(x)\
1287         FIELD_GET(SD25G_LANE_CMU_19_R_CK_RESETB, x)
1288
1289 #define SD25G_LANE_CMU_19_R_PLL_DLOL_EN          BIT(1)
1290 #define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_SET(x)\
1291         FIELD_PREP(SD25G_LANE_CMU_19_R_PLL_DLOL_EN, x)
1292 #define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_GET(x)\
1293         FIELD_GET(SD25G_LANE_CMU_19_R_PLL_DLOL_EN, x)
1294
1295 /* SPARX5 ONLY */
1296 /* SD25G_TARGET:CMU_GRP_0:CMU_1A */
1297 #define SD25G_LANE_CMU_1A(t)                                                   \
1298         __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 104, 0, 1, 4)
1299
1300 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0       GENMASK(2, 0)
1301 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(x)\
1302         FIELD_PREP(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0, x)
1303 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_GET(x)\
1304         FIELD_GET(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0, x)
1305
1306 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT  BIT(4)
1307 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET(x)\
1308         FIELD_PREP(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT, x)
1309 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_GET(x)\
1310         FIELD_GET(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT, x)
1311
1312 #define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE       BIT(5)
1313 #define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_SET(x)\
1314         FIELD_PREP(SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE, x)
1315 #define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_GET(x)\
1316         FIELD_GET(SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE, x)
1317
1318 #define SD25G_LANE_CMU_1A_R_REG_MANUAL           BIT(6)
1319 #define SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(x)\
1320         FIELD_PREP(SD25G_LANE_CMU_1A_R_REG_MANUAL, x)
1321 #define SD25G_LANE_CMU_1A_R_REG_MANUAL_GET(x)\
1322         FIELD_GET(SD25G_LANE_CMU_1A_R_REG_MANUAL, x)
1323
1324 /* SPARX5 ONLY */
1325 /* SD25G_TARGET:CMU_GRP_1:CMU_2A */
1326 #define SD25G_LANE_CMU_2A(t)                                                   \
1327         __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 36, 0, 1, 4)
1328
1329 #define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0          GENMASK(1, 0)
1330 #define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_SET(x)\
1331         FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_SEL_1_0, x)
1332 #define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_GET(x)\
1333         FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_SEL_1_0, x)
1334
1335 #define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE        BIT(4)
1336 #define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_SET(x)\
1337         FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_LINK_LANE, x)
1338 #define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_GET(x)\
1339         FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_LINK_LANE, x)
1340
1341 #define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS       BIT(5)
1342 #define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(x)\
1343         FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, x)
1344 #define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_GET(x)\
1345         FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, x)
1346
1347 /* SPARX5 ONLY */
1348 /* SD25G_TARGET:CMU_GRP_1:CMU_30 */
1349 #define SD25G_LANE_CMU_30(t)                                                   \
1350         __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 60, 0, 1, 4)
1351
1352 #define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0 GENMASK(2, 0)
1353 #define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET(x)\
1354         FIELD_PREP(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0, x)
1355 #define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_GET(x)\
1356         FIELD_GET(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0, x)
1357
1358 #define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0 GENMASK(6, 4)
1359 #define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_SET(x)\
1360         FIELD_PREP(SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, x)
1361 #define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_GET(x)\
1362         FIELD_GET(SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, x)
1363
1364 /* SPARX5 ONLY */
1365 /* SD25G_TARGET:CMU_GRP_1:CMU_31 */
1366 #define SD25G_LANE_CMU_31(t)                                                   \
1367         __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 64, 0, 1, 4)
1368
1369 #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0 GENMASK(7, 0)
1370 #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET(x)\
1371         FIELD_PREP(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, x)
1372 #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_GET(x)\
1373         FIELD_GET(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, x)
1374
1375 /* SPARX5 ONLY */
1376 /* SD25G_TARGET:CMU_GRP_2:CMU_40 */
1377 #define SD25G_LANE_CMU_40(t)                                                   \
1378         __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 0, 0, 1, 4)
1379
1380 #define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL     BIT(0)
1381 #define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_SET(x)\
1382         FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL, x)
1383 #define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_GET(x)\
1384         FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL, x)
1385
1386 #define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD      BIT(1)
1387 #define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_SET(x)\
1388         FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD, x)
1389 #define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_GET(x)\
1390         FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD, x)
1391
1392 #define SD25G_LANE_CMU_40_L0_CFG_PD_CLK          BIT(2)
1393 #define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_SET(x)\
1394         FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_PD_CLK, x)
1395 #define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_GET(x)\
1396         FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_PD_CLK, x)
1397
1398 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN        BIT(3)
1399 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(x)\
1400         FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN, x)
1401 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_GET(x)\
1402         FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN, x)
1403
1404 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN    BIT(4)
1405 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_SET(x)\
1406         FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN, x)
1407 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_GET(x)\
1408         FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN, x)
1409
1410 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST       BIT(5)
1411 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_SET(x)\
1412         FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST, x)
1413 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_GET(x)\
1414         FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST, x)
1415
1416 /* SPARX5 ONLY */
1417 /* SD25G_TARGET:CMU_GRP_2:CMU_45 */
1418 #define SD25G_LANE_CMU_45(t)                                                   \
1419         __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 20, 0, 1, 4)
1420
1421 #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0  GENMASK(7, 0)
1422 #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET(x)\
1423         FIELD_PREP(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, x)
1424 #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_GET(x)\
1425         FIELD_GET(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, x)
1426
1427 /* SPARX5 ONLY */
1428 /* SD25G_TARGET:CMU_GRP_2:CMU_46 */
1429 #define SD25G_LANE_CMU_46(t)                                                   \
1430         __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 24, 0, 1, 4)
1431
1432 #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8 GENMASK(7, 0)
1433 #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET(x)\
1434         FIELD_PREP(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, x)
1435 #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_GET(x)\
1436         FIELD_GET(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, x)
1437
1438 /* SPARX5 ONLY */
1439 /* SD25G_TARGET:CMU_GRP_3:CMU_C0 */
1440 #define SD25G_LANE_CMU_C0(t)                                                   \
1441         __REG(TARGET_SD25G_LANE, t, 8, 768, 0, 1, 252, 0, 0, 1, 4)
1442
1443 #define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0     GENMASK(3, 0)
1444 #define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_SET(x)\
1445         FIELD_PREP(SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0, x)
1446 #define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_GET(x)\
1447         FIELD_GET(SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0, x)
1448
1449 #define SD25G_LANE_CMU_C0_PLL_LOL_UDL            BIT(4)
1450 #define SD25G_LANE_CMU_C0_PLL_LOL_UDL_SET(x)\
1451         FIELD_PREP(SD25G_LANE_CMU_C0_PLL_LOL_UDL, x)
1452 #define SD25G_LANE_CMU_C0_PLL_LOL_UDL_GET(x)\
1453         FIELD_GET(SD25G_LANE_CMU_C0_PLL_LOL_UDL, x)
1454
1455 /* SPARX5 ONLY */
1456 /* SD25G_TARGET:CMU_GRP_4:CMU_FF */
1457 #define SD25G_LANE_CMU_FF(t)                                                   \
1458         __REG(TARGET_SD25G_LANE, t, 8, 1020, 0, 1, 4, 0, 0, 1, 4)
1459
1460 #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX   GENMASK(7, 0)
1461 #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(x)\
1462         FIELD_PREP(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, x)
1463 #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_GET(x)\
1464         FIELD_GET(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, x)
1465
1466 /* SPARX5 ONLY */
1467 /* SD25G_TARGET:LANE_GRP_0:LANE_00 */
1468 #define SD25G_LANE_LANE_00(t)                                                  \
1469         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 0, 0, 1, 4)
1470
1471 #define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0 GENMASK(3, 0)
1472 #define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_SET(x)\
1473         FIELD_PREP(SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0, x)
1474 #define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_GET(x)\
1475         FIELD_GET(SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0, x)
1476
1477 #define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0 GENMASK(5, 4)
1478 #define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_SET(x)\
1479         FIELD_PREP(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, x)
1480 #define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_GET(x)\
1481         FIELD_GET(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, x)
1482
1483 /* SPARX5 ONLY */
1484 /* SD25G_TARGET:LANE_GRP_0:LANE_01 */
1485 #define SD25G_LANE_LANE_01(t)                                                  \
1486         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 4, 0, 1, 4)
1487
1488 #define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0)
1489 #define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\
1490         FIELD_PREP(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0, x)
1491 #define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\
1492         FIELD_GET(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0, x)
1493
1494 #define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0  GENMASK(5, 4)
1495 #define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_SET(x)\
1496         FIELD_PREP(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, x)
1497 #define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_GET(x)\
1498         FIELD_GET(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, x)
1499
1500 /* SPARX5 ONLY */
1501 /* SD25G_TARGET:LANE_GRP_0:LANE_03 */
1502 #define SD25G_LANE_LANE_03(t)                                                  \
1503         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 12, 0, 1, 4)
1504
1505 #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0    GENMASK(4, 0)
1506 #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(x)\
1507         FIELD_PREP(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, x)
1508 #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_GET(x)\
1509         FIELD_GET(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, x)
1510
1511 /* SPARX5 ONLY */
1512 /* SD25G_TARGET:LANE_GRP_0:LANE_04 */
1513 #define SD25G_LANE_LANE_04(t)                                                  \
1514         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 16, 0, 1, 4)
1515
1516 #define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN    BIT(0)
1517 #define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(x)\
1518         FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN, x)
1519 #define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_GET(x)\
1520         FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN, x)
1521
1522 #define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN    BIT(1)
1523 #define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(x)\
1524         FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN, x)
1525 #define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_GET(x)\
1526         FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN, x)
1527
1528 #define SD25G_LANE_LANE_04_LN_CFG_PD_CML         BIT(2)
1529 #define SD25G_LANE_LANE_04_LN_CFG_PD_CML_SET(x)\
1530         FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_CML, x)
1531 #define SD25G_LANE_LANE_04_LN_CFG_PD_CML_GET(x)\
1532         FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_CML, x)
1533
1534 #define SD25G_LANE_LANE_04_LN_CFG_PD_CLK         BIT(3)
1535 #define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_SET(x)\
1536         FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_CLK, x)
1537 #define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_GET(x)\
1538         FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_CLK, x)
1539
1540 #define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER      BIT(4)
1541 #define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_SET(x)\
1542         FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER, x)
1543 #define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_GET(x)\
1544         FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER, x)
1545
1546 #define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN       BIT(5)
1547 #define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_SET(x)\
1548         FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN, x)
1549 #define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_GET(x)\
1550         FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN, x)
1551
1552 /* SPARX5 ONLY */
1553 /* SD25G_TARGET:LANE_GRP_0:LANE_05 */
1554 #define SD25G_LANE_LANE_05(t)                                                  \
1555         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 20, 0, 1, 4)
1556
1557 #define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0   GENMASK(3, 0)
1558 #define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_SET(x)\
1559         FIELD_PREP(SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0, x)
1560 #define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_GET(x)\
1561         FIELD_GET(SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0, x)
1562
1563 #define SD25G_LANE_LANE_05_LN_CFG_BW_1_0         GENMASK(5, 4)
1564 #define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(x)\
1565         FIELD_PREP(SD25G_LANE_LANE_05_LN_CFG_BW_1_0, x)
1566 #define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_GET(x)\
1567         FIELD_GET(SD25G_LANE_LANE_05_LN_CFG_BW_1_0, x)
1568
1569 /* SPARX5 ONLY */
1570 /* SD25G_TARGET:LANE_GRP_0:LANE_06 */
1571 #define SD25G_LANE_LANE_06(t)                                                  \
1572         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 24, 0, 1, 4)
1573
1574 #define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN        BIT(0)
1575 #define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_SET(x)\
1576         FIELD_PREP(SD25G_LANE_LANE_06_LN_CFG_EN_MAIN, x)
1577 #define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_GET(x)\
1578         FIELD_GET(SD25G_LANE_LANE_06_LN_CFG_EN_MAIN, x)
1579
1580 #define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0    GENMASK(7, 4)
1581 #define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(x)\
1582         FIELD_PREP(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, x)
1583 #define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_GET(x)\
1584         FIELD_GET(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, x)
1585
1586 /* SPARX5 ONLY */
1587 /* SD25G_TARGET:LANE_GRP_0:LANE_07 */
1588 #define SD25G_LANE_LANE_07(t)                                                  \
1589         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 28, 0, 1, 4)
1590
1591 #define SD25G_LANE_LANE_07_LN_CFG_EN_ADV         BIT(0)
1592 #define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(x)\
1593         FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_ADV, x)
1594 #define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_GET(x)\
1595         FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_ADV, x)
1596
1597 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2        BIT(1)
1598 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_SET(x)\
1599         FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_DLY2, x)
1600 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_GET(x)\
1601         FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_DLY2, x)
1602
1603 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY         BIT(2)
1604 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_SET(x)\
1605         FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_DLY, x)
1606 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_GET(x)\
1607         FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_DLY, x)
1608
1609 /* SPARX5 ONLY */
1610 /* SD25G_TARGET:LANE_GRP_0:LANE_09 */
1611 #define SD25G_LANE_LANE_09(t)                                                  \
1612         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 36, 0, 1, 4)
1613
1614 #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0 GENMASK(3, 0)
1615 #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_SET(x)\
1616         FIELD_PREP(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, x)
1617 #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_GET(x)\
1618         FIELD_GET(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, x)
1619
1620 /* SPARX5 ONLY */
1621 /* SD25G_TARGET:LANE_GRP_0:LANE_0A */
1622 #define SD25G_LANE_LANE_0A(t)                                                  \
1623         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 40, 0, 1, 4)
1624
1625 #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0 GENMASK(5, 0)
1626 #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_SET(x)\
1627         FIELD_PREP(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, x)
1628 #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_GET(x)\
1629         FIELD_GET(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, x)
1630
1631 /* SPARX5 ONLY */
1632 /* SD25G_TARGET:LANE_GRP_0:LANE_0B */
1633 #define SD25G_LANE_LANE_0B(t)                                                  \
1634         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 44, 0, 1, 4)
1635
1636 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN   BIT(0)
1637 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_SET(x)\
1638         FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN, x)
1639 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_GET(x)\
1640         FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN, x)
1641
1642 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST      BIT(1)
1643 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_SET(x)\
1644         FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST, x)
1645 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_GET(x)\
1646         FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST, x)
1647
1648 #define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0   GENMASK(5, 4)
1649 #define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_SET(x)\
1650         FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0, x)
1651 #define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_GET(x)\
1652         FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0, x)
1653
1654 /* SPARX5 ONLY */
1655 /* SD25G_TARGET:LANE_GRP_0:LANE_0C */
1656 #define SD25G_LANE_LANE_0C(t)                                                  \
1657         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 48, 0, 1, 4)
1658
1659 #define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0)
1660 #define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\
1661         FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
1662 #define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\
1663         FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
1664
1665 #define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN       BIT(4)
1666 #define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_SET(x)\
1667         FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN, x)
1668 #define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_GET(x)\
1669         FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN, x)
1670
1671 #define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD      BIT(5)
1672 #define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_SET(x)\
1673         FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD, x)
1674 #define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_GET(x)\
1675         FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD, x)
1676
1677 /* SPARX5 ONLY */
1678 /* SD25G_TARGET:LANE_GRP_0:LANE_0D */
1679 #define SD25G_LANE_LANE_0D(t)                                                  \
1680         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 52, 0, 1, 4)
1681
1682 #define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0     GENMASK(2, 0)
1683 #define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(x)\
1684         FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0, x)
1685 #define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_GET(x)\
1686         FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0, x)
1687
1688 #define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8    BIT(4)
1689 #define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_SET(x)\
1690         FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8, x)
1691 #define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_GET(x)\
1692         FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8, x)
1693
1694 #define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN      BIT(5)
1695 #define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_SET(x)\
1696         FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN, x)
1697 #define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_GET(x)\
1698         FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN, x)
1699
1700 #define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD        BIT(6)
1701 #define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_SET(x)\
1702         FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD, x)
1703 #define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_GET(x)\
1704         FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD, x)
1705
1706 #define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN       BIT(7)
1707 #define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(x)\
1708         FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN, x)
1709 #define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_GET(x)\
1710         FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN, x)
1711
1712 /* SPARX5 ONLY */
1713 /* SD25G_TARGET:LANE_GRP_0:LANE_0E */
1714 #define SD25G_LANE_LANE_0E(t)                                                  \
1715         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 56, 0, 1, 4)
1716
1717 #define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN       BIT(0)
1718 #define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_SET(x)\
1719         FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN, x)
1720 #define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_GET(x)\
1721         FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN, x)
1722
1723 #define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD    BIT(1)
1724 #define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_SET(x)\
1725         FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD, x)
1726 #define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_GET(x)\
1727         FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD, x)
1728
1729 #define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG      BIT(2)
1730 #define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(x)\
1731         FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG, x)
1732 #define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_GET(x)\
1733         FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG, x)
1734
1735 #define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0   GENMASK(6, 4)
1736 #define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_SET(x)\
1737         FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, x)
1738 #define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_GET(x)\
1739         FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, x)
1740
1741 /* SPARX5 ONLY */
1742 /* SD25G_TARGET:LANE_GRP_0:LANE_0F */
1743 #define SD25G_LANE_LANE_0F(t)                                                  \
1744         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 60, 0, 1, 4)
1745
1746 #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1  GENMASK(4, 0)
1747 #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_SET(x)\
1748         FIELD_PREP(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, x)
1749 #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_GET(x)\
1750         FIELD_GET(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, x)
1751
1752 /* SPARX5 ONLY */
1753 /* SD25G_TARGET:LANE_GRP_0:LANE_18 */
1754 #define SD25G_LANE_LANE_18(t)                                                  \
1755         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 96, 0, 1, 4)
1756
1757 #define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN       BIT(0)
1758 #define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(x)\
1759         FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN, x)
1760 #define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_GET(x)\
1761         FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN, x)
1762
1763 #define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT       BIT(1)
1764 #define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_SET(x)\
1765         FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT, x)
1766 #define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_GET(x)\
1767         FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT, x)
1768
1769 #define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN    BIT(2)
1770 #define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_SET(x)\
1771         FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN, x)
1772 #define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_GET(x)\
1773         FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN, x)
1774
1775 #define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD      BIT(3)
1776 #define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(x)\
1777         FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, x)
1778 #define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_GET(x)\
1779         FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, x)
1780
1781 #define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0  GENMASK(6, 4)
1782 #define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_SET(x)\
1783         FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, x)
1784 #define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_GET(x)\
1785         FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, x)
1786
1787 /* SPARX5 ONLY */
1788 /* SD25G_TARGET:LANE_GRP_0:LANE_19 */
1789 #define SD25G_LANE_LANE_19(t)                                                  \
1790         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 100, 0, 1, 4)
1791
1792 #define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD        BIT(0)
1793 #define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_SET(x)\
1794         FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_DCDR_PD, x)
1795 #define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_GET(x)\
1796         FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_DCDR_PD, x)
1797
1798 #define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD        BIT(1)
1799 #define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(x)\
1800         FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD, x)
1801 #define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_GET(x)\
1802         FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD, x)
1803
1804 #define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL      BIT(2)
1805 #define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_SET(x)\
1806         FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL, x)
1807 #define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_GET(x)\
1808         FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL, x)
1809
1810 #define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN        BIT(3)
1811 #define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(x)\
1812         FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN, x)
1813 #define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_GET(x)\
1814         FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN, x)
1815
1816 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU      BIT(4)
1817 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_SET(x)\
1818         FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU, x)
1819 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_GET(x)\
1820         FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU, x)
1821
1822 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP     BIT(5)
1823 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_SET(x)\
1824         FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP, x)
1825 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_GET(x)\
1826         FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP, x)
1827
1828 #define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET     BIT(6)
1829 #define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_SET(x)\
1830         FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET, x)
1831 #define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_GET(x)\
1832         FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET, x)
1833
1834 #define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE        BIT(7)
1835 #define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_SET(x)\
1836         FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_PD_CTLE, x)
1837 #define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_GET(x)\
1838         FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_PD_CTLE, x)
1839
1840 /* SPARX5 ONLY */
1841 /* SD25G_TARGET:LANE_GRP_0:LANE_1A */
1842 #define SD25G_LANE_LANE_1A(t)                                                  \
1843         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 104, 0, 1, 4)
1844
1845 #define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN     BIT(0)
1846 #define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_SET(x)\
1847         FIELD_PREP(SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN, x)
1848 #define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_GET(x)\
1849         FIELD_GET(SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN, x)
1850
1851 #define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0     GENMASK(6, 4)
1852 #define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(x)\
1853         FIELD_PREP(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, x)
1854 #define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_GET(x)\
1855         FIELD_GET(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, x)
1856
1857 /* SPARX5 ONLY */
1858 /* SD25G_TARGET:LANE_GRP_0:LANE_1B */
1859 #define SD25G_LANE_LANE_1B(t)                                                  \
1860         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 108, 0, 1, 4)
1861
1862 #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0      GENMASK(7, 0)
1863 #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(x)\
1864         FIELD_PREP(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, x)
1865 #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_GET(x)\
1866         FIELD_GET(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, x)
1867
1868 /* SPARX5 ONLY */
1869 /* SD25G_TARGET:LANE_GRP_0:LANE_1C */
1870 #define SD25G_LANE_LANE_1C(t)                                                  \
1871         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 112, 0, 1, 4)
1872
1873 #define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN       BIT(0)
1874 #define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(x)\
1875         FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, x)
1876 #define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_GET(x)\
1877         FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, x)
1878
1879 #define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD         BIT(1)
1880 #define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_SET(x)\
1881         FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_DFE_PD, x)
1882 #define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_GET(x)\
1883         FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_DFE_PD, x)
1884
1885 #define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD      BIT(2)
1886 #define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_SET(x)\
1887         FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD, x)
1888 #define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_GET(x)\
1889         FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD, x)
1890
1891 #define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0  GENMASK(7, 4)
1892 #define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_SET(x)\
1893         FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0, x)
1894 #define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_GET(x)\
1895         FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0, x)
1896
1897 /* SPARX5 ONLY */
1898 /* SD25G_TARGET:LANE_GRP_0:LANE_1D */
1899 #define SD25G_LANE_LANE_1D(t)                                                  \
1900         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 116, 0, 1, 4)
1901
1902 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR  BIT(0)
1903 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_SET(x)\
1904         FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR, x)
1905 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_GET(x)\
1906         FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR, x)
1907
1908 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD     BIT(1)
1909 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_SET(x)\
1910         FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD, x)
1911 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_GET(x)\
1912         FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD, x)
1913
1914 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN     BIT(2)
1915 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_SET(x)\
1916         FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN, x)
1917 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_GET(x)\
1918         FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN, x)
1919
1920 #define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP   BIT(3)
1921 #define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_SET(x)\
1922         FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP, x)
1923 #define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_GET(x)\
1924         FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP, x)
1925
1926 #define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T        BIT(4)
1927 #define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_SET(x)\
1928         FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PHID_1T, x)
1929 #define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_GET(x)\
1930         FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PHID_1T, x)
1931
1932 #define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN      BIT(5)
1933 #define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(x)\
1934         FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN, x)
1935 #define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_GET(x)\
1936         FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN, x)
1937
1938 #define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR     BIT(6)
1939 #define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_SET(x)\
1940         FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR, x)
1941 #define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_GET(x)\
1942         FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR, x)
1943
1944 #define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD        BIT(7)
1945 #define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_SET(x)\
1946         FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD, x)
1947 #define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_GET(x)\
1948         FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD, x)
1949
1950 /* SPARX5 ONLY */
1951 /* SD25G_TARGET:LANE_GRP_0:LANE_1E */
1952 #define SD25G_LANE_LANE_1E(t)                                                  \
1953         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 120, 0, 1, 4)
1954
1955 #define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0   GENMASK(1, 0)
1956 #define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_SET(x)\
1957         FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0, x)
1958 #define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_GET(x)\
1959         FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0, x)
1960
1961 #define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN        BIT(4)
1962 #define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(x)\
1963         FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN, x)
1964 #define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_GET(x)\
1965         FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN, x)
1966
1967 #define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN   BIT(5)
1968 #define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_SET(x)\
1969         FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN, x)
1970 #define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_GET(x)\
1971         FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN, x)
1972
1973 #define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR   BIT(6)
1974 #define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_SET(x)\
1975         FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR, x)
1976 #define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_GET(x)\
1977         FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR, x)
1978
1979 #define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD     BIT(7)
1980 #define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_SET(x)\
1981         FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD, x)
1982 #define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_GET(x)\
1983         FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD, x)
1984
1985 /* SPARX5 ONLY */
1986 /* SD25G_TARGET:LANE_GRP_0:LANE_21 */
1987 #define SD25G_LANE_LANE_21(t)                                                  \
1988         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 132, 0, 1, 4)
1989
1990 #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0 GENMASK(4, 0)
1991 #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_SET(x)\
1992         FIELD_PREP(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, x)
1993 #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_GET(x)\
1994         FIELD_GET(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, x)
1995
1996 /* SPARX5 ONLY */
1997 /* SD25G_TARGET:LANE_GRP_0:LANE_22 */
1998 #define SD25G_LANE_LANE_22(t)                                                  \
1999         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 136, 0, 1, 4)
2000
2001 #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0  GENMASK(3, 0)
2002 #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_SET(x)\
2003         FIELD_PREP(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, x)
2004 #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_GET(x)\
2005         FIELD_GET(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, x)
2006
2007 /* SPARX5 ONLY */
2008 /* SD25G_TARGET:LANE_GRP_0:LANE_25 */
2009 #define SD25G_LANE_LANE_25(t)                                                  \
2010         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 148, 0, 1, 4)
2011
2012 #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0 GENMASK(6, 0)
2013 #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_SET(x)\
2014         FIELD_PREP(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, x)
2015 #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_GET(x)\
2016         FIELD_GET(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, x)
2017
2018 /* SPARX5 ONLY */
2019 /* SD25G_TARGET:LANE_GRP_0:LANE_26 */
2020 #define SD25G_LANE_LANE_26(t)                                                  \
2021         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 152, 0, 1, 4)
2022
2023 #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0 GENMASK(6, 0)
2024 #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_SET(x)\
2025         FIELD_PREP(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, x)
2026 #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_GET(x)\
2027         FIELD_GET(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, x)
2028
2029 /* SPARX5 ONLY */
2030 /* SD25G_TARGET:LANE_GRP_0:LANE_28 */
2031 #define SD25G_LANE_LANE_28(t)                                                  \
2032         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 160, 0, 1, 4)
2033
2034 #define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN  BIT(0)
2035 #define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_SET(x)\
2036         FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN, x)
2037 #define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_GET(x)\
2038         FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN, x)
2039
2040 #define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH      BIT(1)
2041 #define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_SET(x)\
2042         FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH, x)
2043 #define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_GET(x)\
2044         FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH, x)
2045
2046 #define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL   BIT(2)
2047 #define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_SET(x)\
2048         FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL, x)
2049 #define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_GET(x)\
2050         FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL, x)
2051
2052 #define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0 GENMASK(6, 4)
2053 #define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_SET(x)\
2054         FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, x)
2055 #define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_GET(x)\
2056         FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, x)
2057
2058 /* SPARX5 ONLY */
2059 /* SD25G_TARGET:LANE_GRP_0:LANE_2B */
2060 #define SD25G_LANE_LANE_2B(t)                                                  \
2061         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 172, 0, 1, 4)
2062
2063 #define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0      GENMASK(3, 0)
2064 #define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(x)\
2065         FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0, x)
2066 #define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_GET(x)\
2067         FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0, x)
2068
2069 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR BIT(4)
2070 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_SET(x)\
2071         FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR, x)
2072 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_GET(x)\
2073         FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR, x)
2074
2075 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU    BIT(5)
2076 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_SET(x)\
2077         FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU, x)
2078 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_GET(x)\
2079         FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU, x)
2080
2081 /* SPARX5 ONLY */
2082 /* SD25G_TARGET:LANE_GRP_0:LANE_2C */
2083 #define SD25G_LANE_LANE_2C(t)                                                  \
2084         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 176, 0, 1, 4)
2085
2086 #define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0 GENMASK(2, 0)
2087 #define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_SET(x)\
2088         FIELD_PREP(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0, x)
2089 #define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_GET(x)\
2090         FIELD_GET(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0, x)
2091
2092 #define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER   BIT(4)
2093 #define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_SET(x)\
2094         FIELD_PREP(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, x)
2095 #define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_GET(x)\
2096         FIELD_GET(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, x)
2097
2098 /* SPARX5 ONLY */
2099 /* SD25G_TARGET:LANE_GRP_0:LANE_2D */
2100 #define SD25G_LANE_LANE_2D(t)                                                  \
2101         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 180, 0, 1, 4)
2102
2103 #define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0   GENMASK(2, 0)
2104 #define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_SET(x)\
2105         FIELD_PREP(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0, x)
2106 #define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_GET(x)\
2107         FIELD_GET(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0, x)
2108
2109 #define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0 GENMASK(6, 4)
2110 #define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_SET(x)\
2111         FIELD_PREP(SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0, x)
2112 #define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_GET(x)\
2113         FIELD_GET(SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0, x)
2114
2115 /* SPARX5 ONLY */
2116 /* SD25G_TARGET:LANE_GRP_0:LANE_2E */
2117 #define SD25G_LANE_LANE_2E(t)                                                  \
2118         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 184, 0, 1, 4)
2119
2120 #define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN  BIT(0)
2121 #define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_SET(x)\
2122         FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN, x)
2123 #define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_GET(x)\
2124         FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN, x)
2125
2126 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ         BIT(1)
2127 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_SET(x)\
2128         FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ, x)
2129 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_GET(x)\
2130         FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ, x)
2131
2132 #define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ          BIT(2)
2133 #define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_SET(x)\
2134         FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ, x)
2135 #define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_GET(x)\
2136         FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ, x)
2137
2138 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS       BIT(3)
2139 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_SET(x)\
2140         FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS, x)
2141 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_GET(x)\
2142         FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS, x)
2143
2144 #define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC     BIT(4)
2145 #define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_SET(x)\
2146         FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC, x)
2147 #define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_GET(x)\
2148         FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC, x)
2149
2150 #define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG    BIT(5)
2151 #define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(x)\
2152         FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, x)
2153 #define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_GET(x)\
2154         FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, x)
2155
2156 #define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN        BIT(6)
2157 #define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_SET(x)\
2158         FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN, x)
2159 #define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_GET(x)\
2160         FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN, x)
2161
2162 #define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN      BIT(7)
2163 #define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(x)\
2164         FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, x)
2165 #define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_GET(x)\
2166         FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, x)
2167
2168 /* SPARX5 ONLY */
2169 /* SD25G_TARGET:LANE_GRP_0:LANE_40 */
2170 #define SD25G_LANE_LANE_40(t)                                                  \
2171         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 256, 0, 1, 4)
2172
2173 #define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE   BIT(0)
2174 #define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_SET(x)\
2175         FIELD_PREP(SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE, x)
2176 #define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_GET(x)\
2177         FIELD_GET(SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE, x)
2178
2179 #define SD25G_LANE_LANE_40_LN_R_TX_POL_INV       BIT(1)
2180 #define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(x)\
2181         FIELD_PREP(SD25G_LANE_LANE_40_LN_R_TX_POL_INV, x)
2182 #define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_GET(x)\
2183         FIELD_GET(SD25G_LANE_LANE_40_LN_R_TX_POL_INV, x)
2184
2185 #define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE   BIT(2)
2186 #define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_SET(x)\
2187         FIELD_PREP(SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE, x)
2188 #define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_GET(x)\
2189         FIELD_GET(SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE, x)
2190
2191 #define SD25G_LANE_LANE_40_LN_R_RX_POL_INV       BIT(3)
2192 #define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_SET(x)\
2193         FIELD_PREP(SD25G_LANE_LANE_40_LN_R_RX_POL_INV, x)
2194 #define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_GET(x)\
2195         FIELD_GET(SD25G_LANE_LANE_40_LN_R_RX_POL_INV, x)
2196
2197 #define SD25G_LANE_LANE_40_LN_R_CDR_RSTN         BIT(4)
2198 #define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_SET(x)\
2199         FIELD_PREP(SD25G_LANE_LANE_40_LN_R_CDR_RSTN, x)
2200 #define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_GET(x)\
2201         FIELD_GET(SD25G_LANE_LANE_40_LN_R_CDR_RSTN, x)
2202
2203 #define SD25G_LANE_LANE_40_LN_R_DFE_RSTN         BIT(5)
2204 #define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_SET(x)\
2205         FIELD_PREP(SD25G_LANE_LANE_40_LN_R_DFE_RSTN, x)
2206 #define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_GET(x)\
2207         FIELD_GET(SD25G_LANE_LANE_40_LN_R_DFE_RSTN, x)
2208
2209 #define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN        BIT(6)
2210 #define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_SET(x)\
2211         FIELD_PREP(SD25G_LANE_LANE_40_LN_R_CTLE_RSTN, x)
2212 #define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_GET(x)\
2213         FIELD_GET(SD25G_LANE_LANE_40_LN_R_CTLE_RSTN, x)
2214
2215 /* SPARX5 ONLY */
2216 /* SD25G_TARGET:LANE_GRP_0:LANE_42 */
2217 #define SD25G_LANE_LANE_42(t)                                                  \
2218         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 264, 0, 1, 4)
2219
2220 #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0 GENMASK(7, 0)
2221 #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_SET(x)\
2222         FIELD_PREP(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, x)
2223 #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_GET(x)\
2224         FIELD_GET(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, x)
2225
2226 /* SPARX5 ONLY */
2227 /* SD25G_TARGET:LANE_GRP_0:LANE_43 */
2228 #define SD25G_LANE_LANE_43(t)                                                  \
2229         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 268, 0, 1, 4)
2230
2231 #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8 GENMASK(7, 0)
2232 #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_SET(x)\
2233         FIELD_PREP(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, x)
2234 #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_GET(x)\
2235         FIELD_GET(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, x)
2236
2237 /* SPARX5 ONLY */
2238 /* SD25G_TARGET:LANE_GRP_0:LANE_44 */
2239 #define SD25G_LANE_LANE_44(t)                                                  \
2240         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 272, 0, 1, 4)
2241
2242 #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0 GENMASK(7, 0)
2243 #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_SET(x)\
2244         FIELD_PREP(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, x)
2245 #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_GET(x)\
2246         FIELD_GET(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, x)
2247
2248 /* SPARX5 ONLY */
2249 /* SD25G_TARGET:LANE_GRP_0:LANE_45 */
2250 #define SD25G_LANE_LANE_45(t)                                                  \
2251         __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 276, 0, 1, 4)
2252
2253 #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8 GENMASK(7, 0)
2254 #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_SET(x)\
2255         FIELD_PREP(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, x)
2256 #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_GET(x)\
2257         FIELD_GET(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, x)
2258
2259 /* SPARX5 ONLY */
2260 /* SD25G_TARGET:LANE_GRP_1:LANE_DE */
2261 #define SD25G_LANE_LANE_DE(t)                                                  \
2262         __REG(TARGET_SD25G_LANE, t, 8, 1792, 0, 1, 128, 120, 0, 1, 4)
2263
2264 #define SD25G_LANE_LANE_DE_LN_LOL_UDL            BIT(0)
2265 #define SD25G_LANE_LANE_DE_LN_LOL_UDL_SET(x)\
2266         FIELD_PREP(SD25G_LANE_LANE_DE_LN_LOL_UDL, x)
2267 #define SD25G_LANE_LANE_DE_LN_LOL_UDL_GET(x)\
2268         FIELD_GET(SD25G_LANE_LANE_DE_LN_LOL_UDL, x)
2269
2270 #define SD25G_LANE_LANE_DE_LN_LOL                BIT(1)
2271 #define SD25G_LANE_LANE_DE_LN_LOL_SET(x)\
2272         FIELD_PREP(SD25G_LANE_LANE_DE_LN_LOL, x)
2273 #define SD25G_LANE_LANE_DE_LN_LOL_GET(x)\
2274         FIELD_GET(SD25G_LANE_LANE_DE_LN_LOL, x)
2275
2276 #define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED BIT(2)
2277 #define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_SET(x)\
2278         FIELD_PREP(SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED, x)
2279 #define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_GET(x)\
2280         FIELD_GET(SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED, x)
2281
2282 #define SD25G_LANE_LANE_DE_LN_PMA_RXEI           BIT(3)
2283 #define SD25G_LANE_LANE_DE_LN_PMA_RXEI_SET(x)\
2284         FIELD_PREP(SD25G_LANE_LANE_DE_LN_PMA_RXEI, x)
2285 #define SD25G_LANE_LANE_DE_LN_PMA_RXEI_GET(x)\
2286         FIELD_GET(SD25G_LANE_LANE_DE_LN_PMA_RXEI, x)
2287
2288 /* SPARX5 ONLY */
2289 /* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */
2290 #define SD6G_LANE_LANE_DF(t)                                                   \
2291         __REG(TARGET_SD6G_LANE, t, 13, 832, 0, 1, 84, 60, 0, 1, 4)
2292
2293 #define SD6G_LANE_LANE_DF_LOL_UDL                BIT(0)
2294 #define SD6G_LANE_LANE_DF_LOL_UDL_SET(x)\
2295         FIELD_PREP(SD6G_LANE_LANE_DF_LOL_UDL, x)
2296 #define SD6G_LANE_LANE_DF_LOL_UDL_GET(x)\
2297         FIELD_GET(SD6G_LANE_LANE_DF_LOL_UDL, x)
2298
2299 #define SD6G_LANE_LANE_DF_LOL                    BIT(1)
2300 #define SD6G_LANE_LANE_DF_LOL_SET(x)\
2301         FIELD_PREP(SD6G_LANE_LANE_DF_LOL, x)
2302 #define SD6G_LANE_LANE_DF_LOL_GET(x)\
2303         FIELD_GET(SD6G_LANE_LANE_DF_LOL, x)
2304
2305 #define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED  BIT(2)
2306 #define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\
2307         FIELD_PREP(SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
2308 #define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\
2309         FIELD_GET(SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
2310
2311 #define SD6G_LANE_LANE_DF_SQUELCH                BIT(3)
2312 #define SD6G_LANE_LANE_DF_SQUELCH_SET(x)\
2313         FIELD_PREP(SD6G_LANE_LANE_DF_SQUELCH, x)
2314 #define SD6G_LANE_LANE_DF_SQUELCH_GET(x)\
2315         FIELD_GET(SD6G_LANE_LANE_DF_SQUELCH, x)
2316
2317 /* SD10G_CMU_TARGET:CMU_GRP_0:CMU_00 */
2318 #define SD_CMU_CMU_00(t)                                                       \
2319         __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 0, 0, 1, 20, 0, 0, 1, 4)
2320
2321 #define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE      BIT(0)
2322 #define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_SET(x)\
2323         FIELD_PREP(SD_CMU_CMU_00_R_HWT_SIMULATION_MODE, x)
2324 #define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_GET(x)\
2325         FIELD_GET(SD_CMU_CMU_00_R_HWT_SIMULATION_MODE, x)
2326
2327 #define SD_CMU_CMU_00_CFG_PLL_LOL_SET            BIT(1)
2328 #define SD_CMU_CMU_00_CFG_PLL_LOL_SET_SET(x)\
2329         FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_LOL_SET, x)
2330 #define SD_CMU_CMU_00_CFG_PLL_LOL_SET_GET(x)\
2331         FIELD_GET(SD_CMU_CMU_00_CFG_PLL_LOL_SET, x)
2332
2333 #define SD_CMU_CMU_00_CFG_PLL_LOS_SET            BIT(2)
2334 #define SD_CMU_CMU_00_CFG_PLL_LOS_SET_SET(x)\
2335         FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_LOS_SET, x)
2336 #define SD_CMU_CMU_00_CFG_PLL_LOS_SET_GET(x)\
2337         FIELD_GET(SD_CMU_CMU_00_CFG_PLL_LOS_SET, x)
2338
2339 #define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0         GENMASK(5, 4)
2340 #define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(x)\
2341         FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, x)
2342 #define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_GET(x)\
2343         FIELD_GET(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, x)
2344
2345 /* SD10G_CMU_TARGET:CMU_GRP_1:CMU_05 */
2346 #define SD_CMU_CMU_05(t)                                                       \
2347         __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 0, 0, 1, 4)
2348
2349 #define SD_CMU_CMU_05_CFG_REFCK_TERM_EN          BIT(0)
2350 #define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(x)\
2351         FIELD_PREP(SD_CMU_CMU_05_CFG_REFCK_TERM_EN, x)
2352 #define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_GET(x)\
2353         FIELD_GET(SD_CMU_CMU_05_CFG_REFCK_TERM_EN, x)
2354
2355 #define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0        GENMASK(5, 4)
2356 #define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_SET(x)\
2357         FIELD_PREP(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x)
2358 #define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_GET(x)\
2359         FIELD_GET(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x)
2360
2361 /* SD10G_CMU_TARGET:CMU_GRP_1:CMU_06 */
2362 #define SD_CMU_CMU_06(t)                                                       \
2363         __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 4, 0, 1, 4)
2364
2365 #define SD_CMU_CMU_06_CFG_DISLOS                 BIT(0)
2366 #define SD_CMU_CMU_06_CFG_DISLOS_SET(x)\
2367         FIELD_PREP(SD_CMU_CMU_06_CFG_DISLOS, x)
2368 #define SD_CMU_CMU_06_CFG_DISLOS_GET(x)\
2369         FIELD_GET(SD_CMU_CMU_06_CFG_DISLOS, x)
2370
2371 #define SD_CMU_CMU_06_CFG_DISLOL                 BIT(1)
2372 #define SD_CMU_CMU_06_CFG_DISLOL_SET(x)\
2373         FIELD_PREP(SD_CMU_CMU_06_CFG_DISLOL, x)
2374 #define SD_CMU_CMU_06_CFG_DISLOL_GET(x)\
2375         FIELD_GET(SD_CMU_CMU_06_CFG_DISLOL, x)
2376
2377 #define SD_CMU_CMU_06_CFG_DCLOL                  BIT(2)
2378 #define SD_CMU_CMU_06_CFG_DCLOL_SET(x)\
2379         FIELD_PREP(SD_CMU_CMU_06_CFG_DCLOL, x)
2380 #define SD_CMU_CMU_06_CFG_DCLOL_GET(x)\
2381         FIELD_GET(SD_CMU_CMU_06_CFG_DCLOL, x)
2382
2383 #define SD_CMU_CMU_06_CFG_FORCE_RX_FILT          BIT(3)
2384 #define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_SET(x)\
2385         FIELD_PREP(SD_CMU_CMU_06_CFG_FORCE_RX_FILT, x)
2386 #define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_GET(x)\
2387         FIELD_GET(SD_CMU_CMU_06_CFG_FORCE_RX_FILT, x)
2388
2389 #define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD          BIT(4)
2390 #define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_SET(x)\
2391         FIELD_PREP(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, x)
2392 #define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_GET(x)\
2393         FIELD_GET(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, x)
2394
2395 #define SD_CMU_CMU_06_CFG_VCO_PD                 BIT(5)
2396 #define SD_CMU_CMU_06_CFG_VCO_PD_SET(x)\
2397         FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_PD, x)
2398 #define SD_CMU_CMU_06_CFG_VCO_PD_GET(x)\
2399         FIELD_GET(SD_CMU_CMU_06_CFG_VCO_PD, x)
2400
2401 #define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN         BIT(6)
2402 #define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_SET(x)\
2403         FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_CAL_RESETN, x)
2404 #define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_GET(x)\
2405         FIELD_GET(SD_CMU_CMU_06_CFG_VCO_CAL_RESETN, x)
2406
2407 #define SD_CMU_CMU_06_CFG_VCO_CAL_BYP            BIT(7)
2408 #define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_SET(x)\
2409         FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_CAL_BYP, x)
2410 #define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_GET(x)\
2411         FIELD_GET(SD_CMU_CMU_06_CFG_VCO_CAL_BYP, x)
2412
2413 /* SD10G_CMU_TARGET:CMU_GRP_1:CMU_08 */
2414 #define SD_CMU_CMU_08(t)                                                       \
2415         __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 12, 0, 1, 4)
2416
2417 #define SD_CMU_CMU_08_CFG_VFILT2PAD              BIT(0)
2418 #define SD_CMU_CMU_08_CFG_VFILT2PAD_SET(x)\
2419         FIELD_PREP(SD_CMU_CMU_08_CFG_VFILT2PAD, x)
2420 #define SD_CMU_CMU_08_CFG_VFILT2PAD_GET(x)\
2421         FIELD_GET(SD_CMU_CMU_08_CFG_VFILT2PAD, x)
2422
2423 #define SD_CMU_CMU_08_CFG_EN_DUMMY               BIT(1)
2424 #define SD_CMU_CMU_08_CFG_EN_DUMMY_SET(x)\
2425         FIELD_PREP(SD_CMU_CMU_08_CFG_EN_DUMMY, x)
2426 #define SD_CMU_CMU_08_CFG_EN_DUMMY_GET(x)\
2427         FIELD_GET(SD_CMU_CMU_08_CFG_EN_DUMMY, x)
2428
2429 #define SD_CMU_CMU_08_CFG_CK_TREE_PD             BIT(2)
2430 #define SD_CMU_CMU_08_CFG_CK_TREE_PD_SET(x)\
2431         FIELD_PREP(SD_CMU_CMU_08_CFG_CK_TREE_PD, x)
2432 #define SD_CMU_CMU_08_CFG_CK_TREE_PD_GET(x)\
2433         FIELD_GET(SD_CMU_CMU_08_CFG_CK_TREE_PD, x)
2434
2435 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN        BIT(3)
2436 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_SET(x)\
2437         FIELD_PREP(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN, x)
2438 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_GET(x)\
2439         FIELD_GET(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN, x)
2440
2441 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN     BIT(4)
2442 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_SET(x)\
2443         FIELD_PREP(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN, x)
2444 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_GET(x)\
2445         FIELD_GET(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN, x)
2446
2447 /* SD10G_CMU_TARGET:CMU_GRP_1:CMU_09 */
2448 #define SD_CMU_CMU_09(t)                                                       \
2449         __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 16, 0, 1, 4)
2450
2451 #define SD_CMU_CMU_09_CFG_EN_TX_CK_UP            BIT(0)
2452 #define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(x)\
2453         FIELD_PREP(SD_CMU_CMU_09_CFG_EN_TX_CK_UP, x)
2454 #define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_GET(x)\
2455         FIELD_GET(SD_CMU_CMU_09_CFG_EN_TX_CK_UP, x)
2456
2457 #define SD_CMU_CMU_09_CFG_EN_TX_CK_DN            BIT(1)
2458 #define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_SET(x)\
2459         FIELD_PREP(SD_CMU_CMU_09_CFG_EN_TX_CK_DN, x)
2460 #define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_GET(x)\
2461         FIELD_GET(SD_CMU_CMU_09_CFG_EN_TX_CK_DN, x)
2462
2463 #define SD_CMU_CMU_09_CFG_SW_8G                  BIT(4)
2464 #define SD_CMU_CMU_09_CFG_SW_8G_SET(x)\
2465         FIELD_PREP(SD_CMU_CMU_09_CFG_SW_8G, x)
2466 #define SD_CMU_CMU_09_CFG_SW_8G_GET(x)\
2467         FIELD_GET(SD_CMU_CMU_09_CFG_SW_8G, x)
2468
2469 #define SD_CMU_CMU_09_CFG_SW_10G                 BIT(5)
2470 #define SD_CMU_CMU_09_CFG_SW_10G_SET(x)\
2471         FIELD_PREP(SD_CMU_CMU_09_CFG_SW_10G, x)
2472 #define SD_CMU_CMU_09_CFG_SW_10G_GET(x)\
2473         FIELD_GET(SD_CMU_CMU_09_CFG_SW_10G, x)
2474
2475 /* SD10G_CMU_TARGET:CMU_GRP_1:CMU_0D */
2476 #define SD_CMU_CMU_0D(t)                                                       \
2477         __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 32, 0, 1, 4)
2478
2479 #define SD_CMU_CMU_0D_CFG_PD_DIV64               BIT(0)
2480 #define SD_CMU_CMU_0D_CFG_PD_DIV64_SET(x)\
2481         FIELD_PREP(SD_CMU_CMU_0D_CFG_PD_DIV64, x)
2482 #define SD_CMU_CMU_0D_CFG_PD_DIV64_GET(x)\
2483         FIELD_GET(SD_CMU_CMU_0D_CFG_PD_DIV64, x)
2484
2485 #define SD_CMU_CMU_0D_CFG_PD_DIV66               BIT(1)
2486 #define SD_CMU_CMU_0D_CFG_PD_DIV66_SET(x)\
2487         FIELD_PREP(SD_CMU_CMU_0D_CFG_PD_DIV66, x)
2488 #define SD_CMU_CMU_0D_CFG_PD_DIV66_GET(x)\
2489         FIELD_GET(SD_CMU_CMU_0D_CFG_PD_DIV66, x)
2490
2491 #define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD           BIT(2)
2492 #define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(x)\
2493         FIELD_PREP(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, x)
2494 #define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_GET(x)\
2495         FIELD_GET(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, x)
2496
2497 #define SD_CMU_CMU_0D_CFG_JC_BYP                 BIT(3)
2498 #define SD_CMU_CMU_0D_CFG_JC_BYP_SET(x)\
2499         FIELD_PREP(SD_CMU_CMU_0D_CFG_JC_BYP, x)
2500 #define SD_CMU_CMU_0D_CFG_JC_BYP_GET(x)\
2501         FIELD_GET(SD_CMU_CMU_0D_CFG_JC_BYP, x)
2502
2503 #define SD_CMU_CMU_0D_CFG_REFCK_PD               BIT(4)
2504 #define SD_CMU_CMU_0D_CFG_REFCK_PD_SET(x)\
2505         FIELD_PREP(SD_CMU_CMU_0D_CFG_REFCK_PD, x)
2506 #define SD_CMU_CMU_0D_CFG_REFCK_PD_GET(x)\
2507         FIELD_GET(SD_CMU_CMU_0D_CFG_REFCK_PD, x)
2508
2509 /* SD10G_CMU_TARGET:CMU_GRP_3:CMU_1B */
2510 #define SD_CMU_CMU_1B(t)                                                       \
2511         __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 104, 0, 1, 20, 4, 0, 1, 4)
2512
2513 #define SD_CMU_CMU_1B_CFG_RESERVE_7_0            GENMASK(7, 0)
2514 #define SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(x)\
2515         FIELD_PREP(SD_CMU_CMU_1B_CFG_RESERVE_7_0, x)
2516 #define SD_CMU_CMU_1B_CFG_RESERVE_7_0_GET(x)\
2517         FIELD_GET(SD_CMU_CMU_1B_CFG_RESERVE_7_0, x)
2518
2519 /* SD10G_CMU_TARGET:CMU_GRP_4:CMU_1F */
2520 #define SD_CMU_CMU_1F(t)                                                       \
2521         __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 124, 0, 1, 68, 0, 0, 1, 4)
2522
2523 #define SD_CMU_CMU_1F_CFG_BIAS_DN_EN             BIT(0)
2524 #define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_SET(x)\
2525         FIELD_PREP(SD_CMU_CMU_1F_CFG_BIAS_DN_EN, x)
2526 #define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_GET(x)\
2527         FIELD_GET(SD_CMU_CMU_1F_CFG_BIAS_DN_EN, x)
2528
2529 #define SD_CMU_CMU_1F_CFG_BIAS_UP_EN             BIT(1)
2530 #define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_SET(x)\
2531         FIELD_PREP(SD_CMU_CMU_1F_CFG_BIAS_UP_EN, x)
2532 #define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_GET(x)\
2533         FIELD_GET(SD_CMU_CMU_1F_CFG_BIAS_UP_EN, x)
2534
2535 #define SD_CMU_CMU_1F_CFG_IC2IP_N                BIT(2)
2536 #define SD_CMU_CMU_1F_CFG_IC2IP_N_SET(x)\
2537         FIELD_PREP(SD_CMU_CMU_1F_CFG_IC2IP_N, x)
2538 #define SD_CMU_CMU_1F_CFG_IC2IP_N_GET(x)\
2539         FIELD_GET(SD_CMU_CMU_1F_CFG_IC2IP_N, x)
2540
2541 #define SD_CMU_CMU_1F_CFG_VTUNE_SEL              BIT(3)
2542 #define SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(x)\
2543         FIELD_PREP(SD_CMU_CMU_1F_CFG_VTUNE_SEL, x)
2544 #define SD_CMU_CMU_1F_CFG_VTUNE_SEL_GET(x)\
2545         FIELD_GET(SD_CMU_CMU_1F_CFG_VTUNE_SEL, x)
2546
2547 /* SD10G_CMU_TARGET:CMU_GRP_5:CMU_30 */
2548 #define SD_CMU_CMU_30(t)                                                       \
2549         __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 192, 0, 1, 72, 0, 0, 1, 4)
2550
2551 #define SD_CMU_CMU_30_R_PLL_DLOL_EN              BIT(0)
2552 #define SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(x)\
2553         FIELD_PREP(SD_CMU_CMU_30_R_PLL_DLOL_EN, x)
2554 #define SD_CMU_CMU_30_R_PLL_DLOL_EN_GET(x)\
2555         FIELD_GET(SD_CMU_CMU_30_R_PLL_DLOL_EN, x)
2556
2557 /* SD10G_CMU_TARGET:CMU_GRP_6:CMU_44 */
2558 #define SD_CMU_CMU_44(t)                                                       \
2559         __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 8, 0, 1, 4)
2560
2561 #define SD_CMU_CMU_44_R_PLL_RSTN                 BIT(0)
2562 #define SD_CMU_CMU_44_R_PLL_RSTN_SET(x)\
2563         FIELD_PREP(SD_CMU_CMU_44_R_PLL_RSTN, x)
2564 #define SD_CMU_CMU_44_R_PLL_RSTN_GET(x)\
2565         FIELD_GET(SD_CMU_CMU_44_R_PLL_RSTN, x)
2566
2567 #define SD_CMU_CMU_44_R_CK_RESETB                BIT(1)
2568 #define SD_CMU_CMU_44_R_CK_RESETB_SET(x)\
2569         FIELD_PREP(SD_CMU_CMU_44_R_CK_RESETB, x)
2570 #define SD_CMU_CMU_44_R_CK_RESETB_GET(x)\
2571         FIELD_GET(SD_CMU_CMU_44_R_CK_RESETB, x)
2572
2573 /* SD10G_CMU_TARGET:CMU_GRP_6:CMU_45 */
2574 #define SD_CMU_CMU_45(t)                                                       \
2575         __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 12, 0, 1, 4)
2576
2577 #define SD_CMU_CMU_45_R_EN_RATECHG_CTRL          BIT(0)
2578 #define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(x)\
2579         FIELD_PREP(SD_CMU_CMU_45_R_EN_RATECHG_CTRL, x)
2580 #define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_GET(x)\
2581         FIELD_GET(SD_CMU_CMU_45_R_EN_RATECHG_CTRL, x)
2582
2583 #define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT      BIT(1)
2584 #define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(x)\
2585         FIELD_PREP(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT, x)
2586 #define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_GET(x)\
2587         FIELD_GET(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT, x)
2588
2589 #define SD_CMU_CMU_45_RESERVED                   BIT(2)
2590 #define SD_CMU_CMU_45_RESERVED_SET(x)\
2591         FIELD_PREP(SD_CMU_CMU_45_RESERVED, x)
2592 #define SD_CMU_CMU_45_RESERVED_GET(x)\
2593         FIELD_GET(SD_CMU_CMU_45_RESERVED, x)
2594
2595 #define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT    BIT(3)
2596 #define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(x)\
2597         FIELD_PREP(SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT, x)
2598 #define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_GET(x)\
2599         FIELD_GET(SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT, x)
2600
2601 #define SD_CMU_CMU_45_RESERVED_2                 BIT(4)
2602 #define SD_CMU_CMU_45_RESERVED_2_SET(x)\
2603         FIELD_PREP(SD_CMU_CMU_45_RESERVED_2, x)
2604 #define SD_CMU_CMU_45_RESERVED_2_GET(x)\
2605         FIELD_GET(SD_CMU_CMU_45_RESERVED_2, x)
2606
2607 #define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT     BIT(5)
2608 #define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(x)\
2609         FIELD_PREP(SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT, x)
2610 #define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_GET(x)\
2611         FIELD_GET(SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT, x)
2612
2613 #define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT         BIT(6)
2614 #define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(x)\
2615         FIELD_PREP(SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT, x)
2616 #define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_GET(x)\
2617         FIELD_GET(SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT, x)
2618
2619 #define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN     BIT(7)
2620 #define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_SET(x)\
2621         FIELD_PREP(SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN, x)
2622 #define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_GET(x)\
2623         FIELD_GET(SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN, x)
2624
2625 /* SD10G_CMU_TARGET:CMU_GRP_6:CMU_47 */
2626 #define SD_CMU_CMU_47(t)                                                       \
2627         __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 20, 0, 1, 4)
2628
2629 #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0      GENMASK(4, 0)
2630 #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(x)\
2631         FIELD_PREP(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, x)
2632 #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_GET(x)\
2633         FIELD_GET(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, x)
2634
2635 /* SD10G_CMU_TARGET:CMU_GRP_7:CMU_E0 */
2636 #define SD_CMU_CMU_E0(t)                                                       \
2637         __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 896, 0, 1, 8, 0, 0, 1, 4)
2638
2639 #define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0         GENMASK(3, 0)
2640 #define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_SET(x)\
2641         FIELD_PREP(SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0, x)
2642 #define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_GET(x)\
2643         FIELD_GET(SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0, x)
2644
2645 #define SD_CMU_CMU_E0_PLL_LOL_UDL                BIT(4)
2646 #define SD_CMU_CMU_E0_PLL_LOL_UDL_SET(x)\
2647         FIELD_PREP(SD_CMU_CMU_E0_PLL_LOL_UDL, x)
2648 #define SD_CMU_CMU_E0_PLL_LOL_UDL_GET(x)\
2649         FIELD_GET(SD_CMU_CMU_E0_PLL_LOL_UDL, x)
2650
2651 /* SD_CMU_TARGET:SD_CMU_CFG:SD_CMU_CFG */
2652 #define SD_CMU_CFG_SD_CMU_CFG(t)                                               \
2653         __REG(TARGET_SD_CMU_CFG, t, TSIZE(TC_SD_CMU_CFG), 0, 0, 1, 8, 0, 0, 1, \
2654               4)
2655
2656 #define SD_CMU_CFG_SD_CMU_CFG_CMU_RST            BIT(0)
2657 #define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(x)\
2658         FIELD_PREP(SD_CMU_CFG_SD_CMU_CFG_CMU_RST, x)
2659 #define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_GET(x)\
2660         FIELD_GET(SD_CMU_CFG_SD_CMU_CFG_CMU_RST, x)
2661
2662 #define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST        BIT(1)
2663 #define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(x)\
2664         FIELD_PREP(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, x)
2665 #define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_GET(x)\
2666         FIELD_GET(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, x)
2667
2668 /* SD_LANE_TARGET:SD_RESET:SD_SER_RST */
2669 #define SD_LANE_SD_SER_RST(t)                                                  \
2670         __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 0, 0, 1, 8, 0, 0, 1, 4)
2671
2672 #define SD_LANE_SD_SER_RST_SER_RST               BIT(0)
2673 #define SD_LANE_SD_SER_RST_SER_RST_SET(x)\
2674         FIELD_PREP(SD_LANE_SD_SER_RST_SER_RST, x)
2675 #define SD_LANE_SD_SER_RST_SER_RST_GET(x)\
2676         FIELD_GET(SD_LANE_SD_SER_RST_SER_RST, x)
2677
2678 /* SD_LANE_TARGET:SD_RESET:SD_DES_RST */
2679 #define SD_LANE_SD_DES_RST(t)                                                  \
2680         __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 0, 0, 1, 8, 4, 0, 1, 4)
2681
2682 #define SD_LANE_SD_DES_RST_DES_RST               BIT(0)
2683 #define SD_LANE_SD_DES_RST_DES_RST_SET(x)\
2684         FIELD_PREP(SD_LANE_SD_DES_RST_DES_RST, x)
2685 #define SD_LANE_SD_DES_RST_DES_RST_GET(x)\
2686         FIELD_GET(SD_LANE_SD_DES_RST_DES_RST, x)
2687
2688 /* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */
2689 #define SD_LANE_SD_LANE_CFG(t)                                                 \
2690         __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 8, 0, 1, 8, 0, 0, 1, 4)
2691
2692 #define SD_LANE_SD_LANE_CFG_MACRO_RST            BIT(0)
2693 #define SD_LANE_SD_LANE_CFG_MACRO_RST_SET(x)\
2694         FIELD_PREP(SD_LANE_SD_LANE_CFG_MACRO_RST, x)
2695 #define SD_LANE_SD_LANE_CFG_MACRO_RST_GET(x)\
2696         FIELD_GET(SD_LANE_SD_LANE_CFG_MACRO_RST, x)
2697
2698 #define SD_LANE_SD_LANE_CFG_EXT_CFG_RST          BIT(1)
2699 #define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(x)\
2700         FIELD_PREP(SD_LANE_SD_LANE_CFG_EXT_CFG_RST, x)
2701 #define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_GET(x)\
2702         FIELD_GET(SD_LANE_SD_LANE_CFG_EXT_CFG_RST, x)
2703
2704 #define SD_LANE_SD_LANE_CFG_TX_REF_SEL           GENMASK(5, 4)
2705 #define SD_LANE_SD_LANE_CFG_TX_REF_SEL_SET(x)\
2706         FIELD_PREP(SD_LANE_SD_LANE_CFG_TX_REF_SEL, x)
2707 #define SD_LANE_SD_LANE_CFG_TX_REF_SEL_GET(x)\
2708         FIELD_GET(SD_LANE_SD_LANE_CFG_TX_REF_SEL, x)
2709
2710 #define SD_LANE_SD_LANE_CFG_RX_REF_SEL           GENMASK(7, 6)
2711 #define SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(x)\
2712         FIELD_PREP(SD_LANE_SD_LANE_CFG_RX_REF_SEL, x)
2713 #define SD_LANE_SD_LANE_CFG_RX_REF_SEL_GET(x)\
2714         FIELD_GET(SD_LANE_SD_LANE_CFG_RX_REF_SEL, x)
2715
2716 #define SD_LANE_SD_LANE_CFG_LANE_RST             BIT(8)
2717 #define SD_LANE_SD_LANE_CFG_LANE_RST_SET(x)\
2718         FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_RST, x)
2719 #define SD_LANE_SD_LANE_CFG_LANE_RST_GET(x)\
2720         FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_RST, x)
2721
2722 #define SD_LANE_SD_LANE_CFG_LANE_TX_RST          BIT(9)
2723 #define SD_LANE_SD_LANE_CFG_LANE_TX_RST_SET(x)\
2724         FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_TX_RST, x)
2725 #define SD_LANE_SD_LANE_CFG_LANE_TX_RST_GET(x)\
2726         FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_TX_RST, x)
2727
2728 #define SD_LANE_SD_LANE_CFG_LANE_RX_RST          BIT(10)
2729 #define SD_LANE_SD_LANE_CFG_LANE_RX_RST_SET(x)\
2730         FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_RX_RST, x)
2731 #define SD_LANE_SD_LANE_CFG_LANE_RX_RST_GET(x)\
2732         FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_RX_RST, x)
2733
2734 /* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */
2735 #define SD_LANE_SD_LANE_STAT(t)                                                \
2736         __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 8, 0, 1, 8, 4, 0, 1, 4)
2737
2738 #define SD_LANE_SD_LANE_STAT_PMA_RST_DONE        BIT(0)
2739 #define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_SET(x)\
2740         FIELD_PREP(SD_LANE_SD_LANE_STAT_PMA_RST_DONE, x)
2741 #define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_GET(x)\
2742         FIELD_GET(SD_LANE_SD_LANE_STAT_PMA_RST_DONE, x)
2743
2744 #define SD_LANE_SD_LANE_STAT_DFE_RST_DONE        BIT(1)
2745 #define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_SET(x)\
2746         FIELD_PREP(SD_LANE_SD_LANE_STAT_DFE_RST_DONE, x)
2747 #define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_GET(x)\
2748         FIELD_GET(SD_LANE_SD_LANE_STAT_DFE_RST_DONE, x)
2749
2750 #define SD_LANE_SD_LANE_STAT_DBG_OBS             GENMASK(31, 16)
2751 #define SD_LANE_SD_LANE_STAT_DBG_OBS_SET(x)\
2752         FIELD_PREP(SD_LANE_SD_LANE_STAT_DBG_OBS, x)
2753 #define SD_LANE_SD_LANE_STAT_DBG_OBS_GET(x)\
2754         FIELD_GET(SD_LANE_SD_LANE_STAT_DBG_OBS, x)
2755
2756 /* SD_LANE_TARGET:SD_PWR_CFG:QUIET_MODE_6G */
2757 #define SD_LANE_QUIET_MODE_6G(t)                                               \
2758         __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 24, 0, 1, 8, 4, 0, 1, 4)
2759
2760 #define SD_LANE_QUIET_MODE_6G_QUIET_MODE         GENMASK(24, 0)
2761 #define SD_LANE_QUIET_MODE_6G_QUIET_MODE_SET(x)\
2762         FIELD_PREP(SD_LANE_QUIET_MODE_6G_QUIET_MODE, x)
2763 #define SD_LANE_QUIET_MODE_6G_QUIET_MODE_GET(x)\
2764         FIELD_GET(SD_LANE_QUIET_MODE_6G_QUIET_MODE, x)
2765
2766 /* SD_LANE_TARGET:CFG_STAT_FX100:MISC */
2767 #define SD_LANE_MISC(t)                                                        \
2768         __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 56, 0, 1, 56, 0, 0, 1, 4)
2769
2770 #define SD_LANE_MISC_SD_125_RST_DIS              BIT(0)
2771 #define SD_LANE_MISC_SD_125_RST_DIS_SET(x)\
2772         FIELD_PREP(SD_LANE_MISC_SD_125_RST_DIS, x)
2773 #define SD_LANE_MISC_SD_125_RST_DIS_GET(x)\
2774         FIELD_GET(SD_LANE_MISC_SD_125_RST_DIS, x)
2775
2776 #define SD_LANE_MISC_RX_ENA                      BIT(1)
2777 #define SD_LANE_MISC_RX_ENA_SET(x)\
2778         FIELD_PREP(SD_LANE_MISC_RX_ENA, x)
2779 #define SD_LANE_MISC_RX_ENA_GET(x)\
2780         FIELD_GET(SD_LANE_MISC_RX_ENA, x)
2781
2782 #define SD_LANE_MISC_MUX_ENA                     BIT(2)
2783 #define SD_LANE_MISC_MUX_ENA_SET(x)\
2784         FIELD_PREP(SD_LANE_MISC_MUX_ENA, x)
2785 #define SD_LANE_MISC_MUX_ENA_GET(x)\
2786         FIELD_GET(SD_LANE_MISC_MUX_ENA, x)
2787
2788 /* SPARX5 ONLY */
2789 #define SD_LANE_MISC_CORE_CLK_FREQ               GENMASK(5, 4)
2790 #define SD_LANE_MISC_CORE_CLK_FREQ_SET(x)\
2791         FIELD_PREP(SD_LANE_MISC_CORE_CLK_FREQ, x)
2792 #define SD_LANE_MISC_CORE_CLK_FREQ_GET(x)\
2793         FIELD_GET(SD_LANE_MISC_CORE_CLK_FREQ, x)
2794
2795 /* SD_LANE_TARGET:CFG_STAT_FX100:M_STAT_MISC */
2796 #define SD_LANE_M_STAT_MISC(t)                                                 \
2797         __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 56, 0, 1, 56, 36, 0, 1, 4)
2798
2799 #define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM GENMASK(21, 0)
2800 #define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_SET(x)\
2801         FIELD_PREP(SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM, x)
2802 #define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_GET(x)\
2803         FIELD_GET(SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM, x)
2804
2805 #define SD_LANE_M_STAT_MISC_M_LOCK_CNT           GENMASK(31, 24)
2806 #define SD_LANE_M_STAT_MISC_M_LOCK_CNT_SET(x)\
2807         FIELD_PREP(SD_LANE_M_STAT_MISC_M_LOCK_CNT, x)
2808 #define SD_LANE_M_STAT_MISC_M_LOCK_CNT_GET(x)\
2809         FIELD_GET(SD_LANE_M_STAT_MISC_M_LOCK_CNT, x)
2810
2811 /* SPARX5 ONLY */
2812 /* SD25G_CFG_TARGET:SD_RESET:SD_SER_RST */
2813 #define SD_LANE_25G_SD_SER_RST(t)                                              \
2814         __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 0, 0, 1, 4)
2815
2816 #define SD_LANE_25G_SD_SER_RST_SER_RST           BIT(0)
2817 #define SD_LANE_25G_SD_SER_RST_SER_RST_SET(x)\
2818         FIELD_PREP(SD_LANE_25G_SD_SER_RST_SER_RST, x)
2819 #define SD_LANE_25G_SD_SER_RST_SER_RST_GET(x)\
2820         FIELD_GET(SD_LANE_25G_SD_SER_RST_SER_RST, x)
2821
2822 /* SPARX5 ONLY */
2823 /* SD25G_CFG_TARGET:SD_RESET:SD_DES_RST */
2824 #define SD_LANE_25G_SD_DES_RST(t)                                              \
2825         __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 4, 0, 1, 4)
2826
2827 #define SD_LANE_25G_SD_DES_RST_DES_RST           BIT(0)
2828 #define SD_LANE_25G_SD_DES_RST_DES_RST_SET(x)\
2829         FIELD_PREP(SD_LANE_25G_SD_DES_RST_DES_RST, x)
2830 #define SD_LANE_25G_SD_DES_RST_DES_RST_GET(x)\
2831         FIELD_GET(SD_LANE_25G_SD_DES_RST_DES_RST, x)
2832
2833 /* SPARX5 ONLY */
2834 /* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */
2835 #define SD_LANE_25G_SD_LANE_CFG(t)                                             \
2836         __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 0, 0, 1, 4)
2837
2838 #define SD_LANE_25G_SD_LANE_CFG_MACRO_RST        BIT(0)
2839 #define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(x)\
2840         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_MACRO_RST, x)
2841 #define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_GET(x)\
2842         FIELD_GET(SD_LANE_25G_SD_LANE_CFG_MACRO_RST, x)
2843
2844 #define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST      BIT(1)
2845 #define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(x)\
2846         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, x)
2847 #define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_GET(x)\
2848         FIELD_GET(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, x)
2849
2850 #define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE BIT(4)
2851 #define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_SET(x)\
2852         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE, x)
2853 #define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_GET(x)\
2854         FIELD_GET(SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE, x)
2855
2856 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE  GENMASK(7, 5)
2857 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_SET(x)\
2858         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE, x)
2859 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_GET(x)\
2860         FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE, x)
2861
2862 #define SD_LANE_25G_SD_LANE_CFG_LANE_RST         BIT(8)
2863 #define SD_LANE_25G_SD_LANE_CFG_LANE_RST_SET(x)\
2864         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_LANE_RST, x)
2865 #define SD_LANE_25G_SD_LANE_CFG_LANE_RST_GET(x)\
2866         FIELD_GET(SD_LANE_25G_SD_LANE_CFG_LANE_RST, x)
2867
2868 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV       BIT(9)
2869 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_SET(x)\
2870         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV, x)
2871 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_GET(x)\
2872         FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV, x)
2873
2874 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN      BIT(10)
2875 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_SET(x)\
2876         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN, x)
2877 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_GET(x)\
2878         FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN, x)
2879
2880 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY       BIT(11)
2881 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_SET(x)\
2882         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY, x)
2883 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_GET(x)\
2884         FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY, x)
2885
2886 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV      GENMASK(15, 12)
2887 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_SET(x)\
2888         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV, x)
2889 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_GET(x)\
2890         FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV, x)
2891
2892 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN     BIT(16)
2893 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_SET(x)\
2894         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN, x)
2895 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_GET(x)\
2896         FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN, x)
2897
2898 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY      GENMASK(21, 17)
2899 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_SET(x)\
2900         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY, x)
2901 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_GET(x)\
2902         FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY, x)
2903
2904 #define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN     BIT(22)
2905 #define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_SET(x)\
2906         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN, x)
2907 #define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_GET(x)\
2908         FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN, x)
2909
2910 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN BIT(23)
2911 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_SET(x)\
2912         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN, x)
2913 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_GET(x)\
2914         FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN, x)
2915
2916 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING  BIT(24)
2917 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_SET(x)\
2918         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING, x)
2919 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_GET(x)\
2920         FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING, x)
2921
2922 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI     BIT(25)
2923 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_SET(x)\
2924         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI, x)
2925 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_GET(x)\
2926         FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI, x)
2927
2928 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN GENMASK(28, 26)
2929 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_SET(x)\
2930         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN, x)
2931 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_GET(x)\
2932         FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN, x)
2933
2934 /* SPARX5 ONLY */
2935 /* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG2 */
2936 #define SD_LANE_25G_SD_LANE_CFG2(t)                                            \
2937         __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 4, 0, 1, 4)
2938
2939 #define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL  GENMASK(2, 0)
2940 #define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_SET(x)\
2941         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL, x)
2942 #define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_GET(x)\
2943         FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL, x)
2944
2945 #define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL    GENMASK(5, 3)
2946 #define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_SET(x)\
2947         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL, x)
2948 #define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_GET(x)\
2949         FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL, x)
2950
2951 #define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL   GENMASK(8, 6)
2952 #define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_SET(x)\
2953         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL, x)
2954 #define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_GET(x)\
2955         FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL, x)
2956
2957 #define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED GENMASK(10, 9)
2958 #define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_SET(x)\
2959         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED, x)
2960 #define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_GET(x)\
2961         FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED, x)
2962
2963 #define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV   GENMASK(13, 11)
2964 #define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_SET(x)\
2965         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV, x)
2966 #define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_GET(x)\
2967         FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV, x)
2968
2969 #define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV   GENMASK(16, 14)
2970 #define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_SET(x)\
2971         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV, x)
2972 #define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_GET(x)\
2973         FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV, x)
2974
2975 #define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL GENMASK(19, 17)
2976 #define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_SET(x)\
2977         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL, x)
2978 #define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_GET(x)\
2979         FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL, x)
2980
2981 #define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV GENMASK(23, 20)
2982 #define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_SET(x)\
2983         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV, x)
2984 #define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_GET(x)\
2985         FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV, x)
2986
2987 #define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL  GENMASK(25, 24)
2988 #define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_SET(x)\
2989         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL, x)
2990 #define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_GET(x)\
2991         FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL, x)
2992
2993 #define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL      GENMASK(28, 26)
2994 #define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_SET(x)\
2995         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL, x)
2996 #define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_GET(x)\
2997         FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL, x)
2998
2999 #define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL      GENMASK(31, 29)
3000 #define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_SET(x)\
3001         FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL, x)
3002 #define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_GET(x)\
3003         FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL, x)
3004
3005 /* SPARX5 ONLY */
3006 /* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */
3007 #define SD_LANE_25G_SD_LANE_STAT(t)                                            \
3008         __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 8, 0, 1, 4)
3009
3010 #define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE    BIT(0)
3011 #define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_SET(x)\
3012         FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE, x)
3013 #define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_GET(x)\
3014         FIELD_GET(SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE, x)
3015
3016 #define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE   BIT(1)
3017 #define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_SET(x)\
3018         FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE, x)
3019 #define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_GET(x)\
3020         FIELD_GET(SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE, x)
3021
3022 #define SD_LANE_25G_SD_LANE_STAT_DBG_OBS         GENMASK(31, 16)
3023 #define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_SET(x)\
3024         FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x)
3025 #define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_GET(x)\
3026         FIELD_GET(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x)
3027
3028 /* SPARX5 ONLY */
3029 /* SD25G_CFG_TARGET:SD_PWR_CFG:QUIET_MODE_6G */
3030 #define SD_LANE_25G_QUIET_MODE_6G(t)                                           \
3031         __REG(TARGET_SD_LANE_25G, t, 8, 28, 0, 1, 8, 4, 0, 1, 4)
3032
3033 #define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE     GENMASK(24, 0)
3034 #define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_SET(x)\
3035         FIELD_PREP(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE, x)
3036 #define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_GET(x)\
3037         FIELD_GET(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE, x)
3038
3039 #endif /* _SPARX5_SERDES_REGS_H_ */