1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
6 #ifndef QCOM_PHY_QMP_COMMON_H_
7 #define QCOM_PHY_QMP_COMMON_H_
9 struct qmp_phy_init_tbl
{
14 * mask of lanes for which this register is written
15 * for cases when second lane needs different values
20 #define QMP_PHY_INIT_CFG(o, v) \
28 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \
36 static inline void qmp_configure_lane(struct device
*dev
, void __iomem
*base
,
37 const struct qmp_phy_init_tbl tbl
[],
38 int num
, u8 lane_mask
)
41 const struct qmp_phy_init_tbl
*t
= tbl
;
46 for (i
= 0; i
< num
; i
++, t
++) {
47 if (!(t
->lane_mask
& lane_mask
))
50 dev_dbg(dev
, "Writing Reg: %s Offset: 0x%04x Val: 0x%02x\n",
51 t
->name
, t
->offset
, t
->val
);
52 writel(t
->val
, base
+ t
->offset
);
56 static inline void qmp_configure(struct device
*dev
, void __iomem
*base
,
57 const struct qmp_phy_init_tbl tbl
[], int num
)
59 qmp_configure_lane(dev
, base
, tbl
, num
, 0xff);