1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Pin controller and GPIO driver for Amlogic Meson SoCs
5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
8 #include <linux/gpio/driver.h>
9 #include <linux/pinctrl/pinctrl.h>
10 #include <linux/platform_device.h>
11 #include <linux/regmap.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
20 * struct meson_pmx_group - a pinmux group
23 * @pins: pins in the group
24 * @num_pins: number of pins in the group
25 * @is_gpio: whether the group is a single GPIO group
26 * @reg: register offset for the group in the domain mux registers
27 * @bit bit index enabling the group
28 * @domain: index of the domain this group belongs to
30 struct meson_pmx_group
{
32 const unsigned int *pins
;
33 unsigned int num_pins
;
38 * struct meson_pmx_func - a pinmux function
40 * @name: function name
41 * @groups: groups in the function
42 * @num_groups: number of groups in the function
44 struct meson_pmx_func
{
46 const char * const *groups
;
47 unsigned int num_groups
;
51 * struct meson_reg_desc - a register descriptor
53 * @reg: register offset in the regmap
54 * @bit: bit index in register
56 * The structure describes the information needed to control pull,
57 * pull-enable, direction, etc. for a single pin
59 struct meson_reg_desc
{
65 * enum meson_reg_type - type of registers encoded in @meson_reg_desc
78 * enum meson_pinconf_drv - value of drive-strength supported
80 enum meson_pinconf_drv
{
81 MESON_PINCONF_DRV_500UA
,
82 MESON_PINCONF_DRV_2500UA
,
83 MESON_PINCONF_DRV_3000UA
,
84 MESON_PINCONF_DRV_4000UA
,
91 * @first: first pin of the bank
92 * @last: last pin of the bank
93 * @irq: hwirq base number of the bank
94 * @regs: array of register descriptors
96 * A bank represents a set of pins controlled by a contiguous set of
97 * bits in the domain registers. The structure specifies which bits in
98 * the regmap control the different functionalities. Each member of
99 * the @regs array refers to the first pin of the bank.
107 struct meson_reg_desc regs
[MESON_NUM_REG
];
110 struct meson_pinctrl_data
{
112 const struct pinctrl_pin_desc
*pins
;
113 const struct meson_pmx_group
*groups
;
114 const struct meson_pmx_func
*funcs
;
115 unsigned int num_pins
;
116 unsigned int num_groups
;
117 unsigned int num_funcs
;
118 const struct meson_bank
*banks
;
119 unsigned int num_banks
;
120 const struct pinmux_ops
*pmx_ops
;
121 const void *pmx_data
;
122 int (*parse_dt
)(struct meson_pinctrl
*pc
);
125 struct meson_pinctrl
{
127 struct pinctrl_dev
*pcdev
;
128 struct pinctrl_desc desc
;
129 struct meson_pinctrl_data
*data
;
130 struct regmap
*reg_mux
;
131 struct regmap
*reg_pullen
;
132 struct regmap
*reg_pull
;
133 struct regmap
*reg_gpio
;
134 struct regmap
*reg_ds
;
135 struct gpio_chip chip
;
136 struct fwnode_handle
*fwnode
;
139 #define FUNCTION(fn) \
142 .groups = fn ## _groups, \
143 .num_groups = ARRAY_SIZE(fn ## _groups), \
146 #define BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, \
155 [MESON_REG_PULLEN] = { per, peb }, \
156 [MESON_REG_PULL] = { pr, pb }, \
157 [MESON_REG_DIR] = { dr, db }, \
158 [MESON_REG_OUT] = { or, ob }, \
159 [MESON_REG_IN] = { ir, ib }, \
160 [MESON_REG_DS] = { dsr, dsb }, \
164 #define BANK(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
165 BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, 0, 0)
167 #define MESON_PIN(x) PINCTRL_PIN(x, #x)
169 /* Common pmx functions */
170 int meson_pmx_get_funcs_count(struct pinctrl_dev
*pcdev
);
171 const char *meson_pmx_get_func_name(struct pinctrl_dev
*pcdev
,
173 int meson_pmx_get_groups(struct pinctrl_dev
*pcdev
,
175 const char * const **groups
,
176 unsigned * const num_groups
);
178 /* Common probe function */
179 int meson_pinctrl_probe(struct platform_device
*pdev
);
180 /* Common ao groups extra dt parse function for SoCs before g12a */
181 int meson8_aobus_parse_dt_extra(struct meson_pinctrl
*pc
);
182 /* Common extra dt parse function for SoCs like A1 */
183 int meson_a1_parse_dt_extra(struct meson_pinctrl
*pc
);