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Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / pinctrl / pinctrl-lpc18xx.c
blob0f5a7bed2f81b731714e3b65908df23f2ffdfd63
1 /*
2 * Pinctrl driver for NXP LPC18xx/LPC43xx System Control Unit (SCU)
3 *
4 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/clk.h>
13 #include <linux/init.h>
14 #include <linux/io.h>
15 #include <linux/mod_devicetable.h>
16 #include <linux/platform_device.h>
17
18 #include <linux/pinctrl/pinconf-generic.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h>
22
23 #include "core.h"
24 #include "pinctrl-utils.h"
25
26 /* LPC18XX SCU analog function registers */
27 #define LPC18XX_SCU_REG_ENAIO0 0xc88
28 #define LPC18XX_SCU_REG_ENAIO1 0xc8c
29 #define LPC18XX_SCU_REG_ENAIO2 0xc90
30 #define LPC18XX_SCU_REG_ENAIO2_DAC BIT(0)
31
32 /* LPC18XX SCU pin register definitions */
33 #define LPC18XX_SCU_PIN_MODE_MASK 0x7
34 #define LPC18XX_SCU_PIN_EPD BIT(3)
35 #define LPC18XX_SCU_PIN_EPUN BIT(4)
36 #define LPC18XX_SCU_PIN_EHS BIT(5)
37 #define LPC18XX_SCU_PIN_EZI BIT(6)
38 #define LPC18XX_SCU_PIN_ZIF BIT(7)
39 #define LPC18XX_SCU_PIN_EHD_MASK 0x300
40 #define LPC18XX_SCU_PIN_EHD_POS 8
41
42 #define LPC18XX_SCU_USB1_EPD BIT(2)
43 #define LPC18XX_SCU_USB1_EPWR BIT(4)
44
45 #define LPC18XX_SCU_I2C0_EFP BIT(0)
46 #define LPC18XX_SCU_I2C0_EHD BIT(2)
47 #define LPC18XX_SCU_I2C0_EZI BIT(3)
48 #define LPC18XX_SCU_I2C0_ZIF BIT(7)
49 #define LPC18XX_SCU_I2C0_SCL_SHIFT 0
50 #define LPC18XX_SCU_I2C0_SDA_SHIFT 8
51
52 #define LPC18XX_SCU_FUNC_PER_PIN 8
53
54 /* LPC18XX SCU pin interrupt select registers */
55 #define LPC18XX_SCU_PINTSEL0 0xe00
56 #define LPC18XX_SCU_PINTSEL1 0xe04
57 #define LPC18XX_SCU_PINTSEL_VAL_MASK 0xff
58 #define LPC18XX_SCU_PINTSEL_PORT_SHIFT 5
59 #define LPC18XX_SCU_IRQ_PER_PINTSEL 4
60 #define LPC18XX_GPIO_PINS_PER_PORT 32
61 #define LPC18XX_GPIO_PIN_INT_MAX 8
62
63 #define LPC18XX_SCU_PINTSEL_VAL(val, n) \
64 ((val) << (((n) % LPC18XX_SCU_IRQ_PER_PINTSEL) * 8))
65
66 /* LPC18xx pin types */
67 enum {
68 TYPE_ND, /* Normal-drive */
69 TYPE_HD, /* High-drive */
70 TYPE_HS, /* High-speed */
71 TYPE_I2C0,
72 TYPE_USB1,
73 };
74
75 /* LPC18xx pin functions */
76 enum {
77 FUNC_R, /* Reserved */
78 FUNC_ADC,
79 FUNC_ADCTRIG,
80 FUNC_CAN0,
81 FUNC_CAN1,
82 FUNC_CGU_OUT,
83 FUNC_CLKIN,
84 FUNC_CLKOUT,
85 FUNC_CTIN,
86 FUNC_CTOUT,
87 FUNC_DAC,
88 FUNC_EMC,
89 FUNC_EMC_ALT,
90 FUNC_ENET,
91 FUNC_ENET_ALT,
92 FUNC_GPIO,
93 FUNC_I2C0,
94 FUNC_I2C1,
95 FUNC_I2S0_RX_MCLK,
96 FUNC_I2S0_RX_SCK,
97 FUNC_I2S0_RX_SDA,
98 FUNC_I2S0_RX_WS,
99 FUNC_I2S0_TX_MCLK,
100 FUNC_I2S0_TX_SCK,
101 FUNC_I2S0_TX_SDA,
102 FUNC_I2S0_TX_WS,
103 FUNC_I2S1,
104 FUNC_LCD,
105 FUNC_LCD_ALT,
106 FUNC_MCTRL,
107 FUNC_NMI,
108 FUNC_QEI,
109 FUNC_SDMMC,
110 FUNC_SGPIO,
111 FUNC_SPI,
112 FUNC_SPIFI,
113 FUNC_SSP0,
114 FUNC_SSP0_ALT,
115 FUNC_SSP1,
116 FUNC_TIMER0,
117 FUNC_TIMER1,
118 FUNC_TIMER2,
119 FUNC_TIMER3,
120 FUNC_TRACE,
121 FUNC_UART0,
122 FUNC_UART1,
123 FUNC_UART2,
124 FUNC_UART3,
125 FUNC_USB0,
126 FUNC_USB1,
127 FUNC_MAX
128 };
129
130 static const char *const lpc18xx_function_names[] = {
131 [FUNC_R] = "reserved",
132 [FUNC_ADC] = "adc",
133 [FUNC_ADCTRIG] = "adctrig",
134 [FUNC_CAN0] = "can0",
135 [FUNC_CAN1] = "can1",
136 [FUNC_CGU_OUT] = "cgu_out",
137 [FUNC_CLKIN] = "clkin",
138 [FUNC_CLKOUT] = "clkout",
139 [FUNC_CTIN] = "ctin",
140 [FUNC_CTOUT] = "ctout",
141 [FUNC_DAC] = "dac",
142 [FUNC_EMC] = "emc",
143 [FUNC_EMC_ALT] = "emc_alt",
144 [FUNC_ENET] = "enet",
145 [FUNC_ENET_ALT] = "enet_alt",
146 [FUNC_GPIO] = "gpio",
147 [FUNC_I2C0] = "i2c0",
148 [FUNC_I2C1] = "i2c1",
149 [FUNC_I2S0_RX_MCLK] = "i2s0_rx_mclk",
150 [FUNC_I2S0_RX_SCK] = "i2s0_rx_sck",
151 [FUNC_I2S0_RX_SDA] = "i2s0_rx_sda",
152 [FUNC_I2S0_RX_WS] = "i2s0_rx_ws",
153 [FUNC_I2S0_TX_MCLK] = "i2s0_tx_mclk",
154 [FUNC_I2S0_TX_SCK] = "i2s0_tx_sck",
155 [FUNC_I2S0_TX_SDA] = "i2s0_tx_sda",
156 [FUNC_I2S0_TX_WS] = "i2s0_tx_ws",
157 [FUNC_I2S1] = "i2s1",
158 [FUNC_LCD] = "lcd",
159 [FUNC_LCD_ALT] = "lcd_alt",
160 [FUNC_MCTRL] = "mctrl",
161 [FUNC_NMI] = "nmi",
162 [FUNC_QEI] = "qei",
163 [FUNC_SDMMC] = "sdmmc",
164 [FUNC_SGPIO] = "sgpio",
165 [FUNC_SPI] = "spi",
166 [FUNC_SPIFI] = "spifi",
167 [FUNC_SSP0] = "ssp0",
168 [FUNC_SSP0_ALT] = "ssp0_alt",
169 [FUNC_SSP1] = "ssp1",
170 [FUNC_TIMER0] = "timer0",
171 [FUNC_TIMER1] = "timer1",
172 [FUNC_TIMER2] = "timer2",
173 [FUNC_TIMER3] = "timer3",
174 [FUNC_TRACE] = "trace",
175 [FUNC_UART0] = "uart0",
176 [FUNC_UART1] = "uart1",
177 [FUNC_UART2] = "uart2",
178 [FUNC_UART3] = "uart3",
179 [FUNC_USB0] = "usb0",
180 [FUNC_USB1] = "usb1",
181 };
182
183 struct lpc18xx_pmx_func {
184 const char **groups;
185 unsigned ngroups;
186 };
187
188 struct lpc18xx_scu_data {
189 struct pinctrl_dev *pctl;
190 void __iomem *base;
191 struct clk *clk;
192 struct lpc18xx_pmx_func func[FUNC_MAX];
193 };
194
195 struct lpc18xx_pin_caps {
196 unsigned int offset;
197 unsigned char functions[LPC18XX_SCU_FUNC_PER_PIN];
198 unsigned char analog;
199 unsigned char type;
200 };
201
202 /* Analog pins are required to have both bias and input disabled */
203 #define LPC18XX_SCU_ANALOG_PIN_CFG 0x10
204
205 /* Macros to maniupluate analog member in lpc18xx_pin_caps */
206 #define LPC18XX_ANALOG_PIN BIT(7)
207 #define LPC18XX_ANALOG_ADC(a) ((a >> 5) & 0x3)
208 #define LPC18XX_ANALOG_BIT_MASK 0x1f
209 #define ADC0 (LPC18XX_ANALOG_PIN | (0x00 << 5))
210 #define ADC1 (LPC18XX_ANALOG_PIN | (0x01 << 5))
211 #define DAC LPC18XX_ANALOG_PIN
212
213 #define LPC_P(port, pin, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \
214 static struct lpc18xx_pin_caps lpc18xx_pin_p##port##_##pin = { \
215 .offset = 0x##port * 32 * 4 + pin * 4, \
216 .functions = { \
217 FUNC_##f0, FUNC_##f1, FUNC_##f2, \
218 FUNC_##f3, FUNC_##f4, FUNC_##f5, \
219 FUNC_##f6, FUNC_##f7, \
220 }, \
221 .analog = a, \
222 .type = TYPE_##t, \
223 }
224
225 #define LPC_N(pname, off, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \
226 static struct lpc18xx_pin_caps lpc18xx_pin_##pname = { \
227 .offset = off, \
228 .functions = { \
229 FUNC_##f0, FUNC_##f1, FUNC_##f2, \
230 FUNC_##f3, FUNC_##f4, FUNC_##f5, \
231 FUNC_##f6, FUNC_##f7, \
232 }, \
233 .analog = a, \
234 .type = TYPE_##t, \
235 }
236
237
238 /* Pinmuxing table taken from data sheet */
239 /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG TYPE */
240 LPC_P(0,0, GPIO, SSP1, ENET, SGPIO, R, R, I2S0_TX_WS,I2S1, 0, ND);
241 LPC_P(0,1, GPIO, SSP1,ENET_ALT,SGPIO, R, R, ENET, I2S1, 0, ND);
242 LPC_P(1,0, GPIO, CTIN, EMC, R, R, SSP0, SGPIO, R, 0, ND);
243 LPC_P(1,1, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
244 LPC_P(1,2, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
245 LPC_P(1,3, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
246 LPC_P(1,4, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
247 LPC_P(1,5, GPIO, CTOUT, R, EMC, USB0, SSP1, SGPIO, SDMMC, 0, ND);
248 LPC_P(1,6, GPIO, CTIN, R, EMC, R, R, SGPIO, SDMMC, 0, ND);
249 LPC_P(1,7, GPIO, UART1, CTOUT, EMC, USB0, R, R, R, 0, ND);
250 LPC_P(1,8, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
251 LPC_P(1,9, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
252 LPC_P(1,10, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
253 LPC_P(1,11, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
254 LPC_P(1,12, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
255 LPC_P(1,13, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
256 LPC_P(1,14, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, R, 0, ND);
257 LPC_P(1,15, GPIO, UART2, SGPIO, ENET, TIMER0, R, R, R, 0, ND);
258 LPC_P(1,16, GPIO, UART2, SGPIO,ENET_ALT,TIMER0, R, R, ENET, 0, ND);
259 LPC_P(1,17, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, HD);
260 LPC_P(1,18, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, ND);
261 LPC_P(1,19, ENET, SSP1, R, R, CLKOUT, R, I2S0_RX_MCLK,I2S1, 0, ND);
262 LPC_P(1,20, GPIO, SSP1, R, ENET, TIMER0, R, SGPIO, R, 0, ND);
263 LPC_P(2,0, SGPIO, UART0, EMC, USB0, GPIO, R, TIMER3, ENET, 0, ND);
264 LPC_P(2,1, SGPIO, UART0, EMC, USB0, GPIO, R, TIMER3, R, 0, ND);
265 LPC_P(2,2, SGPIO, UART0, EMC, USB0, GPIO, CTIN, TIMER3, R, 0, ND);
266 LPC_P(2,3, SGPIO, I2C1, UART3, CTIN, GPIO, R, TIMER3, USB0, 0, HD);
267 LPC_P(2,4, SGPIO, I2C1, UART3, CTIN, GPIO, R, TIMER3, USB0, 0, HD);
268 LPC_P(2,5, SGPIO, CTIN, USB1, ADCTRIG, GPIO, R, TIMER3, USB0, 0, HD);
269 LPC_P(2,6, SGPIO, UART0, EMC, USB0, GPIO, CTIN, TIMER3, R, 0, ND);
270 LPC_P(2,7, GPIO, CTOUT, UART3, EMC, R, R, TIMER3, R, 0, ND);
271 LPC_P(2,8, SGPIO, CTOUT, UART3, EMC, GPIO, R, R, R, 0, ND);
272 LPC_P(2,9, GPIO, CTOUT, UART3, EMC, R, R, R, R, 0, ND);
273 LPC_P(2,10, GPIO, CTOUT, UART2, EMC, R, R, R, R, 0, ND);
274 LPC_P(2,11, GPIO, CTOUT, UART2, EMC, R, R, R, R, 0, ND);
275 LPC_P(2,12, GPIO, CTOUT, R, EMC, R, R, R, UART2, 0, ND);
276 LPC_P(2,13, GPIO, CTIN, R, EMC, R, R, R, UART2, 0, ND);
277 LPC_P(3,0, I2S0_RX_SCK, I2S0_RX_MCLK, I2S0_TX_SCK, I2S0_TX_MCLK,SSP0,R,R,R, 0, ND);
278 LPC_P(3,1, I2S0_TX_WS, I2S0_RX_WS,CAN0,USB1,GPIO, R, LCD, R, 0, ND);
279 LPC_P(3,2, I2S0_TX_SDA, I2S0_RX_SDA,CAN0,USB1,GPIO, R, LCD, R, 0, ND);
280 LPC_P(3,3, R, SPI, SSP0, SPIFI, CGU_OUT,R, I2S0_TX_MCLK, I2S1, 0, HS);
281 LPC_P(3,4, GPIO, R, R, SPIFI, UART1, I2S0_TX_WS, I2S1, LCD, 0, ND);
282 LPC_P(3,5, GPIO, R, R, SPIFI, UART1, I2S0_TX_SDA,I2S1, LCD, 0, ND);
283 LPC_P(3,6, GPIO, SPI, SSP0, SPIFI, R, SSP0_ALT, R, R, 0, ND);
284 LPC_P(3,7, R, SPI, SSP0, SPIFI, GPIO, SSP0_ALT, R, R, 0, ND);
285 LPC_P(3,8, R, SPI, SSP0, SPIFI, GPIO, SSP0_ALT, R, R, 0, ND);
286 LPC_P(4,0, GPIO, MCTRL, NMI, R, R, LCD, UART3, R, 0, ND);
287 LPC_P(4,1, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, ENET, ADC0|1, ND);
288 LPC_P(4,2, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, 0, ND);
289 LPC_P(4,3, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, ADC0|0, ND);
290 LPC_P(4,4, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, DAC, ND);
291 LPC_P(4,5, GPIO, CTOUT, LCD, R, R, R, R, SGPIO, 0, ND);
292 LPC_P(4,6, GPIO, CTOUT, LCD, R, R, R, R, SGPIO, 0, ND);
293 LPC_P(4,7, LCD, CLKIN, R, R, R, R, I2S1,I2S0_TX_SCK, 0, ND);
294 LPC_P(4,8, R, CTIN, LCD, R, GPIO, LCD_ALT, CAN1, SGPIO, 0, ND);
295 LPC_P(4,9, R, CTIN, LCD, R, GPIO, LCD_ALT, CAN1, SGPIO, 0, ND);
296 LPC_P(4,10, R, CTIN, LCD, R, GPIO, LCD_ALT, R, SGPIO, 0, ND);
297 LPC_P(5,0, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
298 LPC_P(5,1, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
299 LPC_P(5,2, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
300 LPC_P(5,3, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
301 LPC_P(5,4, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
302 LPC_P(5,5, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
303 LPC_P(5,6, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
304 LPC_P(5,7, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
305 LPC_P(6,0, R, I2S0_RX_MCLK,R, R, I2S0_RX_SCK, R, R, R, 0, ND);
306 LPC_P(6,1, GPIO, EMC, UART0, I2S0_RX_WS, R, TIMER2, R, R, 0, ND);
307 LPC_P(6,2, GPIO, EMC, UART0, I2S0_RX_SDA, R, TIMER2, R, R, 0, ND);
308 LPC_P(6,3, GPIO, USB0, SGPIO, EMC, R, TIMER2, R, R, 0, ND);
309 LPC_P(6,4, GPIO, CTIN, UART0, EMC, R, R, R, R, 0, ND);
310 LPC_P(6,5, GPIO, CTOUT, UART0, EMC, R, R, R, R, 0, ND);
311 LPC_P(6,6, GPIO, EMC, SGPIO, USB0, R, TIMER2, R, R, 0, ND);
312 LPC_P(6,7, R, EMC, SGPIO, USB0, GPIO, TIMER2, R, R, 0, ND);
313 LPC_P(6,8, R, EMC, SGPIO, USB0, GPIO, TIMER2, R, R, 0, ND);
314 LPC_P(6,9, GPIO, R, R, EMC, R, TIMER2, R, R, 0, ND);
315 LPC_P(6,10, GPIO, MCTRL, R, EMC, R, R, R, R, 0, ND);
316 LPC_P(6,11, GPIO, R, R, EMC, R, TIMER2, R, R, 0, ND);
317 LPC_P(6,12, GPIO, CTOUT, R, EMC, R, R, R, R, 0, ND);
318 LPC_P(7,0, GPIO, CTOUT, R, LCD, R, R, R, SGPIO, 0, ND);
319 LPC_P(7,1, GPIO, CTOUT,I2S0_TX_WS,LCD,LCD_ALT, R, UART2, SGPIO, 0, ND);
320 LPC_P(7,2, GPIO, CTIN,I2S0_TX_SDA,LCD,LCD_ALT, R, UART2, SGPIO, 0, ND);
321 LPC_P(7,3, GPIO, CTIN, R, LCD,LCD_ALT, R, R, R, 0, ND);
322 LPC_P(7,4, GPIO, CTOUT, R, LCD,LCD_ALT, TRACE, R, R, ADC0|4, ND);
323 LPC_P(7,5, GPIO, CTOUT, R, LCD,LCD_ALT, TRACE, R, R, ADC0|3, ND);
324 LPC_P(7,6, GPIO, CTOUT, R, LCD, R, TRACE, R, R, 0, ND);
325 LPC_P(7,7, GPIO, CTOUT, R, LCD, R, TRACE, ENET, SGPIO, ADC1|6, ND);
326 LPC_P(8,0, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
327 LPC_P(8,1, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
328 LPC_P(8,2, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
329 LPC_P(8,3, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
330 LPC_P(8,4, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
331 LPC_P(8,5, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
332 LPC_P(8,6, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
333 LPC_P(8,7, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
334 LPC_P(8,8, R, USB1, R, R, R, R,CGU_OUT, I2S1, 0, ND);
335 LPC_P(9,0, GPIO, MCTRL, R, R, R, ENET, SGPIO, SSP0, 0, ND);
336 LPC_P(9,1, GPIO, MCTRL, R, R, I2S0_TX_WS,ENET, SGPIO, SSP0, 0, ND);
337 LPC_P(9,2, GPIO, MCTRL, R, R, I2S0_TX_SDA,ENET,SGPIO, SSP0, 0, ND);
338 LPC_P(9,3, GPIO, MCTRL, USB1, R, R, ENET, SGPIO, UART3, 0, ND);
339 LPC_P(9,4, R, MCTRL, USB1, R, GPIO, ENET, SGPIO, UART3, 0, ND);
340 LPC_P(9,5, R, MCTRL, USB1, R, GPIO, ENET, SGPIO, UART0, 0, ND);
341 LPC_P(9,6, GPIO, MCTRL, USB1, R, R, ENET, SGPIO, UART0, 0, ND);
342 LPC_P(a,0, R, R, R, R, R, I2S1, CGU_OUT, R, 0, ND);
343 LPC_P(a,1, GPIO, QEI, R, UART2, R, R, R, R, 0, HD);
344 LPC_P(a,2, GPIO, QEI, R, UART2, R, R, R, R, 0, HD);
345 LPC_P(a,3, GPIO, QEI, R, R, R, R, R, R, 0, HD);
346 LPC_P(a,4, R, CTOUT, R, EMC, GPIO, R, R, R, 0, ND);
347 LPC_P(b,0, R, CTOUT, LCD, R, GPIO, R, R, R, 0, ND);
348 LPC_P(b,1, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND);
349 LPC_P(b,2, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND);
350 LPC_P(b,3, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND);
351 LPC_P(b,4, R, USB1, LCD, R, GPIO, CTIN, R, R, 0, ND);
352 LPC_P(b,5, R, USB1, LCD, R, GPIO, CTIN, LCD_ALT, R, 0, ND);
353 LPC_P(b,6, R, USB1, LCD, R, GPIO, CTIN, LCD_ALT, R, ADC0|6, ND);
354 LPC_P(c,0, R, USB1, R, ENET, LCD, R, R, SDMMC, ADC1|1, ND);
355 LPC_P(c,1, USB1, R, UART1, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
356 LPC_P(c,2, USB1, R, UART1, ENET, GPIO, R, R, SDMMC, 0, ND);
357 LPC_P(c,3, USB1, R, UART1, ENET, GPIO, R, R, SDMMC, ADC1|0, ND);
358 LPC_P(c,4, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
359 LPC_P(c,5, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
360 LPC_P(c,6, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
361 LPC_P(c,7, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
362 LPC_P(c,8, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
363 LPC_P(c,9, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
364 LPC_P(c,10, R, USB1, UART1, R, GPIO, R, TIMER3, SDMMC, 0, ND);
365 LPC_P(c,11, R, USB1, UART1, R, GPIO, R, R, SDMMC, 0, ND);
366 LPC_P(c,12, R, R, UART1, R, GPIO, SGPIO, I2S0_TX_SDA,SDMMC, 0, ND);
367 LPC_P(c,13, R, R, UART1, R, GPIO, SGPIO, I2S0_TX_WS, SDMMC, 0, ND);
368 LPC_P(c,14, R, R, UART1, R, GPIO, SGPIO, ENET, SDMMC, 0, ND);
369 LPC_P(d,0, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
370 LPC_P(d,1, R, R, EMC, R, GPIO, SDMMC, R, SGPIO, 0, ND);
371 LPC_P(d,2, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
372 LPC_P(d,3, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
373 LPC_P(d,4, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
374 LPC_P(d,5, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
375 LPC_P(d,6, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
376 LPC_P(d,7, R, CTIN, EMC, R, GPIO, R, R, SGPIO, 0, ND);
377 LPC_P(d,8, R, CTIN, EMC, R, GPIO, R, R, SGPIO, 0, ND);
378 LPC_P(d,9, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
379 LPC_P(d,10, R, CTIN, EMC, R, GPIO, R, R, R, 0, ND);
380 LPC_P(d,11, R, R, EMC, R, GPIO, USB1, CTOUT, R, 0, ND);
381 LPC_P(d,12, R, R, EMC, R, GPIO, R, CTOUT, R, 0, ND);
382 LPC_P(d,13, R, CTIN, EMC, R, GPIO, R, CTOUT, R, 0, ND);
383 LPC_P(d,14, R, R, EMC, R, GPIO, R, CTOUT, R, 0, ND);
384 LPC_P(d,15, R, R, EMC, R, GPIO, SDMMC, CTOUT, R, 0, ND);
385 LPC_P(d,16, R, R, EMC, R, GPIO, SDMMC, CTOUT, R, 0, ND);
386 LPC_P(e,0, R, R, R, EMC, GPIO, CAN1, R, R, 0, ND);
387 LPC_P(e,1, R, R, R, EMC, GPIO, CAN1, R, R, 0, ND);
388 LPC_P(e,2,ADCTRIG, CAN0, R, EMC, GPIO, R, R, R, 0, ND);
389 LPC_P(e,3, R, CAN0,ADCTRIG, EMC, GPIO, R, R, R, 0, ND);
390 LPC_P(e,4, R, NMI, R, EMC, GPIO, R, R, R, 0, ND);
391 LPC_P(e,5, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
392 LPC_P(e,6, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
393 LPC_P(e,7, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
394 LPC_P(e,8, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
395 LPC_P(e,9, R, CTIN, UART1, EMC, GPIO, R, R, R, 0, ND);
396 LPC_P(e,10, R, CTIN, UART1, EMC, GPIO, R, R, R, 0, ND);
397 LPC_P(e,11, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
398 LPC_P(e,12, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
399 LPC_P(e,13, R, CTOUT, I2C1, EMC, GPIO, R, R, R, 0, ND);
400 LPC_P(e,14, R, R, R, EMC, GPIO, R, R, R, 0, ND);
401 LPC_P(e,15, R, CTOUT, I2C1, EMC, GPIO, R, R, R, 0, ND);
402 LPC_P(f,0, SSP0, CLKIN, R, R, R, R, R, I2S1, 0, ND);
403 LPC_P(f,1, R, R, SSP0, R, GPIO, R, SGPIO, R, 0, ND);
404 LPC_P(f,2, R, UART3, SSP0, R, GPIO, R, SGPIO, R, 0, ND);
405 LPC_P(f,3, R, UART3, SSP0, R, GPIO, R, SGPIO, R, 0, ND);
406 LPC_P(f,4, SSP1, CLKIN, TRACE, R, R, R, I2S0_TX_MCLK,I2S0_RX_SCK, 0, ND);
407 LPC_P(f,5, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, R, ADC1|4, ND);
408 LPC_P(f,6, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, I2S1, ADC1|3, ND);
409 LPC_P(f,7, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, I2S1, ADC1|7, ND);
410 LPC_P(f,8, R, UART0, CTIN, TRACE, GPIO, R, SGPIO, R, ADC0|2, ND);
411 LPC_P(f,9, R, UART0, CTOUT, R, GPIO, R, SGPIO, R, ADC1|2, ND);
412 LPC_P(f,10, R, UART0, R, R, GPIO, R, SDMMC, R, ADC0|5, ND);
413 LPC_P(f,11, R, UART0, R, R, GPIO, R, SDMMC, R, ADC1|5, ND);
414
415 /* Pin Offset FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG TYPE */
416 LPC_N(clk0, 0xc00, EMC, CLKOUT, R, R, SDMMC, EMC_ALT, SSP1, ENET, 0, HS);
417 LPC_N(clk1, 0xc04, EMC, CLKOUT, R, R, R, CGU_OUT, R, I2S1, 0, HS);
418 LPC_N(clk2, 0xc08, EMC, CLKOUT, R, R, SDMMC, EMC_ALT,I2S0_TX_MCLK,I2S1, 0, HS);
419 LPC_N(clk3, 0xc0c, EMC, CLKOUT, R, R, R, CGU_OUT, R, I2S1, 0, HS);
420 LPC_N(usb1_dm, 0xc80, R, R, R, R, R, R, R, R, 0, USB1);
421 LPC_N(usb1_dp, 0xc80, R, R, R, R, R, R, R, R, 0, USB1);
422 LPC_N(i2c0_scl, 0xc84, R, R, R, R, R, R, R, R, 0, I2C0);
423 LPC_N(i2c0_sda, 0xc84, R, R, R, R, R, R, R, R, 0, I2C0);
424
425 #define LPC18XX_PIN_P(port, pin) { \
426 .number = 0x##port * 32 + pin, \
427 .name = "p"#port"_"#pin, \
428 .drv_data = &lpc18xx_pin_p##port##_##pin \
429 }
430
431 /* Pin numbers for special pins */
432 enum {
433 PIN_CLK0 = 600,
434 PIN_CLK1,
435 PIN_CLK2,
436 PIN_CLK3,
437 PIN_USB1_DM,
438 PIN_USB1_DP,
439 PIN_I2C0_SCL,
440 PIN_I2C0_SDA,
441 };
442
443 #define LPC18XX_PIN(pname, n) { \
444 .number = n, \
445 .name = #pname, \
446 .drv_data = &lpc18xx_pin_##pname \
447 }
448
449 static const struct pinctrl_pin_desc lpc18xx_pins[] = {
450 LPC18XX_PIN_P(0,0),
451 LPC18XX_PIN_P(0,1),
452 LPC18XX_PIN_P(1,0),
453 LPC18XX_PIN_P(1,1),
454 LPC18XX_PIN_P(1,2),
455 LPC18XX_PIN_P(1,3),
456 LPC18XX_PIN_P(1,4),
457 LPC18XX_PIN_P(1,5),
458 LPC18XX_PIN_P(1,6),
459 LPC18XX_PIN_P(1,7),
460 LPC18XX_PIN_P(1,8),
461 LPC18XX_PIN_P(1,9),
462 LPC18XX_PIN_P(1,10),
463 LPC18XX_PIN_P(1,11),
464 LPC18XX_PIN_P(1,12),
465 LPC18XX_PIN_P(1,13),
466 LPC18XX_PIN_P(1,14),
467 LPC18XX_PIN_P(1,15),
468 LPC18XX_PIN_P(1,16),
469 LPC18XX_PIN_P(1,17),
470 LPC18XX_PIN_P(1,18),
471 LPC18XX_PIN_P(1,19),
472 LPC18XX_PIN_P(1,20),
473 LPC18XX_PIN_P(2,0),
474 LPC18XX_PIN_P(2,1),
475 LPC18XX_PIN_P(2,2),
476 LPC18XX_PIN_P(2,3),
477 LPC18XX_PIN_P(2,4),
478 LPC18XX_PIN_P(2,5),
479 LPC18XX_PIN_P(2,6),
480 LPC18XX_PIN_P(2,7),
481 LPC18XX_PIN_P(2,8),
482 LPC18XX_PIN_P(2,9),
483 LPC18XX_PIN_P(2,10),
484 LPC18XX_PIN_P(2,11),
485 LPC18XX_PIN_P(2,12),
486 LPC18XX_PIN_P(2,13),
487 LPC18XX_PIN_P(3,0),
488 LPC18XX_PIN_P(3,1),
489 LPC18XX_PIN_P(3,2),
490 LPC18XX_PIN_P(3,3),
491 LPC18XX_PIN_P(3,4),
492 LPC18XX_PIN_P(3,5),
493 LPC18XX_PIN_P(3,6),
494 LPC18XX_PIN_P(3,7),
495 LPC18XX_PIN_P(3,8),
496 LPC18XX_PIN_P(4,0),
497 LPC18XX_PIN_P(4,1),
498 LPC18XX_PIN_P(4,2),
499 LPC18XX_PIN_P(4,3),
500 LPC18XX_PIN_P(4,4),
501 LPC18XX_PIN_P(4,5),
502 LPC18XX_PIN_P(4,6),
503 LPC18XX_PIN_P(4,7),
504 LPC18XX_PIN_P(4,8),
505 LPC18XX_PIN_P(4,9),
506 LPC18XX_PIN_P(4,10),
507 LPC18XX_PIN_P(5,0),
508 LPC18XX_PIN_P(5,1),
509 LPC18XX_PIN_P(5,2),
510 LPC18XX_PIN_P(5,3),
511 LPC18XX_PIN_P(5,4),
512 LPC18XX_PIN_P(5,5),
513 LPC18XX_PIN_P(5,6),
514 LPC18XX_PIN_P(5,7),
515 LPC18XX_PIN_P(6,0),
516 LPC18XX_PIN_P(6,1),
517 LPC18XX_PIN_P(6,2),
518 LPC18XX_PIN_P(6,3),
519 LPC18XX_PIN_P(6,4),
520 LPC18XX_PIN_P(6,5),
521 LPC18XX_PIN_P(6,6),
522 LPC18XX_PIN_P(6,7),
523 LPC18XX_PIN_P(6,8),
524 LPC18XX_PIN_P(6,9),
525 LPC18XX_PIN_P(6,10),
526 LPC18XX_PIN_P(6,11),
527 LPC18XX_PIN_P(6,12),
528 LPC18XX_PIN_P(7,0),
529 LPC18XX_PIN_P(7,1),
530 LPC18XX_PIN_P(7,2),
531 LPC18XX_PIN_P(7,3),
532 LPC18XX_PIN_P(7,4),
533 LPC18XX_PIN_P(7,5),
534 LPC18XX_PIN_P(7,6),
535 LPC18XX_PIN_P(7,7),
536 LPC18XX_PIN_P(8,0),
537 LPC18XX_PIN_P(8,1),
538 LPC18XX_PIN_P(8,2),
539 LPC18XX_PIN_P(8,3),
540 LPC18XX_PIN_P(8,4),
541 LPC18XX_PIN_P(8,5),
542 LPC18XX_PIN_P(8,6),
543 LPC18XX_PIN_P(8,7),
544 LPC18XX_PIN_P(8,8),
545 LPC18XX_PIN_P(9,0),
546 LPC18XX_PIN_P(9,1),
547 LPC18XX_PIN_P(9,2),
548 LPC18XX_PIN_P(9,3),
549 LPC18XX_PIN_P(9,4),
550 LPC18XX_PIN_P(9,5),
551 LPC18XX_PIN_P(9,6),
552 LPC18XX_PIN_P(a,0),
553 LPC18XX_PIN_P(a,1),
554 LPC18XX_PIN_P(a,2),
555 LPC18XX_PIN_P(a,3),
556 LPC18XX_PIN_P(a,4),
557 LPC18XX_PIN_P(b,0),
558 LPC18XX_PIN_P(b,1),
559 LPC18XX_PIN_P(b,2),
560 LPC18XX_PIN_P(b,3),
561 LPC18XX_PIN_P(b,4),
562 LPC18XX_PIN_P(b,5),
563 LPC18XX_PIN_P(b,6),
564 LPC18XX_PIN_P(c,0),
565 LPC18XX_PIN_P(c,1),
566 LPC18XX_PIN_P(c,2),
567 LPC18XX_PIN_P(c,3),
568 LPC18XX_PIN_P(c,4),
569 LPC18XX_PIN_P(c,5),
570 LPC18XX_PIN_P(c,6),
571 LPC18XX_PIN_P(c,7),
572 LPC18XX_PIN_P(c,8),
573 LPC18XX_PIN_P(c,9),
574 LPC18XX_PIN_P(c,10),
575 LPC18XX_PIN_P(c,11),
576 LPC18XX_PIN_P(c,12),
577 LPC18XX_PIN_P(c,13),
578 LPC18XX_PIN_P(c,14),
579 LPC18XX_PIN_P(d,0),
580 LPC18XX_PIN_P(d,1),
581 LPC18XX_PIN_P(d,2),
582 LPC18XX_PIN_P(d,3),
583 LPC18XX_PIN_P(d,4),
584 LPC18XX_PIN_P(d,5),
585 LPC18XX_PIN_P(d,6),
586 LPC18XX_PIN_P(d,7),
587 LPC18XX_PIN_P(d,8),
588 LPC18XX_PIN_P(d,9),
589 LPC18XX_PIN_P(d,10),
590 LPC18XX_PIN_P(d,11),
591 LPC18XX_PIN_P(d,12),
592 LPC18XX_PIN_P(d,13),
593 LPC18XX_PIN_P(d,14),
594 LPC18XX_PIN_P(d,15),
595 LPC18XX_PIN_P(d,16),
596 LPC18XX_PIN_P(e,0),
597 LPC18XX_PIN_P(e,1),
598 LPC18XX_PIN_P(e,2),
599 LPC18XX_PIN_P(e,3),
600 LPC18XX_PIN_P(e,4),
601 LPC18XX_PIN_P(e,5),
602 LPC18XX_PIN_P(e,6),
603 LPC18XX_PIN_P(e,7),
604 LPC18XX_PIN_P(e,8),
605 LPC18XX_PIN_P(e,9),
606 LPC18XX_PIN_P(e,10),
607 LPC18XX_PIN_P(e,11),
608 LPC18XX_PIN_P(e,12),
609 LPC18XX_PIN_P(e,13),
610 LPC18XX_PIN_P(e,14),
611 LPC18XX_PIN_P(e,15),
612 LPC18XX_PIN_P(f,0),
613 LPC18XX_PIN_P(f,1),
614 LPC18XX_PIN_P(f,2),
615 LPC18XX_PIN_P(f,3),
616 LPC18XX_PIN_P(f,4),
617 LPC18XX_PIN_P(f,5),
618 LPC18XX_PIN_P(f,6),
619 LPC18XX_PIN_P(f,7),
620 LPC18XX_PIN_P(f,8),
621 LPC18XX_PIN_P(f,9),
622 LPC18XX_PIN_P(f,10),
623 LPC18XX_PIN_P(f,11),
624
625 LPC18XX_PIN(clk0, PIN_CLK0),
626 LPC18XX_PIN(clk1, PIN_CLK1),
627 LPC18XX_PIN(clk2, PIN_CLK2),
628 LPC18XX_PIN(clk3, PIN_CLK3),
629 LPC18XX_PIN(usb1_dm, PIN_USB1_DM),
630 LPC18XX_PIN(usb1_dp, PIN_USB1_DP),
631 LPC18XX_PIN(i2c0_scl, PIN_I2C0_SCL),
632 LPC18XX_PIN(i2c0_sda, PIN_I2C0_SDA),
633 };
634
635 /* PIN_CONFIG_GPIO_PIN_INT: route gpio to the gpio pin interrupt controller */
636 #define PIN_CONFIG_GPIO_PIN_INT (PIN_CONFIG_END + 1)
637
638 static const struct pinconf_generic_params lpc18xx_params[] = {
639 {"nxp,gpio-pin-interrupt", PIN_CONFIG_GPIO_PIN_INT, 0},
640 };
641
642 #ifdef CONFIG_DEBUG_FS
643 static const struct pin_config_item lpc18xx_conf_items[ARRAY_SIZE(lpc18xx_params)] = {
644 PCONFDUMP(PIN_CONFIG_GPIO_PIN_INT, "gpio pin int", NULL, true),
645 };
646 #endif
647
648 static int lpc18xx_pconf_get_usb1(enum pin_config_param param, int *arg, u32 reg)
649 {
650 switch (param) {
651 case PIN_CONFIG_MODE_LOW_POWER:
652 if (reg & LPC18XX_SCU_USB1_EPWR)
653 *arg = 0;
654 else
655 *arg = 1;
656 break;
657
658 case PIN_CONFIG_BIAS_DISABLE:
659 if (reg & LPC18XX_SCU_USB1_EPD)
660 return -EINVAL;
661 break;
662
663 case PIN_CONFIG_BIAS_PULL_DOWN:
664 if (reg & LPC18XX_SCU_USB1_EPD)
665 *arg = 1;
666 else
667 return -EINVAL;
668 break;
669
670 default:
671 return -ENOTSUPP;
672 }
673
674 return 0;
675 }
676
677 static int lpc18xx_pconf_get_i2c0(enum pin_config_param param, int *arg, u32 reg,
678 unsigned pin)
679 {
680 u8 shift;
681
682 if (pin == PIN_I2C0_SCL)
683 shift = LPC18XX_SCU_I2C0_SCL_SHIFT;
684 else
685 shift = LPC18XX_SCU_I2C0_SDA_SHIFT;
686
687 switch (param) {
688 case PIN_CONFIG_INPUT_ENABLE:
689 if (reg & (LPC18XX_SCU_I2C0_EZI << shift))
690 *arg = 1;
691 else
692 return -EINVAL;
693 break;
694
695 case PIN_CONFIG_SLEW_RATE:
696 if (reg & (LPC18XX_SCU_I2C0_EHD << shift))
697 *arg = 1;
698 else
699 *arg = 0;
700 break;
701
702 case PIN_CONFIG_INPUT_SCHMITT:
703 if (reg & (LPC18XX_SCU_I2C0_EFP << shift))
704 *arg = 3;
705 else
706 *arg = 50;
707 break;
708
709 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
710 if (reg & (LPC18XX_SCU_I2C0_ZIF << shift))
711 return -EINVAL;
712 else
713 *arg = 1;
714 break;
715
716 default:
717 return -ENOTSUPP;
718 }
719
720 return 0;
721 }
722
723 static int lpc18xx_pin_to_gpio(struct pinctrl_dev *pctldev, unsigned pin)
724 {
725 struct pinctrl_gpio_range *range;
726
727 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
728 if (!range)
729 return -EINVAL;
730
731 return pin - range->pin_base + range->base;
732 }
733
734 static int lpc18xx_get_pintsel(void __iomem *addr, u32 val, int *arg)
735 {
736 u32 reg_val;
737 int i;
738
739 reg_val = readl(addr);
740 for (i = 0; i < LPC18XX_SCU_IRQ_PER_PINTSEL; i++) {
741 if ((reg_val & LPC18XX_SCU_PINTSEL_VAL_MASK) == val)
742 return 0;
743
744 reg_val >>= BITS_PER_BYTE;
745 *arg += 1;
746 }
747
748 return -EINVAL;
749 }
750
751 static u32 lpc18xx_gpio_to_pintsel_val(int gpio)
752 {
753 unsigned int gpio_port, gpio_pin;
754
755 gpio_port = gpio / LPC18XX_GPIO_PINS_PER_PORT;
756 gpio_pin = gpio % LPC18XX_GPIO_PINS_PER_PORT;
757
758 return gpio_pin | (gpio_port << LPC18XX_SCU_PINTSEL_PORT_SHIFT);
759 }
760
761 static int lpc18xx_pconf_get_gpio_pin_int(struct pinctrl_dev *pctldev,
762 int *arg, unsigned pin)
763 {
764 struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
765 int gpio, ret;
766 u32 val;
767
768 gpio = lpc18xx_pin_to_gpio(pctldev, pin);
769 if (gpio < 0)
770 return -ENOTSUPP;
771
772 val = lpc18xx_gpio_to_pintsel_val(gpio);
773
774 /*
775 * Check if this pin has been enabled as a interrupt in any of the two
776 * PINTSEL registers. *arg indicates which interrupt number (0-7).
777 */
778 *arg = 0;
779 ret = lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL0, val, arg);
780 if (ret == 0)
781 return ret;
782
783 return lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL1, val, arg);
784 }
785
786 static int lpc18xx_pconf_get_pin(struct pinctrl_dev *pctldev, unsigned param,
787 int *arg, u32 reg, unsigned pin,
788 struct lpc18xx_pin_caps *pin_cap)
789 {
790 switch (param) {
791 case PIN_CONFIG_BIAS_DISABLE:
792 if ((!(reg & LPC18XX_SCU_PIN_EPD)) && (reg & LPC18XX_SCU_PIN_EPUN))
793 ;
794 else
795 return -EINVAL;
796 break;
797
798 case PIN_CONFIG_BIAS_PULL_UP:
799 if (reg & LPC18XX_SCU_PIN_EPUN)
800 return -EINVAL;
801 else
802 *arg = 1;
803 break;
804
805 case PIN_CONFIG_BIAS_PULL_DOWN:
806 if (reg & LPC18XX_SCU_PIN_EPD)
807 *arg = 1;
808 else
809 return -EINVAL;
810 break;
811
812 case PIN_CONFIG_INPUT_ENABLE:
813 if (reg & LPC18XX_SCU_PIN_EZI)
814 *arg = 1;
815 else
816 return -EINVAL;
817 break;
818
819 case PIN_CONFIG_SLEW_RATE:
820 if (pin_cap->type == TYPE_HD)
821 return -ENOTSUPP;
822
823 if (reg & LPC18XX_SCU_PIN_EHS)
824 *arg = 1;
825 else
826 *arg = 0;
827 break;
828
829 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
830 if (reg & LPC18XX_SCU_PIN_ZIF)
831 return -EINVAL;
832 else
833 *arg = 1;
834 break;
835
836 case PIN_CONFIG_DRIVE_STRENGTH:
837 if (pin_cap->type != TYPE_HD)
838 return -ENOTSUPP;
839
840 *arg = (reg & LPC18XX_SCU_PIN_EHD_MASK) >> LPC18XX_SCU_PIN_EHD_POS;
841 switch (*arg) {
842 case 3: *arg += 5;
843 fallthrough;
844 case 2: *arg += 5;
845 fallthrough;
846 case 1: *arg += 3;
847 fallthrough;
848 case 0: *arg += 4;
849 }
850 break;
851
852 case PIN_CONFIG_GPIO_PIN_INT:
853 return lpc18xx_pconf_get_gpio_pin_int(pctldev, arg, pin);
854
855 default:
856 return -ENOTSUPP;
857 }
858
859 return 0;
860 }
861
862 static struct lpc18xx_pin_caps *lpc18xx_get_pin_caps(unsigned pin)
863 {
864 int i;
865
866 for (i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
867 if (lpc18xx_pins[i].number == pin)
868 return lpc18xx_pins[i].drv_data;
869 }
870
871 return NULL;
872 }
873
874 static int lpc18xx_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
875 unsigned long *config)
876 {
877 struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
878 enum pin_config_param param = pinconf_to_config_param(*config);
879 struct lpc18xx_pin_caps *pin_cap;
880 int ret, arg = 0;
881 u32 reg;
882
883 pin_cap = lpc18xx_get_pin_caps(pin);
884 if (!pin_cap)
885 return -EINVAL;
886
887 reg = readl(scu->base + pin_cap->offset);
888
889 if (pin_cap->type == TYPE_I2C0)
890 ret = lpc18xx_pconf_get_i2c0(param, &arg, reg, pin);
891 else if (pin_cap->type == TYPE_USB1)
892 ret = lpc18xx_pconf_get_usb1(param, &arg, reg);
893 else
894 ret = lpc18xx_pconf_get_pin(pctldev, param, &arg, reg, pin, pin_cap);
895
896 if (ret < 0)
897 return ret;
898
899 *config = pinconf_to_config_packed(param, (u16)arg);
900
901 return 0;
902 }
903
904 static int lpc18xx_pconf_set_usb1(struct pinctrl_dev *pctldev,
905 enum pin_config_param param,
906 u32 param_val, u32 *reg)
907 {
908 switch (param) {
909 case PIN_CONFIG_MODE_LOW_POWER:
910 if (param_val)
911 *reg &= ~LPC18XX_SCU_USB1_EPWR;
912 else
913 *reg |= LPC18XX_SCU_USB1_EPWR;
914 break;
915
916 case PIN_CONFIG_BIAS_DISABLE:
917 *reg &= ~LPC18XX_SCU_USB1_EPD;
918 break;
919
920 case PIN_CONFIG_BIAS_PULL_DOWN:
921 *reg |= LPC18XX_SCU_USB1_EPD;
922 break;
923
924 default:
925 dev_err(pctldev->dev, "Property not supported\n");
926 return -ENOTSUPP;
927 }
928
929 return 0;
930 }
931
932 static int lpc18xx_pconf_set_i2c0(struct pinctrl_dev *pctldev,
933 enum pin_config_param param,
934 u32 param_val, u32 *reg,
935 unsigned pin)
936 {
937 u8 shift;
938
939 if (pin == PIN_I2C0_SCL)
940 shift = LPC18XX_SCU_I2C0_SCL_SHIFT;
941 else
942 shift = LPC18XX_SCU_I2C0_SDA_SHIFT;
943
944 switch (param) {
945 case PIN_CONFIG_INPUT_ENABLE:
946 if (param_val)
947 *reg |= (LPC18XX_SCU_I2C0_EZI << shift);
948 else
949 *reg &= ~(LPC18XX_SCU_I2C0_EZI << shift);
950 break;
951
952 case PIN_CONFIG_SLEW_RATE:
953 if (param_val)
954 *reg |= (LPC18XX_SCU_I2C0_EHD << shift);
955 else
956 *reg &= ~(LPC18XX_SCU_I2C0_EHD << shift);
957 break;
958
959 case PIN_CONFIG_INPUT_SCHMITT:
960 if (param_val == 3)
961 *reg |= (LPC18XX_SCU_I2C0_EFP << shift);
962 else if (param_val == 50)
963 *reg &= ~(LPC18XX_SCU_I2C0_EFP << shift);
964 else
965 return -ENOTSUPP;
966 break;
967
968 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
969 if (param_val)
970 *reg &= ~(LPC18XX_SCU_I2C0_ZIF << shift);
971 else
972 *reg |= (LPC18XX_SCU_I2C0_ZIF << shift);
973 break;
974
975 default:
976 dev_err(pctldev->dev, "Property not supported\n");
977 return -ENOTSUPP;
978 }
979
980 return 0;
981 }
982
983 static int lpc18xx_pconf_set_gpio_pin_int(struct pinctrl_dev *pctldev,
984 u32 param_val, unsigned pin)
985 {
986 struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
987 u32 val, reg_val, reg_offset = LPC18XX_SCU_PINTSEL0;
988 int gpio;
989
990 if (param_val >= LPC18XX_GPIO_PIN_INT_MAX)
991 return -EINVAL;
992
993 gpio = lpc18xx_pin_to_gpio(pctldev, pin);
994 if (gpio < 0)
995 return -ENOTSUPP;
996
997 val = lpc18xx_gpio_to_pintsel_val(gpio);
998
999 reg_offset += (param_val / LPC18XX_SCU_IRQ_PER_PINTSEL) * sizeof(u32);
1000
1001 reg_val = readl(scu->base + reg_offset);
1002 reg_val &= ~LPC18XX_SCU_PINTSEL_VAL(LPC18XX_SCU_PINTSEL_VAL_MASK, param_val);
1003 reg_val |= LPC18XX_SCU_PINTSEL_VAL(val, param_val);
1004 writel(reg_val, scu->base + reg_offset);
1005
1006 return 0;
1007 }
1008
1009 static int lpc18xx_pconf_set_pin(struct pinctrl_dev *pctldev, unsigned param,
1010 u32 param_val, u32 *reg, unsigned pin,
1011 struct lpc18xx_pin_caps *pin_cap)
1012 {
1013 switch (param) {
1014 case PIN_CONFIG_BIAS_DISABLE:
1015 *reg &= ~LPC18XX_SCU_PIN_EPD;
1016 *reg |= LPC18XX_SCU_PIN_EPUN;
1017 break;
1018
1019 case PIN_CONFIG_BIAS_PULL_UP:
1020 *reg &= ~LPC18XX_SCU_PIN_EPUN;
1021 break;
1022
1023 case PIN_CONFIG_BIAS_PULL_DOWN:
1024 *reg |= LPC18XX_SCU_PIN_EPD;
1025 break;
1026
1027 case PIN_CONFIG_INPUT_ENABLE:
1028 if (param_val)
1029 *reg |= LPC18XX_SCU_PIN_EZI;
1030 else
1031 *reg &= ~LPC18XX_SCU_PIN_EZI;
1032 break;
1033
1034 case PIN_CONFIG_SLEW_RATE:
1035 if (pin_cap->type == TYPE_HD) {
1036 dev_err(pctldev->dev, "Slew rate unsupported on high-drive pins\n");
1037 return -ENOTSUPP;
1038 }
1039
1040 if (param_val == 0)
1041 *reg &= ~LPC18XX_SCU_PIN_EHS;
1042 else
1043 *reg |= LPC18XX_SCU_PIN_EHS;
1044 break;
1045
1046 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1047 if (param_val)
1048 *reg &= ~LPC18XX_SCU_PIN_ZIF;
1049 else
1050 *reg |= LPC18XX_SCU_PIN_ZIF;
1051 break;
1052
1053 case PIN_CONFIG_DRIVE_STRENGTH:
1054 if (pin_cap->type != TYPE_HD) {
1055 dev_err(pctldev->dev, "Drive strength available only on high-drive pins\n");
1056 return -ENOTSUPP;
1057 }
1058 *reg &= ~LPC18XX_SCU_PIN_EHD_MASK;
1059
1060 switch (param_val) {
1061 case 20: param_val -= 5;
1062 fallthrough;
1063 case 14: param_val -= 5;
1064 fallthrough;
1065 case 8: param_val -= 3;
1066 fallthrough;
1067 case 4: param_val -= 4;
1068 break;
1069 default:
1070 dev_err(pctldev->dev, "Drive strength %u unsupported\n", param_val);
1071 return -ENOTSUPP;
1072 }
1073 *reg |= param_val << LPC18XX_SCU_PIN_EHD_POS;
1074 break;
1075
1076 case PIN_CONFIG_GPIO_PIN_INT:
1077 return lpc18xx_pconf_set_gpio_pin_int(pctldev, param_val, pin);
1078
1079 default:
1080 dev_err(pctldev->dev, "Property not supported\n");
1081 return -ENOTSUPP;
1082 }
1083
1084 return 0;
1085 }
1086
1087 static int lpc18xx_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
1088 unsigned long *configs, unsigned num_configs)
1089 {
1090 struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
1091 struct lpc18xx_pin_caps *pin_cap;
1092 enum pin_config_param param;
1093 u32 param_val;
1094 u32 reg;
1095 int ret;
1096 int i;
1097
1098 pin_cap = lpc18xx_get_pin_caps(pin);
1099 if (!pin_cap)
1100 return -EINVAL;
1101
1102 reg = readl(scu->base + pin_cap->offset);
1103
1104 for (i = 0; i < num_configs; i++) {
1105 param = pinconf_to_config_param(configs[i]);
1106 param_val = pinconf_to_config_argument(configs[i]);
1107
1108 if (pin_cap->type == TYPE_I2C0)
1109 ret = lpc18xx_pconf_set_i2c0(pctldev, param, param_val, &reg, pin);
1110 else if (pin_cap->type == TYPE_USB1)
1111 ret = lpc18xx_pconf_set_usb1(pctldev, param, param_val, &reg);
1112 else
1113 ret = lpc18xx_pconf_set_pin(pctldev, param, param_val, &reg, pin, pin_cap);
1114
1115 if (ret)
1116 return ret;
1117 }
1118
1119 writel(reg, scu->base + pin_cap->offset);
1120
1121 return 0;
1122 }
1123
1124 static const struct pinconf_ops lpc18xx_pconf_ops = {
1125 .is_generic = true,
1126 .pin_config_get = lpc18xx_pconf_get,
1127 .pin_config_set = lpc18xx_pconf_set,
1128 };
1129
1130 static int lpc18xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
1131 {
1132 return ARRAY_SIZE(lpc18xx_function_names);
1133 }
1134
1135 static const char *lpc18xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
1136 unsigned function)
1137 {
1138 return lpc18xx_function_names[function];
1139 }
1140
1141 static int lpc18xx_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1142 unsigned function,
1143 const char *const **groups,
1144 unsigned *const num_groups)
1145 {
1146 struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
1147
1148 *groups = scu->func[function].groups;
1149 *num_groups = scu->func[function].ngroups;
1150
1151 return 0;
1152 }
1153
1154 static int lpc18xx_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
1155 unsigned group)
1156 {
1157 struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
1158 struct lpc18xx_pin_caps *pin = lpc18xx_pins[group].drv_data;
1159 int func;
1160 u32 reg;
1161
1162 /* Dedicated USB1 and I2C0 pins doesn't support muxing */
1163 if (pin->type == TYPE_USB1) {
1164 if (function == FUNC_USB1)
1165 return 0;
1166
1167 goto fail;
1168 }
1169
1170 if (pin->type == TYPE_I2C0) {
1171 if (function == FUNC_I2C0)
1172 return 0;
1173
1174 goto fail;
1175 }
1176
1177 if (function == FUNC_ADC && (pin->analog & LPC18XX_ANALOG_PIN)) {
1178 u32 offset;
1179
1180 writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset);
1181
1182 if (LPC18XX_ANALOG_ADC(pin->analog) == 0)
1183 offset = LPC18XX_SCU_REG_ENAIO0;
1184 else
1185 offset = LPC18XX_SCU_REG_ENAIO1;
1186
1187 reg = readl(scu->base + offset);
1188 reg |= pin->analog & LPC18XX_ANALOG_BIT_MASK;
1189 writel(reg, scu->base + offset);
1190
1191 return 0;
1192 }
1193
1194 if (function == FUNC_DAC && (pin->analog & LPC18XX_ANALOG_PIN)) {
1195 writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset);
1196
1197 reg = readl(scu->base + LPC18XX_SCU_REG_ENAIO2);
1198 reg |= LPC18XX_SCU_REG_ENAIO2_DAC;
1199 writel(reg, scu->base + LPC18XX_SCU_REG_ENAIO2);
1200
1201 return 0;
1202 }
1203
1204 for (func = 0; func < LPC18XX_SCU_FUNC_PER_PIN; func++) {
1205 if (function == pin->functions[func])
1206 break;
1207 }
1208
1209 if (func >= LPC18XX_SCU_FUNC_PER_PIN)
1210 goto fail;
1211
1212 reg = readl(scu->base + pin->offset);
1213 reg &= ~LPC18XX_SCU_PIN_MODE_MASK;
1214 writel(reg | func, scu->base + pin->offset);
1215
1216 return 0;
1217 fail:
1218 dev_err(pctldev->dev, "Pin %s can't be %s\n", lpc18xx_pins[group].name,
1219 lpc18xx_function_names[function]);
1220 return -EINVAL;
1221 }
1222
1223 static const struct pinmux_ops lpc18xx_pmx_ops = {
1224 .get_functions_count = lpc18xx_pmx_get_funcs_count,
1225 .get_function_name = lpc18xx_pmx_get_func_name,
1226 .get_function_groups = lpc18xx_pmx_get_func_groups,
1227 .set_mux = lpc18xx_pmx_set,
1228 };
1229
1230 static int lpc18xx_pctl_get_groups_count(struct pinctrl_dev *pctldev)
1231 {
1232 return ARRAY_SIZE(lpc18xx_pins);
1233 }
1234
1235 static const char *lpc18xx_pctl_get_group_name(struct pinctrl_dev *pctldev,
1236 unsigned group)
1237 {
1238 return lpc18xx_pins[group].name;
1239 }
1240
1241 static int lpc18xx_pctl_get_group_pins(struct pinctrl_dev *pctldev,
1242 unsigned group,
1243 const unsigned **pins,
1244 unsigned *num_pins)
1245 {
1246 *pins = &lpc18xx_pins[group].number;
1247 *num_pins = 1;
1248
1249 return 0;
1250 }
1251
1252 static const struct pinctrl_ops lpc18xx_pctl_ops = {
1253 .get_groups_count = lpc18xx_pctl_get_groups_count,
1254 .get_group_name = lpc18xx_pctl_get_group_name,
1255 .get_group_pins = lpc18xx_pctl_get_group_pins,
1256 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1257 .dt_free_map = pinctrl_utils_free_map,
1258 };
1259
1260 static struct pinctrl_desc lpc18xx_scu_desc = {
1261 .name = "lpc18xx/43xx-scu",
1262 .pins = lpc18xx_pins,
1263 .npins = ARRAY_SIZE(lpc18xx_pins),
1264 .pctlops = &lpc18xx_pctl_ops,
1265 .pmxops = &lpc18xx_pmx_ops,
1266 .confops = &lpc18xx_pconf_ops,
1267 .num_custom_params = ARRAY_SIZE(lpc18xx_params),
1268 .custom_params = lpc18xx_params,
1269 #ifdef CONFIG_DEBUG_FS
1270 .custom_conf_items = lpc18xx_conf_items,
1271 #endif
1272 .owner = THIS_MODULE,
1273 };
1274
1275 static bool lpc18xx_valid_pin_function(unsigned pin, unsigned function)
1276 {
1277 struct lpc18xx_pin_caps *p = lpc18xx_pins[pin].drv_data;
1278 int i;
1279
1280 if (function == FUNC_DAC && p->analog == DAC)
1281 return true;
1282
1283 if (function == FUNC_ADC && p->analog)
1284 return true;
1285
1286 if (function == FUNC_I2C0 && p->type == TYPE_I2C0)
1287 return true;
1288
1289 if (function == FUNC_USB1 && p->type == TYPE_USB1)
1290 return true;
1291
1292 for (i = 0; i < LPC18XX_SCU_FUNC_PER_PIN; i++) {
1293 if (function == p->functions[i])
1294 return true;
1295 }
1296
1297 return false;
1298 }
1299
1300 static int lpc18xx_create_group_func_map(struct device *dev,
1301 struct lpc18xx_scu_data *scu)
1302 {
1303 u16 pins[ARRAY_SIZE(lpc18xx_pins)];
1304 int func, ngroups, i;
1305
1306 for (func = 0; func < FUNC_MAX; func++) {
1307 for (ngroups = 0, i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
1308 if (lpc18xx_valid_pin_function(i, func))
1309 pins[ngroups++] = i;
1310 }
1311
1312 scu->func[func].ngroups = ngroups;
1313 scu->func[func].groups = devm_kcalloc(dev,
1314 ngroups, sizeof(char *),
1315 GFP_KERNEL);
1316 if (!scu->func[func].groups)
1317 return -ENOMEM;
1318
1319 for (i = 0; i < ngroups; i++)
1320 scu->func[func].groups[i] = lpc18xx_pins[pins[i]].name;
1321 }
1322
1323 return 0;
1324 }
1325
1326 static int lpc18xx_scu_probe(struct platform_device *pdev)
1327 {
1328 struct lpc18xx_scu_data *scu;
1329 int ret;
1330
1331 scu = devm_kzalloc(&pdev->dev, sizeof(*scu), GFP_KERNEL);
1332 if (!scu)
1333 return -ENOMEM;
1334
1335 scu->base = devm_platform_ioremap_resource(pdev, 0);
1336 if (IS_ERR(scu->base))
1337 return PTR_ERR(scu->base);
1338
1339 scu->clk = devm_clk_get(&pdev->dev, NULL);
1340 if (IS_ERR(scu->clk)) {
1341 dev_err(&pdev->dev, "Input clock not found.\n");
1342 return PTR_ERR(scu->clk);
1343 }
1344
1345 ret = lpc18xx_create_group_func_map(&pdev->dev, scu);
1346 if (ret) {
1347 dev_err(&pdev->dev, "Unable to create group func map.\n");
1348 return ret;
1349 }
1350
1351 ret = clk_prepare_enable(scu->clk);
1352 if (ret) {
1353 dev_err(&pdev->dev, "Unable to enable clock.\n");
1354 return ret;
1355 }
1356
1357 platform_set_drvdata(pdev, scu);
1358
1359 scu->pctl = devm_pinctrl_register(&pdev->dev, &lpc18xx_scu_desc, scu);
1360 if (IS_ERR(scu->pctl)) {
1361 dev_err(&pdev->dev, "Could not register pinctrl driver\n");
1362 clk_disable_unprepare(scu->clk);
1363 return PTR_ERR(scu->pctl);
1364 }
1365
1366 return 0;
1367 }
1368
1369 static const struct of_device_id lpc18xx_scu_match[] = {
1370 { .compatible = "nxp,lpc1850-scu" },
1371 {},
1372 };
1373
1374 static struct platform_driver lpc18xx_scu_driver = {
1375 .probe = lpc18xx_scu_probe,
1376 .driver = {
1377 .name = "lpc18xx-scu",
1378 .of_match_table = lpc18xx_scu_match,
1379 .suppress_bind_attrs = true,
1380 },
1381 };
1382 builtin_platform_driver(lpc18xx_scu_driver);
Kernel DRM miscellaneous fixes and cross-tree changes