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Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / pinctrl / qcom / pinctrl-sc8180x.c
blobd6a79ad41a40a804c503d97a6279db4b533f0047
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2021, Linaro Ltd.
5 */
6
7 #include <linux/module.h>
8 #include <linux/of.h>
9 #include <linux/platform_device.h>
10
11 #include "pinctrl-msm.h"
12
13 static const char * const sc8180x_tiles[] = {
14 "south",
15 "east",
16 "west"
17 };
18
19 enum {
20 SOUTH,
21 EAST,
22 WEST
23 };
24
25 /*
26 * ACPI DSDT has one single memory resource for TLMM. The offsets below are
27 * used to locate different tiles for ACPI probe.
28 */
29 struct tile_info {
30 u32 offset;
31 u32 size;
32 };
33
34 static const struct tile_info sc8180x_tile_info[] = {
35 { 0x00d00000, 0x00300000, },
36 { 0x00500000, 0x00700000, },
37 { 0x00100000, 0x00300000, },
38 };
39
40 #define REG_SIZE 0x1000
41 #define PINGROUP_OFFSET(id, _tile, offset, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
42 { \
43 .grp = PINCTRL_PINGROUP("gpio" #id, \
44 gpio##id##_pins, \
45 ARRAY_SIZE(gpio##id##_pins)), \
46 .funcs = (int[]){ \
47 msm_mux_gpio, /* gpio mode */ \
48 msm_mux_##f1, \
49 msm_mux_##f2, \
50 msm_mux_##f3, \
51 msm_mux_##f4, \
52 msm_mux_##f5, \
53 msm_mux_##f6, \
54 msm_mux_##f7, \
55 msm_mux_##f8, \
56 msm_mux_##f9 \
57 }, \
58 .nfuncs = 10, \
59 .ctl_reg = REG_SIZE * id + offset, \
60 .io_reg = REG_SIZE * id + 0x4 + offset, \
61 .intr_cfg_reg = REG_SIZE * id + 0x8 + offset, \
62 .intr_status_reg = REG_SIZE * id + 0xc + offset,\
63 .intr_target_reg = REG_SIZE * id + 0x8 + offset,\
64 .tile = _tile, \
65 .mux_bit = 2, \
66 .pull_bit = 0, \
67 .drv_bit = 6, \
68 .oe_bit = 9, \
69 .in_bit = 0, \
70 .out_bit = 1, \
71 .intr_enable_bit = 0, \
72 .intr_status_bit = 0, \
73 .intr_target_bit = 5, \
74 .intr_target_kpss_val = 3, \
75 .intr_raw_status_bit = 4, \
76 .intr_polarity_bit = 1, \
77 .intr_detection_bit = 2, \
78 .intr_detection_width = 2, \
79 }
80
81 #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
82 PINGROUP_OFFSET(id, _tile, 0x0, f1, f2, f3, f4, f5, f6, f7, f8, f9)
83
84 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
85 { \
86 .grp = PINCTRL_PINGROUP(#pg_name, \
87 pg_name##_pins, \
88 ARRAY_SIZE(pg_name##_pins)), \
89 .ctl_reg = ctl, \
90 .io_reg = 0, \
91 .intr_cfg_reg = 0, \
92 .intr_status_reg = 0, \
93 .intr_target_reg = 0, \
94 .tile = EAST, \
95 .mux_bit = -1, \
96 .pull_bit = pull, \
97 .drv_bit = drv, \
98 .oe_bit = -1, \
99 .in_bit = -1, \
100 .out_bit = -1, \
101 .intr_enable_bit = -1, \
102 .intr_status_bit = -1, \
103 .intr_target_bit = -1, \
104 .intr_raw_status_bit = -1, \
105 .intr_polarity_bit = -1, \
106 .intr_detection_bit = -1, \
107 .intr_detection_width = -1, \
108 }
109
110 #define UFS_RESET(pg_name) \
111 { \
112 .grp = PINCTRL_PINGROUP(#pg_name, \
113 pg_name##_pins, \
114 ARRAY_SIZE(pg_name##_pins)), \
115 .ctl_reg = 0xb6000, \
116 .io_reg = 0xb6004, \
117 .intr_cfg_reg = 0, \
118 .intr_status_reg = 0, \
119 .intr_target_reg = 0, \
120 .tile = SOUTH, \
121 .mux_bit = -1, \
122 .pull_bit = 3, \
123 .drv_bit = 0, \
124 .oe_bit = -1, \
125 .in_bit = -1, \
126 .out_bit = 0, \
127 .intr_enable_bit = -1, \
128 .intr_status_bit = -1, \
129 .intr_target_bit = -1, \
130 .intr_raw_status_bit = -1, \
131 .intr_polarity_bit = -1, \
132 .intr_detection_bit = -1, \
133 .intr_detection_width = -1, \
134 }
135 static const struct pinctrl_pin_desc sc8180x_pins[] = {
136 PINCTRL_PIN(0, "GPIO_0"),
137 PINCTRL_PIN(1, "GPIO_1"),
138 PINCTRL_PIN(2, "GPIO_2"),
139 PINCTRL_PIN(3, "GPIO_3"),
140 PINCTRL_PIN(4, "GPIO_4"),
141 PINCTRL_PIN(5, "GPIO_5"),
142 PINCTRL_PIN(6, "GPIO_6"),
143 PINCTRL_PIN(7, "GPIO_7"),
144 PINCTRL_PIN(8, "GPIO_8"),
145 PINCTRL_PIN(9, "GPIO_9"),
146 PINCTRL_PIN(10, "GPIO_10"),
147 PINCTRL_PIN(11, "GPIO_11"),
148 PINCTRL_PIN(12, "GPIO_12"),
149 PINCTRL_PIN(13, "GPIO_13"),
150 PINCTRL_PIN(14, "GPIO_14"),
151 PINCTRL_PIN(15, "GPIO_15"),
152 PINCTRL_PIN(16, "GPIO_16"),
153 PINCTRL_PIN(17, "GPIO_17"),
154 PINCTRL_PIN(18, "GPIO_18"),
155 PINCTRL_PIN(19, "GPIO_19"),
156 PINCTRL_PIN(20, "GPIO_20"),
157 PINCTRL_PIN(21, "GPIO_21"),
158 PINCTRL_PIN(22, "GPIO_22"),
159 PINCTRL_PIN(23, "GPIO_23"),
160 PINCTRL_PIN(24, "GPIO_24"),
161 PINCTRL_PIN(25, "GPIO_25"),
162 PINCTRL_PIN(26, "GPIO_26"),
163 PINCTRL_PIN(27, "GPIO_27"),
164 PINCTRL_PIN(28, "GPIO_28"),
165 PINCTRL_PIN(29, "GPIO_29"),
166 PINCTRL_PIN(30, "GPIO_30"),
167 PINCTRL_PIN(31, "GPIO_31"),
168 PINCTRL_PIN(32, "GPIO_32"),
169 PINCTRL_PIN(33, "GPIO_33"),
170 PINCTRL_PIN(34, "GPIO_34"),
171 PINCTRL_PIN(35, "GPIO_35"),
172 PINCTRL_PIN(36, "GPIO_36"),
173 PINCTRL_PIN(37, "GPIO_37"),
174 PINCTRL_PIN(38, "GPIO_38"),
175 PINCTRL_PIN(39, "GPIO_39"),
176 PINCTRL_PIN(40, "GPIO_40"),
177 PINCTRL_PIN(41, "GPIO_41"),
178 PINCTRL_PIN(42, "GPIO_42"),
179 PINCTRL_PIN(43, "GPIO_43"),
180 PINCTRL_PIN(44, "GPIO_44"),
181 PINCTRL_PIN(45, "GPIO_45"),
182 PINCTRL_PIN(46, "GPIO_46"),
183 PINCTRL_PIN(47, "GPIO_47"),
184 PINCTRL_PIN(48, "GPIO_48"),
185 PINCTRL_PIN(49, "GPIO_49"),
186 PINCTRL_PIN(50, "GPIO_50"),
187 PINCTRL_PIN(51, "GPIO_51"),
188 PINCTRL_PIN(52, "GPIO_52"),
189 PINCTRL_PIN(53, "GPIO_53"),
190 PINCTRL_PIN(54, "GPIO_54"),
191 PINCTRL_PIN(55, "GPIO_55"),
192 PINCTRL_PIN(56, "GPIO_56"),
193 PINCTRL_PIN(57, "GPIO_57"),
194 PINCTRL_PIN(58, "GPIO_58"),
195 PINCTRL_PIN(59, "GPIO_59"),
196 PINCTRL_PIN(60, "GPIO_60"),
197 PINCTRL_PIN(61, "GPIO_61"),
198 PINCTRL_PIN(62, "GPIO_62"),
199 PINCTRL_PIN(63, "GPIO_63"),
200 PINCTRL_PIN(64, "GPIO_64"),
201 PINCTRL_PIN(65, "GPIO_65"),
202 PINCTRL_PIN(66, "GPIO_66"),
203 PINCTRL_PIN(67, "GPIO_67"),
204 PINCTRL_PIN(68, "GPIO_68"),
205 PINCTRL_PIN(69, "GPIO_69"),
206 PINCTRL_PIN(70, "GPIO_70"),
207 PINCTRL_PIN(71, "GPIO_71"),
208 PINCTRL_PIN(72, "GPIO_72"),
209 PINCTRL_PIN(73, "GPIO_73"),
210 PINCTRL_PIN(74, "GPIO_74"),
211 PINCTRL_PIN(75, "GPIO_75"),
212 PINCTRL_PIN(76, "GPIO_76"),
213 PINCTRL_PIN(77, "GPIO_77"),
214 PINCTRL_PIN(78, "GPIO_78"),
215 PINCTRL_PIN(79, "GPIO_79"),
216 PINCTRL_PIN(80, "GPIO_80"),
217 PINCTRL_PIN(81, "GPIO_81"),
218 PINCTRL_PIN(82, "GPIO_82"),
219 PINCTRL_PIN(83, "GPIO_83"),
220 PINCTRL_PIN(84, "GPIO_84"),
221 PINCTRL_PIN(85, "GPIO_85"),
222 PINCTRL_PIN(86, "GPIO_86"),
223 PINCTRL_PIN(87, "GPIO_87"),
224 PINCTRL_PIN(88, "GPIO_88"),
225 PINCTRL_PIN(89, "GPIO_89"),
226 PINCTRL_PIN(90, "GPIO_90"),
227 PINCTRL_PIN(91, "GPIO_91"),
228 PINCTRL_PIN(92, "GPIO_92"),
229 PINCTRL_PIN(93, "GPIO_93"),
230 PINCTRL_PIN(94, "GPIO_94"),
231 PINCTRL_PIN(95, "GPIO_95"),
232 PINCTRL_PIN(96, "GPIO_96"),
233 PINCTRL_PIN(97, "GPIO_97"),
234 PINCTRL_PIN(98, "GPIO_98"),
235 PINCTRL_PIN(99, "GPIO_99"),
236 PINCTRL_PIN(100, "GPIO_100"),
237 PINCTRL_PIN(101, "GPIO_101"),
238 PINCTRL_PIN(102, "GPIO_102"),
239 PINCTRL_PIN(103, "GPIO_103"),
240 PINCTRL_PIN(104, "GPIO_104"),
241 PINCTRL_PIN(105, "GPIO_105"),
242 PINCTRL_PIN(106, "GPIO_106"),
243 PINCTRL_PIN(107, "GPIO_107"),
244 PINCTRL_PIN(108, "GPIO_108"),
245 PINCTRL_PIN(109, "GPIO_109"),
246 PINCTRL_PIN(110, "GPIO_110"),
247 PINCTRL_PIN(111, "GPIO_111"),
248 PINCTRL_PIN(112, "GPIO_112"),
249 PINCTRL_PIN(113, "GPIO_113"),
250 PINCTRL_PIN(114, "GPIO_114"),
251 PINCTRL_PIN(115, "GPIO_115"),
252 PINCTRL_PIN(116, "GPIO_116"),
253 PINCTRL_PIN(117, "GPIO_117"),
254 PINCTRL_PIN(118, "GPIO_118"),
255 PINCTRL_PIN(119, "GPIO_119"),
256 PINCTRL_PIN(120, "GPIO_120"),
257 PINCTRL_PIN(121, "GPIO_121"),
258 PINCTRL_PIN(122, "GPIO_122"),
259 PINCTRL_PIN(123, "GPIO_123"),
260 PINCTRL_PIN(124, "GPIO_124"),
261 PINCTRL_PIN(125, "GPIO_125"),
262 PINCTRL_PIN(126, "GPIO_126"),
263 PINCTRL_PIN(127, "GPIO_127"),
264 PINCTRL_PIN(128, "GPIO_128"),
265 PINCTRL_PIN(129, "GPIO_129"),
266 PINCTRL_PIN(130, "GPIO_130"),
267 PINCTRL_PIN(131, "GPIO_131"),
268 PINCTRL_PIN(132, "GPIO_132"),
269 PINCTRL_PIN(133, "GPIO_133"),
270 PINCTRL_PIN(134, "GPIO_134"),
271 PINCTRL_PIN(135, "GPIO_135"),
272 PINCTRL_PIN(136, "GPIO_136"),
273 PINCTRL_PIN(137, "GPIO_137"),
274 PINCTRL_PIN(138, "GPIO_138"),
275 PINCTRL_PIN(139, "GPIO_139"),
276 PINCTRL_PIN(140, "GPIO_140"),
277 PINCTRL_PIN(141, "GPIO_141"),
278 PINCTRL_PIN(142, "GPIO_142"),
279 PINCTRL_PIN(143, "GPIO_143"),
280 PINCTRL_PIN(144, "GPIO_144"),
281 PINCTRL_PIN(145, "GPIO_145"),
282 PINCTRL_PIN(146, "GPIO_146"),
283 PINCTRL_PIN(147, "GPIO_147"),
284 PINCTRL_PIN(148, "GPIO_148"),
285 PINCTRL_PIN(149, "GPIO_149"),
286 PINCTRL_PIN(150, "GPIO_150"),
287 PINCTRL_PIN(151, "GPIO_151"),
288 PINCTRL_PIN(152, "GPIO_152"),
289 PINCTRL_PIN(153, "GPIO_153"),
290 PINCTRL_PIN(154, "GPIO_154"),
291 PINCTRL_PIN(155, "GPIO_155"),
292 PINCTRL_PIN(156, "GPIO_156"),
293 PINCTRL_PIN(157, "GPIO_157"),
294 PINCTRL_PIN(158, "GPIO_158"),
295 PINCTRL_PIN(159, "GPIO_159"),
296 PINCTRL_PIN(160, "GPIO_160"),
297 PINCTRL_PIN(161, "GPIO_161"),
298 PINCTRL_PIN(162, "GPIO_162"),
299 PINCTRL_PIN(163, "GPIO_163"),
300 PINCTRL_PIN(164, "GPIO_164"),
301 PINCTRL_PIN(165, "GPIO_165"),
302 PINCTRL_PIN(166, "GPIO_166"),
303 PINCTRL_PIN(167, "GPIO_167"),
304 PINCTRL_PIN(168, "GPIO_168"),
305 PINCTRL_PIN(169, "GPIO_169"),
306 PINCTRL_PIN(170, "GPIO_170"),
307 PINCTRL_PIN(171, "GPIO_171"),
308 PINCTRL_PIN(172, "GPIO_172"),
309 PINCTRL_PIN(173, "GPIO_173"),
310 PINCTRL_PIN(174, "GPIO_174"),
311 PINCTRL_PIN(175, "GPIO_175"),
312 PINCTRL_PIN(176, "GPIO_176"),
313 PINCTRL_PIN(177, "GPIO_177"),
314 PINCTRL_PIN(178, "GPIO_178"),
315 PINCTRL_PIN(179, "GPIO_179"),
316 PINCTRL_PIN(180, "GPIO_180"),
317 PINCTRL_PIN(181, "GPIO_181"),
318 PINCTRL_PIN(182, "GPIO_182"),
319 PINCTRL_PIN(183, "GPIO_183"),
320 PINCTRL_PIN(184, "GPIO_184"),
321 PINCTRL_PIN(185, "GPIO_185"),
322 PINCTRL_PIN(186, "GPIO_186"),
323 PINCTRL_PIN(187, "GPIO_187"),
324 PINCTRL_PIN(188, "GPIO_188"),
325 PINCTRL_PIN(189, "GPIO_189"),
326 PINCTRL_PIN(190, "UFS_RESET"),
327 PINCTRL_PIN(191, "SDC2_CLK"),
328 PINCTRL_PIN(192, "SDC2_CMD"),
329 PINCTRL_PIN(193, "SDC2_DATA"),
330 };
331
332 #define DECLARE_MSM_GPIO_PINS(pin) \
333 static const unsigned int gpio##pin##_pins[] = { pin }
334 DECLARE_MSM_GPIO_PINS(0);
335 DECLARE_MSM_GPIO_PINS(1);
336 DECLARE_MSM_GPIO_PINS(2);
337 DECLARE_MSM_GPIO_PINS(3);
338 DECLARE_MSM_GPIO_PINS(4);
339 DECLARE_MSM_GPIO_PINS(5);
340 DECLARE_MSM_GPIO_PINS(6);
341 DECLARE_MSM_GPIO_PINS(7);
342 DECLARE_MSM_GPIO_PINS(8);
343 DECLARE_MSM_GPIO_PINS(9);
344 DECLARE_MSM_GPIO_PINS(10);
345 DECLARE_MSM_GPIO_PINS(11);
346 DECLARE_MSM_GPIO_PINS(12);
347 DECLARE_MSM_GPIO_PINS(13);
348 DECLARE_MSM_GPIO_PINS(14);
349 DECLARE_MSM_GPIO_PINS(15);
350 DECLARE_MSM_GPIO_PINS(16);
351 DECLARE_MSM_GPIO_PINS(17);
352 DECLARE_MSM_GPIO_PINS(18);
353 DECLARE_MSM_GPIO_PINS(19);
354 DECLARE_MSM_GPIO_PINS(20);
355 DECLARE_MSM_GPIO_PINS(21);
356 DECLARE_MSM_GPIO_PINS(22);
357 DECLARE_MSM_GPIO_PINS(23);
358 DECLARE_MSM_GPIO_PINS(24);
359 DECLARE_MSM_GPIO_PINS(25);
360 DECLARE_MSM_GPIO_PINS(26);
361 DECLARE_MSM_GPIO_PINS(27);
362 DECLARE_MSM_GPIO_PINS(28);
363 DECLARE_MSM_GPIO_PINS(29);
364 DECLARE_MSM_GPIO_PINS(30);
365 DECLARE_MSM_GPIO_PINS(31);
366 DECLARE_MSM_GPIO_PINS(32);
367 DECLARE_MSM_GPIO_PINS(33);
368 DECLARE_MSM_GPIO_PINS(34);
369 DECLARE_MSM_GPIO_PINS(35);
370 DECLARE_MSM_GPIO_PINS(36);
371 DECLARE_MSM_GPIO_PINS(37);
372 DECLARE_MSM_GPIO_PINS(38);
373 DECLARE_MSM_GPIO_PINS(39);
374 DECLARE_MSM_GPIO_PINS(40);
375 DECLARE_MSM_GPIO_PINS(41);
376 DECLARE_MSM_GPIO_PINS(42);
377 DECLARE_MSM_GPIO_PINS(43);
378 DECLARE_MSM_GPIO_PINS(44);
379 DECLARE_MSM_GPIO_PINS(45);
380 DECLARE_MSM_GPIO_PINS(46);
381 DECLARE_MSM_GPIO_PINS(47);
382 DECLARE_MSM_GPIO_PINS(48);
383 DECLARE_MSM_GPIO_PINS(49);
384 DECLARE_MSM_GPIO_PINS(50);
385 DECLARE_MSM_GPIO_PINS(51);
386 DECLARE_MSM_GPIO_PINS(52);
387 DECLARE_MSM_GPIO_PINS(53);
388 DECLARE_MSM_GPIO_PINS(54);
389 DECLARE_MSM_GPIO_PINS(55);
390 DECLARE_MSM_GPIO_PINS(56);
391 DECLARE_MSM_GPIO_PINS(57);
392 DECLARE_MSM_GPIO_PINS(58);
393 DECLARE_MSM_GPIO_PINS(59);
394 DECLARE_MSM_GPIO_PINS(60);
395 DECLARE_MSM_GPIO_PINS(61);
396 DECLARE_MSM_GPIO_PINS(62);
397 DECLARE_MSM_GPIO_PINS(63);
398 DECLARE_MSM_GPIO_PINS(64);
399 DECLARE_MSM_GPIO_PINS(65);
400 DECLARE_MSM_GPIO_PINS(66);
401 DECLARE_MSM_GPIO_PINS(67);
402 DECLARE_MSM_GPIO_PINS(68);
403 DECLARE_MSM_GPIO_PINS(69);
404 DECLARE_MSM_GPIO_PINS(70);
405 DECLARE_MSM_GPIO_PINS(71);
406 DECLARE_MSM_GPIO_PINS(72);
407 DECLARE_MSM_GPIO_PINS(73);
408 DECLARE_MSM_GPIO_PINS(74);
409 DECLARE_MSM_GPIO_PINS(75);
410 DECLARE_MSM_GPIO_PINS(76);
411 DECLARE_MSM_GPIO_PINS(77);
412 DECLARE_MSM_GPIO_PINS(78);
413 DECLARE_MSM_GPIO_PINS(79);
414 DECLARE_MSM_GPIO_PINS(80);
415 DECLARE_MSM_GPIO_PINS(81);
416 DECLARE_MSM_GPIO_PINS(82);
417 DECLARE_MSM_GPIO_PINS(83);
418 DECLARE_MSM_GPIO_PINS(84);
419 DECLARE_MSM_GPIO_PINS(85);
420 DECLARE_MSM_GPIO_PINS(86);
421 DECLARE_MSM_GPIO_PINS(87);
422 DECLARE_MSM_GPIO_PINS(88);
423 DECLARE_MSM_GPIO_PINS(89);
424 DECLARE_MSM_GPIO_PINS(90);
425 DECLARE_MSM_GPIO_PINS(91);
426 DECLARE_MSM_GPIO_PINS(92);
427 DECLARE_MSM_GPIO_PINS(93);
428 DECLARE_MSM_GPIO_PINS(94);
429 DECLARE_MSM_GPIO_PINS(95);
430 DECLARE_MSM_GPIO_PINS(96);
431 DECLARE_MSM_GPIO_PINS(97);
432 DECLARE_MSM_GPIO_PINS(98);
433 DECLARE_MSM_GPIO_PINS(99);
434 DECLARE_MSM_GPIO_PINS(100);
435 DECLARE_MSM_GPIO_PINS(101);
436 DECLARE_MSM_GPIO_PINS(102);
437 DECLARE_MSM_GPIO_PINS(103);
438 DECLARE_MSM_GPIO_PINS(104);
439 DECLARE_MSM_GPIO_PINS(105);
440 DECLARE_MSM_GPIO_PINS(106);
441 DECLARE_MSM_GPIO_PINS(107);
442 DECLARE_MSM_GPIO_PINS(108);
443 DECLARE_MSM_GPIO_PINS(109);
444 DECLARE_MSM_GPIO_PINS(110);
445 DECLARE_MSM_GPIO_PINS(111);
446 DECLARE_MSM_GPIO_PINS(112);
447 DECLARE_MSM_GPIO_PINS(113);
448 DECLARE_MSM_GPIO_PINS(114);
449 DECLARE_MSM_GPIO_PINS(115);
450 DECLARE_MSM_GPIO_PINS(116);
451 DECLARE_MSM_GPIO_PINS(117);
452 DECLARE_MSM_GPIO_PINS(118);
453 DECLARE_MSM_GPIO_PINS(119);
454 DECLARE_MSM_GPIO_PINS(120);
455 DECLARE_MSM_GPIO_PINS(121);
456 DECLARE_MSM_GPIO_PINS(122);
457 DECLARE_MSM_GPIO_PINS(123);
458 DECLARE_MSM_GPIO_PINS(124);
459 DECLARE_MSM_GPIO_PINS(125);
460 DECLARE_MSM_GPIO_PINS(126);
461 DECLARE_MSM_GPIO_PINS(127);
462 DECLARE_MSM_GPIO_PINS(128);
463 DECLARE_MSM_GPIO_PINS(129);
464 DECLARE_MSM_GPIO_PINS(130);
465 DECLARE_MSM_GPIO_PINS(131);
466 DECLARE_MSM_GPIO_PINS(132);
467 DECLARE_MSM_GPIO_PINS(133);
468 DECLARE_MSM_GPIO_PINS(134);
469 DECLARE_MSM_GPIO_PINS(135);
470 DECLARE_MSM_GPIO_PINS(136);
471 DECLARE_MSM_GPIO_PINS(137);
472 DECLARE_MSM_GPIO_PINS(138);
473 DECLARE_MSM_GPIO_PINS(139);
474 DECLARE_MSM_GPIO_PINS(140);
475 DECLARE_MSM_GPIO_PINS(141);
476 DECLARE_MSM_GPIO_PINS(142);
477 DECLARE_MSM_GPIO_PINS(143);
478 DECLARE_MSM_GPIO_PINS(144);
479 DECLARE_MSM_GPIO_PINS(145);
480 DECLARE_MSM_GPIO_PINS(146);
481 DECLARE_MSM_GPIO_PINS(147);
482 DECLARE_MSM_GPIO_PINS(148);
483 DECLARE_MSM_GPIO_PINS(149);
484 DECLARE_MSM_GPIO_PINS(150);
485 DECLARE_MSM_GPIO_PINS(151);
486 DECLARE_MSM_GPIO_PINS(152);
487 DECLARE_MSM_GPIO_PINS(153);
488 DECLARE_MSM_GPIO_PINS(154);
489 DECLARE_MSM_GPIO_PINS(155);
490 DECLARE_MSM_GPIO_PINS(156);
491 DECLARE_MSM_GPIO_PINS(157);
492 DECLARE_MSM_GPIO_PINS(158);
493 DECLARE_MSM_GPIO_PINS(159);
494 DECLARE_MSM_GPIO_PINS(160);
495 DECLARE_MSM_GPIO_PINS(161);
496 DECLARE_MSM_GPIO_PINS(162);
497 DECLARE_MSM_GPIO_PINS(163);
498 DECLARE_MSM_GPIO_PINS(164);
499 DECLARE_MSM_GPIO_PINS(165);
500 DECLARE_MSM_GPIO_PINS(166);
501 DECLARE_MSM_GPIO_PINS(167);
502 DECLARE_MSM_GPIO_PINS(168);
503 DECLARE_MSM_GPIO_PINS(169);
504 DECLARE_MSM_GPIO_PINS(170);
505 DECLARE_MSM_GPIO_PINS(171);
506 DECLARE_MSM_GPIO_PINS(172);
507 DECLARE_MSM_GPIO_PINS(173);
508 DECLARE_MSM_GPIO_PINS(174);
509 DECLARE_MSM_GPIO_PINS(175);
510 DECLARE_MSM_GPIO_PINS(176);
511 DECLARE_MSM_GPIO_PINS(177);
512 DECLARE_MSM_GPIO_PINS(178);
513 DECLARE_MSM_GPIO_PINS(179);
514 DECLARE_MSM_GPIO_PINS(180);
515 DECLARE_MSM_GPIO_PINS(181);
516 DECLARE_MSM_GPIO_PINS(182);
517 DECLARE_MSM_GPIO_PINS(183);
518 DECLARE_MSM_GPIO_PINS(184);
519 DECLARE_MSM_GPIO_PINS(185);
520 DECLARE_MSM_GPIO_PINS(186);
521 DECLARE_MSM_GPIO_PINS(187);
522 DECLARE_MSM_GPIO_PINS(188);
523 DECLARE_MSM_GPIO_PINS(189);
524
525 static const unsigned int ufs_reset_pins[] = { 190 };
526 static const unsigned int sdc2_clk_pins[] = { 191 };
527 static const unsigned int sdc2_cmd_pins[] = { 192 };
528 static const unsigned int sdc2_data_pins[] = { 193 };
529
530 enum sc8180x_functions {
531 msm_mux_adsp_ext,
532 msm_mux_agera_pll,
533 msm_mux_aoss_cti,
534 msm_mux_atest_char,
535 msm_mux_atest_tsens,
536 msm_mux_atest_tsens2,
537 msm_mux_atest_usb0,
538 msm_mux_atest_usb1,
539 msm_mux_atest_usb2,
540 msm_mux_atest_usb3,
541 msm_mux_atest_usb4,
542 msm_mux_audio_ref,
543 msm_mux_btfm_slimbus,
544 msm_mux_cam_mclk,
545 msm_mux_cci_async,
546 msm_mux_cci_i2c,
547 msm_mux_cci_timer0,
548 msm_mux_cci_timer1,
549 msm_mux_cci_timer2,
550 msm_mux_cci_timer3,
551 msm_mux_cci_timer4,
552 msm_mux_cci_timer5,
553 msm_mux_cci_timer6,
554 msm_mux_cci_timer7,
555 msm_mux_cci_timer8,
556 msm_mux_cci_timer9,
557 msm_mux_cri_trng,
558 msm_mux_dbg_out,
559 msm_mux_ddr_bist,
560 msm_mux_ddr_pxi,
561 msm_mux_debug_hot,
562 msm_mux_dp_hot,
563 msm_mux_edp_hot,
564 msm_mux_edp_lcd,
565 msm_mux_emac_phy,
566 msm_mux_emac_pps,
567 msm_mux_gcc_gp1,
568 msm_mux_gcc_gp2,
569 msm_mux_gcc_gp3,
570 msm_mux_gcc_gp4,
571 msm_mux_gcc_gp5,
572 msm_mux_gpio,
573 msm_mux_gps,
574 msm_mux_grfc,
575 msm_mux_hs1_mi2s,
576 msm_mux_hs2_mi2s,
577 msm_mux_hs3_mi2s,
578 msm_mux_jitter_bist,
579 msm_mux_lpass_slimbus,
580 msm_mux_m_voc,
581 msm_mux_mdp_vsync,
582 msm_mux_mdp_vsync0,
583 msm_mux_mdp_vsync1,
584 msm_mux_mdp_vsync2,
585 msm_mux_mdp_vsync3,
586 msm_mux_mdp_vsync4,
587 msm_mux_mdp_vsync5,
588 msm_mux_mss_lte,
589 msm_mux_nav_pps,
590 msm_mux_pa_indicator,
591 msm_mux_pci_e0,
592 msm_mux_pci_e1,
593 msm_mux_pci_e2,
594 msm_mux_pci_e3,
595 msm_mux_phase_flag,
596 msm_mux_pll_bist,
597 msm_mux_pll_bypassnl,
598 msm_mux_pll_reset,
599 msm_mux_pri_mi2s,
600 msm_mux_pri_mi2s_ws,
601 msm_mux_prng_rosc,
602 msm_mux_qdss_cti,
603 msm_mux_qdss_gpio,
604 msm_mux_qlink,
605 msm_mux_qspi0,
606 msm_mux_qspi0_clk,
607 msm_mux_qspi0_cs,
608 msm_mux_qspi1,
609 msm_mux_qspi1_clk,
610 msm_mux_qspi1_cs,
611 msm_mux_qua_mi2s,
612 msm_mux_qup0,
613 msm_mux_qup1,
614 msm_mux_qup2,
615 msm_mux_qup3,
616 msm_mux_qup4,
617 msm_mux_qup5,
618 msm_mux_qup6,
619 msm_mux_qup7,
620 msm_mux_qup8,
621 msm_mux_qup9,
622 msm_mux_qup10,
623 msm_mux_qup11,
624 msm_mux_qup12,
625 msm_mux_qup13,
626 msm_mux_qup14,
627 msm_mux_qup15,
628 msm_mux_qup16,
629 msm_mux_qup17,
630 msm_mux_qup18,
631 msm_mux_qup19,
632 msm_mux_qup_l4,
633 msm_mux_qup_l5,
634 msm_mux_qup_l6,
635 msm_mux_rgmii,
636 msm_mux_sd_write,
637 msm_mux_sdc4,
638 msm_mux_sdc4_clk,
639 msm_mux_sdc4_cmd,
640 msm_mux_sec_mi2s,
641 msm_mux_sp_cmu,
642 msm_mux_spkr_i2s,
643 msm_mux_ter_mi2s,
644 msm_mux_tgu,
645 msm_mux_tsense_pwm1,
646 msm_mux_tsense_pwm2,
647 msm_mux_tsif1,
648 msm_mux_tsif2,
649 msm_mux_uim1,
650 msm_mux_uim2,
651 msm_mux_uim_batt,
652 msm_mux_usb0_phy,
653 msm_mux_usb1_phy,
654 msm_mux_usb2phy_ac,
655 msm_mux_vfr_1,
656 msm_mux_vsense_trigger,
657 msm_mux_wlan1_adc,
658 msm_mux_wlan2_adc,
659 msm_mux_wmss_reset,
660 msm_mux__,
661 };
662
663 static const char * const adsp_ext_groups[] = {
664 "gpio115",
665 };
666
667 static const char * const agera_pll_groups[] = {
668 "gpio37",
669 };
670
671 static const char * const aoss_cti_groups[] = {
672 "gpio113",
673 };
674
675 static const char * const atest_char_groups[] = {
676 "gpio133", "gpio134", "gpio135", "gpio140", "gpio142",
677 };
678
679 static const char * const atest_tsens2_groups[] = {
680 "gpio62",
681 };
682
683 static const char * const atest_tsens_groups[] = {
684 "gpio93",
685 };
686
687 static const char * const atest_usb0_groups[] = {
688 "gpio90", "gpio91", "gpio92", "gpio93", "gpio94",
689 };
690
691 static const char * const atest_usb1_groups[] = {
692 "gpio60", "gpio62", "gpio63", "gpio64", "gpio65",
693 };
694
695 static const char * const atest_usb2_groups[] = {
696 "gpio34", "gpio95", "gpio102", "gpio121", "gpio122",
697 };
698
699 static const char * const atest_usb3_groups[] = {
700 "gpio68", "gpio71", "gpio72", "gpio73", "gpio74",
701 };
702
703 static const char * const atest_usb4_groups[] = {
704 "gpio75", "gpio76", "gpio77", "gpio78", "gpio88",
705 };
706
707 static const char * const audio_ref_groups[] = {
708 "gpio148",
709 };
710
711 static const char * const btfm_slimbus_groups[] = {
712 "gpio153", "gpio154",
713 };
714
715 static const char * const cam_mclk_groups[] = {
716 "gpio13", "gpio14", "gpio15", "gpio16", "gpio25", "gpio179", "gpio180",
717 "gpio181",
718 };
719
720 static const char * const cci_async_groups[] = {
721 "gpio24", "gpio25", "gpio26", "gpio176", "gpio185", "gpio186",
722 };
723
724 static const char * const cci_i2c_groups[] = {
725 "gpio0", "gpio1", "gpio2", "gpio3", "gpio17", "gpio18", "gpio19",
726 "gpio20", "gpio31", "gpio32", "gpio33", "gpio34", "gpio39", "gpio40",
727 "gpio41", "gpio42",
728 };
729
730 static const char * const cci_timer0_groups[] = {
731 "gpio21",
732 };
733
734 static const char * const cci_timer1_groups[] = {
735 "gpio22",
736 };
737
738 static const char * const cci_timer2_groups[] = {
739 "gpio23",
740 };
741
742 static const char * const cci_timer3_groups[] = {
743 "gpio24",
744 };
745
746 static const char * const cci_timer4_groups[] = {
747 "gpio178",
748 };
749
750 static const char * const cci_timer5_groups[] = {
751 "gpio182",
752 };
753
754 static const char * const cci_timer6_groups[] = {
755 "gpio183",
756 };
757
758 static const char * const cci_timer7_groups[] = {
759 "gpio184",
760 };
761
762 static const char * const cci_timer8_groups[] = {
763 "gpio185",
764 };
765
766 static const char * const cci_timer9_groups[] = {
767 "gpio186",
768 };
769
770 static const char * const cri_trng_groups[] = {
771 "gpio159",
772 "gpio160",
773 "gpio161",
774 };
775
776 static const char * const dbg_out_groups[] = {
777 "gpio34",
778 };
779
780 static const char * const ddr_bist_groups[] = {
781 "gpio98", "gpio99", "gpio145", "gpio146",
782 };
783
784 static const char * const ddr_pxi_groups[] = {
785 "gpio60", "gpio62", "gpio63", "gpio64", "gpio65", "gpio68", "gpio71",
786 "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", "gpio78",
787 "gpio88", "gpio90",
788 };
789
790 static const char * const debug_hot_groups[] = {
791 "gpio7",
792 };
793
794 static const char * const dp_hot_groups[] = {
795 "gpio189",
796 };
797
798 static const char * const edp_hot_groups[] = {
799 "gpio10",
800 };
801
802 static const char * const edp_lcd_groups[] = {
803 "gpio11",
804 };
805
806 static const char * const emac_phy_groups[] = {
807 "gpio124",
808 };
809
810 static const char * const emac_pps_groups[] = {
811 "gpio81",
812 };
813
814 static const char * const gcc_gp1_groups[] = {
815 "gpio131", "gpio136",
816 };
817
818 static const char * const gcc_gp2_groups[] = {
819 "gpio21", "gpio137",
820 };
821
822 static const char * const gcc_gp3_groups[] = {
823 "gpio22", "gpio138",
824 };
825
826 static const char * const gcc_gp4_groups[] = {
827 "gpio139", "gpio182",
828 };
829
830 static const char * const gcc_gp5_groups[] = {
831 "gpio140", "gpio183",
832 };
833
834 static const char * const gpio_groups[] = {
835 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
836 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio12", "gpio13",
837 "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20",
838 "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27",
839 "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34",
840 "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41",
841 "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
842 "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55",
843 "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62",
844 "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69",
845 "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76",
846 "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
847 "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90",
848 "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97",
849 "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103",
850 "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109",
851 "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115",
852 "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
853 "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio127",
854 "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", "gpio133",
855 "gpio134", "gpio135", "gpio136", "gpio137", "gpio138", "gpio139",
856 "gpio140", "gpio141", "gpio142", "gpio143", "gpio144", "gpio145",
857 "gpio146", "gpio147", "gpio148", "gpio149", "gpio150", "gpio151",
858 "gpio152", "gpio153", "gpio154", "gpio155", "gpio156", "gpio157",
859 "gpio158", "gpio159", "gpio160", "gpio161", "gpio162", "gpio163",
860 "gpio164", "gpio165", "gpio166", "gpio167", "gpio168", "gpio169",
861 "gpio170", "gpio171", "gpio172", "gpio173", "gpio174", "gpio175",
862 "gpio176", "gpio177", "gpio177", "gpio178", "gpio179", "gpio180",
863 "gpio181", "gpio182", "gpio183", "gpio184", "gpio185", "gpio186",
864 "gpio186", "gpio187", "gpio187", "gpio188", "gpio188", "gpio189",
865 };
866
867 static const char * const gps_groups[] = {
868 "gpio60", "gpio76", "gpio77", "gpio81", "gpio82",
869 };
870
871 static const char * const grfc_groups[] = {
872 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio71", "gpio72",
873 "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", "gpio78", "gpio79",
874 "gpio80", "gpio81", "gpio82",
875 };
876
877 static const char * const hs1_mi2s_groups[] = {
878 "gpio155", "gpio156", "gpio157", "gpio158", "gpio159",
879 };
880
881 static const char * const hs2_mi2s_groups[] = {
882 "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
883 };
884
885 static const char * const hs3_mi2s_groups[] = {
886 "gpio125", "gpio165", "gpio166", "gpio167", "gpio168",
887 };
888
889 static const char * const jitter_bist_groups[] = {
890 "gpio129",
891 };
892
893 static const char * const lpass_slimbus_groups[] = {
894 "gpio149", "gpio150", "gpio151", "gpio152",
895 };
896
897 static const char * const m_voc_groups[] = {
898 "gpio10",
899 };
900
901 static const char * const mdp_vsync0_groups[] = {
902 "gpio89",
903 };
904
905 static const char * const mdp_vsync1_groups[] = {
906 "gpio89",
907 };
908
909 static const char * const mdp_vsync2_groups[] = {
910 "gpio89",
911 };
912
913 static const char * const mdp_vsync3_groups[] = {
914 "gpio89",
915 };
916
917 static const char * const mdp_vsync4_groups[] = {
918 "gpio89",
919 };
920
921 static const char * const mdp_vsync5_groups[] = {
922 "gpio89",
923 };
924
925 static const char * const mdp_vsync_groups[] = {
926 "gpio8", "gpio9", "gpio10", "gpio60", "gpio82",
927 };
928
929 static const char * const mss_lte_groups[] = {
930 "gpio69", "gpio70",
931 };
932
933 static const char * const nav_pps_groups[] = {
934 "gpio60", "gpio60", "gpio76", "gpio76", "gpio77", "gpio77", "gpio81",
935 "gpio81", "gpio82", "gpio82",
936 };
937
938 static const char * const pa_indicator_groups[] = {
939 "gpio68",
940 };
941
942 static const char * const pci_e0_groups[] = {
943 "gpio35", "gpio36",
944 };
945
946 static const char * const pci_e1_groups[] = {
947 "gpio102", "gpio103",
948 };
949
950 static const char * const pci_e2_groups[] = {
951 "gpio175", "gpio176",
952 };
953
954 static const char * const pci_e3_groups[] = {
955 "gpio178", "gpio179",
956 };
957
958 static const char * const phase_flag_groups[] = {
959 "gpio4", "gpio5", "gpio6", "gpio7", "gpio33", "gpio53", "gpio54",
960 "gpio102", "gpio120", "gpio121", "gpio122", "gpio123", "gpio125",
961 "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", "gpio155",
962 "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161",
963 "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167",
964 "gpio168",
965 };
966
967 static const char * const pll_bist_groups[] = {
968 "gpio130",
969 };
970
971 static const char * const pll_bypassnl_groups[] = {
972 "gpio100",
973 };
974
975 static const char * const pll_reset_groups[] = {
976 "gpio101",
977 };
978
979 static const char * const pri_mi2s_groups[] = {
980 "gpio143", "gpio144", "gpio146", "gpio147",
981 };
982
983 static const char * const pri_mi2s_ws_groups[] = {
984 "gpio145",
985 };
986
987 static const char * const prng_rosc_groups[] = {
988 "gpio163",
989 };
990
991 static const char * const qdss_cti_groups[] = {
992 "gpio49", "gpio50", "gpio81", "gpio82", "gpio89", "gpio90", "gpio141",
993 "gpio142",
994 };
995
996 static const char * const qdss_gpio_groups[] = {
997 "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
998 "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
999 "gpio27", "gpio28", "gpio29", "gpio30", "gpio39", "gpio40", "gpio41",
1000 "gpio42", "gpio92", "gpio114", "gpio115", "gpio116", "gpio117",
1001 "gpio118", "gpio119", "gpio120", "gpio121", "gpio130", "gpio132",
1002 "gpio133", "gpio134", "gpio135",
1003 };
1004
1005 static const char * const qlink_groups[] = {
1006 "gpio61", "gpio62",
1007 };
1008
1009 static const char * const qspi0_groups[] = {
1010 "gpio89", "gpio90", "gpio91", "gpio93",
1011 };
1012
1013 static const char * const qspi0_clk_groups[] = {
1014 "gpio92",
1015 };
1016
1017 static const char * const qspi0_cs_groups[] = {
1018 "gpio88", "gpio94",
1019 };
1020
1021 static const char * const qspi1_groups[] = {
1022 "gpio56", "gpio57", "gpio161", "gpio162",
1023 };
1024
1025 static const char * const qspi1_clk_groups[] = {
1026 "gpio163",
1027 };
1028
1029 static const char * const qspi1_cs_groups[] = {
1030 "gpio55", "gpio164",
1031 };
1032
1033 static const char * const qua_mi2s_groups[] = {
1034 "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", "gpio141",
1035 "gpio142",
1036 };
1037
1038 static const char * const qup0_groups[] = {
1039 "gpio0", "gpio1", "gpio2", "gpio3",
1040 };
1041
1042 static const char * const qup10_groups[] = {
1043 "gpio9", "gpio10", "gpio11", "gpio12",
1044 };
1045
1046 static const char * const qup11_groups[] = {
1047 "gpio92", "gpio93", "gpio94", "gpio95",
1048 };
1049
1050 static const char * const qup12_groups[] = {
1051 "gpio83", "gpio84", "gpio85", "gpio86",
1052 };
1053
1054 static const char * const qup13_groups[] = {
1055 "gpio43", "gpio44", "gpio45", "gpio46",
1056 };
1057
1058 static const char * const qup14_groups[] = {
1059 "gpio47", "gpio48", "gpio49", "gpio50",
1060 };
1061
1062 static const char * const qup15_groups[] = {
1063 "gpio27", "gpio28", "gpio29", "gpio30",
1064 };
1065
1066 static const char * const qup16_groups[] = {
1067 "gpio83", "gpio84", "gpio85", "gpio86",
1068 };
1069
1070 static const char * const qup17_groups[] = {
1071 "gpio55", "gpio56", "gpio57", "gpio58",
1072 };
1073
1074 static const char * const qup18_groups[] = {
1075 "gpio23", "gpio24", "gpio25", "gpio26",
1076 };
1077
1078 static const char * const qup19_groups[] = {
1079 "gpio181", "gpio182", "gpio183", "gpio184",
1080 };
1081
1082 static const char * const qup1_groups[] = {
1083 "gpio114", "gpio115", "gpio116", "gpio117",
1084 };
1085
1086 static const char * const qup2_groups[] = {
1087 "gpio126", "gpio127", "gpio128", "gpio129",
1088 };
1089
1090 static const char * const qup3_groups[] = {
1091 "gpio144", "gpio145", "gpio146", "gpio147",
1092 };
1093
1094 static const char * const qup4_groups[] = {
1095 "gpio51", "gpio52", "gpio53", "gpio54",
1096 };
1097
1098 static const char * const qup5_groups[] = {
1099 "gpio119", "gpio120", "gpio121", "gpio122",
1100 };
1101
1102 static const char * const qup6_groups[] = {
1103 "gpio4", "gpio5", "gpio6", "gpio7",
1104 };
1105
1106 static const char * const qup7_groups[] = {
1107 "gpio98", "gpio99", "gpio100", "gpio101",
1108 };
1109
1110 static const char * const qup8_groups[] = {
1111 "gpio88", "gpio89", "gpio90", "gpio91",
1112 };
1113
1114 static const char * const qup9_groups[] = {
1115 "gpio39", "gpio40", "gpio41", "gpio42",
1116 };
1117
1118 static const char * const qup_l4_groups[] = {
1119 "gpio35", "gpio59", "gpio60", "gpio95",
1120 };
1121
1122 static const char * const qup_l5_groups[] = {
1123 "gpio7", "gpio33", "gpio36", "gpio96",
1124 };
1125
1126 static const char * const qup_l6_groups[] = {
1127 "gpio6", "gpio34", "gpio37", "gpio97",
1128 };
1129
1130 static const char * const rgmii_groups[] = {
1131 "gpio4", "gpio5", "gpio6", "gpio7", "gpio59", "gpio114", "gpio115",
1132 "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
1133 "gpio122",
1134 };
1135
1136 static const char * const sd_write_groups[] = {
1137 "gpio97",
1138 };
1139
1140 static const char * const sdc4_groups[] = {
1141 "gpio91", "gpio93", "gpio94", "gpio95",
1142 };
1143
1144 static const char * const sdc4_clk_groups[] = {
1145 "gpio92",
1146 };
1147
1148 static const char * const sdc4_cmd_groups[] = {
1149 "gpio90",
1150 };
1151
1152 static const char * const sec_mi2s_groups[] = {
1153 "gpio126", "gpio127", "gpio128", "gpio129", "gpio130",
1154 };
1155
1156 static const char * const sp_cmu_groups[] = {
1157 "gpio162",
1158 };
1159
1160 static const char * const spkr_i2s_groups[] = {
1161 "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
1162 };
1163
1164 static const char * const ter_mi2s_groups[] = {
1165 "gpio131", "gpio132", "gpio133", "gpio134", "gpio135",
1166 };
1167
1168 static const char * const tgu_groups[] = {
1169 "gpio89", "gpio90", "gpio91", "gpio88", "gpio74", "gpio77", "gpio76",
1170 "gpio75",
1171 };
1172
1173 static const char * const tsense_pwm1_groups[] = {
1174 "gpio150",
1175 };
1176
1177 static const char * const tsense_pwm2_groups[] = {
1178 "gpio150",
1179 };
1180
1181 static const char * const tsif1_groups[] = {
1182 "gpio88", "gpio89", "gpio90", "gpio91", "gpio97",
1183 };
1184
1185 static const char * const tsif2_groups[] = {
1186 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96",
1187 };
1188
1189 static const char * const uim1_groups[] = {
1190 "gpio109", "gpio110", "gpio111", "gpio112",
1191 };
1192
1193 static const char * const uim2_groups[] = {
1194 "gpio105", "gpio106", "gpio107", "gpio108",
1195 };
1196
1197 static const char * const uim_batt_groups[] = {
1198 "gpio113",
1199 };
1200
1201 static const char * const usb0_phy_groups[] = {
1202 "gpio38",
1203 };
1204
1205 static const char * const usb1_phy_groups[] = {
1206 "gpio58",
1207 };
1208
1209 static const char * const usb2phy_ac_groups[] = {
1210 "gpio47", "gpio48", "gpio113", "gpio123",
1211 };
1212
1213 static const char * const vfr_1_groups[] = {
1214 "gpio91",
1215 };
1216
1217 static const char * const vsense_trigger_groups[] = {
1218 "gpio62",
1219 };
1220
1221 static const char * const wlan1_adc_groups[] = {
1222 "gpio64", "gpio63",
1223 };
1224
1225 static const char * const wlan2_adc_groups[] = {
1226 "gpio68", "gpio65",
1227 };
1228
1229 static const char * const wmss_reset_groups[] = {
1230 "gpio63",
1231 };
1232
1233 static const struct pinfunction sc8180x_functions[] = {
1234 MSM_PIN_FUNCTION(adsp_ext),
1235 MSM_PIN_FUNCTION(agera_pll),
1236 MSM_PIN_FUNCTION(aoss_cti),
1237 MSM_PIN_FUNCTION(atest_char),
1238 MSM_PIN_FUNCTION(atest_tsens),
1239 MSM_PIN_FUNCTION(atest_tsens2),
1240 MSM_PIN_FUNCTION(atest_usb0),
1241 MSM_PIN_FUNCTION(atest_usb1),
1242 MSM_PIN_FUNCTION(atest_usb2),
1243 MSM_PIN_FUNCTION(atest_usb3),
1244 MSM_PIN_FUNCTION(atest_usb4),
1245 MSM_PIN_FUNCTION(audio_ref),
1246 MSM_PIN_FUNCTION(btfm_slimbus),
1247 MSM_PIN_FUNCTION(cam_mclk),
1248 MSM_PIN_FUNCTION(cci_async),
1249 MSM_PIN_FUNCTION(cci_i2c),
1250 MSM_PIN_FUNCTION(cci_timer0),
1251 MSM_PIN_FUNCTION(cci_timer1),
1252 MSM_PIN_FUNCTION(cci_timer2),
1253 MSM_PIN_FUNCTION(cci_timer3),
1254 MSM_PIN_FUNCTION(cci_timer4),
1255 MSM_PIN_FUNCTION(cci_timer5),
1256 MSM_PIN_FUNCTION(cci_timer6),
1257 MSM_PIN_FUNCTION(cci_timer7),
1258 MSM_PIN_FUNCTION(cci_timer8),
1259 MSM_PIN_FUNCTION(cci_timer9),
1260 MSM_PIN_FUNCTION(cri_trng),
1261 MSM_PIN_FUNCTION(dbg_out),
1262 MSM_PIN_FUNCTION(ddr_bist),
1263 MSM_PIN_FUNCTION(ddr_pxi),
1264 MSM_PIN_FUNCTION(debug_hot),
1265 MSM_PIN_FUNCTION(dp_hot),
1266 MSM_PIN_FUNCTION(edp_hot),
1267 MSM_PIN_FUNCTION(edp_lcd),
1268 MSM_PIN_FUNCTION(emac_phy),
1269 MSM_PIN_FUNCTION(emac_pps),
1270 MSM_PIN_FUNCTION(gcc_gp1),
1271 MSM_PIN_FUNCTION(gcc_gp2),
1272 MSM_PIN_FUNCTION(gcc_gp3),
1273 MSM_PIN_FUNCTION(gcc_gp4),
1274 MSM_PIN_FUNCTION(gcc_gp5),
1275 MSM_PIN_FUNCTION(gpio),
1276 MSM_PIN_FUNCTION(gps),
1277 MSM_PIN_FUNCTION(grfc),
1278 MSM_PIN_FUNCTION(hs1_mi2s),
1279 MSM_PIN_FUNCTION(hs2_mi2s),
1280 MSM_PIN_FUNCTION(hs3_mi2s),
1281 MSM_PIN_FUNCTION(jitter_bist),
1282 MSM_PIN_FUNCTION(lpass_slimbus),
1283 MSM_PIN_FUNCTION(m_voc),
1284 MSM_PIN_FUNCTION(mdp_vsync),
1285 MSM_PIN_FUNCTION(mdp_vsync0),
1286 MSM_PIN_FUNCTION(mdp_vsync1),
1287 MSM_PIN_FUNCTION(mdp_vsync2),
1288 MSM_PIN_FUNCTION(mdp_vsync3),
1289 MSM_PIN_FUNCTION(mdp_vsync4),
1290 MSM_PIN_FUNCTION(mdp_vsync5),
1291 MSM_PIN_FUNCTION(mss_lte),
1292 MSM_PIN_FUNCTION(nav_pps),
1293 MSM_PIN_FUNCTION(pa_indicator),
1294 MSM_PIN_FUNCTION(pci_e0),
1295 MSM_PIN_FUNCTION(pci_e1),
1296 MSM_PIN_FUNCTION(pci_e2),
1297 MSM_PIN_FUNCTION(pci_e3),
1298 MSM_PIN_FUNCTION(phase_flag),
1299 MSM_PIN_FUNCTION(pll_bist),
1300 MSM_PIN_FUNCTION(pll_bypassnl),
1301 MSM_PIN_FUNCTION(pll_reset),
1302 MSM_PIN_FUNCTION(pri_mi2s),
1303 MSM_PIN_FUNCTION(pri_mi2s_ws),
1304 MSM_PIN_FUNCTION(prng_rosc),
1305 MSM_PIN_FUNCTION(qdss_cti),
1306 MSM_PIN_FUNCTION(qdss_gpio),
1307 MSM_PIN_FUNCTION(qlink),
1308 MSM_PIN_FUNCTION(qspi0),
1309 MSM_PIN_FUNCTION(qspi0_clk),
1310 MSM_PIN_FUNCTION(qspi0_cs),
1311 MSM_PIN_FUNCTION(qspi1),
1312 MSM_PIN_FUNCTION(qspi1_clk),
1313 MSM_PIN_FUNCTION(qspi1_cs),
1314 MSM_PIN_FUNCTION(qua_mi2s),
1315 MSM_PIN_FUNCTION(qup0),
1316 MSM_PIN_FUNCTION(qup1),
1317 MSM_PIN_FUNCTION(qup2),
1318 MSM_PIN_FUNCTION(qup3),
1319 MSM_PIN_FUNCTION(qup4),
1320 MSM_PIN_FUNCTION(qup5),
1321 MSM_PIN_FUNCTION(qup6),
1322 MSM_PIN_FUNCTION(qup7),
1323 MSM_PIN_FUNCTION(qup8),
1324 MSM_PIN_FUNCTION(qup9),
1325 MSM_PIN_FUNCTION(qup10),
1326 MSM_PIN_FUNCTION(qup11),
1327 MSM_PIN_FUNCTION(qup12),
1328 MSM_PIN_FUNCTION(qup13),
1329 MSM_PIN_FUNCTION(qup14),
1330 MSM_PIN_FUNCTION(qup15),
1331 MSM_PIN_FUNCTION(qup16),
1332 MSM_PIN_FUNCTION(qup17),
1333 MSM_PIN_FUNCTION(qup18),
1334 MSM_PIN_FUNCTION(qup19),
1335 MSM_PIN_FUNCTION(qup_l4),
1336 MSM_PIN_FUNCTION(qup_l5),
1337 MSM_PIN_FUNCTION(qup_l6),
1338 MSM_PIN_FUNCTION(rgmii),
1339 MSM_PIN_FUNCTION(sd_write),
1340 MSM_PIN_FUNCTION(sdc4),
1341 MSM_PIN_FUNCTION(sdc4_clk),
1342 MSM_PIN_FUNCTION(sdc4_cmd),
1343 MSM_PIN_FUNCTION(sec_mi2s),
1344 MSM_PIN_FUNCTION(sp_cmu),
1345 MSM_PIN_FUNCTION(spkr_i2s),
1346 MSM_PIN_FUNCTION(ter_mi2s),
1347 MSM_PIN_FUNCTION(tgu),
1348 MSM_PIN_FUNCTION(tsense_pwm1),
1349 MSM_PIN_FUNCTION(tsense_pwm2),
1350 MSM_PIN_FUNCTION(tsif1),
1351 MSM_PIN_FUNCTION(tsif2),
1352 MSM_PIN_FUNCTION(uim1),
1353 MSM_PIN_FUNCTION(uim2),
1354 MSM_PIN_FUNCTION(uim_batt),
1355 MSM_PIN_FUNCTION(usb0_phy),
1356 MSM_PIN_FUNCTION(usb1_phy),
1357 MSM_PIN_FUNCTION(usb2phy_ac),
1358 MSM_PIN_FUNCTION(vfr_1),
1359 MSM_PIN_FUNCTION(vsense_trigger),
1360 MSM_PIN_FUNCTION(wlan1_adc),
1361 MSM_PIN_FUNCTION(wlan2_adc),
1362 MSM_PIN_FUNCTION(wmss_reset),
1363 };
1364
1365 /* Every pin is maintained as a single group, and missing or non-existing pin
1366 * would be maintained as dummy group to synchronize pin group index with
1367 * pin descriptor registered with pinctrl core.
1368 * Clients would not be able to request these dummy pin groups.
1369 */
1370 static const struct msm_pingroup sc8180x_groups[] = {
1371 [0] = PINGROUP(0, WEST, qup0, cci_i2c, _, _, _, _, _, _, _),
1372 [1] = PINGROUP(1, WEST, qup0, cci_i2c, _, _, _, _, _, _, _),
1373 [2] = PINGROUP(2, WEST, qup0, cci_i2c, _, _, _, _, _, _, _),
1374 [3] = PINGROUP(3, WEST, qup0, cci_i2c, _, _, _, _, _, _, _),
1375 [4] = PINGROUP(4, WEST, qup6, rgmii, _, phase_flag, _, _, _, _, _),
1376 [5] = PINGROUP(5, WEST, qup6, rgmii, _, phase_flag, _, _, _, _, _),
1377 [6] = PINGROUP(6, WEST, qup6, rgmii, qup_l6, _, phase_flag, _, _, _, _),
1378 [7] = PINGROUP(7, WEST, qup6, debug_hot, rgmii, qup_l5, _, phase_flag, _, _, _),
1379 [8] = PINGROUP(8, EAST, mdp_vsync, _, _, _, _, _, _, _, _),
1380 [9] = PINGROUP(9, EAST, mdp_vsync, qup10, _, _, _, _, _, _, _),
1381 [10] = PINGROUP(10, EAST, edp_hot, m_voc, mdp_vsync, qup10, _, _, _, _, _),
1382 [11] = PINGROUP(11, EAST, edp_lcd, qup10, _, _, _, _, _, _, _),
1383 [12] = PINGROUP(12, EAST, qup10, _, _, _, _, _, _, _, _),
1384 [13] = PINGROUP(13, EAST, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1385 [14] = PINGROUP(14, EAST, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1386 [15] = PINGROUP(15, EAST, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1387 [16] = PINGROUP(16, EAST, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1388 [17] = PINGROUP(17, EAST, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1389 [18] = PINGROUP(18, EAST, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1390 [19] = PINGROUP(19, EAST, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1391 [20] = PINGROUP(20, EAST, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1392 [21] = PINGROUP(21, EAST, cci_timer0, gcc_gp2, qdss_gpio, _, _, _, _, _, _),
1393 [22] = PINGROUP(22, EAST, cci_timer1, gcc_gp3, qdss_gpio, _, _, _, _, _, _),
1394 [23] = PINGROUP(23, EAST, cci_timer2, qup18, qdss_gpio, _, _, _, _, _, _),
1395 [24] = PINGROUP(24, EAST, cci_timer3, cci_async, qup18, qdss_gpio, _, _, _, _, _),
1396 [25] = PINGROUP(25, EAST, cam_mclk, cci_async, qup18, qdss_gpio, _, _, _, _, _),
1397 [26] = PINGROUP(26, EAST, cci_async, qup18, qdss_gpio, _, _, _, _, _, _),
1398 [27] = PINGROUP(27, EAST, qup15, _, qdss_gpio, _, _, _, _, _, _),
1399 [28] = PINGROUP(28, EAST, qup15, qdss_gpio, _, _, _, _, _, _, _),
1400 [29] = PINGROUP(29, EAST, qup15, qdss_gpio, _, _, _, _, _, _, _),
1401 [30] = PINGROUP(30, EAST, qup15, qdss_gpio, _, _, _, _, _, _, _),
1402 [31] = PINGROUP(31, EAST, cci_i2c, _, _, _, _, _, _, _, _),
1403 [32] = PINGROUP(32, EAST, cci_i2c, _, _, _, _, _, _, _, _),
1404 [33] = PINGROUP(33, EAST, cci_i2c, qup_l5, _, phase_flag, _, _, _, _, _),
1405 [34] = PINGROUP(34, EAST, cci_i2c, qup_l6, dbg_out, atest_usb2, _, _, _, _, _),
1406 [35] = PINGROUP(35, SOUTH, pci_e0, qup_l4, _, _, _, _, _, _, _),
1407 [36] = PINGROUP(36, SOUTH, pci_e0, qup_l5, _, _, _, _, _, _, _),
1408 [37] = PINGROUP(37, SOUTH, qup_l6, agera_pll, _, _, _, _, _, _, _),
1409 [38] = PINGROUP(38, SOUTH, usb0_phy, _, _, _, _, _, _, _, _),
1410 [39] = PINGROUP(39, EAST, qup9, cci_i2c, qdss_gpio, _, _, _, _, _, _),
1411 [40] = PINGROUP(40, EAST, qup9, cci_i2c, qdss_gpio, _, _, _, _, _, _),
1412 [41] = PINGROUP(41, EAST, qup9, cci_i2c, qdss_gpio, _, _, _, _, _, _),
1413 [42] = PINGROUP(42, EAST, qup9, cci_i2c, qdss_gpio, _, _, _, _, _, _),
1414 [43] = PINGROUP(43, EAST, qup13, _, _, _, _, _, _, _, _),
1415 [44] = PINGROUP(44, EAST, qup13, _, _, _, _, _, _, _, _),
1416 [45] = PINGROUP(45, EAST, qup13, _, _, _, _, _, _, _, _),
1417 [46] = PINGROUP(46, EAST, qup13, _, _, _, _, _, _, _, _),
1418 [47] = PINGROUP(47, EAST, qup14, usb2phy_ac, _, _, _, _, _, _, _),
1419 [48] = PINGROUP(48, EAST, qup14, usb2phy_ac, _, _, _, _, _, _, _),
1420 [49] = PINGROUP(49, EAST, qup14, qdss_cti, _, _, _, _, _, _, _),
1421 [50] = PINGROUP(50, EAST, qup14, qdss_cti, _, _, _, _, _, _, _),
1422 [51] = PINGROUP(51, WEST, qup4, _, _, _, _, _, _, _, _),
1423 [52] = PINGROUP(52, WEST, qup4, _, _, _, _, _, _, _, _),
1424 [53] = PINGROUP(53, WEST, qup4, _, phase_flag, _, _, _, _, _, _),
1425 [54] = PINGROUP(54, WEST, qup4, _, _, phase_flag, _, _, _, _, _),
1426 [55] = PINGROUP(55, WEST, qup17, qspi1_cs, _, _, _, _, _, _, _),
1427 [56] = PINGROUP(56, WEST, qup17, qspi1, _, _, _, _, _, _, _),
1428 [57] = PINGROUP(57, WEST, qup17, qspi1, _, _, _, _, _, _, _),
1429 [58] = PINGROUP(58, WEST, usb1_phy, qup17, _, _, _, _, _, _, _),
1430 [59] = PINGROUP(59, WEST, rgmii, qup_l4, _, _, _, _, _, _, _),
1431 [60] = PINGROUP(60, EAST, gps, nav_pps, nav_pps, qup_l4, mdp_vsync, atest_usb1, ddr_pxi, _, _),
1432 [61] = PINGROUP(61, EAST, qlink, _, _, _, _, _, _, _, _),
1433 [62] = PINGROUP(62, EAST, qlink, atest_tsens2, atest_usb1, ddr_pxi, vsense_trigger, _, _, _, _),
1434 [63] = PINGROUP(63, EAST, wmss_reset, _, atest_usb1, ddr_pxi, wlan1_adc, _, _, _, _),
1435 [64] = PINGROUP(64, EAST, grfc, _, atest_usb1, ddr_pxi, wlan1_adc, _, _, _, _),
1436 [65] = PINGROUP(65, EAST, grfc, atest_usb1, ddr_pxi, wlan2_adc, _, _, _, _, _),
1437 [66] = PINGROUP(66, EAST, grfc, _, _, _, _, _, _, _, _),
1438 [67] = PINGROUP(67, EAST, grfc, _, _, _, _, _, _, _, _),
1439 [68] = PINGROUP(68, EAST, grfc, pa_indicator, atest_usb3, ddr_pxi, wlan2_adc, _, _, _, _),
1440 [69] = PINGROUP(69, EAST, mss_lte, _, _, _, _, _, _, _, _),
1441 [70] = PINGROUP(70, EAST, mss_lte, _, _, _, _, _, _, _, _),
1442 [71] = PINGROUP(71, EAST, _, grfc, atest_usb3, ddr_pxi, _, _, _, _, _),
1443 [72] = PINGROUP(72, EAST, _, grfc, atest_usb3, ddr_pxi, _, _, _, _, _),
1444 [73] = PINGROUP(73, EAST, _, grfc, atest_usb3, ddr_pxi, _, _, _, _, _),
1445 [74] = PINGROUP(74, EAST, _, grfc, tgu, atest_usb3, ddr_pxi, _, _, _, _),
1446 [75] = PINGROUP(75, EAST, _, grfc, tgu, atest_usb4, ddr_pxi, _, _, _, _),
1447 [76] = PINGROUP(76, EAST, _, grfc, gps, nav_pps, nav_pps, tgu, atest_usb4, ddr_pxi, _),
1448 [77] = PINGROUP(77, EAST, _, grfc, gps, nav_pps, nav_pps, tgu, atest_usb4, ddr_pxi, _),
1449 [78] = PINGROUP(78, EAST, _, grfc, _, atest_usb4, ddr_pxi, _, _, _, _),
1450 [79] = PINGROUP(79, EAST, _, grfc, _, _, _, _, _, _, _),
1451 [80] = PINGROUP(80, EAST, _, grfc, _, _, _, _, _, _, _),
1452 [81] = PINGROUP(81, EAST, _, grfc, gps, nav_pps, nav_pps, qdss_cti, _, emac_pps, _),
1453 [82] = PINGROUP(82, EAST, _, grfc, gps, nav_pps, nav_pps, mdp_vsync, qdss_cti, _, _),
1454 [83] = PINGROUP(83, EAST, qup12, qup16, _, _, _, _, _, _, _),
1455 [84] = PINGROUP(84, EAST, qup12, qup16, _, _, _, _, _, _, _),
1456 [85] = PINGROUP(85, EAST, qup12, qup16, _, _, _, _, _, _, _),
1457 [86] = PINGROUP(86, EAST, qup12, qup16, _, _, _, _, _, _, _),
1458 [87] = PINGROUP(87, SOUTH, _, _, _, _, _, _, _, _, _),
1459 [88] = PINGROUP(88, EAST, tsif1, qup8, qspi0_cs, tgu, atest_usb4, ddr_pxi, _, _, _),
1460 [89] = PINGROUP(89, EAST, tsif1, qup8, qspi0, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5),
1461 [90] = PINGROUP(90, EAST, tsif1, qup8, qspi0, sdc4_cmd, tgu, qdss_cti, atest_usb0, ddr_pxi, _),
1462 [91] = PINGROUP(91, EAST, tsif1, qup8, qspi0, sdc4, vfr_1, tgu, atest_usb0, _, _),
1463 [92] = PINGROUP(92, EAST, tsif2, qup11, qspi0_clk, sdc4_clk, qdss_gpio, atest_usb0, _, _, _),
1464 [93] = PINGROUP(93, EAST, tsif2, qup11, qspi0, sdc4, atest_tsens, atest_usb0, _, _, _),
1465 [94] = PINGROUP(94, EAST, tsif2, qup11, qspi0_cs, sdc4, _, atest_usb0, _, _, _),
1466 [95] = PINGROUP(95, EAST, tsif2, qup11, sdc4, qup_l4, atest_usb2, _, _, _, _),
1467 [96] = PINGROUP(96, WEST, tsif2, qup_l5, _, _, _, _, _, _, _),
1468 [97] = PINGROUP(97, WEST, sd_write, tsif1, qup_l6, _, _, _, _, _, _),
1469 [98] = PINGROUP(98, WEST, qup7, ddr_bist, _, _, _, _, _, _, _),
1470 [99] = PINGROUP(99, WEST, qup7, ddr_bist, _, _, _, _, _, _, _),
1471 [100] = PINGROUP(100, WEST, qup7, pll_bypassnl, _, _, _, _, _, _, _),
1472 [101] = PINGROUP(101, WEST, qup7, pll_reset, _, _, _, _, _, _, _),
1473 [102] = PINGROUP(102, SOUTH, pci_e1, _, phase_flag, atest_usb2, _, _, _, _, _),
1474 [103] = PINGROUP(103, SOUTH, pci_e1, _, _, _, _, _, _, _, _),
1475 [104] = PINGROUP(104, SOUTH, _, _, _, _, _, _, _, _, _),
1476 [105] = PINGROUP(105, WEST, uim2, _, _, _, _, _, _, _, _),
1477 [106] = PINGROUP(106, WEST, uim2, _, _, _, _, _, _, _, _),
1478 [107] = PINGROUP(107, WEST, uim2, _, _, _, _, _, _, _, _),
1479 [108] = PINGROUP(108, WEST, uim2, _, _, _, _, _, _, _, _),
1480 [109] = PINGROUP(109, WEST, uim1, _, _, _, _, _, _, _, _),
1481 [110] = PINGROUP(110, WEST, uim1, _, _, _, _, _, _, _, _),
1482 [111] = PINGROUP(111, WEST, uim1, _, _, _, _, _, _, _, _),
1483 [112] = PINGROUP(112, WEST, uim1, _, _, _, _, _, _, _, _),
1484 [113] = PINGROUP(113, WEST, uim_batt, usb2phy_ac, aoss_cti, _, _, _, _, _, _),
1485 [114] = PINGROUP(114, WEST, qup1, rgmii, _, qdss_gpio, _, _, _, _, _),
1486 [115] = PINGROUP(115, WEST, qup1, rgmii, adsp_ext, _, qdss_gpio, _, _, _, _),
1487 [116] = PINGROUP(116, WEST, qup1, rgmii, _, qdss_gpio, _, _, _, _, _),
1488 [117] = PINGROUP(117, WEST, qup1, rgmii, _, qdss_gpio, _, _, _, _, _),
1489 [118] = PINGROUP(118, WEST, rgmii, _, qdss_gpio, _, _, _, _, _, _),
1490 [119] = PINGROUP(119, WEST, qup5, rgmii, _, qdss_gpio, _, _, _, _, _),
1491 [120] = PINGROUP(120, WEST, qup5, rgmii, _, phase_flag, qdss_gpio, _, _, _, _),
1492 [121] = PINGROUP(121, WEST, qup5, rgmii, _, phase_flag, qdss_gpio, atest_usb2, _, _, _),
1493 [122] = PINGROUP(122, WEST, qup5, rgmii, _, phase_flag, atest_usb2, _, _, _, _),
1494 [123] = PINGROUP(123, SOUTH, usb2phy_ac, _, phase_flag, _, _, _, _, _, _),
1495 [124] = PINGROUP(124, SOUTH, emac_phy, _, _, _, _, _, _, _, _),
1496 [125] = PINGROUP(125, WEST, hs3_mi2s, _, phase_flag, _, _, _, _, _, _),
1497 [126] = PINGROUP(126, WEST, sec_mi2s, qup2, _, _, _, _, _, _, _),
1498 [127] = PINGROUP(127, WEST, sec_mi2s, qup2, _, _, _, _, _, _, _),
1499 [128] = PINGROUP(128, WEST, sec_mi2s, qup2, _, _, _, _, _, _, _),
1500 [129] = PINGROUP(129, WEST, sec_mi2s, qup2, jitter_bist, _, _, _, _, _, _),
1501 [130] = PINGROUP(130, WEST, sec_mi2s, pll_bist, _, qdss_gpio, _, _, _, _, _),
1502 [131] = PINGROUP(131, WEST, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _),
1503 [132] = PINGROUP(132, WEST, ter_mi2s, _, qdss_gpio, _, _, _, _, _, _),
1504 [133] = PINGROUP(133, WEST, ter_mi2s, _, qdss_gpio, atest_char, _, _, _, _, _),
1505 [134] = PINGROUP(134, WEST, ter_mi2s, _, qdss_gpio, atest_char, _, _, _, _, _),
1506 [135] = PINGROUP(135, WEST, ter_mi2s, _, qdss_gpio, atest_char, _, _, _, _, _),
1507 [136] = PINGROUP(136, WEST, qua_mi2s, gcc_gp1, _, _, _, _, _, _, _),
1508 [137] = PINGROUP(137, WEST, qua_mi2s, gcc_gp2, _, _, _, _, _, _, _),
1509 [138] = PINGROUP(138, WEST, qua_mi2s, gcc_gp3, _, _, _, _, _, _, _),
1510 [139] = PINGROUP(139, WEST, qua_mi2s, gcc_gp4, _, _, _, _, _, _, _),
1511 [140] = PINGROUP(140, WEST, qua_mi2s, gcc_gp5, _, atest_char, _, _, _, _, _),
1512 [141] = PINGROUP(141, WEST, qua_mi2s, qdss_cti, _, _, _, _, _, _, _),
1513 [142] = PINGROUP(142, WEST, qua_mi2s, _, _, qdss_cti, atest_char, _, _, _, _),
1514 [143] = PINGROUP(143, WEST, pri_mi2s, _, _, _, _, _, _, _, _),
1515 [144] = PINGROUP(144, WEST, pri_mi2s, qup3, _, _, _, _, _, _, _),
1516 [145] = PINGROUP(145, WEST, pri_mi2s_ws, qup3, ddr_bist, _, _, _, _, _, _),
1517 [146] = PINGROUP(146, WEST, pri_mi2s, qup3, ddr_bist, _, _, _, _, _, _),
1518 [147] = PINGROUP(147, WEST, pri_mi2s, qup3, _, _, _, _, _, _, _),
1519 [148] = PINGROUP(148, WEST, spkr_i2s, audio_ref, _, phase_flag, _, _, _, _, _),
1520 [149] = PINGROUP(149, WEST, lpass_slimbus, spkr_i2s, _, phase_flag, _, _, _, _, _),
1521 [150] = PINGROUP(150, WEST, lpass_slimbus, spkr_i2s, _, phase_flag, tsense_pwm1, tsense_pwm2, _, _, _),
1522 [151] = PINGROUP(151, WEST, lpass_slimbus, spkr_i2s, _, phase_flag, _, _, _, _, _),
1523 [152] = PINGROUP(152, WEST, lpass_slimbus, spkr_i2s, _, phase_flag, _, _, _, _, _),
1524 [153] = PINGROUP(153, WEST, btfm_slimbus, _, _, _, _, _, _, _, _),
1525 [154] = PINGROUP(154, WEST, btfm_slimbus, _, _, _, _, _, _, _, _),
1526 [155] = PINGROUP(155, WEST, hs1_mi2s, _, phase_flag, _, _, _, _, _, _),
1527 [156] = PINGROUP(156, WEST, hs1_mi2s, _, phase_flag, _, _, _, _, _, _),
1528 [157] = PINGROUP(157, WEST, hs1_mi2s, _, phase_flag, _, _, _, _, _, _),
1529 [158] = PINGROUP(158, WEST, hs1_mi2s, _, phase_flag, _, _, _, _, _, _),
1530 [159] = PINGROUP(159, WEST, hs1_mi2s, cri_trng, _, phase_flag, _, _, _, _, _),
1531 [160] = PINGROUP(160, WEST, hs2_mi2s, cri_trng, _, phase_flag, _, _, _, _, _),
1532 [161] = PINGROUP(161, WEST, hs2_mi2s, qspi1, cri_trng, _, phase_flag, _, _, _, _),
1533 [162] = PINGROUP(162, WEST, hs2_mi2s, qspi1, sp_cmu, _, phase_flag, _, _, _, _),
1534 [163] = PINGROUP(163, WEST, hs2_mi2s, qspi1_clk, prng_rosc, _, phase_flag, _, _, _, _),
1535 [164] = PINGROUP(164, WEST, hs2_mi2s, qspi1_cs, _, phase_flag, _, _, _, _, _),
1536 [165] = PINGROUP(165, WEST, hs3_mi2s, _, phase_flag, _, _, _, _, _, _),
1537 [166] = PINGROUP(166, WEST, hs3_mi2s, _, phase_flag, _, _, _, _, _, _),
1538 [167] = PINGROUP(167, WEST, hs3_mi2s, _, phase_flag, _, _, _, _, _, _),
1539 [168] = PINGROUP(168, WEST, hs3_mi2s, _, phase_flag, _, _, _, _, _, _),
1540 [169] = PINGROUP(169, SOUTH, _, _, _, _, _, _, _, _, _),
1541 [170] = PINGROUP(170, SOUTH, _, _, _, _, _, _, _, _, _),
1542 [171] = PINGROUP(171, SOUTH, _, _, _, _, _, _, _, _, _),
1543 [172] = PINGROUP(172, SOUTH, _, _, _, _, _, _, _, _, _),
1544 [173] = PINGROUP(173, SOUTH, _, _, _, _, _, _, _, _, _),
1545 [174] = PINGROUP(174, SOUTH, _, _, _, _, _, _, _, _, _),
1546 [175] = PINGROUP(175, SOUTH, pci_e2, _, _, _, _, _, _, _, _),
1547 [176] = PINGROUP(176, SOUTH, pci_e2, cci_async, _, _, _, _, _, _, _),
1548 [177] = PINGROUP_OFFSET(177, SOUTH, 0x1e000, _, _, _, _, _, _, _, _, _),
1549 [178] = PINGROUP_OFFSET(178, SOUTH, 0x1e000, pci_e3, cci_timer4, _, _, _, _, _, _, _),
1550 [179] = PINGROUP_OFFSET(179, SOUTH, 0x1e000, pci_e3, cam_mclk, _, _, _, _, _, _, _),
1551 [180] = PINGROUP_OFFSET(180, SOUTH, 0x1e000, cam_mclk, _, _, _, _, _, _, _, _),
1552 [181] = PINGROUP_OFFSET(181, SOUTH, 0x1e000, qup19, cam_mclk, _, _, _, _, _, _, _),
1553 [182] = PINGROUP_OFFSET(182, SOUTH, 0x1e000, qup19, cci_timer5, gcc_gp4, _, _, _, _, _, _),
1554 [183] = PINGROUP_OFFSET(183, SOUTH, 0x1e000, qup19, cci_timer6, gcc_gp5, _, _, _, _, _, _),
1555 [184] = PINGROUP_OFFSET(184, SOUTH, 0x1e000, qup19, cci_timer7, _, _, _, _, _, _, _),
1556 [185] = PINGROUP_OFFSET(185, SOUTH, 0x1e000, cci_timer8, cci_async, _, _, _, _, _, _, _),
1557 [186] = PINGROUP_OFFSET(186, SOUTH, 0x1e000, cci_timer9, cci_async, _, _, _, _, _, _, _),
1558 [187] = PINGROUP_OFFSET(187, SOUTH, 0x1e000, _, _, _, _, _, _, _, _, _),
1559 [188] = PINGROUP_OFFSET(188, SOUTH, 0x1e000, _, _, _, _, _, _, _, _, _),
1560 [189] = PINGROUP_OFFSET(189, SOUTH, 0x1e000, dp_hot, _, _, _, _, _, _, _, _),
1561 [190] = UFS_RESET(ufs_reset),
1562 [191] = SDC_QDSD_PINGROUP(sdc2_clk, 0x4b2000, 14, 6),
1563 [192] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x4b2000, 11, 3),
1564 [193] = SDC_QDSD_PINGROUP(sdc2_data, 0x4b2000, 9, 0),
1565 };
1566
1567 static const int sc8180x_acpi_reserved_gpios[] = {
1568 0, 1, 2, 3,
1569 47, 48, 49, 50,
1570 126, 127, 128, 129,
1571 -1 /* terminator */
1572 };
1573
1574 static const struct msm_gpio_wakeirq_map sc8180x_pdc_map[] = {
1575 { 3, 31 }, { 5, 32 }, { 8, 33 }, { 9, 34 }, { 10, 100 }, { 12, 104 },
1576 { 24, 37 }, { 26, 38 }, { 27, 41 }, { 28, 42 }, { 30, 39 }, { 36, 43 },
1577 { 37, 44 }, { 38, 45 }, { 39, 118 }, { 39, 125 }, { 41, 47 },
1578 { 42, 48 }, { 46, 50 }, { 47, 49 }, { 48, 51 }, { 49, 53 }, { 50, 52 },
1579 { 51, 116 }, { 51, 123 }, { 53, 54 }, { 54, 55 }, { 55, 56 },
1580 { 56, 57 }, { 58, 58 }, { 60, 60 }, { 68, 62 }, { 70, 63 }, { 76, 86 },
1581 { 77, 36 }, { 81, 64 }, { 83, 65 }, { 86, 67 }, { 87, 84 }, { 88, 117 },
1582 { 88, 124 }, { 90, 69 }, { 91, 70 }, { 93, 75 }, { 95, 72 }, { 97, 74 },
1583 { 101, 76 }, { 103, 77 }, { 104, 78 }, { 114, 82 }, { 117, 85 },
1584 { 118, 101 }, { 119, 87 }, { 120, 88 }, { 121, 89 }, { 122, 90 },
1585 { 123, 91 }, { 124, 92 }, { 125, 93 }, { 129, 94 }, { 132, 105 },
1586 { 133, 35 }, { 134, 36 }, { 136, 97 }, { 142, 103 }, { 144, 115 },
1587 { 144, 122 }, { 147, 106 }, { 150, 107 }, { 152, 108 }, { 153, 109 },
1588 { 177, 111 }, { 180, 112 }, { 184, 113 }, { 189, 114 }
1589 };
1590
1591 static struct msm_pinctrl_soc_data sc8180x_pinctrl = {
1592 .tiles = sc8180x_tiles,
1593 .ntiles = ARRAY_SIZE(sc8180x_tiles),
1594 .pins = sc8180x_pins,
1595 .npins = ARRAY_SIZE(sc8180x_pins),
1596 .functions = sc8180x_functions,
1597 .nfunctions = ARRAY_SIZE(sc8180x_functions),
1598 .groups = sc8180x_groups,
1599 .ngroups = ARRAY_SIZE(sc8180x_groups),
1600 .ngpios = 191,
1601 .wakeirq_map = sc8180x_pdc_map,
1602 .nwakeirq_map = ARRAY_SIZE(sc8180x_pdc_map),
1603 };
1604
1605 static const struct msm_pinctrl_soc_data sc8180x_acpi_pinctrl = {
1606 .tiles = sc8180x_tiles,
1607 .ntiles = ARRAY_SIZE(sc8180x_tiles),
1608 .pins = sc8180x_pins,
1609 .npins = ARRAY_SIZE(sc8180x_pins),
1610 .groups = sc8180x_groups,
1611 .ngroups = ARRAY_SIZE(sc8180x_groups),
1612 .reserved_gpios = sc8180x_acpi_reserved_gpios,
1613 .ngpios = 190,
1614 };
1615
1616 /*
1617 * ACPI DSDT has one single memory resource for TLMM, which violates the
1618 * hardware layout of 3 separate tiles. Let's split the memory resource into
1619 * 3 named ones, so that msm_pinctrl_probe() can map memory for ACPI in the
1620 * same way as for DT probe.
1621 */
1622 static int sc8180x_pinctrl_add_tile_resources(struct platform_device *pdev)
1623 {
1624 int nres_num = pdev->num_resources + ARRAY_SIZE(sc8180x_tiles) - 1;
1625 struct resource *mres = NULL;
1626 struct resource *nres, *res;
1627 int i, ret;
1628
1629 /*
1630 * DT already has tiles defined properly, so nothing needs to be done
1631 * for DT probe.
1632 */
1633 if (pdev->dev.of_node)
1634 return 0;
1635
1636 /* Allocate for new resources */
1637 nres = devm_kzalloc(&pdev->dev, sizeof(*nres) * nres_num, GFP_KERNEL);
1638 if (!nres)
1639 return -ENOMEM;
1640
1641 res = nres;
1642
1643 for (i = 0; i < pdev->num_resources; i++) {
1644 struct resource *r = &pdev->resource[i];
1645
1646 /* Save memory resource and copy others */
1647 if (resource_type(r) == IORESOURCE_MEM)
1648 mres = r;
1649 else
1650 *res++ = *r;
1651 }
1652
1653 if (!mres)
1654 return -EINVAL;
1655
1656 /* Append tile memory resources */
1657 for (i = 0; i < ARRAY_SIZE(sc8180x_tiles); i++, res++) {
1658 const struct tile_info *info = &sc8180x_tile_info[i];
1659
1660 res->start = mres->start + info->offset;
1661 res->end = mres->start + info->offset + info->size - 1;
1662 res->flags = mres->flags;
1663 res->name = sc8180x_tiles[i];
1664
1665 /* Add new MEM to resource tree */
1666 insert_resource(mres->parent, res);
1667 }
1668
1669 /* Remove old MEM from resource tree */
1670 remove_resource(mres);
1671
1672 /* Free old resources and install new ones */
1673 ret = platform_device_add_resources(pdev, nres, nres_num);
1674 if (ret) {
1675 dev_err(&pdev->dev, "failed to add new resources: %d\n", ret);
1676 return ret;
1677 }
1678
1679 return 0;
1680 }
1681
1682 static int sc8180x_pinctrl_probe(struct platform_device *pdev)
1683 {
1684 const struct msm_pinctrl_soc_data *soc_data;
1685 int ret;
1686
1687 soc_data = device_get_match_data(&pdev->dev);
1688 if (!soc_data)
1689 return -EINVAL;
1690
1691 ret = sc8180x_pinctrl_add_tile_resources(pdev);
1692 if (ret)
1693 return ret;
1694
1695 return msm_pinctrl_probe(pdev, soc_data);
1696 }
1697
1698 static const struct acpi_device_id sc8180x_pinctrl_acpi_match[] = {
1699 {
1700 .id = "QCOM040D",
1701 .driver_data = (kernel_ulong_t) &sc8180x_acpi_pinctrl,
1702 },
1703 { }
1704 };
1705 MODULE_DEVICE_TABLE(acpi, sc8180x_pinctrl_acpi_match);
1706
1707 static const struct of_device_id sc8180x_pinctrl_of_match[] = {
1708 {
1709 .compatible = "qcom,sc8180x-tlmm",
1710 .data = &sc8180x_pinctrl,
1711 },
1712 { },
1713 };
1714 MODULE_DEVICE_TABLE(of, sc8180x_pinctrl_of_match);
1715
1716 static struct platform_driver sc8180x_pinctrl_driver = {
1717 .driver = {
1718 .name = "sc8180x-pinctrl",
1719 .of_match_table = sc8180x_pinctrl_of_match,
1720 .acpi_match_table = sc8180x_pinctrl_acpi_match,
1721 },
1722 .probe = sc8180x_pinctrl_probe,
1723 .remove = msm_pinctrl_remove,
1724 };
1725
1726 static int __init sc8180x_pinctrl_init(void)
1727 {
1728 return platform_driver_register(&sc8180x_pinctrl_driver);
1729 }
1730 arch_initcall(sc8180x_pinctrl_init);
1731
1732 static void __exit sc8180x_pinctrl_exit(void)
1733 {
1734 platform_driver_unregister(&sc8180x_pinctrl_driver);
1735 }
1736 module_exit(sc8180x_pinctrl_exit);
1737
1738 MODULE_DESCRIPTION("QTI SC8180x pinctrl driver");
1739 MODULE_LICENSE("GPL v2");
Kernel DRM miscellaneous fixes and cross-tree changes