| blob | e7c88a5d983f43437cf9ce6645bdb87575d14135 |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A77965 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 * Copyright (C) 2016-2019 Renesas Electronics Corp.
7 *
8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
9 *
10 * R-Car Gen3 processor support - PFC hardware block.
11 *
12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */
15 #include <linux/errno.h>
16 #include <linux/kernel.h>
20 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
22 #define CPU_ALL_GP(fn, sfx) \
23 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
27 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
32 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
36 #define CPU_ALL_NOGP(fn) \
80 /*
81 * F_() : just information
82 * FM() : macro for FN_xxx / xxx_MARK
83 */
85 /* GPSR0 */
86 #define GPSR0_15 F_(D15, IP7_11_8)
87 #define GPSR0_14 F_(D14, IP7_7_4)
88 #define GPSR0_13 F_(D13, IP7_3_0)
89 #define GPSR0_12 F_(D12, IP6_31_28)
90 #define GPSR0_11 F_(D11, IP6_27_24)
91 #define GPSR0_10 F_(D10, IP6_23_20)
92 #define GPSR0_9 F_(D9, IP6_19_16)
93 #define GPSR0_8 F_(D8, IP6_15_12)
94 #define GPSR0_7 F_(D7, IP6_11_8)
95 #define GPSR0_6 F_(D6, IP6_7_4)
96 #define GPSR0_5 F_(D5, IP6_3_0)
97 #define GPSR0_4 F_(D4, IP5_31_28)
98 #define GPSR0_3 F_(D3, IP5_27_24)
99 #define GPSR0_2 F_(D2, IP5_23_20)
100 #define GPSR0_1 F_(D1, IP5_19_16)
101 #define GPSR0_0 F_(D0, IP5_15_12)
103 /* GPSR1 */
104 #define GPSR1_28 FM(CLKOUT)
105 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
106 #define GPSR1_26 F_(WE1_N, IP5_7_4)
107 #define GPSR1_25 F_(WE0_N, IP5_3_0)
108 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
109 #define GPSR1_23 F_(RD_N, IP4_27_24)
110 #define GPSR1_22 F_(BS_N, IP4_23_20)
111 #define GPSR1_21 F_(CS1_N, IP4_19_16)
112 #define GPSR1_20 F_(CS0_N, IP4_15_12)
113 #define GPSR1_19 F_(A19, IP4_11_8)
114 #define GPSR1_18 F_(A18, IP4_7_4)
115 #define GPSR1_17 F_(A17, IP4_3_0)
116 #define GPSR1_16 F_(A16, IP3_31_28)
117 #define GPSR1_15 F_(A15, IP3_27_24)
118 #define GPSR1_14 F_(A14, IP3_23_20)
119 #define GPSR1_13 F_(A13, IP3_19_16)
120 #define GPSR1_12 F_(A12, IP3_15_12)
121 #define GPSR1_11 F_(A11, IP3_11_8)
122 #define GPSR1_10 F_(A10, IP3_7_4)
123 #define GPSR1_9 F_(A9, IP3_3_0)
124 #define GPSR1_8 F_(A8, IP2_31_28)
125 #define GPSR1_7 F_(A7, IP2_27_24)
126 #define GPSR1_6 F_(A6, IP2_23_20)
127 #define GPSR1_5 F_(A5, IP2_19_16)
128 #define GPSR1_4 F_(A4, IP2_15_12)
129 #define GPSR1_3 F_(A3, IP2_11_8)
130 #define GPSR1_2 F_(A2, IP2_7_4)
131 #define GPSR1_1 F_(A1, IP2_3_0)
132 #define GPSR1_0 F_(A0, IP1_31_28)
134 /* GPSR2 */
135 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
136 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
137 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
138 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
139 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
140 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
141 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
142 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
143 #define GPSR2_6 F_(PWM0, IP1_19_16)
144 #define GPSR2_5 F_(IRQ5, IP1_15_12)
145 #define GPSR2_4 F_(IRQ4, IP1_11_8)
146 #define GPSR2_3 F_(IRQ3, IP1_7_4)
147 #define GPSR2_2 F_(IRQ2, IP1_3_0)
148 #define GPSR2_1 F_(IRQ1, IP0_31_28)
149 #define GPSR2_0 F_(IRQ0, IP0_27_24)
151 /* GPSR3 */
152 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
153 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
154 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
155 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
156 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
157 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
158 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
159 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
160 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
161 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
162 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
163 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
164 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
165 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
166 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
167 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
169 /* GPSR4 */
170 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
171 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
172 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
173 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
174 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
175 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
176 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
177 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
178 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
179 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
180 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
181 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
182 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
183 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
184 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
185 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
186 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
187 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
189 /* GPSR5 */
190 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
191 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
192 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
193 #define GPSR5_22 FM(MSIOF0_RXD)
194 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
195 #define GPSR5_20 FM(MSIOF0_TXD)
196 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
197 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
198 #define GPSR5_17 FM(MSIOF0_SCK)
199 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
200 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
201 #define GPSR5_14 F_(HTX0, IP13_19_16)
202 #define GPSR5_13 F_(HRX0, IP13_15_12)
203 #define GPSR5_12 F_(HSCK0, IP13_11_8)
204 #define GPSR5_11 F_(RX2_A, IP13_7_4)
205 #define GPSR5_10 F_(TX2_A, IP13_3_0)
206 #define GPSR5_9 F_(SCK2, IP12_31_28)
207 #define GPSR5_8 F_(RTS1_N, IP12_27_24)
208 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
209 #define GPSR5_6 F_(TX1_A, IP12_19_16)
210 #define GPSR5_5 F_(RX1_A, IP12_15_12)
211 #define GPSR5_4 F_(RTS0_N, IP12_11_8)
212 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
213 #define GPSR5_2 F_(TX0, IP12_3_0)
214 #define GPSR5_1 F_(RX0, IP11_31_28)
215 #define GPSR5_0 F_(SCK0, IP11_27_24)
217 /* GPSR6 */
218 #define GPSR6_31 F_(GP6_31, IP18_7_4)
219 #define GPSR6_30 F_(GP6_30, IP18_3_0)
220 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
221 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
222 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
223 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
224 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
225 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
226 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
227 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
228 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
229 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
230 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
231 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
232 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
233 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
234 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
235 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
236 #define GPSR6_13 FM(SSI_SDATA5)
237 #define GPSR6_12 FM(SSI_WS5)
238 #define GPSR6_11 FM(SSI_SCK5)
239 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
240 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
241 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
242 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
243 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
244 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
245 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
246 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
247 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
248 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
249 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
251 /* GPSR7 */
252 #define GPSR7_3 FM(GP7_03)
253 #define GPSR7_2 FM(GP7_02)
254 #define GPSR7_1 FM(AVS2)
255 #define GPSR7_0 FM(AVS1)
258 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
259 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
288 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
319 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
355 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
376 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
385 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395 #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
403 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
404 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
405 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
406 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
407 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
408 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
409 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
410 #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
411 #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
413 #define PINMUX_GPSR \
414 \
415 GPSR6_31 \
416 GPSR6_30 \
417 GPSR6_29 \
418 GPSR1_28 GPSR6_28 \
419 GPSR1_27 GPSR6_27 \
420 GPSR1_26 GPSR6_26 \
421 GPSR1_25 GPSR5_25 GPSR6_25 \
422 GPSR1_24 GPSR5_24 GPSR6_24 \
423 GPSR1_23 GPSR5_23 GPSR6_23 \
424 GPSR1_22 GPSR5_22 GPSR6_22 \
425 GPSR1_21 GPSR5_21 GPSR6_21 \
426 GPSR1_20 GPSR5_20 GPSR6_20 \
427 GPSR1_19 GPSR5_19 GPSR6_19 \
428 GPSR1_18 GPSR5_18 GPSR6_18 \
429 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
430 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
431 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
432 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
433 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
434 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
435 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
436 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
437 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
438 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
439 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
440 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
441 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
442 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
443 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
444 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
445 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
446 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
448 #define PINMUX_IPSR \
449 \
450 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
451 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
452 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
453 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
454 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
455 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
456 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
457 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
458 \
459 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
460 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
461 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
462 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
463 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
464 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
465 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
466 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
467 \
468 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
469 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
470 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
471 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
472 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
473 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
474 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
475 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
476 \
477 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
478 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
479 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
480 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
481 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
482 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
483 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
484 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
485 \
486 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
487 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
488 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
489 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
490 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
491 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
492 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
493 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
496 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
497 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
498 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
499 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
500 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
501 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
502 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
503 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
504 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
505 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
506 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
507 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
508 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
509 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
510 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
511 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
512 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
513 #define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
516 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
517 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
518 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
519 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
520 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
521 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
522 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
523 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
524 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
525 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
526 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
527 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
528 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
529 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
530 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
531 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
532 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
533 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
534 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
535 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
536 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
537 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
540 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
541 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
542 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
543 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
544 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
545 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
546 #define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
547 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
548 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
549 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
550 #define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
551 #define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
552 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
554 #define PINMUX_MOD_SELS \
555 \
556 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
557 MOD_SEL2_30 \
558 MOD_SEL1_29_28_27 MOD_SEL2_29 \
559 MOD_SEL0_28_27 MOD_SEL2_28_27 \
560 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
561 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
562 MOD_SEL0_23 MOD_SEL1_23_22_21 \
563 MOD_SEL0_22 MOD_SEL2_22 \
564 MOD_SEL0_21 MOD_SEL2_21 \
565 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
566 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
567 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
568 MOD_SEL2_17 \
569 MOD_SEL0_16 MOD_SEL1_16 \
570 MOD_SEL1_15_14 \
571 MOD_SEL0_14_13 \
572 MOD_SEL1_13 \
573 MOD_SEL0_12 MOD_SEL1_12 \
574 MOD_SEL0_11 MOD_SEL1_11 \
575 MOD_SEL0_10 MOD_SEL1_10 \
576 MOD_SEL0_9_8 MOD_SEL1_9 \
577 MOD_SEL0_7_6 \
578 MOD_SEL1_6 \
579 MOD_SEL0_5 MOD_SEL1_5 \
580 MOD_SEL0_4_3 MOD_SEL1_4 \
581 MOD_SEL1_3 \
582 MOD_SEL1_2 \
583 MOD_SEL1_1 \
584 MOD_SEL1_0 MOD_SEL2_0
586 /*
587 * These pins are not able to be muxed but have other properties
588 * that can be set, such as drive-strength or pull-up/pull-down enable.
589 */
590 #define PINMUX_STATIC \
591 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
592 FM(QSPI0_IO2) FM(QSPI0_IO3) \
593 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
594 FM(QSPI1_IO2) FM(QSPI1_IO3) \
595 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
596 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
597 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
598 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
599 FM(PRESETOUT) \
600 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
601 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
603 #define PINMUX_PHYS \
604 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
609 PINMUX_DATA_BEGIN,
611 PINMUX_DATA_END,
613 #define F_(x, y)
614 #define FM(x) FN_##x,
615 PINMUX_FUNCTION_BEGIN,
617 PINMUX_GPSR
618 PINMUX_IPSR
619 PINMUX_MOD_SELS
620 PINMUX_FUNCTION_END,
621 #undef F_
622 #undef FM
624 #define F_(x, y)
625 #define FM(x) x##_MARK,
626 PINMUX_MARK_BEGIN,
627 PINMUX_GPSR
628 PINMUX_IPSR
629 PINMUX_MOD_SELS
630 PINMUX_STATIC
631 PINMUX_PHYS
632 PINMUX_MARK_END,
633 #undef F_
634 #undef FM
635 };
652 /* IPSR0 */
695 /* IPSR1 */
748 /* IPSR2 */
809 /* IPSR3 */
863 /* IPSR4 */
909 /* IPSR5 */
959 /* IPSR6 */
1011 /* IPSR7 */
1053 /* IPSR8 */
1102 /* IPSR9 */
1128 /* IPSR10 */
1156 /* IPSR11 */
1200 /* IPSR12 */
1261 /* IPSR13 */
1321 /* IPSR14 */
1362 /* IPSR15 */
1409 /* IPSR16 */
1462 /* IPSR17 */
1528 /* IPSR18 */
1549 /*
1550 * Static pins can not be muxed between different functions but
1551 * still need mark entries in the pinmux list. Add each static
1552 * pin to the list without an associated function. The sh-pfc
1553 * core will do the right thing and skip trying to mux the pin
1554 * while still applying configuration to it.
1555 */
1556 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1557 PINMUX_STATIC
1558 #undef FM
1559 };
1561 /*
1562 * Pins not associated with a GPIO port.
1563 */
1567 };
1572 };
1574 /* - AUDIO CLOCK ------------------------------------------------------------ */
1576 /* CLK A */
1578 };
1580 AUDIO_CLKA_A_MARK,
1581 };
1583 /* CLK A */
1585 };
1587 AUDIO_CLKA_B_MARK,
1588 };
1590 /* CLK A */
1592 };
1594 AUDIO_CLKA_C_MARK,
1595 };
1597 /* CLK B */
1599 };
1601 AUDIO_CLKB_A_MARK,
1602 };
1604 /* CLK B */
1606 };
1608 AUDIO_CLKB_B_MARK,
1609 };
1611 /* CLK C */
1613 };
1615 AUDIO_CLKC_A_MARK,
1616 };
1618 /* CLK C */
1620 };
1622 AUDIO_CLKC_B_MARK,
1623 };
1625 /* CLKOUT */
1627 };
1629 AUDIO_CLKOUT_A_MARK,
1630 };
1632 /* CLKOUT */
1634 };
1636 AUDIO_CLKOUT_B_MARK,
1637 };
1639 /* CLKOUT */
1641 };
1643 AUDIO_CLKOUT_C_MARK,
1644 };
1646 /* CLKOUT */
1648 };
1650 AUDIO_CLKOUT_D_MARK,
1651 };
1653 /* CLKOUT1 */
1655 };
1657 AUDIO_CLKOUT1_A_MARK,
1658 };
1660 /* CLKOUT1 */
1662 };
1664 AUDIO_CLKOUT1_B_MARK,
1665 };
1667 /* CLKOUT2 */
1669 };
1671 AUDIO_CLKOUT2_A_MARK,
1672 };
1674 /* CLKOUT2 */
1676 };
1678 AUDIO_CLKOUT2_B_MARK,
1679 };
1682 /* CLKOUT3 */
1684 };
1686 AUDIO_CLKOUT3_A_MARK,
1687 };
1689 /* CLKOUT3 */
1691 };
1693 AUDIO_CLKOUT3_B_MARK,
1694 };
1696 /* - EtherAVB --------------------------------------------------------------- */
1698 /* AVB_LINK */
1700 };
1702 AVB_LINK_MARK,
1703 };
1705 /* AVB_MAGIC_ */
1707 };
1709 AVB_MAGIC_MARK,
1710 };
1712 /* AVB_PHY_INT */
1714 };
1716 AVB_PHY_INT_MARK,
1717 };
1719 /* AVB_MDC, AVB_MDIO */
1721 };
1724 };
1726 /*
1727 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1728 * AVB_TD1, AVB_TD2, AVB_TD3,
1729 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1730 * AVB_RD1, AVB_RD2, AVB_RD3,
1731 * AVB_TXCREFCLK
1732 */
1737 PIN_AVB_TXCREFCLK,
1738 };
1744 AVB_TXCREFCLK_MARK,
1745 };
1747 /* AVB_AVTP_PPS */
1749 };
1751 AVB_AVTP_PPS_MARK,
1752 };
1754 /* AVB_AVTP_MATCH_A */
1756 };
1758 AVB_AVTP_MATCH_A_MARK,
1759 };
1761 /* AVB_AVTP_CAPTURE_A */
1763 };
1765 AVB_AVTP_CAPTURE_A_MARK,
1766 };
1768 /* AVB_AVTP_MATCH_B */
1770 };
1772 AVB_AVTP_MATCH_B_MARK,
1773 };
1775 /* AVB_AVTP_CAPTURE_B */
1777 };
1779 AVB_AVTP_CAPTURE_B_MARK,
1780 };
1782 /* - CAN ------------------------------------------------------------------ */
1784 /* TX, RX */
1786 };
1790 };
1793 /* TX, RX */
1795 };
1799 };
1802 /* TX, RX */
1804 };
1808 };
1810 /* - CAN Clock -------------------------------------------------------------- */
1812 /* CLK */
1814 };
1817 CAN_CLK_MARK,
1818 };
1820 /* - CAN FD --------------------------------------------------------------- */
1822 /* TX, RX */
1824 };
1828 };
1831 /* TX, RX */
1833 };
1837 };
1840 /* TX, RX */
1842 };
1846 };
1848 #ifdef CONFIG_PINCTRL_PFC_R8A77965
1849 /* - DRIF0 --------------------------------------------------------------- */
1851 /* CLK, SYNC */
1853 };
1857 };
1860 /* D0 */
1862 };
1865 RIF0_D0_A_MARK,
1866 };
1869 /* D1 */
1871 };
1874 RIF0_D1_A_MARK,
1875 };
1878 /* CLK, SYNC */
1880 };
1884 };
1887 /* D0 */
1889 };
1892 RIF0_D0_B_MARK,
1893 };
1896 /* D1 */
1898 };
1901 RIF0_D1_B_MARK,
1902 };
1905 /* CLK, SYNC */
1907 };
1911 };
1914 /* D0 */
1916 };
1919 RIF0_D0_C_MARK,
1920 };
1923 /* D1 */
1925 };
1928 RIF0_D1_C_MARK,
1929 };
1931 /* - DRIF1 --------------------------------------------------------------- */
1933 /* CLK, SYNC */
1935 };
1939 };
1942 /* D0 */
1944 };
1947 RIF1_D0_A_MARK,
1948 };
1951 /* D1 */
1953 };
1956 RIF1_D1_A_MARK,
1957 };
1960 /* CLK, SYNC */
1962 };
1966 };
1969 /* D0 */
1971 };
1974 RIF1_D0_B_MARK,
1975 };
1978 /* D1 */
1980 };
1983 RIF1_D1_B_MARK,
1984 };
1987 /* CLK, SYNC */
1989 };
1993 };
1996 /* D0 */
1998 };
2001 RIF1_D0_C_MARK,
2002 };
2005 /* D1 */
2007 };
2010 RIF1_D1_C_MARK,
2011 };
2013 /* - DRIF2 --------------------------------------------------------------- */
2015 /* CLK, SYNC */
2017 };
2021 };
2024 /* D0 */
2026 };
2029 RIF2_D0_A_MARK,
2030 };
2033 /* D1 */
2035 };
2038 RIF2_D1_A_MARK,
2039 };
2042 /* CLK, SYNC */
2044 };
2048 };
2051 /* D0 */
2053 };
2056 RIF2_D0_B_MARK,
2057 };
2060 /* D1 */
2062 };
2065 RIF2_D1_B_MARK,
2066 };
2068 /* - DRIF3 --------------------------------------------------------------- */
2070 /* CLK, SYNC */
2072 };
2076 };
2079 /* D0 */
2081 };
2084 RIF3_D0_A_MARK,
2085 };
2088 /* D1 */
2090 };
2093 RIF3_D1_A_MARK,
2094 };
2097 /* CLK, SYNC */
2099 };
2103 };
2106 /* D0 */
2108 };
2111 RIF3_D0_B_MARK,
2112 };
2115 /* D1 */
2117 };
2120 RIF3_D1_B_MARK,
2121 };
2124 /* - DU --------------------------------------------------------------------- */
2126 /* R[7:2], G[7:2], B[7:2] */
2133 };
2142 };
2145 /* R[7:0], G[7:0], B[7:0] */
2155 };
2164 };
2167 /* CLKOUT */
2169 };
2172 DU_DOTCLKOUT0_MARK
2173 };
2176 /* CLKOUT */
2178 };
2181 DU_DOTCLKOUT1_MARK
2182 };
2185 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2187 };
2190 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2191 };
2194 /* EXDISP/EXODDF/EXCDE */
2196 };
2199 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2200 };
2203 /* CDE */
2205 };
2208 DU_CDE_MARK,
2209 };
2212 /* DISP */
2214 };
2217 DU_DISP_MARK,
2218 };
2220 /* - HSCIF0 ----------------------------------------------------------------- */
2222 /* RX, TX */
2224 };
2228 };
2231 /* SCK */
2233 };
2236 HSCK0_MARK,
2237 };
2240 /* RTS, CTS */
2242 };
2246 };
2248 /* - HSCIF1 ----------------------------------------------------------------- */
2250 /* RX, TX */
2252 };
2256 };
2259 /* SCK */
2261 };
2264 HSCK1_A_MARK,
2265 };
2268 /* RTS, CTS */
2270 };
2274 };
2277 /* RX, TX */
2279 };
2283 };
2286 /* SCK */
2288 };
2291 HSCK1_B_MARK,
2292 };
2295 /* RTS, CTS */
2297 };
2301 };
2303 /* - HSCIF2 ----------------------------------------------------------------- */
2305 /* RX, TX */
2307 };
2311 };
2314 /* SCK */
2316 };
2319 HSCK2_A_MARK,
2320 };
2323 /* RTS, CTS */
2325 };
2329 };
2332 /* RX, TX */
2334 };
2338 };
2341 /* SCK */
2343 };
2346 HSCK2_B_MARK,
2347 };
2350 /* RTS, CTS */
2352 };
2356 };
2359 /* RX, TX */
2361 };
2365 };
2368 /* SCK */
2370 };
2373 HSCK2_C_MARK,
2374 };
2377 /* RTS, CTS */
2379 };
2383 };
2385 /* - HSCIF3 ----------------------------------------------------------------- */
2387 /* RX, TX */
2389 };
2393 };
2396 /* SCK */
2398 };
2401 HSCK3_MARK,
2402 };
2405 /* RTS, CTS */
2407 };
2411 };
2414 /* RX, TX */
2416 };
2420 };
2423 /* RX, TX */
2425 };
2429 };
2432 /* RX, TX */
2434 };
2438 };
2440 /* - HSCIF4 ----------------------------------------------------------------- */
2442 /* RX, TX */
2444 };
2448 };
2451 /* SCK */
2453 };
2456 HSCK4_MARK,
2457 };
2460 /* RTS, CTS */
2462 };
2466 };
2469 /* RX, TX */
2471 };
2475 };
2477 /* - I2C -------------------------------------------------------------------- */
2479 /* SCL, SDA */
2481 };
2485 };
2488 /* SDA, SCL */
2490 };
2494 };
2497 /* SDA, SCL */
2499 };
2503 };
2506 /* SDA, SCL */
2508 };
2512 };
2515 /* SDA, SCL */
2517 };
2521 };
2524 /* SCL, SDA */
2526 };
2530 };
2533 /* SCL, SDA */
2535 };
2539 };
2542 /* SDA, SCL */
2544 };
2548 };
2551 /* SDA, SCL */
2553 };
2557 };
2560 /* SDA, SCL */
2562 };
2566 };
2568 /* - INTC-EX ---------------------------------------------------------------- */
2570 /* IRQ0 */
2572 };
2574 IRQ0_MARK,
2575 };
2577 /* IRQ1 */
2579 };
2581 IRQ1_MARK,
2582 };
2584 /* IRQ2 */
2586 };
2588 IRQ2_MARK,
2589 };
2591 /* IRQ3 */
2593 };
2595 IRQ3_MARK,
2596 };
2598 /* IRQ4 */
2600 };
2602 IRQ4_MARK,
2603 };
2605 /* IRQ5 */
2607 };
2609 IRQ5_MARK,
2610 };
2612 #ifdef CONFIG_PINCTRL_PFC_R8A77965
2613 /* - MLB+ ------------------------------------------------------------------- */
2616 };
2619 };
2622 /* - MSIOF0 ----------------------------------------------------------------- */
2624 /* SCK */
2626 };
2628 MSIOF0_SCK_MARK,
2629 };
2631 /* SYNC */
2633 };
2635 MSIOF0_SYNC_MARK,
2636 };
2638 /* SS1 */
2640 };
2642 MSIOF0_SS1_MARK,
2643 };
2645 /* SS2 */
2647 };
2649 MSIOF0_SS2_MARK,
2650 };
2652 /* TXD */
2654 };
2656 MSIOF0_TXD_MARK,
2657 };
2659 /* RXD */
2661 };
2663 MSIOF0_RXD_MARK,
2664 };
2665 /* - MSIOF1 ----------------------------------------------------------------- */
2667 /* SCK */
2669 };
2671 MSIOF1_SCK_A_MARK,
2672 };
2674 /* SYNC */
2676 };
2678 MSIOF1_SYNC_A_MARK,
2679 };
2681 /* SS1 */
2683 };
2685 MSIOF1_SS1_A_MARK,
2686 };
2688 /* SS2 */
2690 };
2692 MSIOF1_SS2_A_MARK,
2693 };
2695 /* TXD */
2697 };
2699 MSIOF1_TXD_A_MARK,
2700 };
2702 /* RXD */
2704 };
2706 MSIOF1_RXD_A_MARK,
2707 };
2709 /* SCK */
2711 };
2713 MSIOF1_SCK_B_MARK,
2714 };
2716 /* SYNC */
2718 };
2720 MSIOF1_SYNC_B_MARK,
2721 };
2723 /* SS1 */
2725 };
2727 MSIOF1_SS1_B_MARK,
2728 };
2730 /* SS2 */
2732 };
2734 MSIOF1_SS2_B_MARK,
2735 };
2737 /* TXD */
2739 };
2741 MSIOF1_TXD_B_MARK,
2742 };
2744 /* RXD */
2746 };
2748 MSIOF1_RXD_B_MARK,
2749 };
2751 /* SCK */
2753 };
2755 MSIOF1_SCK_C_MARK,
2756 };
2758 /* SYNC */
2760 };
2762 MSIOF1_SYNC_C_MARK,
2763 };
2765 /* SS1 */
2767 };
2769 MSIOF1_SS1_C_MARK,
2770 };
2772 /* SS2 */
2774 };
2776 MSIOF1_SS2_C_MARK,
2777 };
2779 /* TXD */
2781 };
2783 MSIOF1_TXD_C_MARK,
2784 };
2786 /* RXD */
2788 };
2790 MSIOF1_RXD_C_MARK,
2791 };
2793 /* SCK */
2795 };
2797 MSIOF1_SCK_D_MARK,
2798 };
2800 /* SYNC */
2802 };
2804 MSIOF1_SYNC_D_MARK,
2805 };
2807 /* SS1 */
2809 };
2811 MSIOF1_SS1_D_MARK,
2812 };
2814 /* SS2 */
2816 };
2818 MSIOF1_SS2_D_MARK,
2819 };
2821 /* TXD */
2823 };
2825 MSIOF1_TXD_D_MARK,
2826 };
2828 /* RXD */
2830 };
2832 MSIOF1_RXD_D_MARK,
2833 };
2835 /* SCK */
2837 };
2839 MSIOF1_SCK_E_MARK,
2840 };
2842 /* SYNC */
2844 };
2846 MSIOF1_SYNC_E_MARK,
2847 };
2849 /* SS1 */
2851 };
2853 MSIOF1_SS1_E_MARK,
2854 };
2856 /* SS2 */
2858 };
2860 MSIOF1_SS2_E_MARK,
2861 };
2863 /* TXD */
2865 };
2867 MSIOF1_TXD_E_MARK,
2868 };
2870 /* RXD */
2872 };
2874 MSIOF1_RXD_E_MARK,
2875 };
2877 /* SCK */
2879 };
2881 MSIOF1_SCK_F_MARK,
2882 };
2884 /* SYNC */
2886 };
2888 MSIOF1_SYNC_F_MARK,
2889 };
2891 /* SS1 */
2893 };
2895 MSIOF1_SS1_F_MARK,
2896 };
2898 /* SS2 */
2900 };
2902 MSIOF1_SS2_F_MARK,
2903 };
2905 /* TXD */
2907 };
2909 MSIOF1_TXD_F_MARK,
2910 };
2912 /* RXD */
2914 };
2916 MSIOF1_RXD_F_MARK,
2917 };
2919 /* SCK */
2921 };
2923 MSIOF1_SCK_G_MARK,
2924 };
2926 /* SYNC */
2928 };
2930 MSIOF1_SYNC_G_MARK,
2931 };
2933 /* SS1 */
2935 };
2937 MSIOF1_SS1_G_MARK,
2938 };
2940 /* SS2 */
2942 };
2944 MSIOF1_SS2_G_MARK,
2945 };
2947 /* TXD */
2949 };
2951 MSIOF1_TXD_G_MARK,
2952 };
2954 /* RXD */
2956 };
2958 MSIOF1_RXD_G_MARK,
2959 };
2960 /* - MSIOF2 ----------------------------------------------------------------- */
2962 /* SCK */
2964 };
2966 MSIOF2_SCK_A_MARK,
2967 };
2969 /* SYNC */
2971 };
2973 MSIOF2_SYNC_A_MARK,
2974 };
2976 /* SS1 */
2978 };
2980 MSIOF2_SS1_A_MARK,
2981 };
2983 /* SS2 */
2985 };
2987 MSIOF2_SS2_A_MARK,
2988 };
2990 /* TXD */
2992 };
2994 MSIOF2_TXD_A_MARK,
2995 };
2997 /* RXD */
2999 };
3001 MSIOF2_RXD_A_MARK,
3002 };
3004 /* SCK */
3006 };
3008 MSIOF2_SCK_B_MARK,
3009 };
3011 /* SYNC */
3013 };
3015 MSIOF2_SYNC_B_MARK,
3016 };
3018 /* SS1 */
3020 };
3022 MSIOF2_SS1_B_MARK,
3023 };
3025 /* SS2 */
3027 };
3029 MSIOF2_SS2_B_MARK,
3030 };
3032 /* TXD */
3034 };
3036 MSIOF2_TXD_B_MARK,
3037 };
3039 /* RXD */
3041 };
3043 MSIOF2_RXD_B_MARK,
3044 };
3046 /* SCK */
3048 };
3050 MSIOF2_SCK_C_MARK,
3051 };
3053 /* SYNC */
3055 };
3057 MSIOF2_SYNC_C_MARK,
3058 };
3060 /* SS1 */
3062 };
3064 MSIOF2_SS1_C_MARK,
3065 };
3067 /* SS2 */
3069 };
3071 MSIOF2_SS2_C_MARK,
3072 };
3074 /* TXD */
3076 };
3078 MSIOF2_TXD_C_MARK,
3079 };
3081 /* RXD */
3083 };
3085 MSIOF2_RXD_C_MARK,
3086 };
3088 /* SCK */
3090 };
3092 MSIOF2_SCK_D_MARK,
3093 };
3095 /* SYNC */
3097 };
3099 MSIOF2_SYNC_D_MARK,
3100 };
3102 /* SS1 */
3104 };
3106 MSIOF2_SS1_D_MARK,
3107 };
3109 /* SS2 */
3111 };
3113 MSIOF2_SS2_D_MARK,
3114 };
3116 /* TXD */
3118 };
3120 MSIOF2_TXD_D_MARK,
3121 };
3123 /* RXD */
3125 };
3127 MSIOF2_RXD_D_MARK,
3128 };
3129 /* - MSIOF3 ----------------------------------------------------------------- */
3131 /* SCK */
3133 };
3135 MSIOF3_SCK_A_MARK,
3136 };
3138 /* SYNC */
3140 };
3142 MSIOF3_SYNC_A_MARK,
3143 };
3145 /* SS1 */
3147 };
3149 MSIOF3_SS1_A_MARK,
3150 };
3152 /* SS2 */
3154 };
3156 MSIOF3_SS2_A_MARK,
3157 };
3159 /* TXD */
3161 };
3163 MSIOF3_TXD_A_MARK,
3164 };
3166 /* RXD */
3168 };
3170 MSIOF3_RXD_A_MARK,
3171 };
3173 /* SCK */
3175 };
3177 MSIOF3_SCK_B_MARK,
3178 };
3180 /* SYNC */
3182 };
3184 MSIOF3_SYNC_B_MARK,
3185 };
3187 /* SS1 */
3189 };
3191 MSIOF3_SS1_B_MARK,
3192 };
3194 /* SS2 */
3196 };
3198 MSIOF3_SS2_B_MARK,
3199 };
3201 /* TXD */
3203 };
3205 MSIOF3_TXD_B_MARK,
3206 };
3208 /* RXD */
3210 };
3212 MSIOF3_RXD_B_MARK,
3213 };
3215 /* SCK */
3217 };
3219 MSIOF3_SCK_C_MARK,
3220 };
3222 /* SYNC */
3224 };
3226 MSIOF3_SYNC_C_MARK,
3227 };
3229 /* TXD */
3231 };
3233 MSIOF3_TXD_C_MARK,
3234 };
3236 /* RXD */
3238 };
3240 MSIOF3_RXD_C_MARK,
3241 };
3243 /* SCK */
3245 };
3247 MSIOF3_SCK_D_MARK,
3248 };
3250 /* SYNC */
3252 };
3254 MSIOF3_SYNC_D_MARK,
3255 };
3257 /* SS1 */
3259 };
3261 MSIOF3_SS1_D_MARK,
3262 };
3264 /* TXD */
3266 };
3268 MSIOF3_TXD_D_MARK,
3269 };
3271 /* RXD */
3273 };
3275 MSIOF3_RXD_D_MARK,
3276 };
3278 /* SCK */
3280 };
3282 MSIOF3_SCK_E_MARK,
3283 };
3285 /* SYNC */
3287 };
3289 MSIOF3_SYNC_E_MARK,
3290 };
3292 /* SS1 */
3294 };
3296 MSIOF3_SS1_E_MARK,
3297 };
3299 /* SS2 */
3301 };
3303 MSIOF3_SS2_E_MARK,
3304 };
3306 /* TXD */
3308 };
3310 MSIOF3_TXD_E_MARK,
3311 };
3313 /* RXD */
3315 };
3317 MSIOF3_RXD_E_MARK,
3318 };
3320 /* - PWM0 --------------------------------------------------------------------*/
3322 /* PWM */
3324 };
3326 PWM0_MARK,
3327 };
3328 /* - PWM1 --------------------------------------------------------------------*/
3330 /* PWM */
3332 };
3334 PWM1_A_MARK,
3335 };
3337 /* PWM */
3339 };
3341 PWM1_B_MARK,
3342 };
3343 /* - PWM2 --------------------------------------------------------------------*/
3345 /* PWM */
3347 };
3349 PWM2_A_MARK,
3350 };
3352 /* PWM */
3354 };
3356 PWM2_B_MARK,
3357 };
3358 /* - PWM3 --------------------------------------------------------------------*/
3360 /* PWM */
3362 };
3364 PWM3_A_MARK,
3365 };
3367 /* PWM */
3369 };
3371 PWM3_B_MARK,
3372 };
3373 /* - PWM4 --------------------------------------------------------------------*/
3375 /* PWM */
3377 };
3379 PWM4_A_MARK,
3380 };
3382 /* PWM */
3384 };
3386 PWM4_B_MARK,
3387 };
3388 /* - PWM5 --------------------------------------------------------------------*/
3390 /* PWM */
3392 };
3394 PWM5_A_MARK,
3395 };
3397 /* PWM */
3399 };
3401 PWM5_B_MARK,
3402 };
3403 /* - PWM6 --------------------------------------------------------------------*/
3405 /* PWM */
3407 };
3409 PWM6_A_MARK,
3410 };
3412 /* PWM */
3414 };
3416 PWM6_B_MARK,
3417 };
3419 /* - QSPI0 ------------------------------------------------------------------ */
3421 /* QSPI0_SPCLK, QSPI0_SSL */
3423 };
3426 };
3428 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3430 /* QSPI0_IO2, QSPI0_IO3 */
3432 };
3436 };
3437 /* - QSPI1 ------------------------------------------------------------------ */
3439 /* QSPI1_SPCLK, QSPI1_SSL */
3441 };
3444 };
3446 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3448 /* QSPI1_IO2, QSPI1_IO3 */
3450 };
3454 };
3456 /* - SATA --------------------------------------------------------------------*/
3458 /* DEVSLP */
3460 };
3463 SATA_DEVSLP_A_MARK,
3464 };
3467 /* DEVSLP */
3469 };
3472 SATA_DEVSLP_B_MARK,
3473 };
3475 /* - SCIF0 ------------------------------------------------------------------ */
3477 /* RX, TX */
3479 };
3482 };
3484 /* SCK */
3486 };
3488 SCK0_MARK,
3489 };
3491 /* RTS, CTS */
3493 };
3496 };
3497 /* - SCIF1 ------------------------------------------------------------------ */
3499 /* RX, TX */
3501 };
3504 };
3506 /* SCK */
3508 };
3510 SCK1_MARK,
3511 };
3513 /* RTS, CTS */
3515 };
3518 };
3520 /* RX, TX */
3522 };
3525 };
3526 /* - SCIF2 ------------------------------------------------------------------ */
3528 /* RX, TX */
3530 };
3533 };
3535 /* SCK */
3537 };
3539 SCK2_MARK,
3540 };
3542 /* RX, TX */
3544 };
3547 };
3548 /* - SCIF3 ------------------------------------------------------------------ */
3550 /* RX, TX */
3552 };
3555 };
3557 /* SCK */
3559 };
3561 SCK3_MARK,
3562 };
3564 /* RTS, CTS */
3566 };
3569 };
3571 /* RX, TX */
3573 };
3576 };
3577 /* - SCIF4 ------------------------------------------------------------------ */
3579 /* RX, TX */
3581 };
3584 };
3586 /* SCK */
3588 };
3590 SCK4_A_MARK,
3591 };
3593 /* RTS, CTS */
3595 };
3598 };
3600 /* RX, TX */
3602 };
3605 };
3607 /* SCK */
3609 };
3611 SCK4_B_MARK,
3612 };
3614 /* RTS, CTS */
3616 };
3619 };
3621 /* RX, TX */
3623 };
3626 };
3628 /* SCK */
3630 };
3632 SCK4_C_MARK,
3633 };
3635 /* RTS, CTS */
3637 };
3640 };
3641 /* - SCIF5 ------------------------------------------------------------------ */
3643 /* RX, TX */
3645 };
3648 };
3650 /* SCK */
3652 };
3654 SCK5_A_MARK,
3655 };
3657 /* RX, TX */
3659 };
3662 };
3664 /* SCK */
3666 };
3668 SCK5_B_MARK,
3669 };
3670 /* - SCIF Clock ------------------------------------------------------------- */
3672 /* SCIF_CLK */
3674 };
3676 SCIF_CLK_A_MARK,
3677 };
3679 /* SCIF_CLK */
3681 };
3683 SCIF_CLK_B_MARK,
3684 };
3686 /* - SDHI0 ------------------------------------------------------------------ */
3688 /* D[0:3] */
3691 };
3696 };
3699 /* CLK, CMD */
3701 };
3705 };
3708 /* CD */
3710 };
3713 SD0_CD_MARK,
3714 };
3717 /* WP */
3719 };
3722 SD0_WP_MARK,
3723 };
3725 /* - SDHI1 ------------------------------------------------------------------ */
3727 /* D[0:3] */
3730 };
3735 };
3738 /* CLK, CMD */
3740 };
3744 };
3747 /* CD */
3749 };
3752 SD1_CD_MARK,
3753 };
3756 /* WP */
3758 };
3761 SD1_WP_MARK,
3762 };
3764 /* - SDHI2 ------------------------------------------------------------------ */
3766 /* D[0:7] */
3771 };
3778 };
3781 /* CLK, CMD */
3783 };
3787 };
3790 /* CD */
3792 };
3795 SD2_CD_A_MARK,
3796 };
3799 /* CD */
3801 };
3804 SD2_CD_B_MARK,
3805 };
3808 /* WP */
3810 };
3813 SD2_WP_A_MARK,
3814 };
3817 /* WP */
3819 };
3822 SD2_WP_B_MARK,
3823 };
3826 /* DS */
3828 };
3831 SD2_DS_MARK,
3832 };
3834 /* - SDHI3 ------------------------------------------------------------------ */
3836 /* D[0:7] */
3841 };
3848 };
3851 /* CLK, CMD */
3853 };
3857 };
3860 /* CD */
3862 };
3865 SD3_CD_MARK,
3866 };
3869 /* WP */
3871 };
3874 SD3_WP_MARK,
3875 };
3878 /* DS */
3880 };
3883 SD3_DS_MARK,
3884 };
3886 /* - SSI -------------------------------------------------------------------- */
3888 /* SDATA */
3890 };
3892 SSI_SDATA0_MARK,
3893 };
3895 /* SCK, WS */
3897 };
3900 };
3902 /* SDATA */
3904 };
3906 SSI_SDATA1_A_MARK,
3907 };
3909 /* SDATA */
3911 };
3913 SSI_SDATA1_B_MARK,
3914 };
3916 /* SCK, WS */
3918 };
3921 };
3923 /* SCK, WS */
3925 };
3928 };
3930 /* SDATA */
3932 };
3934 SSI_SDATA2_A_MARK,
3935 };
3937 /* SDATA */
3939 };
3941 SSI_SDATA2_B_MARK,
3942 };
3944 /* SCK, WS */
3946 };
3949 };
3951 /* SCK, WS */
3953 };
3956 };
3958 /* SDATA */
3960 };
3962 SSI_SDATA3_MARK,
3963 };
3965 /* SCK, WS */
3967 };
3970 };
3972 /* SDATA */
3974 };
3976 SSI_SDATA4_MARK,
3977 };
3979 /* SCK, WS */
3981 };
3984 };
3986 /* SDATA */
3988 };
3990 SSI_SDATA5_MARK,
3991 };
3993 /* SCK, WS */
3995 };
3998 };
4000 /* SDATA */
4002 };
4004 SSI_SDATA6_MARK,
4005 };
4007 /* SCK, WS */
4009 };
4012 };
4014 /* SDATA */
4016 };
4018 SSI_SDATA7_MARK,
4019 };
4021 /* SCK, WS */
4023 };
4026 };
4028 /* SDATA */
4030 };
4032 SSI_SDATA8_MARK,
4033 };
4035 /* SDATA */
4037 };
4039 SSI_SDATA9_A_MARK,
4040 };
4042 /* SDATA */
4044 };
4046 SSI_SDATA9_B_MARK,
4047 };
4049 /* SCK, WS */
4051 };
4054 };
4056 /* SCK, WS */
4058 };
4061 };
4063 /* - TMU -------------------------------------------------------------------- */
4065 /* TCLK */
4067 };
4070 TCLK1_A_MARK,
4071 };
4074 /* TCLK */
4076 };
4079 TCLK1_B_MARK,
4080 };
4083 /* TCLK */
4085 };
4088 TCLK2_A_MARK,
4089 };
4092 /* TCLK */
4094 };
4097 TCLK2_B_MARK,
4098 };
4100 /* - TPU ------------------------------------------------------------------- */
4102 /* TPU0TO0 */
4104 };
4106 TPU0TO0_MARK,
4107 };
4109 /* TPU0TO1 */
4111 };
4113 TPU0TO1_MARK,
4114 };
4116 /* TPU0TO2 */
4118 };
4120 TPU0TO2_MARK,
4121 };
4123 /* TPU0TO3 */
4125 };
4127 TPU0TO3_MARK,
4128 };
4130 /* - USB0 ------------------------------------------------------------------- */
4132 /* PWEN, OVC */
4134 };
4138 };
4140 /* - USB1 ------------------------------------------------------------------- */
4142 /* PWEN, OVC */
4144 };
4148 };
4150 /* - USB30 ------------------------------------------------------------------ */
4152 /* PWEN, OVC */
4154 };
4158 };
4160 /* - VIN4 ------------------------------------------------------------------- */
4171 };
4183 };
4198 };
4213 };
4225 };
4237 };
4252 };
4267 };
4270 /* VSYNC_N, HSYNC_N */
4272 };
4276 };
4280 };
4283 VI4_FIELD_MARK,
4284 };
4288 };
4291 VI4_CLKENB_MARK,
4292 };
4296 };
4299 VI4_CLK_MARK,
4300 };
4302 /* - VIN5 ------------------------------------------------------------------- */
4312 };
4323 };
4326 /* VSYNC_N, HSYNC_N */
4328 };
4332 };
4336 };
4339 VI5_FIELD_MARK,
4340 };
4344 };
4347 VI5_CLKENB_MARK,
4348 };
4352 };
4355 VI5_CLK_MARK,
4356 };
4360 #ifdef CONFIG_PINCTRL_PFC_R8A77965
4362 #endif
4691 },
4692 #ifdef CONFIG_PINCTRL_PFC_R8A77965
4725 }
4727 };
4747 };
4761 };
4766 };
4770 };
4774 };
4779 };
4783 };
4785 #ifdef CONFIG_PINCTRL_PFC_R8A77965
4796 };
4808 };
4817 };
4826 };
4838 };
4844 };
4853 };
4865 };
4874 };
4881 };
4885 };
4890 };
4895 };
4899 };
4903 };
4909 };
4918 };
4920 #ifdef CONFIG_PINCTRL_PFC_R8A77965
4923 };
4933 };
4978 };
5005 };
5035 };
5039 };
5044 };
5049 };
5054 };
5059 };
5064 };
5069 };
5075 };
5081 };
5086 };
5092 };
5099 };
5104 };
5111 };
5123 };
5130 };
5135 };
5143 };
5151 };
5163 };
5173 };
5201 };
5208 };
5215 };
5219 };
5223 };
5227 };
5249 };
5261 };
5265 #ifdef CONFIG_PINCTRL_PFC_R8A77965
5267 #endif
5323 },
5324 #ifdef CONFIG_PINCTRL_PFC_R8A77965
5331 }
5333 };
5336 #define F_(x, y) FN_##y
5337 #define FM(x) FN_##x
5342 /* GP0_31_16 RESERVED */
5359 },
5393 },
5398 /* GP2_31_15 RESERVED */
5414 },
5419 /* GP3_31_16 RESERVED */
5436 },
5441 /* GP4_31_18 RESERVED */
5460 },
5494 },
5528 },
5532 /* GP7_31_4 RESERVED */
5537 },
5538 #undef F_
5539 #undef FM
5541 #define F_(x, y) x,
5542 #define FM(x) FN_##x,
5544 IP0_31_28
5545 IP0_27_24
5546 IP0_23_20
5547 IP0_19_16
5548 IP0_15_12
5549 IP0_11_8
5550 IP0_7_4
5551 IP0_3_0 ))
5552 },
5554 IP1_31_28
5555 IP1_27_24
5556 IP1_23_20
5557 IP1_19_16
5558 IP1_15_12
5559 IP1_11_8
5560 IP1_7_4
5561 IP1_3_0 ))
5562 },
5564 IP2_31_28
5565 IP2_27_24
5566 IP2_23_20
5567 IP2_19_16
5568 IP2_15_12
5569 IP2_11_8
5570 IP2_7_4
5571 IP2_3_0 ))
5572 },
5574 IP3_31_28
5575 IP3_27_24
5576 IP3_23_20
5577 IP3_19_16
5578 IP3_15_12
5579 IP3_11_8
5580 IP3_7_4
5581 IP3_3_0 ))
5582 },
5584 IP4_31_28
5585 IP4_27_24
5586 IP4_23_20
5587 IP4_19_16
5588 IP4_15_12
5589 IP4_11_8
5590 IP4_7_4
5591 IP4_3_0 ))
5592 },
5594 IP5_31_28
5595 IP5_27_24
5596 IP5_23_20
5597 IP5_19_16
5598 IP5_15_12
5599 IP5_11_8
5600 IP5_7_4
5601 IP5_3_0 ))
5602 },
5604 IP6_31_28
5605 IP6_27_24
5606 IP6_23_20
5607 IP6_19_16
5608 IP6_15_12
5609 IP6_11_8
5610 IP6_7_4
5611 IP6_3_0 ))
5612 },
5616 IP7_31_28
5617 IP7_27_24
5618 IP7_23_20
5619 IP7_19_16
5620 /* IP7_15_12 RESERVED */
5621 IP7_11_8
5622 IP7_7_4
5623 IP7_3_0 ))
5624 },
5626 IP8_31_28
5627 IP8_27_24
5628 IP8_23_20
5629 IP8_19_16
5630 IP8_15_12
5631 IP8_11_8
5632 IP8_7_4
5633 IP8_3_0 ))
5634 },
5636 IP9_31_28
5637 IP9_27_24
5638 IP9_23_20
5639 IP9_19_16
5640 IP9_15_12
5641 IP9_11_8
5642 IP9_7_4
5643 IP9_3_0 ))
5644 },
5646 IP10_31_28
5647 IP10_27_24
5648 IP10_23_20
5649 IP10_19_16
5650 IP10_15_12
5651 IP10_11_8
5652 IP10_7_4
5653 IP10_3_0 ))
5654 },
5656 IP11_31_28
5657 IP11_27_24
5658 IP11_23_20
5659 IP11_19_16
5660 IP11_15_12
5661 IP11_11_8
5662 IP11_7_4
5663 IP11_3_0 ))
5664 },
5666 IP12_31_28
5667 IP12_27_24
5668 IP12_23_20
5669 IP12_19_16
5670 IP12_15_12
5671 IP12_11_8
5672 IP12_7_4
5673 IP12_3_0 ))
5674 },
5676 IP13_31_28
5677 IP13_27_24
5678 IP13_23_20
5679 IP13_19_16
5680 IP13_15_12
5681 IP13_11_8
5682 IP13_7_4
5683 IP13_3_0 ))
5684 },
5686 IP14_31_28
5687 IP14_27_24
5688 IP14_23_20
5689 IP14_19_16
5690 IP14_15_12
5691 IP14_11_8
5692 IP14_7_4
5693 IP14_3_0 ))
5694 },
5696 IP15_31_28
5697 IP15_27_24
5698 IP15_23_20
5699 IP15_19_16
5700 IP15_15_12
5701 IP15_11_8
5702 IP15_7_4
5703 IP15_3_0 ))
5704 },
5706 IP16_31_28
5707 IP16_27_24
5708 IP16_23_20
5709 IP16_19_16
5710 IP16_15_12
5711 IP16_11_8
5712 IP16_7_4
5713 IP16_3_0 ))
5714 },
5716 IP17_31_28
5717 IP17_27_24
5718 IP17_23_20
5719 IP17_19_16
5720 IP17_15_12
5721 IP17_11_8
5722 IP17_7_4
5723 IP17_3_0 ))
5724 },
5728 /* IP18_31_8 RESERVED */
5729 IP18_7_4
5730 IP18_3_0 ))
5731 },
5732 #undef F_
5733 #undef FM
5735 #define F_(x, y) x,
5736 #define FM(x) FN_##x,
5741 MOD_SEL0_31_30_29
5742 MOD_SEL0_28_27
5743 MOD_SEL0_26_25_24
5744 MOD_SEL0_23
5745 MOD_SEL0_22
5746 MOD_SEL0_21
5747 MOD_SEL0_20
5748 MOD_SEL0_19
5749 MOD_SEL0_18_17
5750 MOD_SEL0_16
5751 /* RESERVED 15 */
5752 MOD_SEL0_14_13
5753 MOD_SEL0_12
5754 MOD_SEL0_11
5755 MOD_SEL0_10
5756 MOD_SEL0_9_8
5757 MOD_SEL0_7_6
5758 MOD_SEL0_5
5759 MOD_SEL0_4_3
5761 },
5766 MOD_SEL1_31_30
5767 MOD_SEL1_29_28_27
5768 MOD_SEL1_26
5769 MOD_SEL1_25_24
5770 MOD_SEL1_23_22_21
5771 MOD_SEL1_20
5772 MOD_SEL1_19
5773 MOD_SEL1_18_17
5774 MOD_SEL1_16
5775 MOD_SEL1_15_14
5776 MOD_SEL1_13
5777 MOD_SEL1_12
5778 MOD_SEL1_11
5779 MOD_SEL1_10
5780 MOD_SEL1_9
5781 /* RESERVED 8, 7 */
5782 MOD_SEL1_6
5783 MOD_SEL1_5
5784 MOD_SEL1_4
5785 MOD_SEL1_3
5786 MOD_SEL1_2
5787 MOD_SEL1_1
5788 MOD_SEL1_0 ))
5789 },
5794 MOD_SEL2_31
5795 MOD_SEL2_30
5796 MOD_SEL2_29
5797 MOD_SEL2_28_27
5798 MOD_SEL2_26
5799 MOD_SEL2_25_24_23
5800 MOD_SEL2_22
5801 MOD_SEL2_21
5802 MOD_SEL2_20
5803 MOD_SEL2_19
5804 MOD_SEL2_18
5805 MOD_SEL2_17
5806 /* RESERVED 16-1 */
5807 MOD_SEL2_0 ))
5808 },
5810 };
5822 } },
5832 } },
5842 } },
5852 } },
5862 } },
5872 } },
5882 } },
5892 } },
5902 } },
5912 } },
5922 } },
5932 } },
5937 } },
5947 } },
5957 } },
5967 } },
5977 } },
5987 } },
5997 } },
6007 } },
6017 } },
6027 } },
6037 } },
6047 } },
6056 } },
6058 };
6061 POCCTRL,
6062 TDSELCTRL,
6063 };
6069 };
6072 {
6084 }
6120 } },
6154 } },
6188 } },
6222 } },
6256 } },
6290 } },
6324 } },
6326 };
6332 };
6334 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
6356 };
6357 #endif
6359 #ifdef CONFIG_PINCTRL_PFC_R8A77965
6383 };
6384 #endif