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Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / pinctrl / renesas / pfc-r8a77980.c
blob877134d78c7e50c6948c81438822583bad06b3c2
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A77980 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 *
8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
9 *
10 * R-Car Gen3 processor support - PFC hardware block.
11 *
12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */
14
15 #include <linux/errno.h>
16 #include <linux/io.h>
17 #include <linux/kernel.h>
18
19 #include "sh_pfc.h"
20
21 #define CPU_ALL_GP(fn, sfx) \
22 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
23 PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
24 PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
25 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
26 PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
27 PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
28
29 #define CPU_ALL_NOGP(fn) \
30 PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
31 PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
32 PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
33 PIN_NOGP_CFG(DCUTRST_N, "DCUTRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
34 PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
35 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
36 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
37 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
38 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
39 PIN_NOGP_CFG(VDDQ_AVB, "VDDQ_AVB", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33), \
40 PIN_NOGP_CFG(VDDQ_GE, "VDDQ_GE", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
41
42 /*
43 * F_() : just information
44 * FM() : macro for FN_xxx / xxx_MARK
45 */
46
47 /* GPSR0 */
48 #define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
49 #define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
50 #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
51 #define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
52 #define GPSR0_17 F_(DU_DB7, IP2_7_4)
53 #define GPSR0_16 F_(DU_DB6, IP2_3_0)
54 #define GPSR0_15 F_(DU_DB5, IP1_31_28)
55 #define GPSR0_14 F_(DU_DB4, IP1_27_24)
56 #define GPSR0_13 F_(DU_DB3, IP1_23_20)
57 #define GPSR0_12 F_(DU_DB2, IP1_19_16)
58 #define GPSR0_11 F_(DU_DG7, IP1_15_12)
59 #define GPSR0_10 F_(DU_DG6, IP1_11_8)
60 #define GPSR0_9 F_(DU_DG5, IP1_7_4)
61 #define GPSR0_8 F_(DU_DG4, IP1_3_0)
62 #define GPSR0_7 F_(DU_DG3, IP0_31_28)
63 #define GPSR0_6 F_(DU_DG2, IP0_27_24)
64 #define GPSR0_5 F_(DU_DR7, IP0_23_20)
65 #define GPSR0_4 F_(DU_DR6, IP0_19_16)
66 #define GPSR0_3 F_(DU_DR5, IP0_15_12)
67 #define GPSR0_2 F_(DU_DR4, IP0_11_8)
68 #define GPSR0_1 F_(DU_DR3, IP0_7_4)
69 #define GPSR0_0 F_(DU_DR2, IP0_3_0)
70
71 /* GPSR1 */
72 #define GPSR1_27 F_(DIGRF_CLKOUT, IP8_31_28)
73 #define GPSR1_26 F_(DIGRF_CLKIN, IP8_27_24)
74 #define GPSR1_25 F_(CANFD_CLK_A, IP8_23_20)
75 #define GPSR1_24 F_(CANFD1_RX, IP8_19_16)
76 #define GPSR1_23 F_(CANFD1_TX, IP8_15_12)
77 #define GPSR1_22 F_(CANFD0_RX_A, IP8_11_8)
78 #define GPSR1_21 F_(CANFD0_TX_A, IP8_7_4)
79 #define GPSR1_20 F_(AVB_AVTP_CAPTURE, IP8_3_0)
80 #define GPSR1_19 F_(AVB_AVTP_MATCH, IP7_31_28)
81 #define GPSR1_18 FM(AVB_LINK)
82 #define GPSR1_17 FM(AVB_PHY_INT)
83 #define GPSR1_16 FM(AVB_MAGIC)
84 #define GPSR1_15 FM(AVB_MDC)
85 #define GPSR1_14 FM(AVB_MDIO)
86 #define GPSR1_13 FM(AVB_TXCREFCLK)
87 #define GPSR1_12 FM(AVB_TD3)
88 #define GPSR1_11 FM(AVB_TD2)
89 #define GPSR1_10 FM(AVB_TD1)
90 #define GPSR1_9 FM(AVB_TD0)
91 #define GPSR1_8 FM(AVB_TXC)
92 #define GPSR1_7 FM(AVB_TX_CTL)
93 #define GPSR1_6 FM(AVB_RD3)
94 #define GPSR1_5 FM(AVB_RD2)
95 #define GPSR1_4 FM(AVB_RD1)
96 #define GPSR1_3 FM(AVB_RD0)
97 #define GPSR1_2 FM(AVB_RXC)
98 #define GPSR1_1 FM(AVB_RX_CTL)
99 #define GPSR1_0 F_(IRQ0, IP2_27_24)
100
101 /* GPSR2 */
102 #define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
103 #define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12)
104 #define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8)
105 #define GPSR2_26 F_(SDA3, IP10_7_4)
106 #define GPSR2_25 F_(SCL3, IP10_3_0)
107 #define GPSR2_24 F_(MSIOF0_SS2, IP9_31_28)
108 #define GPSR2_23 F_(MSIOF0_SS1, IP9_27_24)
109 #define GPSR2_22 F_(MSIOF0_SYNC, IP9_23_20)
110 #define GPSR2_21 F_(MSIOF0_SCK, IP9_19_16)
111 #define GPSR2_20 F_(MSIOF0_TXD, IP9_15_12)
112 #define GPSR2_19 F_(MSIOF0_RXD, IP9_11_8)
113 #define GPSR2_18 F_(IRQ5, IP9_7_4)
114 #define GPSR2_17 F_(IRQ4, IP9_3_0)
115 #define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
116 #define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
117 #define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
118 #define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
119 #define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
120 #define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
121 #define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
122 #define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
123 #define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
124 #define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
125 #define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
126 #define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
127 #define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
128 #define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
129 #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
130 #define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
131 #define GPSR2_0 F_(VI0_CLK, IP2_31_28)
132
133 /* GPSR3 */
134 #define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
135 #define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
136 #define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
137 #define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
138 #define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
139 #define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
140 #define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
141 #define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
142 #define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
143 #define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
144 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
145 #define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
146 #define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
147 #define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
148 #define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
149 #define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
150 #define GPSR3_0 F_(VI1_CLK, IP5_3_0)
151
152 /* GPSR4 */
153 #define GPSR4_24 FM(GETHER_LINK_A)
154 #define GPSR4_23 FM(GETHER_PHY_INT_A)
155 #define GPSR4_22 FM(GETHER_MAGIC)
156 #define GPSR4_21 FM(GETHER_MDC_A)
157 #define GPSR4_20 FM(GETHER_MDIO_A)
158 #define GPSR4_19 FM(GETHER_TXCREFCLK_MEGA)
159 #define GPSR4_18 FM(GETHER_TXCREFCLK)
160 #define GPSR4_17 FM(GETHER_TD3)
161 #define GPSR4_16 FM(GETHER_TD2)
162 #define GPSR4_15 FM(GETHER_TD1)
163 #define GPSR4_14 FM(GETHER_TD0)
164 #define GPSR4_13 FM(GETHER_TXC)
165 #define GPSR4_12 FM(GETHER_TX_CTL)
166 #define GPSR4_11 FM(GETHER_RD3)
167 #define GPSR4_10 FM(GETHER_RD2)
168 #define GPSR4_9 FM(GETHER_RD1)
169 #define GPSR4_8 FM(GETHER_RD0)
170 #define GPSR4_7 FM(GETHER_RXC)
171 #define GPSR4_6 FM(GETHER_RX_CTL)
172 #define GPSR4_5 F_(SDA2, IP7_27_24)
173 #define GPSR4_4 F_(SCL2, IP7_23_20)
174 #define GPSR4_3 F_(SDA1, IP7_19_16)
175 #define GPSR4_2 F_(SCL1, IP7_15_12)
176 #define GPSR4_1 F_(SDA0, IP7_11_8)
177 #define GPSR4_0 F_(SCL0, IP7_7_4)
178
179 /* GPSR5 */
180 #define GPSR5_14 FM(RPC_INT_N)
181 #define GPSR5_13 FM(RPC_WP_N)
182 #define GPSR5_12 FM(RPC_RESET_N)
183 #define GPSR5_11 FM(QSPI1_SSL)
184 #define GPSR5_10 FM(QSPI1_IO3)
185 #define GPSR5_9 FM(QSPI1_IO2)
186 #define GPSR5_8 FM(QSPI1_MISO_IO1)
187 #define GPSR5_7 FM(QSPI1_MOSI_IO0)
188 #define GPSR5_6 FM(QSPI1_SPCLK)
189 #define GPSR5_5 FM(QSPI0_SSL)
190 #define GPSR5_4 FM(QSPI0_IO3)
191 #define GPSR5_3 FM(QSPI0_IO2)
192 #define GPSR5_2 FM(QSPI0_MISO_IO1)
193 #define GPSR5_1 FM(QSPI0_MOSI_IO0)
194 #define GPSR5_0 FM(QSPI0_SPCLK)
195
196
197 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
198 #define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
199 #define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
200 #define IP0_11_8 FM(DU_DR4) FM(TX4) FM(GETHER_RMII_RXD0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201 #define IP0_15_12 FM(DU_DR5) FM(CTS4_N) FM(GETHER_RMII_RXD1) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202 #define IP0_19_16 FM(DU_DR6) FM(RTS4_N) FM(GETHER_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203 #define IP0_23_20 FM(DU_DR7) F_(0, 0) FM(GETHER_RMII_TXD0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204 #define IP0_27_24 FM(DU_DG2) F_(0, 0) FM(GETHER_RMII_TXD1) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205 #define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206 #define IP1_3_0 FM(DU_DG4) FM(SCL5) F_(0, 0) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207 #define IP1_7_4 FM(DU_DG5) FM(SDA5) FM(GETHER_MDC_B) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208 #define IP1_11_8 FM(DU_DG6) FM(SCIF_CLK_A) FM(GETHER_MDIO_B) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209 #define IP1_15_12 FM(DU_DG7) FM(HRX0_A) F_(0, 0) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210 #define IP1_19_16 FM(DU_DB2) FM(HSCK0_A) F_(0, 0) FM(A12) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211 #define IP1_23_20 FM(DU_DB3) FM(HRTS0_N_A) F_(0, 0) FM(A13) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212 #define IP1_27_24 FM(DU_DB4) FM(HCTS0_N_A) F_(0, 0) FM(A14) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP1_31_28 FM(DU_DB5) FM(HTX0_A) FM(PWM0_A) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP2_3_0 FM(DU_DB6) FM(MSIOF3_RXD) F_(0, 0) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP2_7_4 FM(DU_DB7) FM(MSIOF3_TXD) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP2_11_8 FM(DU_DOTCLKOUT) FM(MSIOF3_SS1) FM(GETHER_LINK_B) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(MSIOF3_SS2) FM(GETHER_PHY_INT_B) FM(A19) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP3_23_20 FM(VI0_DATA2) FM(AVB_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP6_7_4 FM(VI1_DATA5) F_(0, 0) F_(0, 0) FM(D8) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP6_11_8 FM(VI1_DATA6) F_(0, 0) F_(0, 0) FM(D9) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP6_15_12 FM(VI1_DATA7) F_(0, 0) F_(0, 0) FM(D10) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP6_19_16 FM(VI1_DATA8) F_(0, 0) F_(0, 0) FM(D11) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP6_23_20 FM(VI1_DATA9) FM(TCLK1_A) F_(0, 0) FM(D12) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP6_27_24 FM(VI1_DATA10) FM(TCLK2_A) F_(0, 0) FM(D13) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) F_(0, 0) FM(D14) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) F_(0, 0) FM(D15) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP7_7_4 FM(SCL0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP7_11_8 FM(SDA0) F_(0, 0) F_(0, 0) FM(BS_N) FM(SCK0) FM(HSCK0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP7_15_12 FM(SCL1) F_(0, 0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(HCTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP7_19_16 FM(SDA1) F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP7_23_20 FM(SCL2) F_(0, 0) F_(0, 0) FM(WE1_N) FM(RX0) FM(HRX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP7_27_24 FM(SDA2) F_(0, 0) F_(0, 0) FM(EX_WAIT0) FM(TX0) FM(HTX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP7_31_28 FM(AVB_AVTP_MATCH) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP8_3_0 FM(AVB_AVTP_CAPTURE) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP8_7_4 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP9_23_20 FM(MSIOF0_SYNC) FM(DU_DG1) F_(0, 0) FM(VI0_DATA17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP9_27_24 FM(MSIOF0_SS1) FM(DU_DB0) FM(TCLK3) FM(VI0_DATA18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP9_31_28 FM(MSIOF0_SS2) FM(DU_DB1) FM(TCLK4) FM(VI0_DATA19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP10_3_0 FM(SCL3) F_(0, 0) F_(0, 0) FM(VI0_DATA20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP10_7_4 FM(SDA3) F_(0, 0) F_(0, 0) FM(VI0_DATA21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP10_11_8 FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) FM(VI0_DATA22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP10_15_12 FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) FM(VI0_DATA23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP10_19_16 FM(FSO_TOE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283
284 #define PINMUX_GPSR \
285 \
286 GPSR2_29 \
287 GPSR2_28 \
288 GPSR1_27 GPSR2_27 \
289 GPSR1_26 GPSR2_26 \
290 GPSR1_25 GPSR2_25 \
291 GPSR1_24 GPSR2_24 GPSR4_24 \
292 GPSR1_23 GPSR2_23 GPSR4_23 \
293 GPSR1_22 GPSR2_22 GPSR4_22 \
294 GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \
295 GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 \
296 GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 \
297 GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 \
298 GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 \
299 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 \
300 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 \
301 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 \
302 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 \
303 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 \
304 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 \
305 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 \
306 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 \
307 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 \
308 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 \
309 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 \
310 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
311 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
312 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
313 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
314 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
315 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
316
317 #define PINMUX_IPSR \
318 \
319 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
320 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
321 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
322 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
323 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
324 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
325 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
326 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
327 \
328 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
329 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
330 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
331 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
332 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
333 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
334 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
335 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
336 \
337 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 \
338 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 \
339 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 \
340 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 \
341 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 \
342 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 \
343 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 \
344 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28
345
346 /* MOD_SEL0 */ /* 0 */ /* 1 */
347 #define MOD_SEL0_11 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
348 #define MOD_SEL0_10 FM(SEL_GETHER_0) FM(SEL_GETHER_1)
349 #define MOD_SEL0_9 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
350 #define MOD_SEL0_8 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
351 #define MOD_SEL0_7 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
352 #define MOD_SEL0_6 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
353 #define MOD_SEL0_5 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
354 #define MOD_SEL0_4 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
355 #define MOD_SEL0_2 FM(SEL_RSP_0) FM(SEL_RSP_1)
356 #define MOD_SEL0_1 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
357 #define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
358
359 #define PINMUX_MOD_SELS \
360 \
361 MOD_SEL0_11 \
362 MOD_SEL0_10 \
363 MOD_SEL0_9 \
364 MOD_SEL0_8 \
365 MOD_SEL0_7 \
366 MOD_SEL0_6 \
367 MOD_SEL0_5 \
368 MOD_SEL0_4 \
369 MOD_SEL0_2 \
370 MOD_SEL0_1 \
371 MOD_SEL0_0
372
373 enum {
374 PINMUX_RESERVED = 0,
375
376 PINMUX_DATA_BEGIN,
377 GP_ALL(DATA),
378 PINMUX_DATA_END,
379
380 #define F_(x, y)
381 #define FM(x) FN_##x,
382 PINMUX_FUNCTION_BEGIN,
383 GP_ALL(FN),
384 PINMUX_GPSR
385 PINMUX_IPSR
386 PINMUX_MOD_SELS
387 PINMUX_FUNCTION_END,
388 #undef F_
389 #undef FM
390
391 #define F_(x, y)
392 #define FM(x) x##_MARK,
393 PINMUX_MARK_BEGIN,
394 PINMUX_GPSR
395 PINMUX_IPSR
396 PINMUX_MOD_SELS
397 PINMUX_MARK_END,
398 #undef F_
399 #undef FM
400 };
401
402 static const u16 pinmux_data[] = {
403 PINMUX_DATA_GP_ALL(),
404
405 PINMUX_SINGLE(AVB_RX_CTL),
406 PINMUX_SINGLE(AVB_RXC),
407 PINMUX_SINGLE(AVB_RD0),
408 PINMUX_SINGLE(AVB_RD1),
409 PINMUX_SINGLE(AVB_RD2),
410 PINMUX_SINGLE(AVB_RD3),
411 PINMUX_SINGLE(AVB_TX_CTL),
412 PINMUX_SINGLE(AVB_TXC),
413 PINMUX_SINGLE(AVB_TD0),
414 PINMUX_SINGLE(AVB_TD1),
415 PINMUX_SINGLE(AVB_TD2),
416 PINMUX_SINGLE(AVB_TD3),
417 PINMUX_SINGLE(AVB_TXCREFCLK),
418 PINMUX_SINGLE(AVB_MDIO),
419 PINMUX_SINGLE(AVB_MDC),
420 PINMUX_SINGLE(AVB_MAGIC),
421 PINMUX_SINGLE(AVB_PHY_INT),
422 PINMUX_SINGLE(AVB_LINK),
423
424 PINMUX_SINGLE(GETHER_RX_CTL),
425 PINMUX_SINGLE(GETHER_RXC),
426 PINMUX_SINGLE(GETHER_RD0),
427 PINMUX_SINGLE(GETHER_RD1),
428 PINMUX_SINGLE(GETHER_RD2),
429 PINMUX_SINGLE(GETHER_RD3),
430 PINMUX_SINGLE(GETHER_TX_CTL),
431 PINMUX_SINGLE(GETHER_TXC),
432 PINMUX_SINGLE(GETHER_TD0),
433 PINMUX_SINGLE(GETHER_TD1),
434 PINMUX_SINGLE(GETHER_TD2),
435 PINMUX_SINGLE(GETHER_TD3),
436 PINMUX_SINGLE(GETHER_TXCREFCLK),
437 PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA),
438 PINMUX_SINGLE(GETHER_MDIO_A),
439 PINMUX_SINGLE(GETHER_MDC_A),
440 PINMUX_SINGLE(GETHER_MAGIC),
441 PINMUX_SINGLE(GETHER_PHY_INT_A),
442 PINMUX_SINGLE(GETHER_LINK_A),
443
444 PINMUX_SINGLE(QSPI0_SPCLK),
445 PINMUX_SINGLE(QSPI0_MOSI_IO0),
446 PINMUX_SINGLE(QSPI0_MISO_IO1),
447 PINMUX_SINGLE(QSPI0_IO2),
448 PINMUX_SINGLE(QSPI0_IO3),
449 PINMUX_SINGLE(QSPI0_SSL),
450 PINMUX_SINGLE(QSPI1_SPCLK),
451 PINMUX_SINGLE(QSPI1_MOSI_IO0),
452 PINMUX_SINGLE(QSPI1_MISO_IO1),
453 PINMUX_SINGLE(QSPI1_IO2),
454 PINMUX_SINGLE(QSPI1_IO3),
455 PINMUX_SINGLE(QSPI1_SSL),
456 PINMUX_SINGLE(RPC_RESET_N),
457 PINMUX_SINGLE(RPC_WP_N),
458 PINMUX_SINGLE(RPC_INT_N),
459
460 /* IPSR0 */
461 PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
462 PINMUX_IPSR_GPSR(IP0_3_0, SCK4),
463 PINMUX_IPSR_GPSR(IP0_3_0, GETHER_RMII_CRS_DV),
464 PINMUX_IPSR_GPSR(IP0_3_0, A0),
465
466 PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
467 PINMUX_IPSR_GPSR(IP0_7_4, RX4),
468 PINMUX_IPSR_GPSR(IP0_7_4, GETHER_RMII_RX_ER),
469 PINMUX_IPSR_GPSR(IP0_7_4, A1),
470
471 PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
472 PINMUX_IPSR_GPSR(IP0_11_8, TX4),
473 PINMUX_IPSR_GPSR(IP0_11_8, GETHER_RMII_RXD0),
474 PINMUX_IPSR_GPSR(IP0_11_8, A2),
475
476 PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
477 PINMUX_IPSR_GPSR(IP0_15_12, CTS4_N),
478 PINMUX_IPSR_GPSR(IP0_15_12, GETHER_RMII_RXD1),
479 PINMUX_IPSR_GPSR(IP0_15_12, A3),
480
481 PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
482 PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N),
483 PINMUX_IPSR_GPSR(IP0_19_16, GETHER_RMII_TXD_EN),
484 PINMUX_IPSR_GPSR(IP0_19_16, A4),
485
486 PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
487 PINMUX_IPSR_GPSR(IP0_23_20, GETHER_RMII_TXD0),
488 PINMUX_IPSR_GPSR(IP0_23_20, A5),
489
490 PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
491 PINMUX_IPSR_GPSR(IP0_27_24, GETHER_RMII_TXD1),
492 PINMUX_IPSR_GPSR(IP0_27_24, A6),
493
494 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
495 PINMUX_IPSR_GPSR(IP0_31_28, CPG_CPCKOUT),
496 PINMUX_IPSR_GPSR(IP0_31_28, GETHER_RMII_REFCLK),
497 PINMUX_IPSR_GPSR(IP0_31_28, A7),
498 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
499
500 /* IPSR1 */
501 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
502 PINMUX_IPSR_GPSR(IP1_3_0, SCL5),
503 PINMUX_IPSR_GPSR(IP1_3_0, A8),
504
505 PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
506 PINMUX_IPSR_GPSR(IP1_7_4, SDA5),
507 PINMUX_IPSR_MSEL(IP1_7_4, GETHER_MDC_B, SEL_GETHER_1),
508 PINMUX_IPSR_GPSR(IP1_7_4, A9),
509
510 PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
511 PINMUX_IPSR_MSEL(IP1_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
512 PINMUX_IPSR_MSEL(IP1_11_8, GETHER_MDIO_B, SEL_GETHER_1),
513 PINMUX_IPSR_GPSR(IP1_11_8, A10),
514
515 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
516 PINMUX_IPSR_MSEL(IP1_15_12, HRX0_A, SEL_HSCIF0_0),
517 PINMUX_IPSR_GPSR(IP1_15_12, A11),
518
519 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
520 PINMUX_IPSR_MSEL(IP1_19_16, HSCK0_A, SEL_HSCIF0_0),
521 PINMUX_IPSR_GPSR(IP1_19_16, A12),
522 PINMUX_IPSR_GPSR(IP1_19_16, IRQ1),
523
524 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
525 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_A, SEL_HSCIF0_0),
526 PINMUX_IPSR_GPSR(IP1_23_20, A13),
527 PINMUX_IPSR_GPSR(IP1_23_20, IRQ2),
528
529 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
530 PINMUX_IPSR_MSEL(IP1_27_24, HCTS0_N_A, SEL_HSCIF0_0),
531 PINMUX_IPSR_GPSR(IP1_27_24, A14),
532 PINMUX_IPSR_GPSR(IP1_27_24, IRQ3),
533
534 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
535 PINMUX_IPSR_MSEL(IP1_31_28, HTX0_A, SEL_HSCIF0_0),
536 PINMUX_IPSR_MSEL(IP1_31_28, PWM0_A, SEL_PWM0_0),
537 PINMUX_IPSR_GPSR(IP1_31_28, A15),
538
539 /* IPSR2 */
540 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
541 PINMUX_IPSR_GPSR(IP2_3_0, MSIOF3_RXD),
542 PINMUX_IPSR_GPSR(IP2_3_0, A16),
543
544 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
545 PINMUX_IPSR_GPSR(IP2_7_4, MSIOF3_TXD),
546 PINMUX_IPSR_GPSR(IP2_7_4, A17),
547
548 PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
549 PINMUX_IPSR_GPSR(IP2_11_8, MSIOF3_SS1),
550 PINMUX_IPSR_MSEL(IP2_11_8, GETHER_LINK_B, SEL_GETHER_1),
551 PINMUX_IPSR_GPSR(IP2_11_8, A18),
552
553 PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
554 PINMUX_IPSR_GPSR(IP2_15_12, MSIOF3_SS2),
555 PINMUX_IPSR_MSEL(IP2_15_12, GETHER_PHY_INT_B, SEL_GETHER_1),
556 PINMUX_IPSR_GPSR(IP2_15_12, A19),
557 PINMUX_IPSR_GPSR(IP2_15_12, FXR_TXENA_N),
558
559 PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
560 PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
561 PINMUX_IPSR_GPSR(IP2_19_16, FXR_TXENB_N),
562
563 PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
564 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
565
566 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
567
568 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
569 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
570 PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
571 PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
572
573 /* IPSR3 */
574 PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
575 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
576 PINMUX_IPSR_GPSR(IP3_3_0, RX3),
577 PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
578 PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
579
580 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
581 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
582 PINMUX_IPSR_GPSR(IP3_7_4, TX3),
583 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
584
585 PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
586 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
587 PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
588 PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
589
590 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
591 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
592 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
593 PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
594
595 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
596 PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
597 PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
598 PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
599
600 PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
601 PINMUX_IPSR_GPSR(IP3_23_20, AVB_AVTP_PPS),
602
603 PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
604 PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
605
606 PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
607 PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
608 PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
609
610 /* IPSR4 */
611 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
612 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
613 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
614
615 PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
616 PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
617 PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
618
619 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
620 PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
621 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N),
622
623 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
624 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
625
626 PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
627 PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
628 PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
629
630 PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
631 PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
632 PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
633
634 PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
635 PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
636 PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
637
638 PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
639 PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
640 PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
641 PINMUX_IPSR_GPSR(IP4_31_28, CS1_N),
642
643 /* IPSR5 */
644 PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
645 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
646 PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
647
648 PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
649 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
650 PINMUX_IPSR_GPSR(IP5_7_4, D0),
651
652 PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
653 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
654 PINMUX_IPSR_GPSR(IP5_11_8, D1),
655
656 PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
657 PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
658 PINMUX_IPSR_GPSR(IP5_15_12, D2),
659
660 PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
661 PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
662 PINMUX_IPSR_GPSR(IP5_19_16, D3),
663 PINMUX_IPSR_GPSR(IP5_19_16, MMC_WP),
664
665 PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
666 PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
667 PINMUX_IPSR_GPSR(IP5_23_20, D4),
668 PINMUX_IPSR_GPSR(IP5_23_20, MMC_CD),
669
670 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
671 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
672 PINMUX_IPSR_GPSR(IP5_27_24, D5),
673 PINMUX_IPSR_GPSR(IP5_27_24, MMC_DS),
674
675 PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
676 PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
677 PINMUX_IPSR_GPSR(IP5_31_28, D6),
678 PINMUX_IPSR_GPSR(IP5_31_28, MMC_CMD),
679
680 /* IPSR6 */
681 PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
682 PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
683 PINMUX_IPSR_GPSR(IP6_3_0, D7),
684 PINMUX_IPSR_GPSR(IP6_3_0, MMC_D0),
685
686 PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
687 PINMUX_IPSR_GPSR(IP6_7_4, D8),
688 PINMUX_IPSR_GPSR(IP6_7_4, MMC_D1),
689
690 PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
691 PINMUX_IPSR_GPSR(IP6_11_8, D9),
692 PINMUX_IPSR_GPSR(IP6_11_8, MMC_D2),
693
694 PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
695 PINMUX_IPSR_GPSR(IP6_15_12, D10),
696 PINMUX_IPSR_GPSR(IP6_15_12, MMC_D3),
697
698 PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
699 PINMUX_IPSR_GPSR(IP6_19_16, D11),
700 PINMUX_IPSR_GPSR(IP6_19_16, MMC_CLK),
701
702 PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
703 PINMUX_IPSR_MSEL(IP6_23_20, TCLK1_A, SEL_TMU_0),
704 PINMUX_IPSR_GPSR(IP6_23_20, D12),
705 PINMUX_IPSR_GPSR(IP6_23_20, MMC_D4),
706
707 PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
708 PINMUX_IPSR_MSEL(IP6_27_24, TCLK2_A, SEL_TMU_0),
709 PINMUX_IPSR_GPSR(IP6_27_24, D13),
710 PINMUX_IPSR_GPSR(IP6_27_24, MMC_D5),
711
712 PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
713 PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
714 PINMUX_IPSR_GPSR(IP6_31_28, D14),
715 PINMUX_IPSR_GPSR(IP6_31_28, MMC_D6),
716
717 /* IPSR7 */
718 PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
719 PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
720 PINMUX_IPSR_GPSR(IP7_3_0, D15),
721 PINMUX_IPSR_GPSR(IP7_3_0, MMC_D7),
722
723 PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
724 PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
725
726 PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
727 PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
728 PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
729 PINMUX_IPSR_MSEL(IP7_11_8, HSCK0_B, SEL_HSCIF0_1),
730
731 PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
732 PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
733 PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
734 PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
735 PINMUX_IPSR_GPSR(IP7_15_12, HCTS0_N_B),
736
737 PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
738 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
739 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
740 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
741 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_B, SEL_HSCIF0_1),
742
743 PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
744 PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
745 PINMUX_IPSR_GPSR(IP7_23_20, RX0),
746 PINMUX_IPSR_MSEL(IP7_23_20, HRX0_B, SEL_HSCIF0_1),
747
748 PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
749 PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
750 PINMUX_IPSR_GPSR(IP7_27_24, TX0),
751 PINMUX_IPSR_MSEL(IP7_27_24, HTX0_B, SEL_HSCIF0_1),
752
753 PINMUX_IPSR_GPSR(IP7_31_28, AVB_AVTP_MATCH),
754 PINMUX_IPSR_GPSR(IP7_31_28, TPU0TO0),
755
756 /* IPSR8 */
757 PINMUX_IPSR_GPSR(IP8_3_0, AVB_AVTP_CAPTURE),
758 PINMUX_IPSR_GPSR(IP8_3_0, TPU0TO1),
759
760 PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_TX_A, SEL_CANFD0_0),
761 PINMUX_IPSR_GPSR(IP8_7_4, FXR_TXDA),
762 PINMUX_IPSR_MSEL(IP8_7_4, PWM0_B, SEL_PWM0_1),
763 PINMUX_IPSR_GPSR(IP8_7_4, DU_DISP),
764
765 PINMUX_IPSR_MSEL(IP8_11_8, CANFD0_RX_A, SEL_CANFD0_0),
766 PINMUX_IPSR_GPSR(IP8_11_8, RXDA_EXTFXR),
767 PINMUX_IPSR_MSEL(IP8_11_8, PWM1_B, SEL_PWM1_1),
768 PINMUX_IPSR_GPSR(IP8_11_8, DU_CDE),
769
770 PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_TX),
771 PINMUX_IPSR_GPSR(IP8_15_12, FXR_TXDB),
772 PINMUX_IPSR_MSEL(IP8_15_12, PWM2_B, SEL_PWM2_1),
773 PINMUX_IPSR_MSEL(IP8_15_12, TCLK1_B, SEL_TMU_1),
774 PINMUX_IPSR_MSEL(IP8_15_12, TX1_B, SEL_SCIF1_1),
775
776 PINMUX_IPSR_GPSR(IP8_19_16, CANFD1_RX),
777 PINMUX_IPSR_GPSR(IP8_19_16, RXDB_EXTFXR),
778 PINMUX_IPSR_MSEL(IP8_19_16, PWM3_B, SEL_PWM3_1),
779 PINMUX_IPSR_MSEL(IP8_19_16, TCLK2_B, SEL_TMU_1),
780 PINMUX_IPSR_MSEL(IP8_19_16, RX1_B, SEL_SCIF1_1),
781
782 PINMUX_IPSR_MSEL(IP8_23_20, CANFD_CLK_A, SEL_CANFD0_0),
783 PINMUX_IPSR_GPSR(IP8_23_20, CLK_EXTFXR),
784 PINMUX_IPSR_MSEL(IP8_23_20, PWM4_B, SEL_PWM4_1),
785 PINMUX_IPSR_MSEL(IP8_23_20, SPEEDIN_B, SEL_RSP_1),
786 PINMUX_IPSR_MSEL(IP8_23_20, SCIF_CLK_B, SEL_HSCIF0_1),
787
788 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKIN),
789 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_IN),
790
791 PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKOUT),
792 PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKEN_OUT),
793
794 /* IPSR9 */
795 PINMUX_IPSR_GPSR(IP9_3_0, IRQ4),
796 PINMUX_IPSR_GPSR(IP9_3_0, VI0_DATA12),
797
798 PINMUX_IPSR_GPSR(IP9_7_4, IRQ5),
799 PINMUX_IPSR_GPSR(IP9_7_4, VI0_DATA13),
800
801 PINMUX_IPSR_GPSR(IP9_11_8, MSIOF0_RXD),
802 PINMUX_IPSR_GPSR(IP9_11_8, DU_DR0),
803 PINMUX_IPSR_GPSR(IP9_11_8, VI0_DATA14),
804
805 PINMUX_IPSR_GPSR(IP9_15_12, MSIOF0_TXD),
806 PINMUX_IPSR_GPSR(IP9_15_12, DU_DR1),
807 PINMUX_IPSR_GPSR(IP9_15_12, VI0_DATA15),
808
809 PINMUX_IPSR_GPSR(IP9_19_16, MSIOF0_SCK),
810 PINMUX_IPSR_GPSR(IP9_19_16, DU_DG0),
811 PINMUX_IPSR_GPSR(IP9_19_16, VI0_DATA16),
812
813 PINMUX_IPSR_GPSR(IP9_23_20, MSIOF0_SYNC),
814 PINMUX_IPSR_GPSR(IP9_23_20, DU_DG1),
815 PINMUX_IPSR_GPSR(IP9_23_20, VI0_DATA17),
816
817 PINMUX_IPSR_GPSR(IP9_27_24, MSIOF0_SS1),
818 PINMUX_IPSR_GPSR(IP9_27_24, DU_DB0),
819 PINMUX_IPSR_GPSR(IP9_27_24, TCLK3),
820 PINMUX_IPSR_GPSR(IP9_27_24, VI0_DATA18),
821
822 PINMUX_IPSR_GPSR(IP9_31_28, MSIOF0_SS2),
823 PINMUX_IPSR_GPSR(IP9_31_28, DU_DB1),
824 PINMUX_IPSR_GPSR(IP9_31_28, TCLK4),
825 PINMUX_IPSR_GPSR(IP9_31_28, VI0_DATA19),
826
827 /* IPSR10 */
828 PINMUX_IPSR_GPSR(IP10_3_0, SCL3),
829 PINMUX_IPSR_GPSR(IP10_3_0, VI0_DATA20),
830
831 PINMUX_IPSR_GPSR(IP10_7_4, SDA3),
832 PINMUX_IPSR_GPSR(IP10_7_4, VI0_DATA21),
833
834 PINMUX_IPSR_GPSR(IP10_11_8, FSO_CFE_0_N),
835 PINMUX_IPSR_GPSR(IP10_11_8, VI0_DATA22),
836
837 PINMUX_IPSR_GPSR(IP10_15_12, FSO_CFE_1_N),
838 PINMUX_IPSR_GPSR(IP10_15_12, VI0_DATA23),
839
840 PINMUX_IPSR_GPSR(IP10_19_16, FSO_TOE_N),
841 };
842
843 /*
844 * Pins not associated with a GPIO port.
845 */
846 enum {
847 GP_ASSIGN_LAST(),
848 NOGP_ALL(),
849 };
850
851 static const struct sh_pfc_pin pinmux_pins[] = {
852 PINMUX_GPIO_GP_ALL(),
853 PINMUX_NOGP_ALL(),
854 };
855
856 /* - AVB -------------------------------------------------------------------- */
857 static const unsigned int avb_link_pins[] = {
858 /* AVB_LINK */
859 RCAR_GP_PIN(1, 18),
860 };
861 static const unsigned int avb_link_mux[] = {
862 AVB_LINK_MARK,
863 };
864 static const unsigned int avb_magic_pins[] = {
865 /* AVB_MAGIC */
866 RCAR_GP_PIN(1, 16),
867 };
868 static const unsigned int avb_magic_mux[] = {
869 AVB_MAGIC_MARK,
870 };
871 static const unsigned int avb_phy_int_pins[] = {
872 /* AVB_PHY_INT */
873 RCAR_GP_PIN(1, 17),
874 };
875 static const unsigned int avb_phy_int_mux[] = {
876 AVB_PHY_INT_MARK,
877 };
878 static const unsigned int avb_mdio_pins[] = {
879 /* AVB_MDC, AVB_MDIO */
880 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
881 };
882 static const unsigned int avb_mdio_mux[] = {
883 AVB_MDC_MARK, AVB_MDIO_MARK,
884 };
885 static const unsigned int avb_rgmii_pins[] = {
886 /*
887 * AVB_TX_CTL, AVB_TXC, AVB_TD0, AVB_TD1, AVB_TD2, AVB_TD3,
888 * AVB_RX_CTL, AVB_RXC, AVB_RD0, AVB_RD1, AVB_RD2, AVB_RD3,
889 */
890 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
891 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
892 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
893 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
894 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
895 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
896 };
897 static const unsigned int avb_rgmii_mux[] = {
898 AVB_TX_CTL_MARK, AVB_TXC_MARK,
899 AVB_TD0_MARK, AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
900 AVB_RX_CTL_MARK, AVB_RXC_MARK,
901 AVB_RD0_MARK, AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
902 };
903 static const unsigned int avb_txcrefclk_pins[] = {
904 /* AVB_TXCREFCLK */
905 RCAR_GP_PIN(1, 13),
906 };
907 static const unsigned int avb_txcrefclk_mux[] = {
908 AVB_TXCREFCLK_MARK,
909 };
910 static const unsigned int avb_avtp_pps_pins[] = {
911 /* AVB_AVTP_PPS */
912 RCAR_GP_PIN(2, 6),
913 };
914 static const unsigned int avb_avtp_pps_mux[] = {
915 AVB_AVTP_PPS_MARK,
916 };
917 static const unsigned int avb_avtp_capture_pins[] = {
918 /* AVB_AVTP_CAPTURE */
919 RCAR_GP_PIN(1, 20),
920 };
921 static const unsigned int avb_avtp_capture_mux[] = {
922 AVB_AVTP_CAPTURE_MARK,
923 };
924 static const unsigned int avb_avtp_match_pins[] = {
925 /* AVB_AVTP_MATCH */
926 RCAR_GP_PIN(1, 19),
927 };
928 static const unsigned int avb_avtp_match_mux[] = {
929 AVB_AVTP_MATCH_MARK,
930 };
931
932 /* - CANFD0 ----------------------------------------------------------------- */
933 static const unsigned int canfd0_data_a_pins[] = {
934 /* CANFD0_TX, CANFD0_RX */
935 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
936 };
937 static const unsigned int canfd0_data_a_mux[] = {
938 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
939 };
940 static const unsigned int canfd0_data_b_pins[] = {
941 /* CANFD0_TX, CANFD0_RX */
942 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
943 };
944 static const unsigned int canfd0_data_b_mux[] = {
945 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
946 };
947
948 /* - CANFD1 ----------------------------------------------------------------- */
949 static const unsigned int canfd1_data_pins[] = {
950 /* CANFD1_TX, CANFD1_RX */
951 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
952 };
953 static const unsigned int canfd1_data_mux[] = {
954 CANFD1_TX_MARK, CANFD1_RX_MARK,
955 };
956
957 /* - CANFD Clock ------------------------------------------------------------ */
958 static const unsigned int canfd_clk_a_pins[] = {
959 /* CANFD_CLK */
960 RCAR_GP_PIN(1, 25),
961 };
962 static const unsigned int canfd_clk_a_mux[] = {
963 CANFD_CLK_A_MARK,
964 };
965 static const unsigned int canfd_clk_b_pins[] = {
966 /* CANFD_CLK */
967 RCAR_GP_PIN(3, 8),
968 };
969 static const unsigned int canfd_clk_b_mux[] = {
970 CANFD_CLK_B_MARK,
971 };
972
973 /* - DU --------------------------------------------------------------------- */
974 static const unsigned int du_rgb666_pins[] = {
975 /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
976 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
977 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
978 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
979 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
980 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
981 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
982 };
983 static const unsigned int du_rgb666_mux[] = {
984 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
985 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
986 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
987 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
988 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
989 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
990 };
991 static const unsigned int du_rgb888_pins[] = {
992 /* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */
993 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
994 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
995 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19),
996 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
997 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
998 RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
999 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
1000 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
1001 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
1002 };
1003 static const unsigned int du_rgb888_mux[] = {
1004 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
1005 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
1006 DU_DR1_MARK, DU_DR0_MARK,
1007 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
1008 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
1009 DU_DG1_MARK, DU_DG0_MARK,
1010 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
1011 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
1012 DU_DB1_MARK, DU_DB0_MARK,
1013 };
1014 static const unsigned int du_clk_out_pins[] = {
1015 /* DU_DOTCLKOUT */
1016 RCAR_GP_PIN(0, 18),
1017 };
1018 static const unsigned int du_clk_out_mux[] = {
1019 DU_DOTCLKOUT_MARK,
1020 };
1021 static const unsigned int du_sync_pins[] = {
1022 /* DU_EXVSYNC/DU_VSYNC, DU_EXHSYNC/DU_HSYNC */
1023 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
1024 };
1025 static const unsigned int du_sync_mux[] = {
1026 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
1027 };
1028 static const unsigned int du_oddf_pins[] = {
1029 /* DU_EXODDF/DU_ODDF/DISP/CDE */
1030 RCAR_GP_PIN(0, 21),
1031 };
1032 static const unsigned int du_oddf_mux[] = {
1033 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1034 };
1035 static const unsigned int du_cde_pins[] = {
1036 /* DU_CDE */
1037 RCAR_GP_PIN(1, 22),
1038 };
1039 static const unsigned int du_cde_mux[] = {
1040 DU_CDE_MARK,
1041 };
1042 static const unsigned int du_disp_pins[] = {
1043 /* DU_DISP */
1044 RCAR_GP_PIN(1, 21),
1045 };
1046 static const unsigned int du_disp_mux[] = {
1047 DU_DISP_MARK,
1048 };
1049
1050 /* - GETHER ----------------------------------------------------------------- */
1051 static const unsigned int gether_link_a_pins[] = {
1052 /* GETHER_LINK */
1053 RCAR_GP_PIN(4, 24),
1054 };
1055 static const unsigned int gether_link_a_mux[] = {
1056 GETHER_LINK_A_MARK,
1057 };
1058 static const unsigned int gether_phy_int_a_pins[] = {
1059 /* GETHER_PHY_INT */
1060 RCAR_GP_PIN(4, 23),
1061 };
1062 static const unsigned int gether_phy_int_a_mux[] = {
1063 GETHER_PHY_INT_A_MARK,
1064 };
1065 static const unsigned int gether_mdio_a_pins[] = {
1066 /* GETHER_MDC, GETHER_MDIO */
1067 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1068 };
1069 static const unsigned int gether_mdio_a_mux[] = {
1070 GETHER_MDC_A_MARK, GETHER_MDIO_A_MARK,
1071 };
1072 static const unsigned int gether_link_b_pins[] = {
1073 /* GETHER_LINK */
1074 RCAR_GP_PIN(0, 18),
1075 };
1076 static const unsigned int gether_link_b_mux[] = {
1077 GETHER_LINK_B_MARK,
1078 };
1079 static const unsigned int gether_phy_int_b_pins[] = {
1080 /* GETHER_PHY_INT */
1081 RCAR_GP_PIN(0, 19),
1082 };
1083 static const unsigned int gether_phy_int_b_mux[] = {
1084 GETHER_PHY_INT_B_MARK,
1085 };
1086 static const unsigned int gether_mdio_b_mux[] = {
1087 GETHER_MDC_B_MARK, GETHER_MDIO_B_MARK,
1088 };
1089 static const unsigned int gether_mdio_b_pins[] = {
1090 /* GETHER_MDC, GETHER_MDIO */
1091 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1092 };
1093 static const unsigned int gether_magic_pins[] = {
1094 /* GETHER_MAGIC */
1095 RCAR_GP_PIN(4, 22),
1096 };
1097 static const unsigned int gether_magic_mux[] = {
1098 GETHER_MAGIC_MARK,
1099 };
1100 static const unsigned int gether_rgmii_pins[] = {
1101 /*
1102 * GETHER_TX_CTL, GETHER_TXC,
1103 * GETHER_TD0, GETHER_TD1, GETHER_TD2, GETHER_TD3,
1104 * GETHER_RX_CTL, GETHER_RXC,
1105 * GETHER_RD0, GETHER_RD1, GETHER_RD2, GETHER_RD3,
1106 */
1107 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1108 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1109 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1110 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1111 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1112 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1113 };
1114 static const unsigned int gether_rgmii_mux[] = {
1115 GETHER_TX_CTL_MARK, GETHER_TXC_MARK,
1116 GETHER_TD0_MARK, GETHER_TD1_MARK,
1117 GETHER_TD2_MARK, GETHER_TD3_MARK,
1118 GETHER_RX_CTL_MARK, GETHER_RXC_MARK,
1119 GETHER_RD0_MARK, AVB_RD1_MARK,
1120 GETHER_RD2_MARK, AVB_RD3_MARK,
1121 };
1122 static const unsigned int gether_txcrefclk_pins[] = {
1123 /* GETHER_TXCREFCLK */
1124 RCAR_GP_PIN(4, 18),
1125 };
1126 static const unsigned int gether_txcrefclk_mux[] = {
1127 GETHER_TXCREFCLK_MARK,
1128 };
1129 static const unsigned int gether_txcrefclk_mega_pins[] = {
1130 /* GETHER_TXCREFCLK_MEGA */
1131 RCAR_GP_PIN(4, 19),
1132 };
1133 static const unsigned int gether_txcrefclk_mega_mux[] = {
1134 GETHER_TXCREFCLK_MEGA_MARK,
1135 };
1136 static const unsigned int gether_rmii_pins[] = {
1137 /*
1138 * GETHER_RMII_CRS_DV, GETHER_RMII_RX_ER,
1139 * GETHER_RMII_RXD0, GETHER_RMII_RXD1,
1140 * GETHER_RMII_TXD_EN, GETHER_RMII_TXD0,
1141 * GETHER_RMII_TXD1, GETHER_RMII_REFCLK
1142 */
1143 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
1144 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
1145 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1146 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
1147 };
1148 static const unsigned int gether_rmii_mux[] = {
1149 GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK,
1150 GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK,
1151 GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK,
1152 GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK,
1153 };
1154
1155 /* - HSCIF0 ----------------------------------------------------------------- */
1156 static const unsigned int hscif0_data_a_pins[] = {
1157 /* HRX0, HTX0 */
1158 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15),
1159 };
1160 static const unsigned int hscif0_data_a_mux[] = {
1161 HRX0_A_MARK, HTX0_A_MARK,
1162 };
1163 static const unsigned int hscif0_clk_a_pins[] = {
1164 /* HSCK0 */
1165 RCAR_GP_PIN(0, 12),
1166 };
1167 static const unsigned int hscif0_clk_a_mux[] = {
1168 HSCK0_A_MARK,
1169 };
1170 static const unsigned int hscif0_ctrl_a_pins[] = {
1171 /* HRTS0#, HCTS0# */
1172 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1173 };
1174 static const unsigned int hscif0_ctrl_a_mux[] = {
1175 HRTS0_N_A_MARK, HCTS0_N_A_MARK,
1176 };
1177 static const unsigned int hscif0_data_b_pins[] = {
1178 /* HRX0, HTX0 */
1179 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1180 };
1181 static const unsigned int hscif0_data_b_mux[] = {
1182 HRX0_B_MARK, HTX0_B_MARK,
1183 };
1184 static const unsigned int hscif0_clk_b_pins[] = {
1185 /* HSCK0 */
1186 RCAR_GP_PIN(4, 1),
1187 };
1188 static const unsigned int hscif0_clk_b_mux[] = {
1189 HSCK0_B_MARK,
1190 };
1191 static const unsigned int hscif0_ctrl_b_pins[] = {
1192 /* HRTS0#, HCTS0# */
1193 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1194 };
1195 static const unsigned int hscif0_ctrl_b_mux[] = {
1196 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
1197 };
1198
1199 /* - HSCIF1 ----------------------------------------------------------------- */
1200 static const unsigned int hscif1_data_pins[] = {
1201 /* HRX1, HTX1 */
1202 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1203 };
1204 static const unsigned int hscif1_data_mux[] = {
1205 HRX1_MARK, HTX1_MARK,
1206 };
1207 static const unsigned int hscif1_clk_pins[] = {
1208 /* HSCK1 */
1209 RCAR_GP_PIN(2, 7),
1210 };
1211 static const unsigned int hscif1_clk_mux[] = {
1212 HSCK1_MARK,
1213 };
1214 static const unsigned int hscif1_ctrl_pins[] = {
1215 /* HRTS1#, HCTS1# */
1216 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1217 };
1218 static const unsigned int hscif1_ctrl_mux[] = {
1219 HRTS1_N_MARK, HCTS1_N_MARK,
1220 };
1221
1222 /* - HSCIF2 ----------------------------------------------------------------- */
1223 static const unsigned int hscif2_data_pins[] = {
1224 /* HRX2, HTX2 */
1225 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
1226 };
1227 static const unsigned int hscif2_data_mux[] = {
1228 HRX2_MARK, HTX2_MARK,
1229 };
1230 static const unsigned int hscif2_clk_pins[] = {
1231 /* HSCK2 */
1232 RCAR_GP_PIN(2, 12),
1233 };
1234 static const unsigned int hscif2_clk_mux[] = {
1235 HSCK2_MARK,
1236 };
1237 static const unsigned int hscif2_ctrl_pins[] = {
1238 /* HRTS2#, HCTS2# */
1239 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1240 };
1241 static const unsigned int hscif2_ctrl_mux[] = {
1242 HRTS2_N_MARK, HCTS2_N_MARK,
1243 };
1244
1245 /* - HSCIF3 ----------------------------------------------------------------- */
1246 static const unsigned int hscif3_data_pins[] = {
1247 /* HRX3, HTX3 */
1248 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1249 };
1250 static const unsigned int hscif3_data_mux[] = {
1251 HRX3_MARK, HTX3_MARK,
1252 };
1253 static const unsigned int hscif3_clk_pins[] = {
1254 /* HSCK3 */
1255 RCAR_GP_PIN(2, 0),
1256 };
1257 static const unsigned int hscif3_clk_mux[] = {
1258 HSCK3_MARK,
1259 };
1260 static const unsigned int hscif3_ctrl_pins[] = {
1261 /* HRTS3#, HCTS3# */
1262 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
1263 };
1264 static const unsigned int hscif3_ctrl_mux[] = {
1265 HRTS3_N_MARK, HCTS3_N_MARK,
1266 };
1267
1268 /* - I2C0 ------------------------------------------------------------------- */
1269 static const unsigned int i2c0_pins[] = {
1270 /* SDA0, SCL0 */
1271 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
1272 };
1273 static const unsigned int i2c0_mux[] = {
1274 SDA0_MARK, SCL0_MARK,
1275 };
1276
1277 /* - I2C1 ------------------------------------------------------------------- */
1278 static const unsigned int i2c1_pins[] = {
1279 /* SDA1, SCL1 */
1280 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1281 };
1282 static const unsigned int i2c1_mux[] = {
1283 SDA1_MARK, SCL1_MARK,
1284 };
1285
1286 /* - I2C2 ------------------------------------------------------------------- */
1287 static const unsigned int i2c2_pins[] = {
1288 /* SDA2, SCL2 */
1289 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1290 };
1291 static const unsigned int i2c2_mux[] = {
1292 SDA2_MARK, SCL2_MARK,
1293 };
1294
1295 /* - I2C3 ------------------------------------------------------------------- */
1296 static const unsigned int i2c3_pins[] = {
1297 /* SDA3, SCL3 */
1298 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
1299 };
1300 static const unsigned int i2c3_mux[] = {
1301 SDA3_MARK, SCL3_MARK,
1302 };
1303
1304 /* - I2C4 ------------------------------------------------------------------- */
1305 static const unsigned int i2c4_pins[] = {
1306 /* SDA4, SCL4 */
1307 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1308 };
1309 static const unsigned int i2c4_mux[] = {
1310 SDA4_MARK, SCL4_MARK,
1311 };
1312
1313 /* - I2C5 ------------------------------------------------------------------- */
1314 static const unsigned int i2c5_pins[] = {
1315 /* SDA5, SCL5 */
1316 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1317 };
1318 static const unsigned int i2c5_mux[] = {
1319 SDA5_MARK, SCL5_MARK,
1320 };
1321
1322 /* - INTC-EX ---------------------------------------------------------------- */
1323 static const unsigned int intc_ex_irq0_pins[] = {
1324 /* IRQ0 */
1325 RCAR_GP_PIN(1, 0),
1326 };
1327 static const unsigned int intc_ex_irq0_mux[] = {
1328 IRQ0_MARK,
1329 };
1330 static const unsigned int intc_ex_irq1_pins[] = {
1331 /* IRQ1 */
1332 RCAR_GP_PIN(0, 12),
1333 };
1334 static const unsigned int intc_ex_irq1_mux[] = {
1335 IRQ1_MARK,
1336 };
1337 static const unsigned int intc_ex_irq2_pins[] = {
1338 /* IRQ2 */
1339 RCAR_GP_PIN(0, 13),
1340 };
1341 static const unsigned int intc_ex_irq2_mux[] = {
1342 IRQ2_MARK,
1343 };
1344 static const unsigned int intc_ex_irq3_pins[] = {
1345 /* IRQ3 */
1346 RCAR_GP_PIN(0, 14),
1347 };
1348 static const unsigned int intc_ex_irq3_mux[] = {
1349 IRQ3_MARK,
1350 };
1351 static const unsigned int intc_ex_irq4_pins[] = {
1352 /* IRQ4 */
1353 RCAR_GP_PIN(2, 17),
1354 };
1355 static const unsigned int intc_ex_irq4_mux[] = {
1356 IRQ4_MARK,
1357 };
1358 static const unsigned int intc_ex_irq5_pins[] = {
1359 /* IRQ5 */
1360 RCAR_GP_PIN(2, 18),
1361 };
1362 static const unsigned int intc_ex_irq5_mux[] = {
1363 IRQ5_MARK,
1364 };
1365
1366 /* - MMC -------------------------------------------------------------------- */
1367 static const unsigned int mmc_data_pins[] = {
1368 /* MMC_D[0:7] */
1369 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1370 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1371 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1372 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1373 };
1374 static const unsigned int mmc_data_mux[] = {
1375 MMC_D0_MARK, MMC_D1_MARK,
1376 MMC_D2_MARK, MMC_D3_MARK,
1377 MMC_D4_MARK, MMC_D5_MARK,
1378 MMC_D6_MARK, MMC_D7_MARK,
1379 };
1380 static const unsigned int mmc_ctrl_pins[] = {
1381 /* MMC_CLK, MMC_CMD */
1382 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7),
1383 };
1384 static const unsigned int mmc_ctrl_mux[] = {
1385 MMC_CLK_MARK, MMC_CMD_MARK,
1386 };
1387 static const unsigned int mmc_cd_pins[] = {
1388 /* MMC_CD */
1389 RCAR_GP_PIN(3, 5),
1390 };
1391 static const unsigned int mmc_cd_mux[] = {
1392 MMC_CD_MARK,
1393 };
1394 static const unsigned int mmc_wp_pins[] = {
1395 /* MMC_WP */
1396 RCAR_GP_PIN(3, 4),
1397 };
1398 static const unsigned int mmc_wp_mux[] = {
1399 MMC_WP_MARK,
1400 };
1401 static const unsigned int mmc_ds_pins[] = {
1402 /* MMC_DS */
1403 RCAR_GP_PIN(3, 6),
1404 };
1405 static const unsigned int mmc_ds_mux[] = {
1406 MMC_DS_MARK,
1407 };
1408
1409 /* - MSIOF0 ----------------------------------------------------------------- */
1410 static const unsigned int msiof0_clk_pins[] = {
1411 /* MSIOF0_SCK */
1412 RCAR_GP_PIN(2, 21),
1413 };
1414 static const unsigned int msiof0_clk_mux[] = {
1415 MSIOF0_SCK_MARK,
1416 };
1417 static const unsigned int msiof0_sync_pins[] = {
1418 /* MSIOF0_SYNC */
1419 RCAR_GP_PIN(2, 22),
1420 };
1421 static const unsigned int msiof0_sync_mux[] = {
1422 MSIOF0_SYNC_MARK,
1423 };
1424 static const unsigned int msiof0_ss1_pins[] = {
1425 /* MSIOF0_SS1 */
1426 RCAR_GP_PIN(2, 23),
1427 };
1428 static const unsigned int msiof0_ss1_mux[] = {
1429 MSIOF0_SS1_MARK,
1430 };
1431 static const unsigned int msiof0_ss2_pins[] = {
1432 /* MSIOF0_SS2 */
1433 RCAR_GP_PIN(2, 24),
1434 };
1435 static const unsigned int msiof0_ss2_mux[] = {
1436 MSIOF0_SS2_MARK,
1437 };
1438 static const unsigned int msiof0_txd_pins[] = {
1439 /* MSIOF0_TXD */
1440 RCAR_GP_PIN(2, 20),
1441 };
1442 static const unsigned int msiof0_txd_mux[] = {
1443 MSIOF0_TXD_MARK,
1444 };
1445 static const unsigned int msiof0_rxd_pins[] = {
1446 /* MSIOF0_RXD */
1447 RCAR_GP_PIN(2, 19),
1448 };
1449 static const unsigned int msiof0_rxd_mux[] = {
1450 MSIOF0_RXD_MARK,
1451 };
1452
1453 /* - MSIOF1 ----------------------------------------------------------------- */
1454 static const unsigned int msiof1_clk_pins[] = {
1455 /* MSIOF1_SCK */
1456 RCAR_GP_PIN(3, 2),
1457 };
1458 static const unsigned int msiof1_clk_mux[] = {
1459 MSIOF1_SCK_MARK,
1460 };
1461 static const unsigned int msiof1_sync_pins[] = {
1462 /* MSIOF1_SYNC */
1463 RCAR_GP_PIN(3, 3),
1464 };
1465 static const unsigned int msiof1_sync_mux[] = {
1466 MSIOF1_SYNC_MARK,
1467 };
1468 static const unsigned int msiof1_ss1_pins[] = {
1469 /* MSIOF1_SS1 */
1470 RCAR_GP_PIN(3, 4),
1471 };
1472 static const unsigned int msiof1_ss1_mux[] = {
1473 MSIOF1_SS1_MARK,
1474 };
1475 static const unsigned int msiof1_ss2_pins[] = {
1476 /* MSIOF1_SS2 */
1477 RCAR_GP_PIN(3, 5),
1478 };
1479 static const unsigned int msiof1_ss2_mux[] = {
1480 MSIOF1_SS2_MARK,
1481 };
1482 static const unsigned int msiof1_txd_pins[] = {
1483 /* MSIOF1_TXD */
1484 RCAR_GP_PIN(3, 1),
1485 };
1486 static const unsigned int msiof1_txd_mux[] = {
1487 MSIOF1_TXD_MARK,
1488 };
1489 static const unsigned int msiof1_rxd_pins[] = {
1490 /* MSIOF1_RXD */
1491 RCAR_GP_PIN(3, 0),
1492 };
1493 static const unsigned int msiof1_rxd_mux[] = {
1494 MSIOF1_RXD_MARK,
1495 };
1496
1497 /* - MSIOF2 ----------------------------------------------------------------- */
1498 static const unsigned int msiof2_clk_pins[] = {
1499 /* MSIOF2_SCK */
1500 RCAR_GP_PIN(2, 0),
1501 };
1502 static const unsigned int msiof2_clk_mux[] = {
1503 MSIOF2_SCK_MARK,
1504 };
1505 static const unsigned int msiof2_sync_pins[] = {
1506 /* MSIOF2_SYNC */
1507 RCAR_GP_PIN(2, 3),
1508 };
1509 static const unsigned int msiof2_sync_mux[] = {
1510 MSIOF2_SYNC_MARK,
1511 };
1512 static const unsigned int msiof2_ss1_pins[] = {
1513 /* MSIOF2_SS1 */
1514 RCAR_GP_PIN(2, 4),
1515 };
1516 static const unsigned int msiof2_ss1_mux[] = {
1517 MSIOF2_SS1_MARK,
1518 };
1519 static const unsigned int msiof2_ss2_pins[] = {
1520 /* MSIOF2_SS2 */
1521 RCAR_GP_PIN(2, 5),
1522 };
1523 static const unsigned int msiof2_ss2_mux[] = {
1524 MSIOF2_SS2_MARK,
1525 };
1526 static const unsigned int msiof2_txd_pins[] = {
1527 /* MSIOF2_TXD */
1528 RCAR_GP_PIN(2, 2),
1529 };
1530 static const unsigned int msiof2_txd_mux[] = {
1531 MSIOF2_TXD_MARK,
1532 };
1533 static const unsigned int msiof2_rxd_pins[] = {
1534 /* MSIOF2_RXD */
1535 RCAR_GP_PIN(2, 1),
1536 };
1537 static const unsigned int msiof2_rxd_mux[] = {
1538 MSIOF2_RXD_MARK,
1539 };
1540
1541 /* - MSIOF3 ----------------------------------------------------------------- */
1542 static const unsigned int msiof3_clk_pins[] = {
1543 /* MSIOF3_SCK */
1544 RCAR_GP_PIN(0, 20),
1545 };
1546 static const unsigned int msiof3_clk_mux[] = {
1547 MSIOF3_SCK_MARK,
1548 };
1549 static const unsigned int msiof3_sync_pins[] = {
1550 /* MSIOF3_SYNC */
1551 RCAR_GP_PIN(0, 21),
1552 };
1553 static const unsigned int msiof3_sync_mux[] = {
1554 MSIOF3_SYNC_MARK,
1555 };
1556 static const unsigned int msiof3_ss1_pins[] = {
1557 /* MSIOF3_SS1 */
1558 RCAR_GP_PIN(0, 18),
1559 };
1560 static const unsigned int msiof3_ss1_mux[] = {
1561 MSIOF3_SS1_MARK,
1562 };
1563 static const unsigned int msiof3_ss2_pins[] = {
1564 /* MSIOF3_SS2 */
1565 RCAR_GP_PIN(0, 19),
1566 };
1567 static const unsigned int msiof3_ss2_mux[] = {
1568 MSIOF3_SS2_MARK,
1569 };
1570 static const unsigned int msiof3_txd_pins[] = {
1571 /* MSIOF3_TXD */
1572 RCAR_GP_PIN(0, 17),
1573 };
1574 static const unsigned int msiof3_txd_mux[] = {
1575 MSIOF3_TXD_MARK,
1576 };
1577 static const unsigned int msiof3_rxd_pins[] = {
1578 /* MSIOF3_RXD */
1579 RCAR_GP_PIN(0, 16),
1580 };
1581 static const unsigned int msiof3_rxd_mux[] = {
1582 MSIOF3_RXD_MARK,
1583 };
1584
1585 /* - PWM0 ------------------------------------------------------------------- */
1586 static const unsigned int pwm0_a_pins[] = {
1587 /* PWM0 */
1588 RCAR_GP_PIN(0, 15),
1589 };
1590 static const unsigned int pwm0_a_mux[] = {
1591 PWM0_A_MARK,
1592 };
1593 static const unsigned int pwm0_b_pins[] = {
1594 /* PWM0 */
1595 RCAR_GP_PIN(1, 21),
1596 };
1597 static const unsigned int pwm0_b_mux[] = {
1598 PWM0_B_MARK,
1599 };
1600
1601 /* - PWM1 ------------------------------------------------------------------- */
1602 static const unsigned int pwm1_a_pins[] = {
1603 /* PWM1 */
1604 RCAR_GP_PIN(2, 13),
1605 };
1606 static const unsigned int pwm1_a_mux[] = {
1607 PWM1_A_MARK,
1608 };
1609 static const unsigned int pwm1_b_pins[] = {
1610 /* PWM1 */
1611 RCAR_GP_PIN(1, 22),
1612 };
1613 static const unsigned int pwm1_b_mux[] = {
1614 PWM1_B_MARK,
1615 };
1616
1617 /* - PWM2 ------------------------------------------------------------------- */
1618 static const unsigned int pwm2_a_pins[] = {
1619 /* PWM2 */
1620 RCAR_GP_PIN(2, 14),
1621 };
1622 static const unsigned int pwm2_a_mux[] = {
1623 PWM2_A_MARK,
1624 };
1625 static const unsigned int pwm2_b_pins[] = {
1626 /* PWM2 */
1627 RCAR_GP_PIN(1, 23),
1628 };
1629 static const unsigned int pwm2_b_mux[] = {
1630 PWM2_B_MARK,
1631 };
1632
1633 /* - PWM3 ------------------------------------------------------------------- */
1634 static const unsigned int pwm3_a_pins[] = {
1635 /* PWM3 */
1636 RCAR_GP_PIN(2, 15),
1637 };
1638 static const unsigned int pwm3_a_mux[] = {
1639 PWM3_A_MARK,
1640 };
1641 static const unsigned int pwm3_b_pins[] = {
1642 /* PWM3 */
1643 RCAR_GP_PIN(1, 24),
1644 };
1645 static const unsigned int pwm3_b_mux[] = {
1646 PWM3_B_MARK,
1647 };
1648
1649 /* - PWM4 ------------------------------------------------------------------- */
1650 static const unsigned int pwm4_a_pins[] = {
1651 /* PWM4 */
1652 RCAR_GP_PIN(2, 16),
1653 };
1654 static const unsigned int pwm4_a_mux[] = {
1655 PWM4_A_MARK,
1656 };
1657 static const unsigned int pwm4_b_pins[] = {
1658 /* PWM4 */
1659 RCAR_GP_PIN(1, 25),
1660 };
1661 static const unsigned int pwm4_b_mux[] = {
1662 PWM4_B_MARK,
1663 };
1664
1665 /* - QSPI0 ------------------------------------------------------------------ */
1666 static const unsigned int qspi0_ctrl_pins[] = {
1667 /* SPCLK, SSL */
1668 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
1669 };
1670 static const unsigned int qspi0_ctrl_mux[] = {
1671 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1672 };
1673
1674 /* - QSPI1 ------------------------------------------------------------------ */
1675 static const unsigned int qspi1_ctrl_pins[] = {
1676 /* SPCLK, SSL */
1677 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
1678 };
1679 static const unsigned int qspi1_ctrl_mux[] = {
1680 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1681 };
1682
1683 /* - RPC -------------------------------------------------------------------- */
1684 static const unsigned int rpc_clk_pins[] = {
1685 /* Octal-SPI flash: C/SCLK */
1686 /* HyperFlash: CK, CK# */
1687 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
1688 };
1689 static const unsigned int rpc_clk_mux[] = {
1690 QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
1691 };
1692 static const unsigned int rpc_ctrl_pins[] = {
1693 /* Octal-SPI flash: S#/CS, DQS */
1694 /* HyperFlash: CS#, RDS */
1695 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1696 };
1697 static const unsigned int rpc_ctrl_mux[] = {
1698 QSPI0_SSL_MARK, QSPI1_SSL_MARK,
1699 };
1700 static const unsigned int rpc_data_pins[] = {
1701 /* DQ[0:7] */
1702 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1703 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1704 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1705 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1706 };
1707 static const unsigned int rpc_data_mux[] = {
1708 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1709 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
1710 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1711 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
1712 };
1713 static const unsigned int rpc_reset_pins[] = {
1714 /* RPC_RESET# */
1715 RCAR_GP_PIN(5, 12),
1716 };
1717 static const unsigned int rpc_reset_mux[] = {
1718 RPC_RESET_N_MARK,
1719 };
1720 static const unsigned int rpc_int_pins[] = {
1721 /* RPC_INT# */
1722 RCAR_GP_PIN(5, 14),
1723 };
1724 static const unsigned int rpc_int_mux[] = {
1725 RPC_INT_N_MARK,
1726 };
1727 static const unsigned int rpc_wp_pins[] = {
1728 /* RPC_WP# */
1729 RCAR_GP_PIN(5, 13),
1730 };
1731 static const unsigned int rpc_wp_mux[] = {
1732 RPC_WP_N_MARK,
1733 };
1734
1735 /* - SCIF0 ------------------------------------------------------------------ */
1736 static const unsigned int scif0_data_pins[] = {
1737 /* RX0, TX0 */
1738 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1739 };
1740 static const unsigned int scif0_data_mux[] = {
1741 RX0_MARK, TX0_MARK,
1742 };
1743 static const unsigned int scif0_clk_pins[] = {
1744 /* SCK0 */
1745 RCAR_GP_PIN(4, 1),
1746 };
1747 static const unsigned int scif0_clk_mux[] = {
1748 SCK0_MARK,
1749 };
1750 static const unsigned int scif0_ctrl_pins[] = {
1751 /* RTS0#, CTS0# */
1752 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1753 };
1754 static const unsigned int scif0_ctrl_mux[] = {
1755 RTS0_N_MARK, CTS0_N_MARK,
1756 };
1757
1758 /* - SCIF1 ------------------------------------------------------------------ */
1759 static const unsigned int scif1_data_a_pins[] = {
1760 /* RX1, TX1 */
1761 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1762 };
1763 static const unsigned int scif1_data_a_mux[] = {
1764 RX1_A_MARK, TX1_A_MARK,
1765 };
1766 static const unsigned int scif1_clk_pins[] = {
1767 /* SCK1 */
1768 RCAR_GP_PIN(2, 5),
1769 };
1770 static const unsigned int scif1_clk_mux[] = {
1771 SCK1_MARK,
1772 };
1773 static const unsigned int scif1_ctrl_pins[] = {
1774 /* RTS1#, CTS1# */
1775 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1776 };
1777 static const unsigned int scif1_ctrl_mux[] = {
1778 RTS1_N_MARK, CTS1_N_MARK,
1779 };
1780 static const unsigned int scif1_data_b_pins[] = {
1781 /* RX1, TX1 */
1782 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1783 };
1784 static const unsigned int scif1_data_b_mux[] = {
1785 RX1_B_MARK, TX1_B_MARK,
1786 };
1787
1788 /* - SCIF3 ------------------------------------------------------------------ */
1789 static const unsigned int scif3_data_pins[] = {
1790 /* RX3, TX3 */
1791 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1792 };
1793 static const unsigned int scif3_data_mux[] = {
1794 RX3_MARK, TX3_MARK,
1795 };
1796 static const unsigned int scif3_clk_pins[] = {
1797 /* SCK3 */
1798 RCAR_GP_PIN(2, 0),
1799 };
1800 static const unsigned int scif3_clk_mux[] = {
1801 SCK3_MARK,
1802 };
1803 static const unsigned int scif3_ctrl_pins[] = {
1804 /* RTS3#, CTS3# */
1805 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1806 };
1807 static const unsigned int scif3_ctrl_mux[] = {
1808 RTS3_N_MARK, CTS3_N_MARK,
1809 };
1810
1811 /* - SCIF4 ------------------------------------------------------------------ */
1812 static const unsigned int scif4_data_pins[] = {
1813 /* RX4, TX4 */
1814 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
1815 };
1816 static const unsigned int scif4_data_mux[] = {
1817 RX4_MARK, TX4_MARK,
1818 };
1819 static const unsigned int scif4_clk_pins[] = {
1820 /* SCK4 */
1821 RCAR_GP_PIN(0, 0),
1822 };
1823 static const unsigned int scif4_clk_mux[] = {
1824 SCK4_MARK,
1825 };
1826 static const unsigned int scif4_ctrl_pins[] = {
1827 /* RTS4#, CTS4# */
1828 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
1829 };
1830 static const unsigned int scif4_ctrl_mux[] = {
1831 RTS4_N_MARK, CTS4_N_MARK,
1832 };
1833
1834 /* - SCIF Clock ------------------------------------------------------------- */
1835 static const unsigned int scif_clk_a_pins[] = {
1836 /* SCIF_CLK */
1837 RCAR_GP_PIN(0, 10),
1838 };
1839 static const unsigned int scif_clk_a_mux[] = {
1840 SCIF_CLK_A_MARK,
1841 };
1842 static const unsigned int scif_clk_b_pins[] = {
1843 /* SCIF_CLK */
1844 RCAR_GP_PIN(1, 25),
1845 };
1846 static const unsigned int scif_clk_b_mux[] = {
1847 SCIF_CLK_B_MARK,
1848 };
1849
1850 /* - TMU -------------------------------------------------------------------- */
1851 static const unsigned int tmu_tclk1_a_pins[] = {
1852 /* TCLK1 */
1853 RCAR_GP_PIN(3, 13),
1854 };
1855 static const unsigned int tmu_tclk1_a_mux[] = {
1856 TCLK1_A_MARK,
1857 };
1858 static const unsigned int tmu_tclk1_b_pins[] = {
1859 /* TCLK1 */
1860 RCAR_GP_PIN(1, 23),
1861 };
1862 static const unsigned int tmu_tclk1_b_mux[] = {
1863 TCLK1_B_MARK,
1864 };
1865 static const unsigned int tmu_tclk2_a_pins[] = {
1866 /* TCLK2 */
1867 RCAR_GP_PIN(3, 14),
1868 };
1869 static const unsigned int tmu_tclk2_a_mux[] = {
1870 TCLK2_A_MARK,
1871 };
1872 static const unsigned int tmu_tclk2_b_pins[] = {
1873 /* TCLK2 */
1874 RCAR_GP_PIN(1, 24),
1875 };
1876 static const unsigned int tmu_tclk2_b_mux[] = {
1877 TCLK2_B_MARK,
1878 };
1879
1880 /* - TPU ------------------------------------------------------------------- */
1881 static const unsigned int tpu_to0_pins[] = {
1882 /* TPU0TO0 */
1883 RCAR_GP_PIN(1, 19),
1884 };
1885 static const unsigned int tpu_to0_mux[] = {
1886 TPU0TO0_MARK,
1887 };
1888 static const unsigned int tpu_to1_pins[] = {
1889 /* TPU0TO1 */
1890 RCAR_GP_PIN(1, 20),
1891 };
1892 static const unsigned int tpu_to1_mux[] = {
1893 TPU0TO1_MARK,
1894 };
1895 static const unsigned int tpu_to2_pins[] = {
1896 /* TPU0TO2 */
1897 RCAR_GP_PIN(4, 2),
1898 };
1899 static const unsigned int tpu_to2_mux[] = {
1900 TPU0TO2_MARK,
1901 };
1902 static const unsigned int tpu_to3_pins[] = {
1903 /* TPU0TO3 */
1904 RCAR_GP_PIN(4, 3),
1905 };
1906 static const unsigned int tpu_to3_mux[] = {
1907 TPU0TO3_MARK,
1908 };
1909
1910 /* - VIN0 ------------------------------------------------------------------- */
1911 static const unsigned int vin0_data_pins[] = {
1912 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1913 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1914 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1915 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1916 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1917 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1918 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1919 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1920 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1921 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1922 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
1923 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
1924 };
1925 static const unsigned int vin0_data_mux[] = {
1926 VI0_DATA0_MARK, VI0_DATA1_MARK,
1927 VI0_DATA2_MARK, VI0_DATA3_MARK,
1928 VI0_DATA4_MARK, VI0_DATA5_MARK,
1929 VI0_DATA6_MARK, VI0_DATA7_MARK,
1930 VI0_DATA8_MARK, VI0_DATA9_MARK,
1931 VI0_DATA10_MARK, VI0_DATA11_MARK,
1932 VI0_DATA12_MARK, VI0_DATA13_MARK,
1933 VI0_DATA14_MARK, VI0_DATA15_MARK,
1934 VI0_DATA16_MARK, VI0_DATA17_MARK,
1935 VI0_DATA18_MARK, VI0_DATA19_MARK,
1936 VI0_DATA20_MARK, VI0_DATA21_MARK,
1937 VI0_DATA22_MARK, VI0_DATA23_MARK,
1938 };
1939 static const unsigned int vin0_data18_pins[] = {
1940 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1941 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1942 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1943 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1944 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1945 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1946 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1947 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
1948 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
1949 };
1950 static const unsigned int vin0_data18_mux[] = {
1951 VI0_DATA2_MARK, VI0_DATA3_MARK,
1952 VI0_DATA4_MARK, VI0_DATA5_MARK,
1953 VI0_DATA6_MARK, VI0_DATA7_MARK,
1954 VI0_DATA10_MARK, VI0_DATA11_MARK,
1955 VI0_DATA12_MARK, VI0_DATA13_MARK,
1956 VI0_DATA14_MARK, VI0_DATA15_MARK,
1957 VI0_DATA18_MARK, VI0_DATA19_MARK,
1958 VI0_DATA20_MARK, VI0_DATA21_MARK,
1959 VI0_DATA22_MARK, VI0_DATA23_MARK,
1960 };
1961 static const unsigned int vin0_sync_pins[] = {
1962 /* VI0_VSYNC#, VI0_HSYNC# */
1963 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1964 };
1965 static const unsigned int vin0_sync_mux[] = {
1966 VI0_VSYNC_N_MARK, VI0_HSYNC_N_MARK,
1967 };
1968 static const unsigned int vin0_field_pins[] = {
1969 /* VI0_FIELD */
1970 RCAR_GP_PIN(2, 16),
1971 };
1972 static const unsigned int vin0_field_mux[] = {
1973 VI0_FIELD_MARK,
1974 };
1975 static const unsigned int vin0_clkenb_pins[] = {
1976 /* VI0_CLKENB */
1977 RCAR_GP_PIN(2, 1),
1978 };
1979 static const unsigned int vin0_clkenb_mux[] = {
1980 VI0_CLKENB_MARK,
1981 };
1982 static const unsigned int vin0_clk_pins[] = {
1983 /* VI0_CLK */
1984 RCAR_GP_PIN(2, 0),
1985 };
1986 static const unsigned int vin0_clk_mux[] = {
1987 VI0_CLK_MARK,
1988 };
1989
1990 /* - VIN1 ------------------------------------------------------------------- */
1991 static const unsigned int vin1_data_pins[] = {
1992 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1993 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1994 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1995 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1996 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1997 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1998 };
1999 static const unsigned int vin1_data_mux[] = {
2000 VI1_DATA0_MARK, VI1_DATA1_MARK,
2001 VI1_DATA2_MARK, VI1_DATA3_MARK,
2002 VI1_DATA4_MARK, VI1_DATA5_MARK,
2003 VI1_DATA6_MARK, VI1_DATA7_MARK,
2004 VI1_DATA8_MARK, VI1_DATA9_MARK,
2005 VI1_DATA10_MARK, VI1_DATA11_MARK,
2006 };
2007 static const unsigned int vin1_sync_pins[] = {
2008 /* VI1_VSYNC#, VI1_HSYNC# */
2009 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
2010 };
2011 static const unsigned int vin1_sync_mux[] = {
2012 VI1_VSYNC_N_MARK, VI1_HSYNC_N_MARK,
2013 };
2014 static const unsigned int vin1_field_pins[] = {
2015 /* VI1_FIELD */
2016 RCAR_GP_PIN(3, 16),
2017 };
2018 static const unsigned int vin1_field_mux[] = {
2019 VI1_FIELD_MARK,
2020 };
2021 static const unsigned int vin1_clkenb_pins[] = {
2022 /* VI1_CLKENB */
2023 RCAR_GP_PIN(3, 1),
2024 };
2025 static const unsigned int vin1_clkenb_mux[] = {
2026 VI1_CLKENB_MARK,
2027 };
2028 static const unsigned int vin1_clk_pins[] = {
2029 /* VI1_CLK */
2030 RCAR_GP_PIN(3, 0),
2031 };
2032 static const unsigned int vin1_clk_mux[] = {
2033 VI1_CLK_MARK,
2034 };
2035
2036 static const struct sh_pfc_pin_group pinmux_groups[] = {
2037 SH_PFC_PIN_GROUP(avb_link),
2038 SH_PFC_PIN_GROUP(avb_magic),
2039 SH_PFC_PIN_GROUP(avb_phy_int),
2040 SH_PFC_PIN_GROUP(avb_mdio),
2041 SH_PFC_PIN_GROUP(avb_rgmii),
2042 SH_PFC_PIN_GROUP(avb_txcrefclk),
2043 SH_PFC_PIN_GROUP(avb_avtp_pps),
2044 SH_PFC_PIN_GROUP(avb_avtp_capture),
2045 SH_PFC_PIN_GROUP(avb_avtp_match),
2046 SH_PFC_PIN_GROUP(canfd0_data_a),
2047 SH_PFC_PIN_GROUP(canfd0_data_b),
2048 SH_PFC_PIN_GROUP(canfd1_data),
2049 SH_PFC_PIN_GROUP(canfd_clk_a),
2050 SH_PFC_PIN_GROUP(canfd_clk_b),
2051 SH_PFC_PIN_GROUP(du_rgb666),
2052 SH_PFC_PIN_GROUP(du_rgb888),
2053 SH_PFC_PIN_GROUP(du_clk_out),
2054 SH_PFC_PIN_GROUP(du_sync),
2055 SH_PFC_PIN_GROUP(du_oddf),
2056 SH_PFC_PIN_GROUP(du_cde),
2057 SH_PFC_PIN_GROUP(du_disp),
2058 SH_PFC_PIN_GROUP(gether_link_a),
2059 SH_PFC_PIN_GROUP(gether_phy_int_a),
2060 SH_PFC_PIN_GROUP(gether_mdio_a),
2061 SH_PFC_PIN_GROUP(gether_link_b),
2062 SH_PFC_PIN_GROUP(gether_phy_int_b),
2063 SH_PFC_PIN_GROUP(gether_mdio_b),
2064 SH_PFC_PIN_GROUP(gether_magic),
2065 SH_PFC_PIN_GROUP(gether_rgmii),
2066 SH_PFC_PIN_GROUP(gether_txcrefclk),
2067 SH_PFC_PIN_GROUP(gether_txcrefclk_mega),
2068 SH_PFC_PIN_GROUP(gether_rmii),
2069 SH_PFC_PIN_GROUP(hscif0_data_a),
2070 SH_PFC_PIN_GROUP(hscif0_clk_a),
2071 SH_PFC_PIN_GROUP(hscif0_ctrl_a),
2072 SH_PFC_PIN_GROUP(hscif0_data_b),
2073 SH_PFC_PIN_GROUP(hscif0_clk_b),
2074 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
2075 SH_PFC_PIN_GROUP(hscif1_data),
2076 SH_PFC_PIN_GROUP(hscif1_clk),
2077 SH_PFC_PIN_GROUP(hscif1_ctrl),
2078 SH_PFC_PIN_GROUP(hscif2_data),
2079 SH_PFC_PIN_GROUP(hscif2_clk),
2080 SH_PFC_PIN_GROUP(hscif2_ctrl),
2081 SH_PFC_PIN_GROUP(hscif3_data),
2082 SH_PFC_PIN_GROUP(hscif3_clk),
2083 SH_PFC_PIN_GROUP(hscif3_ctrl),
2084 SH_PFC_PIN_GROUP(i2c0),
2085 SH_PFC_PIN_GROUP(i2c1),
2086 SH_PFC_PIN_GROUP(i2c2),
2087 SH_PFC_PIN_GROUP(i2c3),
2088 SH_PFC_PIN_GROUP(i2c4),
2089 SH_PFC_PIN_GROUP(i2c5),
2090 SH_PFC_PIN_GROUP(intc_ex_irq0),
2091 SH_PFC_PIN_GROUP(intc_ex_irq1),
2092 SH_PFC_PIN_GROUP(intc_ex_irq2),
2093 SH_PFC_PIN_GROUP(intc_ex_irq3),
2094 SH_PFC_PIN_GROUP(intc_ex_irq4),
2095 SH_PFC_PIN_GROUP(intc_ex_irq5),
2096 BUS_DATA_PIN_GROUP(mmc_data, 1),
2097 BUS_DATA_PIN_GROUP(mmc_data, 4),
2098 BUS_DATA_PIN_GROUP(mmc_data, 8),
2099 SH_PFC_PIN_GROUP(mmc_ctrl),
2100 SH_PFC_PIN_GROUP(mmc_cd),
2101 SH_PFC_PIN_GROUP(mmc_wp),
2102 SH_PFC_PIN_GROUP(mmc_ds),
2103 SH_PFC_PIN_GROUP(msiof0_clk),
2104 SH_PFC_PIN_GROUP(msiof0_sync),
2105 SH_PFC_PIN_GROUP(msiof0_ss1),
2106 SH_PFC_PIN_GROUP(msiof0_ss2),
2107 SH_PFC_PIN_GROUP(msiof0_txd),
2108 SH_PFC_PIN_GROUP(msiof0_rxd),
2109 SH_PFC_PIN_GROUP(msiof1_clk),
2110 SH_PFC_PIN_GROUP(msiof1_sync),
2111 SH_PFC_PIN_GROUP(msiof1_ss1),
2112 SH_PFC_PIN_GROUP(msiof1_ss2),
2113 SH_PFC_PIN_GROUP(msiof1_txd),
2114 SH_PFC_PIN_GROUP(msiof1_rxd),
2115 SH_PFC_PIN_GROUP(msiof2_clk),
2116 SH_PFC_PIN_GROUP(msiof2_sync),
2117 SH_PFC_PIN_GROUP(msiof2_ss1),
2118 SH_PFC_PIN_GROUP(msiof2_ss2),
2119 SH_PFC_PIN_GROUP(msiof2_txd),
2120 SH_PFC_PIN_GROUP(msiof2_rxd),
2121 SH_PFC_PIN_GROUP(msiof3_clk),
2122 SH_PFC_PIN_GROUP(msiof3_sync),
2123 SH_PFC_PIN_GROUP(msiof3_ss1),
2124 SH_PFC_PIN_GROUP(msiof3_ss2),
2125 SH_PFC_PIN_GROUP(msiof3_txd),
2126 SH_PFC_PIN_GROUP(msiof3_rxd),
2127 SH_PFC_PIN_GROUP(pwm0_a),
2128 SH_PFC_PIN_GROUP(pwm0_b),
2129 SH_PFC_PIN_GROUP(pwm1_a),
2130 SH_PFC_PIN_GROUP(pwm1_b),
2131 SH_PFC_PIN_GROUP(pwm2_a),
2132 SH_PFC_PIN_GROUP(pwm2_b),
2133 SH_PFC_PIN_GROUP(pwm3_a),
2134 SH_PFC_PIN_GROUP(pwm3_b),
2135 SH_PFC_PIN_GROUP(pwm4_a),
2136 SH_PFC_PIN_GROUP(pwm4_b),
2137 SH_PFC_PIN_GROUP(qspi0_ctrl),
2138 SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
2139 SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
2140 SH_PFC_PIN_GROUP(qspi1_ctrl),
2141 SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
2142 SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
2143 BUS_DATA_PIN_GROUP(rpc_clk, 1),
2144 BUS_DATA_PIN_GROUP(rpc_clk, 2),
2145 SH_PFC_PIN_GROUP(rpc_ctrl),
2146 SH_PFC_PIN_GROUP(rpc_data),
2147 SH_PFC_PIN_GROUP(rpc_reset),
2148 SH_PFC_PIN_GROUP(rpc_int),
2149 SH_PFC_PIN_GROUP(rpc_wp),
2150 SH_PFC_PIN_GROUP(scif0_data),
2151 SH_PFC_PIN_GROUP(scif0_clk),
2152 SH_PFC_PIN_GROUP(scif0_ctrl),
2153 SH_PFC_PIN_GROUP(scif1_data_a),
2154 SH_PFC_PIN_GROUP(scif1_clk),
2155 SH_PFC_PIN_GROUP(scif1_ctrl),
2156 SH_PFC_PIN_GROUP(scif1_data_b),
2157 SH_PFC_PIN_GROUP(scif3_data),
2158 SH_PFC_PIN_GROUP(scif3_clk),
2159 SH_PFC_PIN_GROUP(scif3_ctrl),
2160 SH_PFC_PIN_GROUP(scif4_data),
2161 SH_PFC_PIN_GROUP(scif4_clk),
2162 SH_PFC_PIN_GROUP(scif4_ctrl),
2163 SH_PFC_PIN_GROUP(scif_clk_a),
2164 SH_PFC_PIN_GROUP(scif_clk_b),
2165 SH_PFC_PIN_GROUP(tmu_tclk1_a),
2166 SH_PFC_PIN_GROUP(tmu_tclk1_b),
2167 SH_PFC_PIN_GROUP(tmu_tclk2_a),
2168 SH_PFC_PIN_GROUP(tmu_tclk2_b),
2169 SH_PFC_PIN_GROUP(tpu_to0),
2170 SH_PFC_PIN_GROUP(tpu_to1),
2171 SH_PFC_PIN_GROUP(tpu_to2),
2172 SH_PFC_PIN_GROUP(tpu_to3),
2173 BUS_DATA_PIN_GROUP(vin0_data, 8),
2174 BUS_DATA_PIN_GROUP(vin0_data, 10),
2175 BUS_DATA_PIN_GROUP(vin0_data, 12),
2176 BUS_DATA_PIN_GROUP(vin0_data, 16),
2177 SH_PFC_PIN_GROUP(vin0_data18),
2178 BUS_DATA_PIN_GROUP(vin0_data, 20),
2179 BUS_DATA_PIN_GROUP(vin0_data, 24),
2180 SH_PFC_PIN_GROUP(vin0_sync),
2181 SH_PFC_PIN_GROUP(vin0_field),
2182 SH_PFC_PIN_GROUP(vin0_clkenb),
2183 SH_PFC_PIN_GROUP(vin0_clk),
2184 BUS_DATA_PIN_GROUP(vin1_data, 8),
2185 BUS_DATA_PIN_GROUP(vin1_data, 10),
2186 BUS_DATA_PIN_GROUP(vin1_data, 12),
2187 SH_PFC_PIN_GROUP(vin1_sync),
2188 SH_PFC_PIN_GROUP(vin1_field),
2189 SH_PFC_PIN_GROUP(vin1_clkenb),
2190 SH_PFC_PIN_GROUP(vin1_clk),
2191 };
2192
2193 static const char * const avb_groups[] = {
2194 "avb_link",
2195 "avb_magic",
2196 "avb_phy_int",
2197 "avb_mdio",
2198 "avb_rgmii",
2199 "avb_txcrefclk",
2200 "avb_avtp_pps",
2201 "avb_avtp_capture",
2202 "avb_avtp_match",
2203 };
2204
2205 static const char * const canfd0_groups[] = {
2206 "canfd0_data_a",
2207 "canfd0_data_b",
2208 };
2209
2210 static const char * const canfd1_groups[] = {
2211 "canfd1_data",
2212 };
2213
2214 static const char * const canfd_clk_groups[] = {
2215 "canfd_clk_a",
2216 "canfd_clk_b",
2217 };
2218
2219 static const char * const du_groups[] = {
2220 "du_rgb666",
2221 "du_rgb888",
2222 "du_clk_out",
2223 "du_sync",
2224 "du_oddf",
2225 "du_cde",
2226 "du_disp",
2227 };
2228
2229 static const char * const gether_groups[] = {
2230 "gether_link_a",
2231 "gether_phy_int_a",
2232 "gether_mdio_a",
2233 "gether_link_b",
2234 "gether_phy_int_b",
2235 "gether_mdio_b",
2236 "gether_magic",
2237 "gether_rgmii",
2238 "gether_txcrefclk",
2239 "gether_txcrefclk_mega",
2240 "gether_rmii",
2241 };
2242
2243 static const char * const hscif0_groups[] = {
2244 "hscif0_data_a",
2245 "hscif0_clk_a",
2246 "hscif0_ctrl_a",
2247 "hscif0_data_b",
2248 "hscif0_clk_b",
2249 "hscif0_ctrl_b",
2250 };
2251
2252 static const char * const hscif1_groups[] = {
2253 "hscif1_data",
2254 "hscif1_clk",
2255 "hscif1_ctrl",
2256 };
2257
2258 static const char * const hscif2_groups[] = {
2259 "hscif2_data",
2260 "hscif2_clk",
2261 "hscif2_ctrl",
2262 };
2263
2264 static const char * const hscif3_groups[] = {
2265 "hscif3_data",
2266 "hscif3_clk",
2267 "hscif3_ctrl",
2268 };
2269
2270 static const char * const i2c0_groups[] = {
2271 "i2c0",
2272 };
2273
2274 static const char * const i2c1_groups[] = {
2275 "i2c1",
2276 };
2277
2278 static const char * const i2c2_groups[] = {
2279 "i2c2",
2280 };
2281
2282 static const char * const i2c3_groups[] = {
2283 "i2c3",
2284 };
2285
2286 static const char * const i2c4_groups[] = {
2287 "i2c4",
2288 };
2289
2290 static const char * const i2c5_groups[] = {
2291 "i2c5",
2292 };
2293
2294 static const char * const intc_ex_groups[] = {
2295 "intc_ex_irq0",
2296 "intc_ex_irq1",
2297 "intc_ex_irq2",
2298 "intc_ex_irq3",
2299 "intc_ex_irq4",
2300 "intc_ex_irq5",
2301 };
2302
2303 static const char * const mmc_groups[] = {
2304 "mmc_data1",
2305 "mmc_data4",
2306 "mmc_data8",
2307 "mmc_ctrl",
2308 "mmc_cd",
2309 "mmc_wp",
2310 "mmc_ds",
2311 };
2312
2313 static const char * const msiof0_groups[] = {
2314 "msiof0_clk",
2315 "msiof0_sync",
2316 "msiof0_ss1",
2317 "msiof0_ss2",
2318 "msiof0_txd",
2319 "msiof0_rxd",
2320 };
2321
2322 static const char * const msiof1_groups[] = {
2323 "msiof1_clk",
2324 "msiof1_sync",
2325 "msiof1_ss1",
2326 "msiof1_ss2",
2327 "msiof1_txd",
2328 "msiof1_rxd",
2329 };
2330
2331 static const char * const msiof2_groups[] = {
2332 "msiof2_clk",
2333 "msiof2_sync",
2334 "msiof2_ss1",
2335 "msiof2_ss2",
2336 "msiof2_txd",
2337 "msiof2_rxd",
2338 };
2339
2340 static const char * const msiof3_groups[] = {
2341 "msiof3_clk",
2342 "msiof3_sync",
2343 "msiof3_ss1",
2344 "msiof3_ss2",
2345 "msiof3_txd",
2346 "msiof3_rxd",
2347 };
2348
2349 static const char * const pwm0_groups[] = {
2350 "pwm0_a",
2351 "pwm0_b",
2352 };
2353
2354 static const char * const pwm1_groups[] = {
2355 "pwm1_a",
2356 "pwm1_b",
2357 };
2358
2359 static const char * const pwm2_groups[] = {
2360 "pwm2_a",
2361 "pwm2_b",
2362 };
2363
2364 static const char * const pwm3_groups[] = {
2365 "pwm3_a",
2366 "pwm3_b",
2367 };
2368
2369 static const char * const pwm4_groups[] = {
2370 "pwm4_a",
2371 "pwm4_b",
2372 };
2373
2374 static const char * const qspi0_groups[] = {
2375 "qspi0_ctrl",
2376 "qspi0_data2",
2377 "qspi0_data4",
2378 };
2379
2380 static const char * const qspi1_groups[] = {
2381 "qspi1_ctrl",
2382 "qspi1_data2",
2383 "qspi1_data4",
2384 };
2385
2386 static const char * const rpc_groups[] = {
2387 "rpc_clk1",
2388 "rpc_clk2",
2389 "rpc_ctrl",
2390 "rpc_data",
2391 "rpc_reset",
2392 "rpc_int",
2393 "rpc_wp",
2394 };
2395
2396 static const char * const scif0_groups[] = {
2397 "scif0_data",
2398 "scif0_clk",
2399 "scif0_ctrl",
2400 };
2401
2402 static const char * const scif1_groups[] = {
2403 "scif1_data_a",
2404 "scif1_clk",
2405 "scif1_ctrl",
2406 "scif1_data_b",
2407 };
2408
2409 static const char * const scif3_groups[] = {
2410 "scif3_data",
2411 "scif3_clk",
2412 "scif3_ctrl",
2413 };
2414
2415 static const char * const scif4_groups[] = {
2416 "scif4_data",
2417 "scif4_clk",
2418 "scif4_ctrl",
2419 };
2420
2421 static const char * const scif_clk_groups[] = {
2422 "scif_clk_a",
2423 "scif_clk_b",
2424 };
2425
2426 static const char * const tmu_groups[] = {
2427 "tmu_tclk1_a",
2428 "tmu_tclk1_b",
2429 "tmu_tclk2_a",
2430 "tmu_tclk2_b",
2431 };
2432
2433 static const char * const tpu_groups[] = {
2434 "tpu_to0",
2435 "tpu_to1",
2436 "tpu_to2",
2437 "tpu_to3",
2438 };
2439
2440 static const char * const vin0_groups[] = {
2441 "vin0_data8",
2442 "vin0_data10",
2443 "vin0_data12",
2444 "vin0_data16",
2445 "vin0_data18",
2446 "vin0_data20",
2447 "vin0_data24",
2448 "vin0_sync",
2449 "vin0_field",
2450 "vin0_clkenb",
2451 "vin0_clk",
2452 };
2453
2454 static const char * const vin1_groups[] = {
2455 "vin1_data8",
2456 "vin1_data10",
2457 "vin1_data12",
2458 "vin1_sync",
2459 "vin1_field",
2460 "vin1_clkenb",
2461 "vin1_clk",
2462 };
2463
2464 static const struct sh_pfc_function pinmux_functions[] = {
2465 SH_PFC_FUNCTION(avb),
2466 SH_PFC_FUNCTION(canfd0),
2467 SH_PFC_FUNCTION(canfd1),
2468 SH_PFC_FUNCTION(canfd_clk),
2469 SH_PFC_FUNCTION(du),
2470 SH_PFC_FUNCTION(gether),
2471 SH_PFC_FUNCTION(hscif0),
2472 SH_PFC_FUNCTION(hscif1),
2473 SH_PFC_FUNCTION(hscif2),
2474 SH_PFC_FUNCTION(hscif3),
2475 SH_PFC_FUNCTION(i2c0),
2476 SH_PFC_FUNCTION(i2c1),
2477 SH_PFC_FUNCTION(i2c2),
2478 SH_PFC_FUNCTION(i2c3),
2479 SH_PFC_FUNCTION(i2c4),
2480 SH_PFC_FUNCTION(i2c5),
2481 SH_PFC_FUNCTION(intc_ex),
2482 SH_PFC_FUNCTION(mmc),
2483 SH_PFC_FUNCTION(msiof0),
2484 SH_PFC_FUNCTION(msiof1),
2485 SH_PFC_FUNCTION(msiof2),
2486 SH_PFC_FUNCTION(msiof3),
2487 SH_PFC_FUNCTION(pwm0),
2488 SH_PFC_FUNCTION(pwm1),
2489 SH_PFC_FUNCTION(pwm2),
2490 SH_PFC_FUNCTION(pwm3),
2491 SH_PFC_FUNCTION(pwm4),
2492 SH_PFC_FUNCTION(qspi0),
2493 SH_PFC_FUNCTION(qspi1),
2494 SH_PFC_FUNCTION(rpc),
2495 SH_PFC_FUNCTION(scif0),
2496 SH_PFC_FUNCTION(scif1),
2497 SH_PFC_FUNCTION(scif3),
2498 SH_PFC_FUNCTION(scif4),
2499 SH_PFC_FUNCTION(scif_clk),
2500 SH_PFC_FUNCTION(tmu),
2501 SH_PFC_FUNCTION(tpu),
2502 SH_PFC_FUNCTION(vin0),
2503 SH_PFC_FUNCTION(vin1),
2504 };
2505
2506 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2507 #define F_(x, y) FN_##y
2508 #define FM(x) FN_##x
2509 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
2510 GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2511 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2512 GROUP(
2513 /* GP0_31_22 RESERVED */
2514 GP_0_21_FN, GPSR0_21,
2515 GP_0_20_FN, GPSR0_20,
2516 GP_0_19_FN, GPSR0_19,
2517 GP_0_18_FN, GPSR0_18,
2518 GP_0_17_FN, GPSR0_17,
2519 GP_0_16_FN, GPSR0_16,
2520 GP_0_15_FN, GPSR0_15,
2521 GP_0_14_FN, GPSR0_14,
2522 GP_0_13_FN, GPSR0_13,
2523 GP_0_12_FN, GPSR0_12,
2524 GP_0_11_FN, GPSR0_11,
2525 GP_0_10_FN, GPSR0_10,
2526 GP_0_9_FN, GPSR0_9,
2527 GP_0_8_FN, GPSR0_8,
2528 GP_0_7_FN, GPSR0_7,
2529 GP_0_6_FN, GPSR0_6,
2530 GP_0_5_FN, GPSR0_5,
2531 GP_0_4_FN, GPSR0_4,
2532 GP_0_3_FN, GPSR0_3,
2533 GP_0_2_FN, GPSR0_2,
2534 GP_0_1_FN, GPSR0_1,
2535 GP_0_0_FN, GPSR0_0, ))
2536 },
2537 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2538 0, 0,
2539 0, 0,
2540 0, 0,
2541 0, 0,
2542 GP_1_27_FN, GPSR1_27,
2543 GP_1_26_FN, GPSR1_26,
2544 GP_1_25_FN, GPSR1_25,
2545 GP_1_24_FN, GPSR1_24,
2546 GP_1_23_FN, GPSR1_23,
2547 GP_1_22_FN, GPSR1_22,
2548 GP_1_21_FN, GPSR1_21,
2549 GP_1_20_FN, GPSR1_20,
2550 GP_1_19_FN, GPSR1_19,
2551 GP_1_18_FN, GPSR1_18,
2552 GP_1_17_FN, GPSR1_17,
2553 GP_1_16_FN, GPSR1_16,
2554 GP_1_15_FN, GPSR1_15,
2555 GP_1_14_FN, GPSR1_14,
2556 GP_1_13_FN, GPSR1_13,
2557 GP_1_12_FN, GPSR1_12,
2558 GP_1_11_FN, GPSR1_11,
2559 GP_1_10_FN, GPSR1_10,
2560 GP_1_9_FN, GPSR1_9,
2561 GP_1_8_FN, GPSR1_8,
2562 GP_1_7_FN, GPSR1_7,
2563 GP_1_6_FN, GPSR1_6,
2564 GP_1_5_FN, GPSR1_5,
2565 GP_1_4_FN, GPSR1_4,
2566 GP_1_3_FN, GPSR1_3,
2567 GP_1_2_FN, GPSR1_2,
2568 GP_1_1_FN, GPSR1_1,
2569 GP_1_0_FN, GPSR1_0, ))
2570 },
2571 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2572 0, 0,
2573 0, 0,
2574 GP_2_29_FN, GPSR2_29,
2575 GP_2_28_FN, GPSR2_28,
2576 GP_2_27_FN, GPSR2_27,
2577 GP_2_26_FN, GPSR2_26,
2578 GP_2_25_FN, GPSR2_25,
2579 GP_2_24_FN, GPSR2_24,
2580 GP_2_23_FN, GPSR2_23,
2581 GP_2_22_FN, GPSR2_22,
2582 GP_2_21_FN, GPSR2_21,
2583 GP_2_20_FN, GPSR2_20,
2584 GP_2_19_FN, GPSR2_19,
2585 GP_2_18_FN, GPSR2_18,
2586 GP_2_17_FN, GPSR2_17,
2587 GP_2_16_FN, GPSR2_16,
2588 GP_2_15_FN, GPSR2_15,
2589 GP_2_14_FN, GPSR2_14,
2590 GP_2_13_FN, GPSR2_13,
2591 GP_2_12_FN, GPSR2_12,
2592 GP_2_11_FN, GPSR2_11,
2593 GP_2_10_FN, GPSR2_10,
2594 GP_2_9_FN, GPSR2_9,
2595 GP_2_8_FN, GPSR2_8,
2596 GP_2_7_FN, GPSR2_7,
2597 GP_2_6_FN, GPSR2_6,
2598 GP_2_5_FN, GPSR2_5,
2599 GP_2_4_FN, GPSR2_4,
2600 GP_2_3_FN, GPSR2_3,
2601 GP_2_2_FN, GPSR2_2,
2602 GP_2_1_FN, GPSR2_1,
2603 GP_2_0_FN, GPSR2_0, ))
2604 },
2605 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
2606 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2607 1, 1, 1, 1, 1, 1),
2608 GROUP(
2609 /* GP3_31_17 RESERVED */
2610 GP_3_16_FN, GPSR3_16,
2611 GP_3_15_FN, GPSR3_15,
2612 GP_3_14_FN, GPSR3_14,
2613 GP_3_13_FN, GPSR3_13,
2614 GP_3_12_FN, GPSR3_12,
2615 GP_3_11_FN, GPSR3_11,
2616 GP_3_10_FN, GPSR3_10,
2617 GP_3_9_FN, GPSR3_9,
2618 GP_3_8_FN, GPSR3_8,
2619 GP_3_7_FN, GPSR3_7,
2620 GP_3_6_FN, GPSR3_6,
2621 GP_3_5_FN, GPSR3_5,
2622 GP_3_4_FN, GPSR3_4,
2623 GP_3_3_FN, GPSR3_3,
2624 GP_3_2_FN, GPSR3_2,
2625 GP_3_1_FN, GPSR3_1,
2626 GP_3_0_FN, GPSR3_0, ))
2627 },
2628 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
2629 GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2630 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2631 1, 1),
2632 GROUP(
2633 /* GP4_31_25 RESERVED */
2634 GP_4_24_FN, GPSR4_24,
2635 GP_4_23_FN, GPSR4_23,
2636 GP_4_22_FN, GPSR4_22,
2637 GP_4_21_FN, GPSR4_21,
2638 GP_4_20_FN, GPSR4_20,
2639 GP_4_19_FN, GPSR4_19,
2640 GP_4_18_FN, GPSR4_18,
2641 GP_4_17_FN, GPSR4_17,
2642 GP_4_16_FN, GPSR4_16,
2643 GP_4_15_FN, GPSR4_15,
2644 GP_4_14_FN, GPSR4_14,
2645 GP_4_13_FN, GPSR4_13,
2646 GP_4_12_FN, GPSR4_12,
2647 GP_4_11_FN, GPSR4_11,
2648 GP_4_10_FN, GPSR4_10,
2649 GP_4_9_FN, GPSR4_9,
2650 GP_4_8_FN, GPSR4_8,
2651 GP_4_7_FN, GPSR4_7,
2652 GP_4_6_FN, GPSR4_6,
2653 GP_4_5_FN, GPSR4_5,
2654 GP_4_4_FN, GPSR4_4,
2655 GP_4_3_FN, GPSR4_3,
2656 GP_4_2_FN, GPSR4_2,
2657 GP_4_1_FN, GPSR4_1,
2658 GP_4_0_FN, GPSR4_0, ))
2659 },
2660 { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
2661 GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2662 1, 1, 1, 1),
2663 GROUP(
2664 /* GP5_31_15 RESERVED */
2665 GP_5_14_FN, GPSR5_14,
2666 GP_5_13_FN, GPSR5_13,
2667 GP_5_12_FN, GPSR5_12,
2668 GP_5_11_FN, GPSR5_11,
2669 GP_5_10_FN, GPSR5_10,
2670 GP_5_9_FN, GPSR5_9,
2671 GP_5_8_FN, GPSR5_8,
2672 GP_5_7_FN, GPSR5_7,
2673 GP_5_6_FN, GPSR5_6,
2674 GP_5_5_FN, GPSR5_5,
2675 GP_5_4_FN, GPSR5_4,
2676 GP_5_3_FN, GPSR5_3,
2677 GP_5_2_FN, GPSR5_2,
2678 GP_5_1_FN, GPSR5_1,
2679 GP_5_0_FN, GPSR5_0, ))
2680 },
2681 #undef F_
2682 #undef FM
2683
2684 #define F_(x, y) x,
2685 #define FM(x) FN_##x,
2686 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2687 IP0_31_28
2688 IP0_27_24
2689 IP0_23_20
2690 IP0_19_16
2691 IP0_15_12
2692 IP0_11_8
2693 IP0_7_4
2694 IP0_3_0 ))
2695 },
2696 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2697 IP1_31_28
2698 IP1_27_24
2699 IP1_23_20
2700 IP1_19_16
2701 IP1_15_12
2702 IP1_11_8
2703 IP1_7_4
2704 IP1_3_0 ))
2705 },
2706 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2707 IP2_31_28
2708 IP2_27_24
2709 IP2_23_20
2710 IP2_19_16
2711 IP2_15_12
2712 IP2_11_8
2713 IP2_7_4
2714 IP2_3_0 ))
2715 },
2716 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2717 IP3_31_28
2718 IP3_27_24
2719 IP3_23_20
2720 IP3_19_16
2721 IP3_15_12
2722 IP3_11_8
2723 IP3_7_4
2724 IP3_3_0 ))
2725 },
2726 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2727 IP4_31_28
2728 IP4_27_24
2729 IP4_23_20
2730 IP4_19_16
2731 IP4_15_12
2732 IP4_11_8
2733 IP4_7_4
2734 IP4_3_0 ))
2735 },
2736 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2737 IP5_31_28
2738 IP5_27_24
2739 IP5_23_20
2740 IP5_19_16
2741 IP5_15_12
2742 IP5_11_8
2743 IP5_7_4
2744 IP5_3_0 ))
2745 },
2746 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2747 IP6_31_28
2748 IP6_27_24
2749 IP6_23_20
2750 IP6_19_16
2751 IP6_15_12
2752 IP6_11_8
2753 IP6_7_4
2754 IP6_3_0 ))
2755 },
2756 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2757 IP7_31_28
2758 IP7_27_24
2759 IP7_23_20
2760 IP7_19_16
2761 IP7_15_12
2762 IP7_11_8
2763 IP7_7_4
2764 IP7_3_0 ))
2765 },
2766 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
2767 IP8_31_28
2768 IP8_27_24
2769 IP8_23_20
2770 IP8_19_16
2771 IP8_15_12
2772 IP8_11_8
2773 IP8_7_4
2774 IP8_3_0 ))
2775 },
2776 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
2777 IP9_31_28
2778 IP9_27_24
2779 IP9_23_20
2780 IP9_19_16
2781 IP9_15_12
2782 IP9_11_8
2783 IP9_7_4
2784 IP9_3_0 ))
2785 },
2786 { PINMUX_CFG_REG_VAR("IPSR10", 0xe6060228, 32,
2787 GROUP(-12, 4, 4, 4, 4, 4),
2788 GROUP(
2789 /* IP10_31_20 RESERVED */
2790 IP10_19_16
2791 IP10_15_12
2792 IP10_11_8
2793 IP10_7_4
2794 IP10_3_0 ))
2795 },
2796 #undef F_
2797 #undef FM
2798
2799 #define F_(x, y) x,
2800 #define FM(x) FN_##x,
2801 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2802 GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, -1, 1, 1, 1),
2803 GROUP(
2804 /* RESERVED 31-12 */
2805 MOD_SEL0_11
2806 MOD_SEL0_10
2807 MOD_SEL0_9
2808 MOD_SEL0_8
2809 MOD_SEL0_7
2810 MOD_SEL0_6
2811 MOD_SEL0_5
2812 MOD_SEL0_4
2813 /* RESERVED 3 */
2814 MOD_SEL0_2
2815 MOD_SEL0_1
2816 MOD_SEL0_0 ))
2817 },
2818 { /* sentinel */ }
2819 };
2820
2821 enum ioctrl_regs {
2822 POCCTRL0,
2823 POCCTRL1,
2824 POCCTRL2,
2825 POCCTRL3,
2826 TDSELCTRL,
2827 };
2828
2829 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2830 [POCCTRL0] = { 0xe6060380, },
2831 [POCCTRL1] = { 0xe6060384, },
2832 [POCCTRL2] = { 0xe6060388, },
2833 [POCCTRL3] = { 0xe606038c, },
2834 [TDSELCTRL] = { 0xe60603c0, },
2835 { /* sentinel */ }
2836 };
2837
2838 static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
2839 {
2840 int bit = pin & 0x1f;
2841
2842 switch (pin) {
2843 case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21):
2844 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
2845 return bit;
2846
2847 case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9):
2848 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
2849 return bit + 22;
2850
2851 case RCAR_GP_PIN(2, 10) ... RCAR_GP_PIN(2, 16):
2852 *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
2853 return bit - 10;
2854
2855 case RCAR_GP_PIN(2, 17) ... RCAR_GP_PIN(2, 24):
2856 case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 16):
2857 *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
2858 return bit + 7;
2859
2860 case RCAR_GP_PIN(2, 25) ... RCAR_GP_PIN(2, 29):
2861 *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
2862 return pin - 25;
2863
2864 case PIN_VDDQ_AVB:
2865 *pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
2866 return 0;
2867
2868 case PIN_VDDQ_GE:
2869 *pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
2870 return 1;
2871
2872 default:
2873 return -EINVAL;
2874 }
2875 }
2876
2877 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
2878 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
2879 [ 0] = RCAR_GP_PIN(0, 0), /* DU_DR2 */
2880 [ 1] = RCAR_GP_PIN(0, 1), /* DU_DR3 */
2881 [ 2] = RCAR_GP_PIN(0, 2), /* DU_DR4 */
2882 [ 3] = RCAR_GP_PIN(0, 3), /* DU_DR5 */
2883 [ 4] = RCAR_GP_PIN(0, 4), /* DU_DR6 */
2884 [ 5] = RCAR_GP_PIN(0, 5), /* DU_DR7 */
2885 [ 6] = RCAR_GP_PIN(0, 6), /* DU_DG2 */
2886 [ 7] = RCAR_GP_PIN(0, 7), /* DU_DG3 */
2887 [ 8] = RCAR_GP_PIN(0, 8), /* DU_DG4 */
2888 [ 9] = RCAR_GP_PIN(0, 9), /* DU_DG5 */
2889 [10] = RCAR_GP_PIN(0, 10), /* DU_DG6 */
2890 [11] = RCAR_GP_PIN(0, 11), /* DU_DG7 */
2891 [12] = RCAR_GP_PIN(0, 12), /* DU_DB2 */
2892 [13] = RCAR_GP_PIN(0, 13), /* DU_DB3 */
2893 [14] = RCAR_GP_PIN(0, 14), /* DU_DB4 */
2894 [15] = RCAR_GP_PIN(0, 15), /* DU_DB5 */
2895 [16] = RCAR_GP_PIN(0, 16), /* DU_DB6 */
2896 [17] = RCAR_GP_PIN(0, 17), /* DU_DB7 */
2897 [18] = RCAR_GP_PIN(0, 18), /* DU_DOTCLKOUT */
2898 [19] = RCAR_GP_PIN(0, 19), /* DU_EXHSYNC/DU_HSYNC */
2899 [20] = RCAR_GP_PIN(0, 20), /* DU_EXVSYNC/DU_VSYNC */
2900 [21] = RCAR_GP_PIN(0, 21), /* DU_EXODDF/DU_ODDF/DISP/CDE */
2901 [22] = SH_PFC_PIN_NONE,
2902 [23] = SH_PFC_PIN_NONE,
2903 [24] = PIN_DU_DOTCLKIN, /* DU_DOTCLKIN */
2904 [25] = SH_PFC_PIN_NONE,
2905 [26] = PIN_PRESETOUT_N, /* PRESETOUT# */
2906 [27] = SH_PFC_PIN_NONE,
2907 [28] = SH_PFC_PIN_NONE,
2908 [29] = SH_PFC_PIN_NONE,
2909 [30] = PIN_EXTALR, /* EXTALR */
2910 [31] = PIN_FSCLKST_N, /* FSCLKST# */
2911 } },
2912 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
2913 [ 0] = PIN_FSCLKST, /* FSCLKST */
2914 [ 1] = SH_PFC_PIN_NONE,
2915 [ 2] = RCAR_GP_PIN(1, 0), /* IRQ0 */
2916 [ 3] = PIN_DCUTRST_N, /* DCUTRST# */
2917 [ 4] = PIN_DCUTCK_LPDCLK, /* DCUTCK_LPDCLK */
2918 [ 5] = PIN_DCUTMS, /* DCUTMS */
2919 [ 6] = PIN_DCUTDI_LPDI, /* DCUTDI_LPDI */
2920 [ 7] = SH_PFC_PIN_NONE,
2921 [ 8] = RCAR_GP_PIN(2, 0), /* VI0_CLK */
2922 [ 9] = RCAR_GP_PIN(2, 1), /* VI0_CLKENB */
2923 [10] = RCAR_GP_PIN(2, 2), /* VI0_HSYNC# */
2924 [11] = RCAR_GP_PIN(2, 3), /* VI0_VSYNC# */
2925 [12] = RCAR_GP_PIN(2, 4), /* VI0_DATA0 */
2926 [13] = RCAR_GP_PIN(2, 5), /* VI0_DATA1 */
2927 [14] = RCAR_GP_PIN(2, 6), /* VI0_DATA2 */
2928 [15] = RCAR_GP_PIN(2, 7), /* VI0_DATA3 */
2929 [16] = RCAR_GP_PIN(2, 8), /* VI0_DATA4 */
2930 [17] = RCAR_GP_PIN(2, 9), /* VI0_DATA5 */
2931 [18] = RCAR_GP_PIN(2, 10), /* VI0_DATA6 */
2932 [19] = RCAR_GP_PIN(2, 11), /* VI0_DATA7 */
2933 [20] = RCAR_GP_PIN(2, 12), /* VI0_DATA8 */
2934 [21] = RCAR_GP_PIN(2, 13), /* VI0_DATA9 */
2935 [22] = RCAR_GP_PIN(2, 14), /* VI0_DATA10 */
2936 [23] = RCAR_GP_PIN(2, 15), /* VI0_DATA11 */
2937 [24] = RCAR_GP_PIN(2, 16), /* VI0_FIELD */
2938 [25] = RCAR_GP_PIN(3, 0), /* VI1_CLK */
2939 [26] = RCAR_GP_PIN(3, 1), /* VI1_CLKENB */
2940 [27] = RCAR_GP_PIN(3, 2), /* VI1_HSYNC# */
2941 [28] = RCAR_GP_PIN(3, 3), /* VI1_VSYNC# */
2942 [29] = RCAR_GP_PIN(3, 4), /* VI1_DATA0 */
2943 [30] = RCAR_GP_PIN(3, 5), /* VI1_DATA1 */
2944 [31] = RCAR_GP_PIN(3, 6), /* VI1_DATA2 */
2945 } },
2946 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
2947 [ 0] = RCAR_GP_PIN(3, 7), /* VI1_DATA3 */
2948 [ 1] = RCAR_GP_PIN(3, 8), /* VI1_DATA4 */
2949 [ 2] = RCAR_GP_PIN(3, 9), /* VI1_DATA5 */
2950 [ 3] = RCAR_GP_PIN(3, 10), /* VI1_DATA6 */
2951 [ 4] = RCAR_GP_PIN(3, 11), /* VI1_DATA7 */
2952 [ 5] = RCAR_GP_PIN(3, 12), /* VI1_DATA8 */
2953 [ 6] = RCAR_GP_PIN(3, 13), /* VI1_DATA9 */
2954 [ 7] = RCAR_GP_PIN(3, 14), /* VI1_DATA10 */
2955 [ 8] = RCAR_GP_PIN(3, 15), /* VI1_DATA11 */
2956 [ 9] = RCAR_GP_PIN(3, 16), /* VI1_FIELD */
2957 [10] = RCAR_GP_PIN(4, 0), /* SCL0 */
2958 [11] = RCAR_GP_PIN(4, 1), /* SDA0 */
2959 [12] = RCAR_GP_PIN(4, 2), /* SCL1 */
2960 [13] = RCAR_GP_PIN(4, 3), /* SDA1 */
2961 [14] = RCAR_GP_PIN(4, 4), /* SCL2 */
2962 [15] = RCAR_GP_PIN(4, 5), /* SDA2 */
2963 [16] = RCAR_GP_PIN(1, 1), /* AVB_RX_CTL */
2964 [17] = RCAR_GP_PIN(1, 2), /* AVB_RXC */
2965 [18] = RCAR_GP_PIN(1, 3), /* AVB_RD0 */
2966 [19] = RCAR_GP_PIN(1, 4), /* AVB_RD1 */
2967 [20] = RCAR_GP_PIN(1, 5), /* AVB_RD2 */
2968 [21] = RCAR_GP_PIN(1, 6), /* AVB_RD3 */
2969 [22] = RCAR_GP_PIN(1, 7), /* AVB_TX_CTL */
2970 [23] = RCAR_GP_PIN(1, 8), /* AVB_TXC */
2971 [24] = RCAR_GP_PIN(1, 9), /* AVB_TD0 */
2972 [25] = RCAR_GP_PIN(1, 10), /* AVB_TD1 */
2973 [26] = RCAR_GP_PIN(1, 11), /* AVB_TD2 */
2974 [27] = RCAR_GP_PIN(1, 12), /* AVB_TD3 */
2975 [28] = RCAR_GP_PIN(1, 13), /* AVB_TXCREFCLK */
2976 [29] = RCAR_GP_PIN(1, 14), /* AVB_MDIO */
2977 [30] = RCAR_GP_PIN(1, 15), /* AVB_MDC */
2978 [31] = RCAR_GP_PIN(1, 16), /* AVB_MAGIC */
2979 } },
2980 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
2981 [ 0] = RCAR_GP_PIN(1, 17), /* AVB_PHY_INT */
2982 [ 1] = RCAR_GP_PIN(1, 18), /* AVB_LINK */
2983 [ 2] = RCAR_GP_PIN(1, 19), /* AVB_AVTP_MATCH */
2984 [ 3] = RCAR_GP_PIN(1, 20), /* AVTP_CAPTURE */
2985 [ 4] = RCAR_GP_PIN(4, 6), /* GETHER_RX_CTL */
2986 [ 5] = RCAR_GP_PIN(4, 7), /* GETHER_RXC */
2987 [ 6] = RCAR_GP_PIN(4, 8), /* GETHER_RD0 */
2988 [ 7] = RCAR_GP_PIN(4, 9), /* GETHER_RD1 */
2989 [ 8] = RCAR_GP_PIN(4, 10), /* GETHER_RD2 */
2990 [ 9] = RCAR_GP_PIN(4, 11), /* GETHER_RD3 */
2991 [10] = RCAR_GP_PIN(4, 12), /* GETHER_TX_CTL */
2992 [11] = RCAR_GP_PIN(4, 13), /* GETHER_TXC */
2993 [12] = RCAR_GP_PIN(4, 14), /* GETHER_TD0 */
2994 [13] = RCAR_GP_PIN(4, 15), /* GETHER_TD1 */
2995 [14] = RCAR_GP_PIN(4, 16), /* GETHER_TD2 */
2996 [15] = RCAR_GP_PIN(4, 17), /* GETHER_TD3 */
2997 [16] = RCAR_GP_PIN(4, 18), /* GETHER_TXCREFCLK */
2998 [17] = RCAR_GP_PIN(4, 19), /* GETHER_TXCREFCLK_MEGA */
2999 [18] = RCAR_GP_PIN(4, 20), /* GETHER_MDIO_A */
3000 [19] = RCAR_GP_PIN(4, 21), /* GETHER_MDC_A */
3001 [20] = RCAR_GP_PIN(4, 22), /* GETHER_MAGIC */
3002 [21] = RCAR_GP_PIN(4, 23), /* GETHER_PHY_INT_A */
3003 [22] = RCAR_GP_PIN(4, 24), /* GETHER_LINK_A */
3004 [23] = RCAR_GP_PIN(1, 21), /* CANFD0_TX_A */
3005 [24] = RCAR_GP_PIN(1, 22), /* CANFD0_RX_A */
3006 [25] = RCAR_GP_PIN(1, 23), /* CANFD1_TX */
3007 [26] = RCAR_GP_PIN(1, 24), /* CANFD1_RX */
3008 [27] = RCAR_GP_PIN(1, 25), /* CAN_CLK_A */
3009 [28] = RCAR_GP_PIN(5, 0), /* QSPI0_SPCLK */
3010 [29] = RCAR_GP_PIN(5, 1), /* QSPI0_MOSI_IO0 */
3011 [30] = RCAR_GP_PIN(5, 2), /* QSPI0_MISO_IO1 */
3012 [31] = RCAR_GP_PIN(5, 3), /* QSPI0_IO2 */
3013 } },
3014 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
3015 [ 0] = RCAR_GP_PIN(5, 4), /* QSPI0_IO3 */
3016 [ 1] = RCAR_GP_PIN(5, 5), /* QSPI0_SSL */
3017 [ 2] = RCAR_GP_PIN(5, 6), /* QSPI1_SPCLK */
3018 [ 3] = RCAR_GP_PIN(5, 7), /* QSPI1_MOSI_IO0 */
3019 [ 4] = RCAR_GP_PIN(5, 8), /* QSPI1_MISO_IO1 */
3020 [ 5] = RCAR_GP_PIN(5, 9), /* QSPI1_IO2 */
3021 [ 6] = RCAR_GP_PIN(5, 10), /* QSPI1_IO3 */
3022 [ 7] = RCAR_GP_PIN(5, 11), /* QSPI1_SSL */
3023 [ 8] = RCAR_GP_PIN(5, 12), /* RPC_RESET# */
3024 [ 9] = RCAR_GP_PIN(5, 13), /* RPC_WP# */
3025 [10] = RCAR_GP_PIN(5, 14), /* RPC_INT# */
3026 [11] = RCAR_GP_PIN(1, 26), /* DIGRF_CLKIN */
3027 [12] = RCAR_GP_PIN(1, 27), /* DIGRF_CLKOUT */
3028 [13] = RCAR_GP_PIN(2, 17), /* IRQ4 */
3029 [14] = RCAR_GP_PIN(2, 18), /* IRQ5 */
3030 [15] = RCAR_GP_PIN(2, 25), /* SCL3 */
3031 [16] = RCAR_GP_PIN(2, 26), /* SDA3 */
3032 [17] = RCAR_GP_PIN(2, 19), /* MSIOF0_RXD */
3033 [18] = RCAR_GP_PIN(2, 20), /* MSIOF0_TXD */
3034 [19] = RCAR_GP_PIN(2, 21), /* MSIOF0_SCK */
3035 [20] = RCAR_GP_PIN(2, 22), /* MSIOF0_SYNC */
3036 [21] = RCAR_GP_PIN(2, 23), /* MSIOF0_SS1 */
3037 [22] = RCAR_GP_PIN(2, 24), /* MSIOF0_SS2 */
3038 [23] = RCAR_GP_PIN(2, 27), /* FSO_CFE_0# */
3039 [24] = RCAR_GP_PIN(2, 28), /* FSO_CFE_1# */
3040 [25] = RCAR_GP_PIN(2, 29), /* FSO_TOE# */
3041 [26] = SH_PFC_PIN_NONE,
3042 [27] = SH_PFC_PIN_NONE,
3043 [28] = SH_PFC_PIN_NONE,
3044 [29] = SH_PFC_PIN_NONE,
3045 [30] = SH_PFC_PIN_NONE,
3046 [31] = SH_PFC_PIN_NONE,
3047 } },
3048 { /* sentinel */ }
3049 };
3050
3051 static const struct sh_pfc_soc_operations r8a77980_pfc_ops = {
3052 .pin_to_pocctrl = r8a77980_pin_to_pocctrl,
3053 .get_bias = rcar_pinmux_get_bias,
3054 .set_bias = rcar_pinmux_set_bias,
3055 };
3056
3057 const struct sh_pfc_soc_info r8a77980_pinmux_info = {
3058 .name = "r8a77980_pfc",
3059 .ops = &r8a77980_pfc_ops,
3060 .unlock_reg = 0xe6060000, /* PMMR */
3061
3062 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3063
3064 .pins = pinmux_pins,
3065 .nr_pins = ARRAY_SIZE(pinmux_pins),
3066 .groups = pinmux_groups,
3067 .nr_groups = ARRAY_SIZE(pinmux_groups),
3068 .functions = pinmux_functions,
3069 .nr_functions = ARRAY_SIZE(pinmux_functions),
3070
3071 .cfg_regs = pinmux_config_regs,
3072 .bias_regs = pinmux_bias_regs,
3073 .ioctrl_regs = pinmux_ioctrl_regs,
3074
3075 .pinmux_data = pinmux_data,
3076 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3077 };
Kernel DRM miscellaneous fixes and cross-tree changes