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Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / pinctrl / renesas / pfc-r8a779f0.c
blob16e722a4d18fa6351fa30955817d7f0eb8bfeed2
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A779F0 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 *
7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c
8 */
9
10 #include <linux/errno.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13
14 #include "sh_pfc.h"
15
16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
17
18 #define CPU_ALL_GP(fn, sfx) \
19 PORT_GP_CFG_21(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
20 PORT_GP_CFG_25(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
21 PORT_GP_CFG_17(2, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_19(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
23
24 #define CPU_ALL_NOGP(fn) \
25 PIN_NOGP_CFG(PRESETOUT0_N, "PRESETOUT0#", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
26 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
27
28 /*
29 * F_() : just information
30 * FM() : macro for FN_xxx / xxx_MARK
31 */
32
33 /* GPSR0 */
34 #define GPSR0_20 F_(IRQ3, IP2SR0_19_16)
35 #define GPSR0_19 F_(IRQ2, IP2SR0_15_12)
36 #define GPSR0_18 F_(IRQ1, IP2SR0_11_8)
37 #define GPSR0_17 F_(IRQ0, IP2SR0_7_4)
38 #define GPSR0_16 F_(MSIOF0_SS2, IP2SR0_3_0)
39 #define GPSR0_15 F_(MSIOF0_SS1, IP1SR0_31_28)
40 #define GPSR0_14 F_(MSIOF0_SCK, IP1SR0_27_24)
41 #define GPSR0_13 F_(MSIOF0_TXD, IP1SR0_23_20)
42 #define GPSR0_12 F_(MSIOF0_RXD, IP1SR0_19_16)
43 #define GPSR0_11 F_(MSIOF0_SYNC, IP1SR0_15_12)
44 #define GPSR0_10 F_(CTS0_N, IP1SR0_11_8)
45 #define GPSR0_9 F_(RTS0_N, IP1SR0_7_4)
46 #define GPSR0_8 F_(SCK0, IP1SR0_3_0)
47 #define GPSR0_7 F_(TX0, IP0SR0_31_28)
48 #define GPSR0_6 F_(RX0, IP0SR0_27_24)
49 #define GPSR0_5 F_(HRTS0_N, IP0SR0_23_20)
50 #define GPSR0_4 F_(HCTS0_N, IP0SR0_19_16)
51 #define GPSR0_3 F_(HTX0, IP0SR0_15_12)
52 #define GPSR0_2 F_(HRX0, IP0SR0_11_8)
53 #define GPSR0_1 F_(HSCK0, IP0SR0_7_4)
54 #define GPSR0_0 F_(SCIF_CLK, IP0SR0_3_0)
55
56 /* GPSR1 */
57 #define GPSR1_24 FM(SD_WP)
58 #define GPSR1_23 FM(SD_CD)
59 #define GPSR1_22 FM(MMC_SD_CMD)
60 #define GPSR1_21 FM(MMC_D7)
61 #define GPSR1_20 FM(MMC_DS)
62 #define GPSR1_19 FM(MMC_D6)
63 #define GPSR1_18 FM(MMC_D4)
64 #define GPSR1_17 FM(MMC_D5)
65 #define GPSR1_16 FM(MMC_SD_D3)
66 #define GPSR1_15 FM(MMC_SD_D2)
67 #define GPSR1_14 FM(MMC_SD_D1)
68 #define GPSR1_13 FM(MMC_SD_D0)
69 #define GPSR1_12 FM(MMC_SD_CLK)
70 #define GPSR1_11 FM(GP1_11)
71 #define GPSR1_10 FM(GP1_10)
72 #define GPSR1_9 FM(GP1_09)
73 #define GPSR1_8 FM(GP1_08)
74 #define GPSR1_7 F_(GP1_07, IP0SR1_31_28)
75 #define GPSR1_6 F_(GP1_06, IP0SR1_27_24)
76 #define GPSR1_5 F_(GP1_05, IP0SR1_23_20)
77 #define GPSR1_4 F_(GP1_04, IP0SR1_19_16)
78 #define GPSR1_3 F_(GP1_03, IP0SR1_15_12)
79 #define GPSR1_2 F_(GP1_02, IP0SR1_11_8)
80 #define GPSR1_1 F_(GP1_01, IP0SR1_7_4)
81 #define GPSR1_0 F_(GP1_00, IP0SR1_3_0)
82
83 /* GPSR2 */
84 #define GPSR2_16 FM(PCIE1_CLKREQ_N)
85 #define GPSR2_15 FM(PCIE0_CLKREQ_N)
86 #define GPSR2_14 FM(QSPI0_IO3)
87 #define GPSR2_13 FM(QSPI0_SSL)
88 #define GPSR2_12 FM(QSPI0_MISO_IO1)
89 #define GPSR2_11 FM(QSPI0_IO2)
90 #define GPSR2_10 FM(QSPI0_SPCLK)
91 #define GPSR2_9 FM(QSPI0_MOSI_IO0)
92 #define GPSR2_8 FM(QSPI1_SPCLK)
93 #define GPSR2_7 FM(QSPI1_MOSI_IO0)
94 #define GPSR2_6 FM(QSPI1_IO2)
95 #define GPSR2_5 FM(QSPI1_MISO_IO1)
96 #define GPSR2_4 FM(QSPI1_IO3)
97 #define GPSR2_3 FM(QSPI1_SSL)
98 #define GPSR2_2 FM(RPC_RESET_N)
99 #define GPSR2_1 FM(RPC_WP_N)
100 #define GPSR2_0 FM(RPC_INT_N)
101
102 /* GPSR3 */
103 #define GPSR3_18 FM(TSN0_AVTP_CAPTURE_B)
104 #define GPSR3_17 FM(TSN0_AVTP_MATCH_B)
105 #define GPSR3_16 FM(TSN0_AVTP_PPS)
106 #define GPSR3_15 FM(TSN1_AVTP_CAPTURE_B)
107 #define GPSR3_14 FM(TSN1_AVTP_MATCH_B)
108 #define GPSR3_13 FM(TSN1_AVTP_PPS)
109 #define GPSR3_12 FM(TSN0_MAGIC_B)
110 #define GPSR3_11 FM(TSN1_PHY_INT_B)
111 #define GPSR3_10 FM(TSN0_PHY_INT_B)
112 #define GPSR3_9 FM(TSN2_PHY_INT_B)
113 #define GPSR3_8 FM(TSN0_LINK_B)
114 #define GPSR3_7 FM(TSN2_LINK_B)
115 #define GPSR3_6 FM(TSN1_LINK_B)
116 #define GPSR3_5 FM(TSN1_MDC_B)
117 #define GPSR3_4 FM(TSN0_MDC_B)
118 #define GPSR3_3 FM(TSN2_MDC_B)
119 #define GPSR3_2 FM(TSN0_MDIO_B)
120 #define GPSR3_1 FM(TSN2_MDIO_B)
121 #define GPSR3_0 FM(TSN1_MDIO_B)
122
123 /* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */
124 #define IP0SR0_3_0 FM(SCIF_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
125 #define IP0SR0_7_4 FM(HSCK0) FM(SCK3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(TSN0_AVTP_CAPTURE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
126 #define IP0SR0_11_8 FM(HRX0) FM(RX3) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) FM(TSN0_AVTP_MATCH_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
127 #define IP0SR0_15_12 FM(HTX0) FM(TX3) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
128 #define IP0SR0_19_16 FM(HCTS0_N) FM(CTS3_N) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) FM(TSN0_MDC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
129 #define IP0SR0_23_20 FM(HRTS0_N) FM(RTS3_N) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) FM(TSN0_MDIO_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
130 #define IP0SR0_27_24 FM(RX0) FM(HRX1) F_(0, 0) FM(MSIOF1_RXD) F_(0, 0) FM(TSN1_AVTP_MATCH_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
131 #define IP0SR0_31_28 FM(TX0) FM(HTX1) F_(0, 0) FM(MSIOF1_TXD) F_(0, 0) FM(TSN1_AVTP_CAPTURE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
132 /* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */
133 #define IP1SR0_3_0 FM(SCK0) FM(HSCK1) F_(0, 0) FM(MSIOF1_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
134 #define IP1SR0_7_4 FM(RTS0_N) FM(HRTS1_N) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) FM(TSN1_MDIO_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
135 #define IP1SR0_11_8 FM(CTS0_N) FM(HCTS1_N) F_(0, 0) FM(MSIOF1_SYNC) F_(0, 0) FM(TSN1_MDC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
136 #define IP1SR0_15_12 FM(MSIOF0_SYNC) FM(HCTS3_N) FM(CTS1_N) FM(IRQ4) F_(0, 0) FM(TSN0_LINK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
137 #define IP1SR0_19_16 FM(MSIOF0_RXD) FM(HRX3) FM(RX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
138 #define IP1SR0_23_20 FM(MSIOF0_TXD) FM(HTX3) FM(TX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
139 #define IP1SR0_27_24 FM(MSIOF0_SCK) FM(HSCK3) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
140 #define IP1SR0_31_28 FM(MSIOF0_SS1) FM(HRTS3_N) FM(RTS1_N) FM(IRQ5) F_(0, 0) FM(TSN1_LINK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
141 /* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */
142 #define IP2SR0_3_0 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TSN2_LINK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
143 #define IP2SR0_7_4 FM(IRQ0) F_(0, 0) F_(0, 0) FM(MSIOF1_SS1) F_(0, 0) FM(TSN0_MAGIC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
144 #define IP2SR0_11_8 FM(IRQ1) F_(0, 0) F_(0, 0) FM(MSIOF1_SS2) F_(0, 0) FM(TSN0_PHY_INT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
145 #define IP2SR0_15_12 FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TSN1_PHY_INT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
146 #define IP2SR0_19_16 FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TSN2_PHY_INT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
147
148 /* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */
149 #define IP0SR1_3_0 FM(GP1_00) FM(TCLK1) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
150 #define IP0SR1_7_4 FM(GP1_01) FM(TCLK4) FM(HRX2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
151 #define IP0SR1_11_8 FM(GP1_02) F_(0, 0) FM(HTX2) FM(MSIOF2_SS1) F_(0, 0) FM(TSN2_MDC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
152 #define IP0SR1_15_12 FM(GP1_03) FM(TCLK2) FM(HCTS2_N) FM(MSIOF2_SS2) FM(CTS4_N) FM(TSN2_MDIO_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
153 #define IP0SR1_19_16 FM(GP1_04) FM(TCLK3) FM(HRTS2_N) FM(MSIOF2_SYNC) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
154 #define IP0SR1_23_20 FM(GP1_05) FM(MSIOF2_SCK) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
155 #define IP0SR1_27_24 FM(GP1_06) FM(MSIOF2_RXD) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
156 #define IP0SR1_31_28 FM(GP1_07) FM(MSIOF2_TXD) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
157
158 #define PINMUX_GPSR \
159 GPSR1_24 \
160 GPSR1_23 \
161 GPSR1_22 \
162 GPSR1_21 \
163 GPSR0_20 GPSR1_20 \
164 GPSR0_19 GPSR1_19 \
165 GPSR0_18 GPSR1_18 GPSR3_18 \
166 GPSR0_17 GPSR1_17 GPSR3_17 \
167 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 \
168 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 \
169 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 \
170 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 \
171 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 \
172 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 \
173 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 \
174 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 \
175 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 \
176 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 \
177 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 \
178 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 \
179 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 \
180 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 \
181 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 \
182 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 \
183 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0
184
185 #define PINMUX_IPSR \
186 \
187 FM(IP0SR0_3_0) IP0SR0_3_0 FM(IP1SR0_3_0) IP1SR0_3_0 FM(IP2SR0_3_0) IP2SR0_3_0 \
188 FM(IP0SR0_7_4) IP0SR0_7_4 FM(IP1SR0_7_4) IP1SR0_7_4 FM(IP2SR0_7_4) IP2SR0_7_4 \
189 FM(IP0SR0_11_8) IP0SR0_11_8 FM(IP1SR0_11_8) IP1SR0_11_8 FM(IP2SR0_11_8) IP2SR0_11_8 \
190 FM(IP0SR0_15_12) IP0SR0_15_12 FM(IP1SR0_15_12) IP1SR0_15_12 FM(IP2SR0_15_12) IP2SR0_15_12 \
191 FM(IP0SR0_19_16) IP0SR0_19_16 FM(IP1SR0_19_16) IP1SR0_19_16 FM(IP2SR0_19_16) IP2SR0_19_16 \
192 FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 \
193 FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 \
194 FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 \
195 \
196 FM(IP0SR1_3_0) IP0SR1_3_0 \
197 FM(IP0SR1_7_4) IP0SR1_7_4 \
198 FM(IP0SR1_11_8) IP0SR1_11_8 \
199 FM(IP0SR1_15_12) IP0SR1_15_12 \
200 FM(IP0SR1_19_16) IP0SR1_19_16 \
201 FM(IP0SR1_23_20) IP0SR1_23_20 \
202 FM(IP0SR1_27_24) IP0SR1_27_24 \
203 FM(IP0SR1_31_28) IP0SR1_31_28
204
205 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
206 #define MOD_SEL1_11_10 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3)
207 #define MOD_SEL1_9_8 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3)
208 #define MOD_SEL1_7_6 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3)
209 #define MOD_SEL1_5_4 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3)
210 #define MOD_SEL1_3_2 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3)
211 #define MOD_SEL1_1_0 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3)
212
213 #define PINMUX_MOD_SELS \
214 \
215 MOD_SEL1_11_10 \
216 MOD_SEL1_9_8 \
217 MOD_SEL1_7_6 \
218 MOD_SEL1_5_4 \
219 MOD_SEL1_3_2 \
220 MOD_SEL1_1_0
221
222 #define PINMUX_PHYS \
223 FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \
224 FM(SCL4) FM(SDA4) FM(SCL5) FM(SDA5)
225
226 enum {
227 PINMUX_RESERVED = 0,
228
229 PINMUX_DATA_BEGIN,
230 GP_ALL(DATA),
231 PINMUX_DATA_END,
232
233 #define F_(x, y)
234 #define FM(x) FN_##x,
235 PINMUX_FUNCTION_BEGIN,
236 GP_ALL(FN),
237 PINMUX_GPSR
238 PINMUX_IPSR
239 PINMUX_MOD_SELS
240 PINMUX_FUNCTION_END,
241 #undef F_
242 #undef FM
243
244 #define F_(x, y)
245 #define FM(x) x##_MARK,
246 PINMUX_MARK_BEGIN,
247 PINMUX_GPSR
248 PINMUX_IPSR
249 PINMUX_MOD_SELS
250 PINMUX_PHYS
251 PINMUX_MARK_END,
252 #undef F_
253 #undef FM
254 };
255
256 static const u16 pinmux_data[] = {
257 /* Using GP_1_[0-9] requires disabling I2C in MOD_SEL1 */
258 #define GP_1_0_FN GP_1_0_FN, FN_SEL_I2C0_0
259 #define GP_1_1_FN GP_1_1_FN, FN_SEL_I2C0_0
260 #define GP_1_2_FN GP_1_2_FN, FN_SEL_I2C1_0
261 #define GP_1_3_FN GP_1_3_FN, FN_SEL_I2C1_0
262 #define GP_1_4_FN GP_1_4_FN, FN_SEL_I2C2_0
263 #define GP_1_5_FN GP_1_5_FN, FN_SEL_I2C2_0
264 #define GP_1_6_FN GP_1_6_FN, FN_SEL_I2C3_0
265 #define GP_1_7_FN GP_1_7_FN, FN_SEL_I2C3_0
266 #define GP_1_8_FN GP_1_8_FN, FN_SEL_I2C4_0
267 #define GP_1_9_FN GP_1_9_FN, FN_SEL_I2C4_0
268 PINMUX_DATA_GP_ALL(),
269 #undef GP_1_0_FN
270 #undef GP_1_1_FN
271 #undef GP_1_2_FN
272 #undef GP_1_3_FN
273 #undef GP_1_4_FN
274 #undef GP_1_5_FN
275 #undef GP_1_6_FN
276 #undef GP_1_7_FN
277 #undef GP_1_8_FN
278 #undef GP_1_9_FN
279
280 PINMUX_SINGLE(SD_WP),
281 PINMUX_SINGLE(SD_CD),
282 PINMUX_SINGLE(MMC_SD_CMD),
283 PINMUX_SINGLE(MMC_D7),
284 PINMUX_SINGLE(MMC_DS),
285 PINMUX_SINGLE(MMC_D6),
286 PINMUX_SINGLE(MMC_D4),
287 PINMUX_SINGLE(MMC_D5),
288 PINMUX_SINGLE(MMC_SD_D3),
289 PINMUX_SINGLE(MMC_SD_D2),
290 PINMUX_SINGLE(MMC_SD_D1),
291 PINMUX_SINGLE(MMC_SD_D0),
292 PINMUX_SINGLE(MMC_SD_CLK),
293 PINMUX_SINGLE(PCIE1_CLKREQ_N),
294 PINMUX_SINGLE(PCIE0_CLKREQ_N),
295 PINMUX_SINGLE(QSPI0_IO3),
296 PINMUX_SINGLE(QSPI0_SSL),
297 PINMUX_SINGLE(QSPI0_MISO_IO1),
298 PINMUX_SINGLE(QSPI0_IO2),
299 PINMUX_SINGLE(QSPI0_SPCLK),
300 PINMUX_SINGLE(QSPI0_MOSI_IO0),
301 PINMUX_SINGLE(QSPI1_SPCLK),
302 PINMUX_SINGLE(QSPI1_MOSI_IO0),
303 PINMUX_SINGLE(QSPI1_IO2),
304 PINMUX_SINGLE(QSPI1_MISO_IO1),
305 PINMUX_SINGLE(QSPI1_IO3),
306 PINMUX_SINGLE(QSPI1_SSL),
307 PINMUX_SINGLE(RPC_RESET_N),
308 PINMUX_SINGLE(RPC_WP_N),
309 PINMUX_SINGLE(RPC_INT_N),
310
311 PINMUX_SINGLE(TSN0_AVTP_CAPTURE_B),
312 PINMUX_SINGLE(TSN0_AVTP_MATCH_B),
313 PINMUX_SINGLE(TSN0_AVTP_PPS),
314 PINMUX_SINGLE(TSN1_AVTP_CAPTURE_B),
315 PINMUX_SINGLE(TSN1_AVTP_MATCH_B),
316 PINMUX_SINGLE(TSN1_AVTP_PPS),
317 PINMUX_SINGLE(TSN0_MAGIC_B),
318 PINMUX_SINGLE(TSN1_PHY_INT_B),
319 PINMUX_SINGLE(TSN0_PHY_INT_B),
320 PINMUX_SINGLE(TSN2_PHY_INT_B),
321 PINMUX_SINGLE(TSN0_LINK_B),
322 PINMUX_SINGLE(TSN2_LINK_B),
323 PINMUX_SINGLE(TSN1_LINK_B),
324 PINMUX_SINGLE(TSN1_MDC_B),
325 PINMUX_SINGLE(TSN0_MDC_B),
326 PINMUX_SINGLE(TSN2_MDC_B),
327 PINMUX_SINGLE(TSN0_MDIO_B),
328 PINMUX_SINGLE(TSN2_MDIO_B),
329 PINMUX_SINGLE(TSN1_MDIO_B),
330
331 /* IP0SR0 */
332 PINMUX_IPSR_GPSR(IP0SR0_3_0, SCIF_CLK),
333
334 PINMUX_IPSR_GPSR(IP0SR0_7_4, HSCK0),
335 PINMUX_IPSR_GPSR(IP0SR0_7_4, SCK3),
336 PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SCK),
337 PINMUX_IPSR_GPSR(IP0SR0_7_4, TSN0_AVTP_CAPTURE_A),
338
339 PINMUX_IPSR_GPSR(IP0SR0_11_8, HRX0),
340 PINMUX_IPSR_GPSR(IP0SR0_11_8, RX3),
341 PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_RXD),
342 PINMUX_IPSR_GPSR(IP0SR0_11_8, TSN0_AVTP_MATCH_A),
343
344 PINMUX_IPSR_GPSR(IP0SR0_15_12, HTX0),
345 PINMUX_IPSR_GPSR(IP0SR0_15_12, TX3),
346 PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_TXD),
347
348 PINMUX_IPSR_GPSR(IP0SR0_19_16, HCTS0_N),
349 PINMUX_IPSR_GPSR(IP0SR0_19_16, CTS3_N),
350 PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_SS1),
351 PINMUX_IPSR_GPSR(IP0SR0_19_16, TSN0_MDC_A),
352
353 PINMUX_IPSR_GPSR(IP0SR0_23_20, HRTS0_N),
354 PINMUX_IPSR_GPSR(IP0SR0_23_20, RTS3_N),
355 PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_SS2),
356 PINMUX_IPSR_GPSR(IP0SR0_23_20, TSN0_MDIO_A),
357
358 PINMUX_IPSR_GPSR(IP0SR0_27_24, RX0),
359 PINMUX_IPSR_GPSR(IP0SR0_27_24, HRX1),
360 PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF1_RXD),
361 PINMUX_IPSR_GPSR(IP0SR0_27_24, TSN1_AVTP_MATCH_A),
362
363 PINMUX_IPSR_GPSR(IP0SR0_31_28, TX0),
364 PINMUX_IPSR_GPSR(IP0SR0_31_28, HTX1),
365 PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF1_TXD),
366 PINMUX_IPSR_GPSR(IP0SR0_31_28, TSN1_AVTP_CAPTURE_A),
367
368 /* IP1SR0 */
369 PINMUX_IPSR_GPSR(IP1SR0_3_0, SCK0),
370 PINMUX_IPSR_GPSR(IP1SR0_3_0, HSCK1),
371 PINMUX_IPSR_GPSR(IP1SR0_3_0, MSIOF1_SCK),
372
373 PINMUX_IPSR_GPSR(IP1SR0_7_4, RTS0_N),
374 PINMUX_IPSR_GPSR(IP1SR0_7_4, HRTS1_N),
375 PINMUX_IPSR_GPSR(IP1SR0_7_4, MSIOF3_SYNC),
376 PINMUX_IPSR_GPSR(IP1SR0_7_4, TSN1_MDIO_A),
377
378 PINMUX_IPSR_GPSR(IP1SR0_11_8, CTS0_N),
379 PINMUX_IPSR_GPSR(IP1SR0_11_8, HCTS1_N),
380 PINMUX_IPSR_GPSR(IP1SR0_11_8, MSIOF1_SYNC),
381 PINMUX_IPSR_GPSR(IP1SR0_11_8, TSN1_MDC_A),
382
383 PINMUX_IPSR_GPSR(IP1SR0_15_12, MSIOF0_SYNC),
384 PINMUX_IPSR_GPSR(IP1SR0_15_12, HCTS3_N),
385 PINMUX_IPSR_GPSR(IP1SR0_15_12, CTS1_N),
386 PINMUX_IPSR_GPSR(IP1SR0_15_12, IRQ4),
387 PINMUX_IPSR_GPSR(IP1SR0_15_12, TSN0_LINK_A),
388
389 PINMUX_IPSR_GPSR(IP1SR0_19_16, MSIOF0_RXD),
390 PINMUX_IPSR_GPSR(IP1SR0_19_16, HRX3),
391 PINMUX_IPSR_GPSR(IP1SR0_19_16, RX1),
392
393 PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF0_TXD),
394 PINMUX_IPSR_GPSR(IP1SR0_23_20, HTX3),
395 PINMUX_IPSR_GPSR(IP1SR0_23_20, TX1),
396
397 PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF0_SCK),
398 PINMUX_IPSR_GPSR(IP1SR0_27_24, HSCK3),
399 PINMUX_IPSR_GPSR(IP1SR0_27_24, SCK1),
400
401 PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF0_SS1),
402 PINMUX_IPSR_GPSR(IP1SR0_31_28, HRTS3_N),
403 PINMUX_IPSR_GPSR(IP1SR0_31_28, RTS1_N),
404 PINMUX_IPSR_GPSR(IP1SR0_31_28, IRQ5),
405 PINMUX_IPSR_GPSR(IP1SR0_31_28, TSN1_LINK_A),
406
407 /* IP2SR0 */
408 PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF0_SS2),
409 PINMUX_IPSR_GPSR(IP2SR0_3_0, TSN2_LINK_A),
410
411 PINMUX_IPSR_GPSR(IP2SR0_7_4, IRQ0),
412 PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF1_SS1),
413 PINMUX_IPSR_GPSR(IP2SR0_7_4, TSN0_MAGIC_A),
414
415 PINMUX_IPSR_GPSR(IP2SR0_11_8, IRQ1),
416 PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF1_SS2),
417 PINMUX_IPSR_GPSR(IP2SR0_11_8, TSN0_PHY_INT_A),
418
419 PINMUX_IPSR_GPSR(IP2SR0_15_12, IRQ2),
420 PINMUX_IPSR_GPSR(IP2SR0_15_12, TSN1_PHY_INT_A),
421
422 PINMUX_IPSR_GPSR(IP2SR0_19_16, IRQ3),
423 PINMUX_IPSR_GPSR(IP2SR0_19_16, TSN2_PHY_INT_A),
424
425 /* IP0SR1 */
426 /* GP1_00 = SCL0 */
427 PINMUX_IPSR_MSEL(IP0SR1_3_0, GP1_00, SEL_I2C0_0),
428 PINMUX_IPSR_MSEL(IP0SR1_3_0, TCLK1, SEL_I2C0_0),
429 PINMUX_IPSR_MSEL(IP0SR1_3_0, HSCK2, SEL_I2C0_0),
430 PINMUX_IPSR_PHYS(IP0SR1_3_0, SCL0, SEL_I2C0_3),
431
432 /* GP1_01 = SDA0 */
433 PINMUX_IPSR_MSEL(IP0SR1_7_4, GP1_01, SEL_I2C0_0),
434 PINMUX_IPSR_MSEL(IP0SR1_7_4, TCLK4, SEL_I2C0_0),
435 PINMUX_IPSR_MSEL(IP0SR1_7_4, HRX2, SEL_I2C0_0),
436 PINMUX_IPSR_PHYS(IP0SR1_7_4, SDA0, SEL_I2C0_3),
437
438 /* GP1_02 = SCL1 */
439 PINMUX_IPSR_MSEL(IP0SR1_11_8, GP1_02, SEL_I2C1_0),
440 PINMUX_IPSR_MSEL(IP0SR1_11_8, HTX2, SEL_I2C1_0),
441 PINMUX_IPSR_MSEL(IP0SR1_11_8, MSIOF2_SS1, SEL_I2C1_0),
442 PINMUX_IPSR_MSEL(IP0SR1_11_8, TSN2_MDC_A, SEL_I2C1_0),
443 PINMUX_IPSR_PHYS(IP0SR1_11_8, SCL1, SEL_I2C1_3),
444
445 /* GP1_03 = SDA1 */
446 PINMUX_IPSR_MSEL(IP0SR1_15_12, GP1_03, SEL_I2C1_0),
447 PINMUX_IPSR_MSEL(IP0SR1_15_12, TCLK2, SEL_I2C1_0),
448 PINMUX_IPSR_MSEL(IP0SR1_15_12, HCTS2_N, SEL_I2C1_0),
449 PINMUX_IPSR_MSEL(IP0SR1_15_12, MSIOF2_SS2, SEL_I2C1_0),
450 PINMUX_IPSR_MSEL(IP0SR1_15_12, CTS4_N, SEL_I2C1_0),
451 PINMUX_IPSR_MSEL(IP0SR1_15_12, TSN2_MDIO_A, SEL_I2C1_0),
452 PINMUX_IPSR_PHYS(IP0SR1_15_12, SDA1, SEL_I2C1_3),
453
454 /* GP1_04 = SCL2 */
455 PINMUX_IPSR_MSEL(IP0SR1_19_16, GP1_04, SEL_I2C2_0),
456 PINMUX_IPSR_MSEL(IP0SR1_19_16, TCLK3, SEL_I2C2_0),
457 PINMUX_IPSR_MSEL(IP0SR1_19_16, HRTS2_N, SEL_I2C2_0),
458 PINMUX_IPSR_MSEL(IP0SR1_19_16, MSIOF2_SYNC, SEL_I2C2_0),
459 PINMUX_IPSR_MSEL(IP0SR1_19_16, RTS4_N, SEL_I2C2_0),
460 PINMUX_IPSR_PHYS(IP0SR1_19_16, SCL2, SEL_I2C2_3),
461
462 /* GP1_05 = SDA2 */
463 PINMUX_IPSR_MSEL(IP0SR1_23_20, GP1_05, SEL_I2C2_0),
464 PINMUX_IPSR_MSEL(IP0SR1_23_20, MSIOF2_SCK, SEL_I2C2_0),
465 PINMUX_IPSR_MSEL(IP0SR1_23_20, SCK4, SEL_I2C2_0),
466 PINMUX_IPSR_PHYS(IP0SR1_23_20, SDA2, SEL_I2C2_3),
467
468 /* GP1_06 = SCL3 */
469 PINMUX_IPSR_MSEL(IP0SR1_27_24, GP1_06, SEL_I2C3_0),
470 PINMUX_IPSR_MSEL(IP0SR1_27_24, MSIOF2_RXD, SEL_I2C3_0),
471 PINMUX_IPSR_MSEL(IP0SR1_27_24, RX4, SEL_I2C3_0),
472 PINMUX_IPSR_PHYS(IP0SR1_27_24, SCL3, SEL_I2C3_3),
473
474 /* GP1_07 = SDA3 */
475 PINMUX_IPSR_MSEL(IP0SR1_31_28, GP1_07, SEL_I2C3_0),
476 PINMUX_IPSR_MSEL(IP0SR1_31_28, MSIOF2_TXD, SEL_I2C3_0),
477 PINMUX_IPSR_MSEL(IP0SR1_31_28, TX4, SEL_I2C3_0),
478 PINMUX_IPSR_PHYS(IP0SR1_31_28, SDA3, SEL_I2C3_3),
479
480 /* GP1_08 = SCL4 */
481 PINMUX_IPSR_NOGM(0, GP1_08, SEL_I2C4_0),
482 PINMUX_IPSR_NOFN(GP1_08, SCL4, SEL_I2C4_3),
483
484 /* GP1_09 = SDA4 */
485 PINMUX_IPSR_NOGM(0, GP1_09, SEL_I2C4_0),
486 PINMUX_IPSR_NOFN(GP1_09, SDA4, SEL_I2C4_3),
487
488 /* GP1_10 = SCL5 */
489 PINMUX_IPSR_NOGM(0, GP1_10, SEL_I2C5_0),
490 PINMUX_IPSR_NOFN(GP1_10, SCL5, SEL_I2C5_3),
491
492 /* GP1_11 = SDA5 */
493 PINMUX_IPSR_NOGM(0, GP1_11, SEL_I2C5_0),
494 PINMUX_IPSR_NOFN(GP1_11, SDA5, SEL_I2C5_3),
495 };
496
497 /*
498 * Pins not associated with a GPIO port.
499 */
500 enum {
501 GP_ASSIGN_LAST(),
502 NOGP_ALL(),
503 };
504
505 static const struct sh_pfc_pin pinmux_pins[] = {
506 PINMUX_GPIO_GP_ALL(),
507 };
508
509 /* - HSCIF0 ----------------------------------------------------------------- */
510 static const unsigned int hscif0_data_pins[] = {
511 /* HRX0, HTX0 */
512 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
513 };
514 static const unsigned int hscif0_data_mux[] = {
515 HRX0_MARK, HTX0_MARK,
516 };
517 static const unsigned int hscif0_clk_pins[] = {
518 /* HSCK0 */
519 RCAR_GP_PIN(0, 1),
520 };
521 static const unsigned int hscif0_clk_mux[] = {
522 HSCK0_MARK,
523 };
524 static const unsigned int hscif0_ctrl_pins[] = {
525 /* HRTS0#, HCTS0# */
526 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4),
527 };
528 static const unsigned int hscif0_ctrl_mux[] = {
529 HRTS0_N_MARK, HCTS0_N_MARK,
530 };
531
532 /* - HSCIF1 ----------------------------------------------------------------- */
533 static const unsigned int hscif1_data_pins[] = {
534 /* HRX1, HTX1 */
535 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
536 };
537 static const unsigned int hscif1_data_mux[] = {
538 HRX1_MARK, HTX1_MARK,
539 };
540 static const unsigned int hscif1_clk_pins[] = {
541 /* HSCK1 */
542 RCAR_GP_PIN(0, 8),
543 };
544 static const unsigned int hscif1_clk_mux[] = {
545 HSCK1_MARK,
546 };
547 static const unsigned int hscif1_ctrl_pins[] = {
548 /* HRTS1#, HCTS1# */
549 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
550 };
551 static const unsigned int hscif1_ctrl_mux[] = {
552 HRTS1_N_MARK, HCTS1_N_MARK,
553 };
554
555 /* - HSCIF2 ----------------------------------------------------------------- */
556 static const unsigned int hscif2_data_pins[] = {
557 /* HRX2, HTX2 */
558 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
559 };
560 static const unsigned int hscif2_data_mux[] = {
561 HRX2_MARK, HTX2_MARK,
562 };
563 static const unsigned int hscif2_clk_pins[] = {
564 /* HSCK2 */
565 RCAR_GP_PIN(1, 0),
566 };
567 static const unsigned int hscif2_clk_mux[] = {
568 HSCK2_MARK,
569 };
570 static const unsigned int hscif2_ctrl_pins[] = {
571 /* HRTS2#, HCTS2# */
572 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
573 };
574 static const unsigned int hscif2_ctrl_mux[] = {
575 HRTS2_N_MARK, HCTS2_N_MARK,
576 };
577
578 /* - HSCIF3 ----------------------------------------------------------------- */
579 static const unsigned int hscif3_data_pins[] = {
580 /* HRX3, HTX3 */
581 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
582 };
583 static const unsigned int hscif3_data_mux[] = {
584 HRX3_MARK, HTX3_MARK,
585 };
586 static const unsigned int hscif3_clk_pins[] = {
587 /* HSCK3 */
588 RCAR_GP_PIN(0, 14),
589 };
590 static const unsigned int hscif3_clk_mux[] = {
591 HSCK3_MARK,
592 };
593 static const unsigned int hscif3_ctrl_pins[] = {
594 /* HRTS3#, HCTS3# */
595 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
596 };
597 static const unsigned int hscif3_ctrl_mux[] = {
598 HRTS3_N_MARK, HCTS3_N_MARK,
599 };
600
601 /* - I2C0 ------------------------------------------------------------------- */
602 static const unsigned int i2c0_pins[] = {
603 /* SDA0, SCL0 */
604 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
605 };
606 static const unsigned int i2c0_mux[] = {
607 SDA0_MARK, SCL0_MARK,
608 };
609
610 /* - I2C1 ------------------------------------------------------------------- */
611 static const unsigned int i2c1_pins[] = {
612 /* SDA1, SCL1 */
613 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
614 };
615 static const unsigned int i2c1_mux[] = {
616 SDA1_MARK, SCL1_MARK,
617 };
618
619 /* - I2C2 ------------------------------------------------------------------- */
620 static const unsigned int i2c2_pins[] = {
621 /* SDA2, SCL2 */
622 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4),
623 };
624 static const unsigned int i2c2_mux[] = {
625 SDA2_MARK, SCL2_MARK,
626 };
627
628 /* - I2C3 ------------------------------------------------------------------- */
629 static const unsigned int i2c3_pins[] = {
630 /* SDA3, SCL3 */
631 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
632 };
633 static const unsigned int i2c3_mux[] = {
634 SDA3_MARK, SCL3_MARK,
635 };
636
637 /* - I2C4 ------------------------------------------------------------------- */
638 static const unsigned int i2c4_pins[] = {
639 /* SDA4, SCL4 */
640 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
641 };
642 static const unsigned int i2c4_mux[] = {
643 SDA4_MARK, SCL4_MARK,
644 };
645
646 /* - I2C5 ------------------------------------------------------------------- */
647 static const unsigned int i2c5_pins[] = {
648 /* SDA5, SCL5 */
649 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
650 };
651 static const unsigned int i2c5_mux[] = {
652 SDA5_MARK, SCL5_MARK,
653 };
654
655
656 /* - INTC-EX ---------------------------------------------------------------- */
657 static const unsigned int intc_ex_irq0_pins[] = {
658 /* IRQ0 */
659 RCAR_GP_PIN(0, 17),
660 };
661 static const unsigned int intc_ex_irq0_mux[] = {
662 IRQ0_MARK,
663 };
664 static const unsigned int intc_ex_irq1_pins[] = {
665 /* IRQ1 */
666 RCAR_GP_PIN(0, 18),
667 };
668 static const unsigned int intc_ex_irq1_mux[] = {
669 IRQ1_MARK,
670 };
671 static const unsigned int intc_ex_irq2_pins[] = {
672 /* IRQ2 */
673 RCAR_GP_PIN(0, 19),
674 };
675 static const unsigned int intc_ex_irq2_mux[] = {
676 IRQ2_MARK,
677 };
678 static const unsigned int intc_ex_irq3_pins[] = {
679 /* IRQ3 */
680 RCAR_GP_PIN(0, 20),
681 };
682 static const unsigned int intc_ex_irq3_mux[] = {
683 IRQ3_MARK,
684 };
685 static const unsigned int intc_ex_irq4_pins[] = {
686 /* IRQ4 */
687 RCAR_GP_PIN(0, 11),
688 };
689 static const unsigned int intc_ex_irq4_mux[] = {
690 IRQ4_MARK,
691 };
692 static const unsigned int intc_ex_irq5_pins[] = {
693 /* IRQ5 */
694 RCAR_GP_PIN(0, 15),
695 };
696 static const unsigned int intc_ex_irq5_mux[] = {
697 IRQ5_MARK,
698 };
699
700 /* - MMC -------------------------------------------------------------------- */
701 static const unsigned int mmc_data_pins[] = {
702 /* MMC_SD_D[0:3], MMC_D[4:7] */
703 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
704 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
705 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
706 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 21),
707 };
708 static const unsigned int mmc_data_mux[] = {
709 MMC_SD_D0_MARK, MMC_SD_D1_MARK,
710 MMC_SD_D2_MARK, MMC_SD_D3_MARK,
711 MMC_D4_MARK, MMC_D5_MARK,
712 MMC_D6_MARK, MMC_D7_MARK,
713 };
714 static const unsigned int mmc_ctrl_pins[] = {
715 /* MMC_SD_CLK, MMC_SD_CMD */
716 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 22),
717 };
718 static const unsigned int mmc_ctrl_mux[] = {
719 MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
720 };
721 static const unsigned int mmc_cd_pins[] = {
722 /* SD_CD */
723 RCAR_GP_PIN(1, 23),
724 };
725 static const unsigned int mmc_cd_mux[] = {
726 SD_CD_MARK,
727 };
728 static const unsigned int mmc_wp_pins[] = {
729 /* SD_WP */
730 RCAR_GP_PIN(1, 24),
731 };
732 static const unsigned int mmc_wp_mux[] = {
733 SD_WP_MARK,
734 };
735 static const unsigned int mmc_ds_pins[] = {
736 /* MMC_DS */
737 RCAR_GP_PIN(1, 20),
738 };
739 static const unsigned int mmc_ds_mux[] = {
740 MMC_DS_MARK,
741 };
742
743 /* - MSIOF0 ----------------------------------------------------------------- */
744 static const unsigned int msiof0_clk_pins[] = {
745 /* MSIOF0_SCK */
746 RCAR_GP_PIN(0, 14),
747 };
748 static const unsigned int msiof0_clk_mux[] = {
749 MSIOF0_SCK_MARK,
750 };
751 static const unsigned int msiof0_sync_pins[] = {
752 /* MSIOF0_SYNC */
753 RCAR_GP_PIN(0, 11),
754 };
755 static const unsigned int msiof0_sync_mux[] = {
756 MSIOF0_SYNC_MARK,
757 };
758 static const unsigned int msiof0_ss1_pins[] = {
759 /* MSIOF0_SS1 */
760 RCAR_GP_PIN(0, 15),
761 };
762 static const unsigned int msiof0_ss1_mux[] = {
763 MSIOF0_SS1_MARK,
764 };
765 static const unsigned int msiof0_ss2_pins[] = {
766 /* MSIOF0_SS2 */
767 RCAR_GP_PIN(0, 16),
768 };
769 static const unsigned int msiof0_ss2_mux[] = {
770 MSIOF0_SS2_MARK,
771 };
772 static const unsigned int msiof0_txd_pins[] = {
773 /* MSIOF0_TXD */
774 RCAR_GP_PIN(0, 13),
775 };
776 static const unsigned int msiof0_txd_mux[] = {
777 MSIOF0_TXD_MARK,
778 };
779 static const unsigned int msiof0_rxd_pins[] = {
780 /* MSIOF0_RXD */
781 RCAR_GP_PIN(0, 12),
782 };
783 static const unsigned int msiof0_rxd_mux[] = {
784 MSIOF0_RXD_MARK,
785 };
786
787 /* - MSIOF1 ----------------------------------------------------------------- */
788 static const unsigned int msiof1_clk_pins[] = {
789 /* MSIOF1_SCK */
790 RCAR_GP_PIN(0, 8),
791 };
792 static const unsigned int msiof1_clk_mux[] = {
793 MSIOF1_SCK_MARK,
794 };
795 static const unsigned int msiof1_sync_pins[] = {
796 /* MSIOF1_SYNC */
797 RCAR_GP_PIN(0, 10),
798 };
799 static const unsigned int msiof1_sync_mux[] = {
800 MSIOF1_SYNC_MARK,
801 };
802 static const unsigned int msiof1_ss1_pins[] = {
803 /* MSIOF1_SS1 */
804 RCAR_GP_PIN(0, 17),
805 };
806 static const unsigned int msiof1_ss1_mux[] = {
807 MSIOF1_SS1_MARK,
808 };
809 static const unsigned int msiof1_ss2_pins[] = {
810 /* MSIOF1_SS2 */
811 RCAR_GP_PIN(0, 18),
812 };
813 static const unsigned int msiof1_ss2_mux[] = {
814 MSIOF1_SS2_MARK,
815 };
816 static const unsigned int msiof1_txd_pins[] = {
817 /* MSIOF1_TXD */
818 RCAR_GP_PIN(0, 7),
819 };
820 static const unsigned int msiof1_txd_mux[] = {
821 MSIOF1_TXD_MARK,
822 };
823 static const unsigned int msiof1_rxd_pins[] = {
824 /* MSIOF1_RXD */
825 RCAR_GP_PIN(0, 6),
826 };
827 static const unsigned int msiof1_rxd_mux[] = {
828 MSIOF1_RXD_MARK,
829 };
830
831 /* - MSIOF2 ----------------------------------------------------------------- */
832 static const unsigned int msiof2_clk_pins[] = {
833 /* MSIOF2_SCK */
834 RCAR_GP_PIN(1, 5),
835 };
836 static const unsigned int msiof2_clk_mux[] = {
837 MSIOF2_SCK_MARK,
838 };
839 static const unsigned int msiof2_sync_pins[] = {
840 /* MSIOF2_SYNC */
841 RCAR_GP_PIN(1, 4),
842 };
843 static const unsigned int msiof2_sync_mux[] = {
844 MSIOF2_SYNC_MARK,
845 };
846 static const unsigned int msiof2_ss1_pins[] = {
847 /* MSIOF2_SS1 */
848 RCAR_GP_PIN(1, 2),
849 };
850 static const unsigned int msiof2_ss1_mux[] = {
851 MSIOF2_SS1_MARK,
852 };
853 static const unsigned int msiof2_ss2_pins[] = {
854 /* MSIOF2_SS2 */
855 RCAR_GP_PIN(1, 3),
856 };
857 static const unsigned int msiof2_ss2_mux[] = {
858 MSIOF2_SS2_MARK,
859 };
860 static const unsigned int msiof2_txd_pins[] = {
861 /* MSIOF2_TXD */
862 RCAR_GP_PIN(1, 7),
863 };
864 static const unsigned int msiof2_txd_mux[] = {
865 MSIOF2_TXD_MARK,
866 };
867 static const unsigned int msiof2_rxd_pins[] = {
868 /* MSIOF2_RXD */
869 RCAR_GP_PIN(1, 6),
870 };
871 static const unsigned int msiof2_rxd_mux[] = {
872 MSIOF2_RXD_MARK,
873 };
874
875 /* - MSIOF3 ----------------------------------------------------------------- */
876 static const unsigned int msiof3_clk_pins[] = {
877 /* MSIOF3_SCK */
878 RCAR_GP_PIN(0, 1),
879 };
880 static const unsigned int msiof3_clk_mux[] = {
881 MSIOF3_SCK_MARK,
882 };
883 static const unsigned int msiof3_sync_pins[] = {
884 /* MSIOF3_SYNC */
885 RCAR_GP_PIN(0, 9),
886 };
887 static const unsigned int msiof3_sync_mux[] = {
888 MSIOF3_SYNC_MARK,
889 };
890 static const unsigned int msiof3_ss1_pins[] = {
891 /* MSIOF3_SS1 */
892 RCAR_GP_PIN(0, 4),
893 };
894 static const unsigned int msiof3_ss1_mux[] = {
895 MSIOF3_SS1_MARK,
896 };
897 static const unsigned int msiof3_ss2_pins[] = {
898 /* MSIOF3_SS2 */
899 RCAR_GP_PIN(0, 5),
900 };
901 static const unsigned int msiof3_ss2_mux[] = {
902 MSIOF3_SS2_MARK,
903 };
904 static const unsigned int msiof3_txd_pins[] = {
905 /* MSIOF3_TXD */
906 RCAR_GP_PIN(0, 3),
907 };
908 static const unsigned int msiof3_txd_mux[] = {
909 MSIOF3_TXD_MARK,
910 };
911 static const unsigned int msiof3_rxd_pins[] = {
912 /* MSIOF3_RXD */
913 RCAR_GP_PIN(0, 2),
914 };
915 static const unsigned int msiof3_rxd_mux[] = {
916 MSIOF3_RXD_MARK,
917 };
918
919 /* - PCIE ------------------------------------------------------------------- */
920 static const unsigned int pcie0_clkreq_n_pins[] = {
921 /* PCIE0_CLKREQ# */
922 RCAR_GP_PIN(2, 15),
923 };
924
925 static const unsigned int pcie0_clkreq_n_mux[] = {
926 PCIE0_CLKREQ_N_MARK,
927 };
928
929 static const unsigned int pcie1_clkreq_n_pins[] = {
930 /* PCIE1_CLKREQ# */
931 RCAR_GP_PIN(2, 16),
932 };
933
934 static const unsigned int pcie1_clkreq_n_mux[] = {
935 PCIE1_CLKREQ_N_MARK,
936 };
937
938 /* - QSPI0 ------------------------------------------------------------------ */
939 static const unsigned int qspi0_ctrl_pins[] = {
940 /* SPCLK, SSL */
941 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13),
942 };
943 static const unsigned int qspi0_ctrl_mux[] = {
944 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
945 };
946 static const unsigned int qspi0_data_pins[] = {
947 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
948 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 12),
949 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 14),
950 };
951 static const unsigned int qspi0_data_mux[] = {
952 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
953 QSPI0_IO2_MARK, QSPI0_IO3_MARK
954 };
955
956 /* - QSPI1 ------------------------------------------------------------------ */
957 static const unsigned int qspi1_ctrl_pins[] = {
958 /* SPCLK, SSL */
959 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 3),
960 };
961 static const unsigned int qspi1_ctrl_mux[] = {
962 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
963 };
964 static const unsigned int qspi1_data_pins[] = {
965 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
966 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 5),
967 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 4),
968 };
969 static const unsigned int qspi1_data_mux[] = {
970 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
971 QSPI1_IO2_MARK, QSPI1_IO3_MARK
972 };
973
974 /* - SCIF0 ------------------------------------------------------------------ */
975 static const unsigned int scif0_data_pins[] = {
976 /* RX0, TX0 */
977 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
978 };
979 static const unsigned int scif0_data_mux[] = {
980 RX0_MARK, TX0_MARK,
981 };
982 static const unsigned int scif0_clk_pins[] = {
983 /* SCK0 */
984 RCAR_GP_PIN(0, 8),
985 };
986 static const unsigned int scif0_clk_mux[] = {
987 SCK0_MARK,
988 };
989 static const unsigned int scif0_ctrl_pins[] = {
990 /* RTS0#, CTS0# */
991 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
992 };
993 static const unsigned int scif0_ctrl_mux[] = {
994 RTS0_N_MARK, CTS0_N_MARK,
995 };
996
997 /* - SCIF1 ------------------------------------------------------------------ */
998 static const unsigned int scif1_data_pins[] = {
999 /* RX1, TX1 */
1000 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1001 };
1002 static const unsigned int scif1_data_mux[] = {
1003 RX1_MARK, TX1_MARK,
1004 };
1005 static const unsigned int scif1_clk_pins[] = {
1006 /* SCK1 */
1007 RCAR_GP_PIN(0, 14),
1008 };
1009 static const unsigned int scif1_clk_mux[] = {
1010 SCK1_MARK,
1011 };
1012 static const unsigned int scif1_ctrl_pins[] = {
1013 /* RTS1#, CTS1# */
1014 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
1015 };
1016 static const unsigned int scif1_ctrl_mux[] = {
1017 RTS1_N_MARK, CTS1_N_MARK,
1018 };
1019
1020 /* - SCIF3 ------------------------------------------------------------------ */
1021 static const unsigned int scif3_data_pins[] = {
1022 /* RX3, TX3 */
1023 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
1024 };
1025 static const unsigned int scif3_data_mux[] = {
1026 RX3_MARK, TX3_MARK,
1027 };
1028 static const unsigned int scif3_clk_pins[] = {
1029 /* SCK3 */
1030 RCAR_GP_PIN(0, 1),
1031 };
1032 static const unsigned int scif3_clk_mux[] = {
1033 SCK3_MARK,
1034 };
1035 static const unsigned int scif3_ctrl_pins[] = {
1036 /* RTS3#, CTS3# */
1037 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4),
1038 };
1039 static const unsigned int scif3_ctrl_mux[] = {
1040 RTS3_N_MARK, CTS3_N_MARK,
1041 };
1042
1043 /* - SCIF4 ------------------------------------------------------------------ */
1044 static const unsigned int scif4_data_pins[] = {
1045 /* RX4, TX4 */
1046 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
1047 };
1048 static const unsigned int scif4_data_mux[] = {
1049 RX4_MARK, TX4_MARK,
1050 };
1051 static const unsigned int scif4_clk_pins[] = {
1052 /* SCK4 */
1053 RCAR_GP_PIN(1, 5),
1054 };
1055 static const unsigned int scif4_clk_mux[] = {
1056 SCK4_MARK,
1057 };
1058 static const unsigned int scif4_ctrl_pins[] = {
1059 /* RTS4#, CTS4# */
1060 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
1061 };
1062 static const unsigned int scif4_ctrl_mux[] = {
1063 RTS4_N_MARK, CTS4_N_MARK,
1064 };
1065
1066 /* - SCIF Clock ------------------------------------------------------------- */
1067 static const unsigned int scif_clk_pins[] = {
1068 /* SCIF_CLK */
1069 RCAR_GP_PIN(0, 0),
1070 };
1071 static const unsigned int scif_clk_mux[] = {
1072 SCIF_CLK_MARK,
1073 };
1074
1075 /* - TSN0 ------------------------------------------------ */
1076 static const unsigned int tsn0_link_a_pins[] = {
1077 /* TSN0_LINK_A */
1078 RCAR_GP_PIN(0, 11),
1079 };
1080 static const unsigned int tsn0_link_a_mux[] = {
1081 TSN0_LINK_A_MARK,
1082 };
1083 static const unsigned int tsn0_magic_a_pins[] = {
1084 /* TSN0_MAGIC_A */
1085 RCAR_GP_PIN(0, 17),
1086 };
1087 static const unsigned int tsn0_magic_a_mux[] = {
1088 TSN0_MAGIC_A_MARK,
1089 };
1090 static const unsigned int tsn0_phy_int_a_pins[] = {
1091 /* TSN0_PHY_INT_A */
1092 RCAR_GP_PIN(0, 18),
1093 };
1094 static const unsigned int tsn0_phy_int_a_mux[] = {
1095 TSN0_PHY_INT_A_MARK,
1096 };
1097 static const unsigned int tsn0_mdio_a_pins[] = {
1098 /* TSN0_MDC_A, TSN0_MDIO_A */
1099 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1100 };
1101 static const unsigned int tsn0_mdio_a_mux[] = {
1102 TSN0_MDC_A_MARK, TSN0_MDIO_A_MARK,
1103 };
1104 static const unsigned int tsn0_link_b_pins[] = {
1105 /* TSN0_LINK_B */
1106 RCAR_GP_PIN(3, 8),
1107 };
1108 static const unsigned int tsn0_link_b_mux[] = {
1109 TSN0_LINK_B_MARK,
1110 };
1111 static const unsigned int tsn0_magic_b_pins[] = {
1112 /* TSN0_MAGIC_B */
1113 RCAR_GP_PIN(3, 12),
1114 };
1115 static const unsigned int tsn0_magic_b_mux[] = {
1116 TSN0_MAGIC_B_MARK,
1117 };
1118 static const unsigned int tsn0_phy_int_b_pins[] = {
1119 /* TSN0_PHY_INT_B */
1120 RCAR_GP_PIN(3, 10),
1121 };
1122 static const unsigned int tsn0_phy_int_b_mux[] = {
1123 TSN0_PHY_INT_B_MARK,
1124 };
1125 static const unsigned int tsn0_mdio_b_pins[] = {
1126 /* TSN0_MDC_B, TSN0_MDIO_B */
1127 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 2),
1128 };
1129 static const unsigned int tsn0_mdio_b_mux[] = {
1130 TSN0_MDC_B_MARK, TSN0_MDIO_B_MARK,
1131 };
1132 static const unsigned int tsn0_avtp_pps_pins[] = {
1133 /* TSN0_AVTP_PPS */
1134 RCAR_GP_PIN(3, 16),
1135 };
1136 static const unsigned int tsn0_avtp_pps_mux[] = {
1137 TSN0_AVTP_PPS_MARK,
1138 };
1139 static const unsigned int tsn0_avtp_capture_a_pins[] = {
1140 /* TSN0_AVTP_CAPTURE_A */
1141 RCAR_GP_PIN(0, 1),
1142 };
1143 static const unsigned int tsn0_avtp_capture_a_mux[] = {
1144 TSN0_AVTP_CAPTURE_A_MARK,
1145 };
1146 static const unsigned int tsn0_avtp_match_a_pins[] = {
1147 /* TSN0_AVTP_MATCH_A */
1148 RCAR_GP_PIN(0, 2),
1149 };
1150 static const unsigned int tsn0_avtp_match_a_mux[] = {
1151 TSN0_AVTP_MATCH_A_MARK,
1152 };
1153 static const unsigned int tsn0_avtp_capture_b_pins[] = {
1154 /* TSN0_AVTP_CAPTURE_B */
1155 RCAR_GP_PIN(3, 18),
1156 };
1157 static const unsigned int tsn0_avtp_capture_b_mux[] = {
1158 TSN0_AVTP_CAPTURE_B_MARK,
1159 };
1160 static const unsigned int tsn0_avtp_match_b_pins[] = {
1161 /* TSN0_AVTP_MATCH_B */
1162 RCAR_GP_PIN(3, 17),
1163 };
1164 static const unsigned int tsn0_avtp_match_b_mux[] = {
1165 TSN0_AVTP_MATCH_B_MARK,
1166 };
1167
1168 /* - TSN1 ------------------------------------------------ */
1169 static const unsigned int tsn1_link_a_pins[] = {
1170 /* TSN1_LINK_A */
1171 RCAR_GP_PIN(0, 15),
1172 };
1173 static const unsigned int tsn1_link_a_mux[] = {
1174 TSN1_LINK_A_MARK,
1175 };
1176 static const unsigned int tsn1_phy_int_a_pins[] = {
1177 /* TSN1_PHY_INT_A */
1178 RCAR_GP_PIN(0, 19),
1179 };
1180 static const unsigned int tsn1_phy_int_a_mux[] = {
1181 TSN1_PHY_INT_A_MARK,
1182 };
1183 static const unsigned int tsn1_mdio_a_pins[] = {
1184 /* TSN1_MDC_A, TSN1_MDIO_A */
1185 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
1186 };
1187 static const unsigned int tsn1_mdio_a_mux[] = {
1188 TSN1_MDC_A_MARK, TSN1_MDIO_A_MARK,
1189 };
1190 static const unsigned int tsn1_link_b_pins[] = {
1191 /* TSN1_LINK_B */
1192 RCAR_GP_PIN(3, 6),
1193 };
1194 static const unsigned int tsn1_link_b_mux[] = {
1195 TSN1_LINK_B_MARK,
1196 };
1197 static const unsigned int tsn1_phy_int_b_pins[] = {
1198 /* TSN1_PHY_INT_B */
1199 RCAR_GP_PIN(3, 11),
1200 };
1201 static const unsigned int tsn1_phy_int_b_mux[] = {
1202 TSN1_PHY_INT_B_MARK,
1203 };
1204 static const unsigned int tsn1_mdio_b_pins[] = {
1205 /* TSN1_MDC_B, TSN1_MDIO_B */
1206 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
1207 };
1208 static const unsigned int tsn1_mdio_b_mux[] = {
1209 TSN1_MDC_B_MARK, TSN1_MDIO_B_MARK,
1210 };
1211 static const unsigned int tsn1_avtp_pps_pins[] = {
1212 /* TSN1_AVTP_PPS */
1213 RCAR_GP_PIN(3, 13),
1214 };
1215 static const unsigned int tsn1_avtp_pps_mux[] = {
1216 TSN1_AVTP_PPS_MARK,
1217 };
1218 static const unsigned int tsn1_avtp_capture_a_pins[] = {
1219 /* TSN1_AVTP_CAPTURE_A */
1220 RCAR_GP_PIN(0, 7),
1221 };
1222 static const unsigned int tsn1_avtp_capture_a_mux[] = {
1223 TSN1_AVTP_CAPTURE_A_MARK,
1224 };
1225 static const unsigned int tsn1_avtp_match_a_pins[] = {
1226 /* TSN1_AVTP_MATCH_A */
1227 RCAR_GP_PIN(0, 6),
1228 };
1229 static const unsigned int tsn1_avtp_match_a_mux[] = {
1230 TSN1_AVTP_MATCH_A_MARK,
1231 };
1232 static const unsigned int tsn1_avtp_capture_b_pins[] = {
1233 /* TSN1_AVTP_CAPTURE_B */
1234 RCAR_GP_PIN(3, 15),
1235 };
1236 static const unsigned int tsn1_avtp_capture_b_mux[] = {
1237 TSN1_AVTP_CAPTURE_B_MARK,
1238 };
1239 static const unsigned int tsn1_avtp_match_b_pins[] = {
1240 /* TSN1_AVTP_MATCH_B */
1241 RCAR_GP_PIN(3, 14),
1242 };
1243 static const unsigned int tsn1_avtp_match_b_mux[] = {
1244 TSN1_AVTP_MATCH_B_MARK,
1245 };
1246
1247 /* - TSN2 ------------------------------------------------ */
1248 static const unsigned int tsn2_link_a_pins[] = {
1249 /* TSN2_LINK_A */
1250 RCAR_GP_PIN(0, 16),
1251 };
1252 static const unsigned int tsn2_link_a_mux[] = {
1253 TSN2_LINK_A_MARK,
1254 };
1255 static const unsigned int tsn2_phy_int_a_pins[] = {
1256 /* TSN2_PHY_INT_A */
1257 RCAR_GP_PIN(0, 20),
1258 };
1259 static const unsigned int tsn2_phy_int_a_mux[] = {
1260 TSN2_PHY_INT_A_MARK,
1261 };
1262 static const unsigned int tsn2_mdio_a_pins[] = {
1263 /* TSN2_MDC_A, TSN2_MDIO_A */
1264 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
1265 };
1266 static const unsigned int tsn2_mdio_a_mux[] = {
1267 TSN2_MDC_A_MARK, TSN2_MDIO_A_MARK,
1268 };
1269 static const unsigned int tsn2_link_b_pins[] = {
1270 /* TSN2_LINK_B */
1271 RCAR_GP_PIN(3, 7),
1272 };
1273 static const unsigned int tsn2_link_b_mux[] = {
1274 TSN2_LINK_B_MARK,
1275 };
1276 static const unsigned int tsn2_phy_int_b_pins[] = {
1277 /* TSN2_PHY_INT_B */
1278 RCAR_GP_PIN(3, 9),
1279 };
1280 static const unsigned int tsn2_phy_int_b_mux[] = {
1281 TSN2_PHY_INT_B_MARK,
1282 };
1283 static const unsigned int tsn2_mdio_b_pins[] = {
1284 /* TSN2_MDC_B, TSN2_MDIO_B */
1285 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 1),
1286 };
1287 static const unsigned int tsn2_mdio_b_mux[] = {
1288 TSN2_MDC_B_MARK, TSN2_MDIO_B_MARK,
1289 };
1290
1291 static const struct sh_pfc_pin_group pinmux_groups[] = {
1292 SH_PFC_PIN_GROUP(hscif0_data),
1293 SH_PFC_PIN_GROUP(hscif0_clk),
1294 SH_PFC_PIN_GROUP(hscif0_ctrl),
1295 SH_PFC_PIN_GROUP(hscif1_data),
1296 SH_PFC_PIN_GROUP(hscif1_clk),
1297 SH_PFC_PIN_GROUP(hscif1_ctrl),
1298 SH_PFC_PIN_GROUP(hscif2_data),
1299 SH_PFC_PIN_GROUP(hscif2_clk),
1300 SH_PFC_PIN_GROUP(hscif2_ctrl),
1301 SH_PFC_PIN_GROUP(hscif3_data),
1302 SH_PFC_PIN_GROUP(hscif3_clk),
1303 SH_PFC_PIN_GROUP(hscif3_ctrl),
1304 SH_PFC_PIN_GROUP(i2c0),
1305 SH_PFC_PIN_GROUP(i2c1),
1306 SH_PFC_PIN_GROUP(i2c2),
1307 SH_PFC_PIN_GROUP(i2c3),
1308 SH_PFC_PIN_GROUP(i2c4),
1309 SH_PFC_PIN_GROUP(i2c5),
1310 SH_PFC_PIN_GROUP(intc_ex_irq0),
1311 SH_PFC_PIN_GROUP(intc_ex_irq1),
1312 SH_PFC_PIN_GROUP(intc_ex_irq2),
1313 SH_PFC_PIN_GROUP(intc_ex_irq3),
1314 SH_PFC_PIN_GROUP(intc_ex_irq4),
1315 SH_PFC_PIN_GROUP(intc_ex_irq5),
1316 BUS_DATA_PIN_GROUP(mmc_data, 1),
1317 BUS_DATA_PIN_GROUP(mmc_data, 4),
1318 BUS_DATA_PIN_GROUP(mmc_data, 8),
1319 SH_PFC_PIN_GROUP(mmc_ctrl),
1320 SH_PFC_PIN_GROUP(mmc_cd),
1321 SH_PFC_PIN_GROUP(mmc_wp),
1322 SH_PFC_PIN_GROUP(mmc_ds),
1323 SH_PFC_PIN_GROUP(msiof0_clk),
1324 SH_PFC_PIN_GROUP(msiof0_sync),
1325 SH_PFC_PIN_GROUP(msiof0_ss1),
1326 SH_PFC_PIN_GROUP(msiof0_ss2),
1327 SH_PFC_PIN_GROUP(msiof0_txd),
1328 SH_PFC_PIN_GROUP(msiof0_rxd),
1329 SH_PFC_PIN_GROUP(msiof1_clk),
1330 SH_PFC_PIN_GROUP(msiof1_sync),
1331 SH_PFC_PIN_GROUP(msiof1_ss1),
1332 SH_PFC_PIN_GROUP(msiof1_ss2),
1333 SH_PFC_PIN_GROUP(msiof1_txd),
1334 SH_PFC_PIN_GROUP(msiof1_rxd),
1335 SH_PFC_PIN_GROUP(msiof2_clk),
1336 SH_PFC_PIN_GROUP(msiof2_sync),
1337 SH_PFC_PIN_GROUP(msiof2_ss1),
1338 SH_PFC_PIN_GROUP(msiof2_ss2),
1339 SH_PFC_PIN_GROUP(msiof2_txd),
1340 SH_PFC_PIN_GROUP(msiof2_rxd),
1341 SH_PFC_PIN_GROUP(msiof3_clk),
1342 SH_PFC_PIN_GROUP(msiof3_sync),
1343 SH_PFC_PIN_GROUP(msiof3_ss1),
1344 SH_PFC_PIN_GROUP(msiof3_ss2),
1345 SH_PFC_PIN_GROUP(msiof3_txd),
1346 SH_PFC_PIN_GROUP(msiof3_rxd),
1347 SH_PFC_PIN_GROUP(pcie0_clkreq_n),
1348 SH_PFC_PIN_GROUP(pcie1_clkreq_n),
1349 SH_PFC_PIN_GROUP(qspi0_ctrl),
1350 BUS_DATA_PIN_GROUP(qspi0_data, 2),
1351 BUS_DATA_PIN_GROUP(qspi0_data, 4),
1352 SH_PFC_PIN_GROUP(qspi1_ctrl),
1353 BUS_DATA_PIN_GROUP(qspi1_data, 2),
1354 BUS_DATA_PIN_GROUP(qspi1_data, 4),
1355 SH_PFC_PIN_GROUP(scif0_data),
1356 SH_PFC_PIN_GROUP(scif0_clk),
1357 SH_PFC_PIN_GROUP(scif0_ctrl),
1358 SH_PFC_PIN_GROUP(scif1_data),
1359 SH_PFC_PIN_GROUP(scif1_clk),
1360 SH_PFC_PIN_GROUP(scif1_ctrl),
1361 SH_PFC_PIN_GROUP(scif3_data),
1362 SH_PFC_PIN_GROUP(scif3_clk),
1363 SH_PFC_PIN_GROUP(scif3_ctrl),
1364 SH_PFC_PIN_GROUP(scif4_data),
1365 SH_PFC_PIN_GROUP(scif4_clk),
1366 SH_PFC_PIN_GROUP(scif4_ctrl),
1367 SH_PFC_PIN_GROUP(scif_clk),
1368 SH_PFC_PIN_GROUP(tsn0_link_a),
1369 SH_PFC_PIN_GROUP(tsn0_magic_a),
1370 SH_PFC_PIN_GROUP(tsn0_phy_int_a),
1371 SH_PFC_PIN_GROUP(tsn0_mdio_a),
1372 SH_PFC_PIN_GROUP(tsn0_link_b),
1373 SH_PFC_PIN_GROUP(tsn0_magic_b),
1374 SH_PFC_PIN_GROUP(tsn0_phy_int_b),
1375 SH_PFC_PIN_GROUP(tsn0_mdio_b),
1376 SH_PFC_PIN_GROUP(tsn0_avtp_pps),
1377 SH_PFC_PIN_GROUP(tsn0_avtp_capture_a),
1378 SH_PFC_PIN_GROUP(tsn0_avtp_match_a),
1379 SH_PFC_PIN_GROUP(tsn0_avtp_capture_b),
1380 SH_PFC_PIN_GROUP(tsn0_avtp_match_b),
1381 SH_PFC_PIN_GROUP(tsn1_link_a),
1382 SH_PFC_PIN_GROUP(tsn1_phy_int_a),
1383 SH_PFC_PIN_GROUP(tsn1_mdio_a),
1384 SH_PFC_PIN_GROUP(tsn1_link_b),
1385 SH_PFC_PIN_GROUP(tsn1_phy_int_b),
1386 SH_PFC_PIN_GROUP(tsn1_mdio_b),
1387 SH_PFC_PIN_GROUP(tsn1_avtp_pps),
1388 SH_PFC_PIN_GROUP(tsn1_avtp_capture_a),
1389 SH_PFC_PIN_GROUP(tsn1_avtp_match_a),
1390 SH_PFC_PIN_GROUP(tsn1_avtp_capture_b),
1391 SH_PFC_PIN_GROUP(tsn1_avtp_match_b),
1392 SH_PFC_PIN_GROUP(tsn2_link_a),
1393 SH_PFC_PIN_GROUP(tsn2_phy_int_a),
1394 SH_PFC_PIN_GROUP(tsn2_mdio_a),
1395 SH_PFC_PIN_GROUP(tsn2_link_b),
1396 SH_PFC_PIN_GROUP(tsn2_phy_int_b),
1397 SH_PFC_PIN_GROUP(tsn2_mdio_b),
1398 };
1399
1400 static const char * const hscif0_groups[] = {
1401 "hscif0_data",
1402 "hscif0_clk",
1403 "hscif0_ctrl",
1404 };
1405
1406 static const char * const hscif1_groups[] = {
1407 "hscif1_data",
1408 "hscif1_clk",
1409 "hscif1_ctrl",
1410 };
1411
1412 static const char * const hscif2_groups[] = {
1413 "hscif2_data",
1414 "hscif2_clk",
1415 "hscif2_ctrl",
1416 };
1417
1418 static const char * const hscif3_groups[] = {
1419 "hscif3_data",
1420 "hscif3_clk",
1421 "hscif3_ctrl",
1422 };
1423
1424 static const char * const i2c0_groups[] = {
1425 "i2c0",
1426 };
1427
1428 static const char * const i2c1_groups[] = {
1429 "i2c1",
1430 };
1431
1432 static const char * const i2c2_groups[] = {
1433 "i2c2",
1434 };
1435
1436 static const char * const i2c3_groups[] = {
1437 "i2c3",
1438 };
1439
1440 static const char * const i2c4_groups[] = {
1441 "i2c4",
1442 };
1443
1444 static const char * const i2c5_groups[] = {
1445 "i2c5",
1446 };
1447
1448 static const char * const intc_ex_groups[] = {
1449 "intc_ex_irq0",
1450 "intc_ex_irq1",
1451 "intc_ex_irq2",
1452 "intc_ex_irq3",
1453 "intc_ex_irq4",
1454 "intc_ex_irq5",
1455 };
1456
1457 static const char * const mmc_groups[] = {
1458 "mmc_data1",
1459 "mmc_data4",
1460 "mmc_data8",
1461 "mmc_ctrl",
1462 "mmc_cd",
1463 "mmc_wp",
1464 "mmc_ds",
1465 };
1466
1467 static const char * const msiof0_groups[] = {
1468 "msiof0_clk",
1469 "msiof0_sync",
1470 "msiof0_ss1",
1471 "msiof0_ss2",
1472 "msiof0_txd",
1473 "msiof0_rxd",
1474 };
1475
1476 static const char * const msiof1_groups[] = {
1477 "msiof1_clk",
1478 "msiof1_sync",
1479 "msiof1_ss1",
1480 "msiof1_ss2",
1481 "msiof1_txd",
1482 "msiof1_rxd",
1483 };
1484
1485 static const char * const msiof2_groups[] = {
1486 "msiof2_clk",
1487 "msiof2_sync",
1488 "msiof2_ss1",
1489 "msiof2_ss2",
1490 "msiof2_txd",
1491 "msiof2_rxd",
1492 };
1493
1494 static const char * const msiof3_groups[] = {
1495 "msiof3_clk",
1496 "msiof3_sync",
1497 "msiof3_ss1",
1498 "msiof3_ss2",
1499 "msiof3_txd",
1500 "msiof3_rxd",
1501 };
1502
1503 static const char * const pcie_groups[] = {
1504 "pcie0_clkreq_n",
1505 "pcie1_clkreq_n",
1506 };
1507
1508 static const char * const qspi0_groups[] = {
1509 "qspi0_ctrl",
1510 "qspi0_data2",
1511 "qspi0_data4",
1512 };
1513
1514 static const char * const qspi1_groups[] = {
1515 "qspi1_ctrl",
1516 "qspi1_data2",
1517 "qspi1_data4",
1518 };
1519
1520 static const char * const scif0_groups[] = {
1521 "scif0_data",
1522 "scif0_clk",
1523 "scif0_ctrl",
1524 };
1525
1526 static const char * const scif1_groups[] = {
1527 "scif1_data",
1528 "scif1_clk",
1529 "scif1_ctrl",
1530 };
1531
1532 static const char * const scif3_groups[] = {
1533 "scif3_data",
1534 "scif3_clk",
1535 "scif3_ctrl",
1536 };
1537
1538 static const char * const scif4_groups[] = {
1539 "scif4_data",
1540 "scif4_clk",
1541 "scif4_ctrl",
1542 };
1543
1544 static const char * const scif_clk_groups[] = {
1545 "scif_clk",
1546 };
1547
1548 static const char * const tsn0_groups[] = {
1549 "tsn0_link_a",
1550 "tsn0_magic_a",
1551 "tsn0_phy_int_a",
1552 "tsn0_mdio_a",
1553 "tsn0_link_b",
1554 "tsn0_magic_b",
1555 "tsn0_phy_int_b",
1556 "tsn0_mdio_b",
1557 "tsn0_avtp_pps",
1558 "tsn0_avtp_capture_a",
1559 "tsn0_avtp_match_a",
1560 "tsn0_avtp_capture_b",
1561 "tsn0_avtp_match_b",
1562 };
1563
1564 static const char * const tsn1_groups[] = {
1565 "tsn1_link_a",
1566 "tsn1_phy_int_a",
1567 "tsn1_mdio_a",
1568 "tsn1_link_b",
1569 "tsn1_phy_int_b",
1570 "tsn1_mdio_b",
1571 "tsn1_avtp_pps",
1572 "tsn1_avtp_capture_a",
1573 "tsn1_avtp_match_a",
1574 "tsn1_avtp_capture_b",
1575 "tsn1_avtp_match_b",
1576 };
1577
1578 static const char * const tsn2_groups[] = {
1579 "tsn2_link_a",
1580 "tsn2_phy_int_a",
1581 "tsn2_mdio_a",
1582 "tsn2_link_b",
1583 "tsn2_phy_int_b",
1584 "tsn2_mdio_b",
1585 };
1586
1587 static const struct sh_pfc_function pinmux_functions[] = {
1588 SH_PFC_FUNCTION(hscif0),
1589 SH_PFC_FUNCTION(hscif1),
1590 SH_PFC_FUNCTION(hscif2),
1591 SH_PFC_FUNCTION(hscif3),
1592 SH_PFC_FUNCTION(i2c0),
1593 SH_PFC_FUNCTION(i2c1),
1594 SH_PFC_FUNCTION(i2c2),
1595 SH_PFC_FUNCTION(i2c3),
1596 SH_PFC_FUNCTION(i2c4),
1597 SH_PFC_FUNCTION(i2c5),
1598 SH_PFC_FUNCTION(intc_ex),
1599 SH_PFC_FUNCTION(mmc),
1600 SH_PFC_FUNCTION(msiof0),
1601 SH_PFC_FUNCTION(msiof1),
1602 SH_PFC_FUNCTION(msiof2),
1603 SH_PFC_FUNCTION(msiof3),
1604 SH_PFC_FUNCTION(pcie),
1605 SH_PFC_FUNCTION(qspi0),
1606 SH_PFC_FUNCTION(qspi1),
1607 SH_PFC_FUNCTION(scif0),
1608 SH_PFC_FUNCTION(scif1),
1609 SH_PFC_FUNCTION(scif3),
1610 SH_PFC_FUNCTION(scif4),
1611 SH_PFC_FUNCTION(scif_clk),
1612 SH_PFC_FUNCTION(tsn0),
1613 SH_PFC_FUNCTION(tsn1),
1614 SH_PFC_FUNCTION(tsn2),
1615 };
1616
1617 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1618 #define F_(x, y) FN_##y
1619 #define FM(x) FN_##x
1620 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6050040, 32,
1621 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1622 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
1623 GROUP(
1624 /* GP0_31_21 RESERVED */
1625 GP_0_20_FN, GPSR0_20,
1626 GP_0_19_FN, GPSR0_19,
1627 GP_0_18_FN, GPSR0_18,
1628 GP_0_17_FN, GPSR0_17,
1629 GP_0_16_FN, GPSR0_16,
1630 GP_0_15_FN, GPSR0_15,
1631 GP_0_14_FN, GPSR0_14,
1632 GP_0_13_FN, GPSR0_13,
1633 GP_0_12_FN, GPSR0_12,
1634 GP_0_11_FN, GPSR0_11,
1635 GP_0_10_FN, GPSR0_10,
1636 GP_0_9_FN, GPSR0_9,
1637 GP_0_8_FN, GPSR0_8,
1638 GP_0_7_FN, GPSR0_7,
1639 GP_0_6_FN, GPSR0_6,
1640 GP_0_5_FN, GPSR0_5,
1641 GP_0_4_FN, GPSR0_4,
1642 GP_0_3_FN, GPSR0_3,
1643 GP_0_2_FN, GPSR0_2,
1644 GP_0_1_FN, GPSR0_1,
1645 GP_0_0_FN, GPSR0_0, ))
1646 },
1647 { PINMUX_CFG_REG_VAR("GPSR1", 0xe6050840, 32,
1648 GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1649 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
1650 GROUP(
1651 /* GP1_31_25 RESERVED */
1652 GP_1_24_FN, GPSR1_24,
1653 GP_1_23_FN, GPSR1_23,
1654 GP_1_22_FN, GPSR1_22,
1655 GP_1_21_FN, GPSR1_21,
1656 GP_1_20_FN, GPSR1_20,
1657 GP_1_19_FN, GPSR1_19,
1658 GP_1_18_FN, GPSR1_18,
1659 GP_1_17_FN, GPSR1_17,
1660 GP_1_16_FN, GPSR1_16,
1661 GP_1_15_FN, GPSR1_15,
1662 GP_1_14_FN, GPSR1_14,
1663 GP_1_13_FN, GPSR1_13,
1664 GP_1_12_FN, GPSR1_12,
1665 GP_1_11_FN, GPSR1_11,
1666 GP_1_10_FN, GPSR1_10,
1667 GP_1_9_FN, GPSR1_9,
1668 GP_1_8_FN, GPSR1_8,
1669 GP_1_7_FN, GPSR1_7,
1670 GP_1_6_FN, GPSR1_6,
1671 GP_1_5_FN, GPSR1_5,
1672 GP_1_4_FN, GPSR1_4,
1673 GP_1_3_FN, GPSR1_3,
1674 GP_1_2_FN, GPSR1_2,
1675 GP_1_1_FN, GPSR1_1,
1676 GP_1_0_FN, GPSR1_0, ))
1677 },
1678 { PINMUX_CFG_REG_VAR("GPSR2", 0xe6051040, 32,
1679 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1680 1, 1, 1, 1, 1, 1),
1681 GROUP(
1682 /* GP2_31_17 RESERVED */
1683 GP_2_16_FN, GPSR2_16,
1684 GP_2_15_FN, GPSR2_15,
1685 GP_2_14_FN, GPSR2_14,
1686 GP_2_13_FN, GPSR2_13,
1687 GP_2_12_FN, GPSR2_12,
1688 GP_2_11_FN, GPSR2_11,
1689 GP_2_10_FN, GPSR2_10,
1690 GP_2_9_FN, GPSR2_9,
1691 GP_2_8_FN, GPSR2_8,
1692 GP_2_7_FN, GPSR2_7,
1693 GP_2_6_FN, GPSR2_6,
1694 GP_2_5_FN, GPSR2_5,
1695 GP_2_4_FN, GPSR2_4,
1696 GP_2_3_FN, GPSR2_3,
1697 GP_2_2_FN, GPSR2_2,
1698 GP_2_1_FN, GPSR2_1,
1699 GP_2_0_FN, GPSR2_0, ))
1700 },
1701 { PINMUX_CFG_REG_VAR("GPSR3", 0xe6051840, 32,
1702 GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1703 1, 1, 1, 1, 1, 1, 1, 1),
1704 GROUP(
1705 /* GP3_31_19 RESERVED */
1706 GP_3_18_FN, GPSR3_18,
1707 GP_3_17_FN, GPSR3_17,
1708 GP_3_16_FN, GPSR3_16,
1709 GP_3_15_FN, GPSR3_15,
1710 GP_3_14_FN, GPSR3_14,
1711 GP_3_13_FN, GPSR3_13,
1712 GP_3_12_FN, GPSR3_12,
1713 GP_3_11_FN, GPSR3_11,
1714 GP_3_10_FN, GPSR3_10,
1715 GP_3_9_FN, GPSR3_9,
1716 GP_3_8_FN, GPSR3_8,
1717 GP_3_7_FN, GPSR3_7,
1718 GP_3_6_FN, GPSR3_6,
1719 GP_3_5_FN, GPSR3_5,
1720 GP_3_4_FN, GPSR3_4,
1721 GP_3_3_FN, GPSR3_3,
1722 GP_3_2_FN, GPSR3_2,
1723 GP_3_1_FN, GPSR3_1,
1724 GP_3_0_FN, GPSR3_0, ))
1725 },
1726 #undef F_
1727 #undef FM
1728
1729 #define F_(x, y) x,
1730 #define FM(x) FN_##x,
1731 { PINMUX_CFG_REG("IP0SR0", 0xe6050060, 32, 4, GROUP(
1732 IP0SR0_31_28
1733 IP0SR0_27_24
1734 IP0SR0_23_20
1735 IP0SR0_19_16
1736 IP0SR0_15_12
1737 IP0SR0_11_8
1738 IP0SR0_7_4
1739 IP0SR0_3_0))
1740 },
1741 { PINMUX_CFG_REG("IP1SR0", 0xe6050064, 32, 4, GROUP(
1742 IP1SR0_31_28
1743 IP1SR0_27_24
1744 IP1SR0_23_20
1745 IP1SR0_19_16
1746 IP1SR0_15_12
1747 IP1SR0_11_8
1748 IP1SR0_7_4
1749 IP1SR0_3_0))
1750 },
1751 { PINMUX_CFG_REG_VAR("IP2SR0", 0xe6050068, 32,
1752 GROUP(-12, 4, 4, 4, 4, 4),
1753 GROUP(
1754 /* IP2SR0_31_20 RESERVED */
1755 IP2SR0_19_16
1756 IP2SR0_15_12
1757 IP2SR0_11_8
1758 IP2SR0_7_4
1759 IP2SR0_3_0))
1760 },
1761 { PINMUX_CFG_REG("IP0SR1", 0xe6050860, 32, 4, GROUP(
1762 IP0SR1_31_28
1763 IP0SR1_27_24
1764 IP0SR1_23_20
1765 IP0SR1_19_16
1766 IP0SR1_15_12
1767 IP0SR1_11_8
1768 IP0SR1_7_4
1769 IP0SR1_3_0))
1770 },
1771 #undef F_
1772 #undef FM
1773
1774 #define F_(x, y) x,
1775 #define FM(x) FN_##x,
1776 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6050900, 32,
1777 GROUP(-20, 2, 2, 2, 2, 2, 2),
1778 GROUP(
1779 /* RESERVED 31-12 */
1780 MOD_SEL1_11_10
1781 MOD_SEL1_9_8
1782 MOD_SEL1_7_6
1783 MOD_SEL1_5_4
1784 MOD_SEL1_3_2
1785 MOD_SEL1_1_0))
1786 },
1787 { /* sentinel */ }
1788 };
1789
1790 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
1791 { PINMUX_DRIVE_REG("DRV0CTRL0", 0xe6050080) {
1792 { RCAR_GP_PIN(0, 7), 28, 3 }, /* TX0 */
1793 { RCAR_GP_PIN(0, 6), 24, 3 }, /* RX0 */
1794 { RCAR_GP_PIN(0, 5), 20, 3 }, /* HRTS0_N */
1795 { RCAR_GP_PIN(0, 4), 16, 3 }, /* HCTS0_N */
1796 { RCAR_GP_PIN(0, 3), 12, 3 }, /* HTX0 */
1797 { RCAR_GP_PIN(0, 2), 8, 3 }, /* HRX0 */
1798 { RCAR_GP_PIN(0, 1), 4, 3 }, /* HSCK0 */
1799 { RCAR_GP_PIN(0, 0), 0, 3 }, /* SCIF_CLK */
1800 } },
1801 { PINMUX_DRIVE_REG("DRV1CTRL0", 0xe6050084) {
1802 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF0_SS1 */
1803 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF0_SCK */
1804 { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF0_TXD */
1805 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF0_RXD */
1806 { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF0_SYNC */
1807 { RCAR_GP_PIN(0, 10), 8, 3 }, /* CTS0_N */
1808 { RCAR_GP_PIN(0, 9), 4, 3 }, /* RTS0_N */
1809 { RCAR_GP_PIN(0, 8), 0, 3 }, /* SCK0 */
1810 } },
1811 { PINMUX_DRIVE_REG("DRV2CTRL0", 0xe6050088) {
1812 { RCAR_GP_PIN(0, 20), 16, 3 }, /* IRQ3 */
1813 { RCAR_GP_PIN(0, 19), 12, 3 }, /* IRQ2 */
1814 { RCAR_GP_PIN(0, 18), 8, 3 }, /* IRQ1 */
1815 { RCAR_GP_PIN(0, 17), 4, 3 }, /* IRQ0 */
1816 { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF0_SS2 */
1817 } },
1818 { PINMUX_DRIVE_REG("DRV0CTRL1", 0xe6050880) {
1819 { RCAR_GP_PIN(1, 7), 28, 3 }, /* GP1_07 */
1820 { RCAR_GP_PIN(1, 6), 24, 3 }, /* GP1_06 */
1821 { RCAR_GP_PIN(1, 5), 20, 3 }, /* GP1_05 */
1822 { RCAR_GP_PIN(1, 4), 16, 3 }, /* GP1_04 */
1823 { RCAR_GP_PIN(1, 3), 12, 3 }, /* GP1_03 */
1824 { RCAR_GP_PIN(1, 2), 8, 3 }, /* GP1_02 */
1825 { RCAR_GP_PIN(1, 1), 4, 3 }, /* GP1_01 */
1826 { RCAR_GP_PIN(1, 0), 0, 3 }, /* GP1_00 */
1827 } },
1828 { PINMUX_DRIVE_REG("DRV1CTRL1", 0xe6050884) {
1829 { RCAR_GP_PIN(1, 15), 28, 3 }, /* MMC_SD_D2 */
1830 { RCAR_GP_PIN(1, 14), 24, 3 }, /* MMC_SD_D1 */
1831 { RCAR_GP_PIN(1, 13), 20, 3 }, /* MMC_SD_D0 */
1832 { RCAR_GP_PIN(1, 12), 16, 3 }, /* MMC_SD_CLK */
1833 { RCAR_GP_PIN(1, 11), 12, 3 }, /* GP1_11 */
1834 { RCAR_GP_PIN(1, 10), 8, 3 }, /* GP1_10 */
1835 { RCAR_GP_PIN(1, 9), 4, 3 }, /* GP1_09 */
1836 { RCAR_GP_PIN(1, 8), 0, 3 }, /* GP1_08 */
1837 } },
1838 { PINMUX_DRIVE_REG("DRV2CTRL1", 0xe6050888) {
1839 { RCAR_GP_PIN(1, 23), 28, 3 }, /* SD_CD */
1840 { RCAR_GP_PIN(1, 22), 24, 3 }, /* MMC_SD_CMD */
1841 { RCAR_GP_PIN(1, 21), 20, 3 }, /* MMC_D7 */
1842 { RCAR_GP_PIN(1, 20), 16, 3 }, /* MMC_DS */
1843 { RCAR_GP_PIN(1, 19), 12, 3 }, /* MMC_D6 */
1844 { RCAR_GP_PIN(1, 18), 8, 3 }, /* MMC_D4 */
1845 { RCAR_GP_PIN(1, 17), 4, 3 }, /* MMC_D5 */
1846 { RCAR_GP_PIN(1, 16), 0, 3 }, /* MMC_SD_D3 */
1847 } },
1848 { PINMUX_DRIVE_REG("DRV3CTRL1", 0xe605088c) {
1849 { RCAR_GP_PIN(1, 24), 0, 3 }, /* SD_WP */
1850 } },
1851 { PINMUX_DRIVE_REG("DRV0CTRL2", 0xe6051080) {
1852 { RCAR_GP_PIN(2, 7), 28, 2 }, /* QSPI1_MOSI_IO0 */
1853 { RCAR_GP_PIN(2, 6), 24, 2 }, /* QSPI1_IO2 */
1854 { RCAR_GP_PIN(2, 5), 20, 2 }, /* QSPI1_MISO_IO1 */
1855 { RCAR_GP_PIN(2, 4), 16, 2 }, /* QSPI1_IO3 */
1856 { RCAR_GP_PIN(2, 3), 12, 2 }, /* QSPI1_SSL */
1857 { RCAR_GP_PIN(2, 2), 8, 2 }, /* RPC_RESET_N */
1858 { RCAR_GP_PIN(2, 1), 4, 2 }, /* RPC_WP_N */
1859 { RCAR_GP_PIN(2, 0), 0, 2 }, /* RPC_INT_N */
1860 } },
1861 { PINMUX_DRIVE_REG("DRV1CTRL2", 0xe6051084) {
1862 { RCAR_GP_PIN(2, 15), 28, 3 }, /* PCIE0_CLKREQ_N */
1863 { RCAR_GP_PIN(2, 14), 24, 2 }, /* QSPI0_IO3 */
1864 { RCAR_GP_PIN(2, 13), 20, 2 }, /* QSPI0_SSL */
1865 { RCAR_GP_PIN(2, 12), 16, 2 }, /* QSPI0_MISO_IO1 */
1866 { RCAR_GP_PIN(2, 11), 12, 2 }, /* QSPI0_IO2 */
1867 { RCAR_GP_PIN(2, 10), 8, 2 }, /* QSPI0_SPCLK */
1868 { RCAR_GP_PIN(2, 9), 4, 2 }, /* QSPI0_MOSI_IO0 */
1869 { RCAR_GP_PIN(2, 8), 0, 2 }, /* QSPI1_SPCLK */
1870 } },
1871 { PINMUX_DRIVE_REG("DRV2CTRL2", 0xe6051088) {
1872 { RCAR_GP_PIN(2, 16), 0, 3 }, /* PCIE1_CLKREQ_N */
1873 } },
1874 { PINMUX_DRIVE_REG("DRV0CTRL3", 0xe6051880) {
1875 { RCAR_GP_PIN(3, 7), 28, 3 }, /* TSN2_LINK_B */
1876 { RCAR_GP_PIN(3, 6), 24, 3 }, /* TSN1_LINK_B */
1877 { RCAR_GP_PIN(3, 5), 20, 3 }, /* TSN1_MDC_B */
1878 { RCAR_GP_PIN(3, 4), 16, 3 }, /* TSN0_MDC_B */
1879 { RCAR_GP_PIN(3, 3), 12, 3 }, /* TSN2_MDC_B */
1880 { RCAR_GP_PIN(3, 2), 8, 3 }, /* TSN0_MDIO_B */
1881 { RCAR_GP_PIN(3, 1), 4, 3 }, /* TSN2_MDIO_B */
1882 { RCAR_GP_PIN(3, 0), 0, 3 }, /* TSN1_MDIO_B */
1883 } },
1884 { PINMUX_DRIVE_REG("DRV1CTRL3", 0xe6051884) {
1885 { RCAR_GP_PIN(3, 15), 28, 3 }, /* TSN1_AVTP_CAPTURE_B */
1886 { RCAR_GP_PIN(3, 14), 24, 3 }, /* TSN1_AVTP_MATCH_B */
1887 { RCAR_GP_PIN(3, 13), 20, 3 }, /* TSN1_AVTP_PPS */
1888 { RCAR_GP_PIN(3, 12), 16, 3 }, /* TSN0_MAGIC_B */
1889 { RCAR_GP_PIN(3, 11), 12, 3 }, /* TSN1_PHY_INT_B */
1890 { RCAR_GP_PIN(3, 10), 8, 3 }, /* TSN0_PHY_INT_B */
1891 { RCAR_GP_PIN(3, 9), 4, 3 }, /* TSN2_PHY_INT_B */
1892 { RCAR_GP_PIN(3, 8), 0, 3 }, /* TSN0_LINK_B */
1893 } },
1894 { PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6051888) {
1895 { RCAR_GP_PIN(3, 18), 8, 3 }, /* TSN0_AVTP_CAPTURE_B */
1896 { RCAR_GP_PIN(3, 17), 4, 3 }, /* TSN0_AVTP_MATCH_B */
1897 { RCAR_GP_PIN(3, 16), 0, 3 }, /* TSN0_AVTP_PPS */
1898 } },
1899 { /* sentinel */ }
1900 };
1901
1902 enum ioctrl_regs {
1903 POC0,
1904 POC1,
1905 POC3,
1906 TD0SEL1,
1907 };
1908
1909 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
1910 [POC0] = { 0xe60500a0, },
1911 [POC1] = { 0xe60508a0, },
1912 [POC3] = { 0xe60518a0, },
1913 [TD0SEL1] = { 0xe6050920, },
1914 { /* sentinel */ }
1915 };
1916
1917 static int r8a779f0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
1918 {
1919 int bit = pin & 0x1f;
1920
1921 *pocctrl = pinmux_ioctrl_regs[POC0].reg;
1922 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 20))
1923 return bit;
1924
1925 *pocctrl = pinmux_ioctrl_regs[POC1].reg;
1926 if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 24))
1927 return bit;
1928
1929 *pocctrl = pinmux_ioctrl_regs[POC3].reg;
1930 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 18))
1931 return bit;
1932
1933 return -EINVAL;
1934 }
1935
1936 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
1937 { PINMUX_BIAS_REG("PUEN0", 0xe60500c0, "PUD0", 0xe60500e0) {
1938 [ 0] = RCAR_GP_PIN(0, 0), /* SCIF_CLK */
1939 [ 1] = RCAR_GP_PIN(0, 1), /* HSCK0 */
1940 [ 2] = RCAR_GP_PIN(0, 2), /* HRX0 */
1941 [ 3] = RCAR_GP_PIN(0, 3), /* HTX0 */
1942 [ 4] = RCAR_GP_PIN(0, 4), /* HCTS0_N */
1943 [ 5] = RCAR_GP_PIN(0, 5), /* HRTS0_N */
1944 [ 6] = RCAR_GP_PIN(0, 6), /* RX0 */
1945 [ 7] = RCAR_GP_PIN(0, 7), /* TX0 */
1946 [ 8] = RCAR_GP_PIN(0, 8), /* SCK0 */
1947 [ 9] = RCAR_GP_PIN(0, 9), /* RTS0_N */
1948 [10] = RCAR_GP_PIN(0, 10), /* CTS0_N */
1949 [11] = RCAR_GP_PIN(0, 11), /* MSIOF0_SYNC */
1950 [12] = RCAR_GP_PIN(0, 12), /* MSIOF0_RXD */
1951 [13] = RCAR_GP_PIN(0, 13), /* MSIOF0_TXD */
1952 [14] = RCAR_GP_PIN(0, 14), /* MSIOF0_SCK */
1953 [15] = RCAR_GP_PIN(0, 15), /* MSIOF0_SS1 */
1954 [16] = RCAR_GP_PIN(0, 16), /* MSIOF0_SS2 */
1955 [17] = RCAR_GP_PIN(0, 17), /* IRQ0 */
1956 [18] = RCAR_GP_PIN(0, 18), /* IRQ1 */
1957 [19] = RCAR_GP_PIN(0, 19), /* IRQ2 */
1958 [20] = RCAR_GP_PIN(0, 20), /* IRQ3 */
1959 [21] = SH_PFC_PIN_NONE,
1960 [22] = SH_PFC_PIN_NONE,
1961 [23] = SH_PFC_PIN_NONE,
1962 [24] = SH_PFC_PIN_NONE,
1963 [25] = SH_PFC_PIN_NONE,
1964 [26] = SH_PFC_PIN_NONE,
1965 [27] = SH_PFC_PIN_NONE,
1966 [28] = SH_PFC_PIN_NONE,
1967 [29] = SH_PFC_PIN_NONE,
1968 [30] = SH_PFC_PIN_NONE,
1969 [31] = SH_PFC_PIN_NONE,
1970 } },
1971 { PINMUX_BIAS_REG("PUEN1", 0xe60508c0, "PUD1", 0xe60508e0) {
1972 [ 0] = RCAR_GP_PIN(1, 0), /* GP1_00 */
1973 [ 1] = RCAR_GP_PIN(1, 1), /* GP1_01 */
1974 [ 2] = RCAR_GP_PIN(1, 2), /* GP1_02 */
1975 [ 3] = RCAR_GP_PIN(1, 3), /* GP1_03 */
1976 [ 4] = RCAR_GP_PIN(1, 4), /* GP1_04 */
1977 [ 5] = RCAR_GP_PIN(1, 5), /* GP1_05 */
1978 [ 6] = RCAR_GP_PIN(1, 6), /* GP1_06 */
1979 [ 7] = RCAR_GP_PIN(1, 7), /* GP1_07 */
1980 [ 8] = RCAR_GP_PIN(1, 8), /* GP1_08 */
1981 [ 9] = RCAR_GP_PIN(1, 9), /* GP1_09 */
1982 [10] = RCAR_GP_PIN(1, 10), /* GP1_10 */
1983 [11] = RCAR_GP_PIN(1, 11), /* GP1_11 */
1984 [12] = RCAR_GP_PIN(1, 12), /* MMC_SD_CLK */
1985 [13] = RCAR_GP_PIN(1, 13), /* MMC_SD_D0 */
1986 [14] = RCAR_GP_PIN(1, 14), /* MMC_SD_D1 */
1987 [15] = RCAR_GP_PIN(1, 15), /* MMC_SD_D2 */
1988 [16] = RCAR_GP_PIN(1, 16), /* MMC_SD_D3 */
1989 [17] = RCAR_GP_PIN(1, 17), /* MMC_D5 */
1990 [18] = RCAR_GP_PIN(1, 18), /* MMC_D4 */
1991 [19] = RCAR_GP_PIN(1, 19), /* MMC_D6 */
1992 [20] = RCAR_GP_PIN(1, 20), /* MMC_DS */
1993 [21] = RCAR_GP_PIN(1, 21), /* MMC_D7 */
1994 [22] = RCAR_GP_PIN(1, 22), /* MMC_SD_CMD */
1995 [23] = RCAR_GP_PIN(1, 23), /* SD_CD */
1996 [24] = RCAR_GP_PIN(1, 24), /* SD_WP */
1997 [25] = SH_PFC_PIN_NONE,
1998 [26] = SH_PFC_PIN_NONE,
1999 [27] = SH_PFC_PIN_NONE,
2000 [28] = SH_PFC_PIN_NONE,
2001 [29] = SH_PFC_PIN_NONE,
2002 [30] = SH_PFC_PIN_NONE,
2003 [31] = SH_PFC_PIN_NONE,
2004 } },
2005 { PINMUX_BIAS_REG("PUEN2", 0xe60510c0, "PUD2", 0xe60510e0) {
2006 [ 0] = RCAR_GP_PIN(2, 0), /* RPC_INT_N */
2007 [ 1] = RCAR_GP_PIN(2, 1), /* RPC_WP_N */
2008 [ 2] = RCAR_GP_PIN(2, 2), /* RPC_RESET_N */
2009 [ 3] = RCAR_GP_PIN(2, 3), /* QSPI1_SSL */
2010 [ 4] = RCAR_GP_PIN(2, 4), /* QSPI1_IO3 */
2011 [ 5] = RCAR_GP_PIN(2, 5), /* QSPI1_MISO_IO1 */
2012 [ 6] = RCAR_GP_PIN(2, 6), /* QSPI1_IO2 */
2013 [ 7] = RCAR_GP_PIN(2, 7), /* QSPI1_MOSI_IO0 */
2014 [ 8] = RCAR_GP_PIN(2, 8), /* QSPI1_SPCLK */
2015 [ 9] = RCAR_GP_PIN(2, 9), /* QSPI0_MOSI_IO0 */
2016 [10] = RCAR_GP_PIN(2, 10), /* QSPI0_SPCLK */
2017 [11] = RCAR_GP_PIN(2, 11), /* QSPI0_IO2 */
2018 [12] = RCAR_GP_PIN(2, 12), /* QSPI0_MISO_IO1 */
2019 [13] = RCAR_GP_PIN(2, 13), /* QSPI0_SSL */
2020 [14] = RCAR_GP_PIN(2, 14), /* QSPI0_IO3 */
2021 [15] = RCAR_GP_PIN(2, 15), /* PCIE0_CLKREQ_N */
2022 [16] = RCAR_GP_PIN(2, 16), /* PCIE1_CLKREQ_N */
2023 [17] = SH_PFC_PIN_NONE,
2024 [18] = SH_PFC_PIN_NONE,
2025 [19] = SH_PFC_PIN_NONE,
2026 [20] = SH_PFC_PIN_NONE,
2027 [21] = SH_PFC_PIN_NONE,
2028 [22] = SH_PFC_PIN_NONE,
2029 [23] = SH_PFC_PIN_NONE,
2030 [24] = SH_PFC_PIN_NONE,
2031 [25] = SH_PFC_PIN_NONE,
2032 [26] = SH_PFC_PIN_NONE,
2033 [27] = SH_PFC_PIN_NONE,
2034 [28] = SH_PFC_PIN_NONE,
2035 [29] = SH_PFC_PIN_NONE,
2036 [30] = SH_PFC_PIN_NONE,
2037 [31] = SH_PFC_PIN_NONE,
2038 } },
2039 { PINMUX_BIAS_REG("PUEN3", 0xe60518c0, "PUD3", 0xe60518e0) {
2040 [ 0] = RCAR_GP_PIN(3, 0), /* TSN1_MDIO_B */
2041 [ 1] = RCAR_GP_PIN(3, 1), /* TSN2_MDIO_B */
2042 [ 2] = RCAR_GP_PIN(3, 2), /* TSN0_MDIO_B */
2043 [ 3] = RCAR_GP_PIN(3, 3), /* TSN2_MDC_B */
2044 [ 4] = RCAR_GP_PIN(3, 4), /* TSN0_MDC_B */
2045 [ 5] = RCAR_GP_PIN(3, 5), /* TSN1_MDC_B */
2046 [ 6] = RCAR_GP_PIN(3, 6), /* TSN1_LINK_B */
2047 [ 7] = RCAR_GP_PIN(3, 7), /* TSN2_LINK_B */
2048 [ 8] = RCAR_GP_PIN(3, 8), /* TSN0_LINK_B */
2049 [ 9] = RCAR_GP_PIN(3, 9), /* TSN2_PHY_INT_B */
2050 [10] = RCAR_GP_PIN(3, 10), /* TSN0_PHY_INT_B */
2051 [11] = RCAR_GP_PIN(3, 11), /* TSN1_PHY_INT_B */
2052 [12] = RCAR_GP_PIN(3, 12), /* TSN0_MAGIC_B */
2053 [13] = RCAR_GP_PIN(3, 13), /* TSN1_AVTP_PPS */
2054 [14] = RCAR_GP_PIN(3, 14), /* TSN1_AVTP_MATCH_B */
2055 [15] = RCAR_GP_PIN(3, 15), /* TSN1_AVTP_CAPTURE_B */
2056 [16] = RCAR_GP_PIN(3, 16), /* TSN0_AVTP_PPS */
2057 [17] = RCAR_GP_PIN(3, 17), /* TSN0_AVTP_MATCH_B */
2058 [18] = RCAR_GP_PIN(3, 18), /* TSN0_AVTP_CAPTURE_B */
2059 [19] = SH_PFC_PIN_NONE,
2060 [20] = SH_PFC_PIN_NONE,
2061 [21] = SH_PFC_PIN_NONE,
2062 [22] = SH_PFC_PIN_NONE,
2063 [23] = SH_PFC_PIN_NONE,
2064 [24] = SH_PFC_PIN_NONE,
2065 [25] = SH_PFC_PIN_NONE,
2066 [26] = SH_PFC_PIN_NONE,
2067 [27] = SH_PFC_PIN_NONE,
2068 [28] = SH_PFC_PIN_NONE,
2069 [29] = SH_PFC_PIN_NONE,
2070 [30] = SH_PFC_PIN_NONE,
2071 [31] = SH_PFC_PIN_NONE,
2072 } },
2073 { /* sentinel */ }
2074 };
2075
2076 static const struct sh_pfc_soc_operations r8a779f0_pfc_ops = {
2077 .pin_to_pocctrl = r8a779f0_pin_to_pocctrl,
2078 .get_bias = rcar_pinmux_get_bias,
2079 .set_bias = rcar_pinmux_set_bias,
2080 };
2081
2082 const struct sh_pfc_soc_info r8a779f0_pinmux_info = {
2083 .name = "r8a779f0_pfc",
2084 .ops = &r8a779f0_pfc_ops,
2085 .unlock_reg = 0x1ff, /* PMMRn mask */
2086
2087 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2088
2089 .pins = pinmux_pins,
2090 .nr_pins = ARRAY_SIZE(pinmux_pins),
2091 .groups = pinmux_groups,
2092 .nr_groups = ARRAY_SIZE(pinmux_groups),
2093 .functions = pinmux_functions,
2094 .nr_functions = ARRAY_SIZE(pinmux_functions),
2095
2096 .cfg_regs = pinmux_config_regs,
2097 .drive_regs = pinmux_drive_regs,
2098 .bias_regs = pinmux_bias_regs,
2099 .ioctrl_regs = pinmux_ioctrl_regs,
2100
2101 .pinmux_data = pinmux_data,
2102 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2103 };
Kernel DRM miscellaneous fixes and cross-tree changes