drivers/pinctrl/renesas/pinctrl-rzn1.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2014-2018 Renesas Electronics Europe Limited
   4  *
   5  * Phil Edworthy <phil.edworthy@renesas.com>
   6  * Based on a driver originally written by Michel Pollet at Renesas.
   7  */
   8
   9 #include <dt-bindings/pinctrl/rzn1-pinctrl.h>
  10
  11 #include <linux/clk.h>
  12 #include <linux/device.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/slab.h>
  18
  19 #include <linux/pinctrl/pinconf-generic.h>
  20 #include <linux/pinctrl/pinconf.h>
  21 #include <linux/pinctrl/pinctrl.h>
  22 #include <linux/pinctrl/pinmux.h>
  23
  24 #include "../core.h"
  25 #include "../pinconf.h"
  26 #include "../pinctrl-utils.h"
  27
  28 /* Field positions and masks in the pinmux registers */
  29 #define RZN1_L1_PIN_DRIVE_STRENGTH      10
  30 #define RZN1_L1_PIN_DRIVE_STRENGTH_4MA  0
  31 #define RZN1_L1_PIN_DRIVE_STRENGTH_6MA  1
  32 #define RZN1_L1_PIN_DRIVE_STRENGTH_8MA  2
  33 #define RZN1_L1_PIN_DRIVE_STRENGTH_12MA 3
  34 #define RZN1_L1_PIN_PULL                8
  35 #define RZN1_L1_PIN_PULL_NONE           0
  36 #define RZN1_L1_PIN_PULL_UP             1
  37 #define RZN1_L1_PIN_PULL_DOWN           3
  38 #define RZN1_L1_FUNCTION                0
  39 #define RZN1_L1_FUNC_MASK               0xf
  40 #define RZN1_L1_FUNCTION_L2             0xf
  41
  42 /*
  43  * The hardware manual describes two levels of multiplexing, but it's more
  44  * logical to think of the hardware as three levels, with level 3 consisting of
  45  * the multiplexing for Ethernet MDIO signals.
  46  *
  47  * Level 1 functions go from 0 to 9, with level 1 function '15' (0xf) specifying
  48  * that level 2 functions are used instead. Level 2 has a lot more options,
  49  * going from 0 to 61. Level 3 allows selection of MDIO functions which can be
  50  * floating, or one of seven internal peripherals. Unfortunately, there are two
  51  * level 2 functions that can select MDIO, and two MDIO channels so we have four
  52  * sets of level 3 functions.
  53  *
  54  * For this driver, we've compounded the numbers together, so:
  55  *    0 to   9 is level 1
  56  *   10 to  71 is 10 + level 2 number
  57  *   72 to  79 is 72 + MDIO0 source for level 2 MDIO function.
  58  *   80 to  87 is 80 + MDIO0 source for level 2 MDIO_E1 function.
  59  *   88 to  95 is 88 + MDIO1 source for level 2 MDIO function.
  60  *   96 to 103 is 96 + MDIO1 source for level 2 MDIO_E1 function.
  61  * Examples:
  62  *  Function 28 corresponds UART0
  63  *  Function 73 corresponds to MDIO0 to GMAC0
  64  *
  65  * There are 170 configurable pins (called PL_GPIO in the datasheet).
  66  */
  67
  68 /*
  69  * Structure detailing the HW registers on the RZ/N1 devices.
  70  * Both the Level 1 mux registers and Level 2 mux registers have the same
  71  * structure. The only difference is that Level 2 has additional MDIO registers
  72  * at the end.
  73  */
  74 struct rzn1_pinctrl_regs {
  75         u32     conf[170];
  76         u32     pad0[86];
  77         u32     status_protect; /* 0x400 */
  78         /* MDIO mux registers, level2 only */
  79         u32     l2_mdio[2];
  80 };
  81
  82 /**
  83  * struct rzn1_pmx_func - describes rzn1 pinmux functions
  84  * @name: the name of this specific function
  85  * @groups: corresponding pin groups
  86  * @num_groups: the number of groups
  87  */
  88 struct rzn1_pmx_func {
  89         const char *name;
  90         const char **groups;
  91         unsigned int num_groups;
  92 };
  93
  94 /**
  95  * struct rzn1_pin_group - describes an rzn1 pin group
  96  * @name: the name of this specific pin group
  97  * @func: the name of the function selected by this group
  98  * @npins: the number of pins in this group array, i.e. the number of
  99  *      elements in .pins so we can iterate over that array
 100  * @pins: array of pins. Needed due to pinctrl_ops.get_group_pins()
 101  * @pin_ids: array of pin_ids, i.e. the value used to select the mux
 102  */
 103 struct rzn1_pin_group {
 104         const char *name;
 105         const char *func;
 106         unsigned int npins;
 107         unsigned int *pins;
 108         u8 *pin_ids;
 109 };
 110
 111 struct rzn1_pinctrl {
 112         struct device *dev;
 113         struct clk *clk;
 114         struct pinctrl_dev *pctl;
 115         struct rzn1_pinctrl_regs __iomem *lev1;
 116         struct rzn1_pinctrl_regs __iomem *lev2;
 117         u32 lev1_protect_phys;
 118         u32 lev2_protect_phys;
 119         int mdio_func[2];
 120
 121         struct rzn1_pin_group *groups;
 122         unsigned int ngroups;
 123
 124         struct rzn1_pmx_func *functions;
 125         unsigned int nfunctions;
 126 };
 127
 128 #define RZN1_PINS_PROP "pinmux"
 129
 130 #define RZN1_PIN(pin) PINCTRL_PIN(pin, "pl_gpio"#pin)
 131
 132 static const struct pinctrl_pin_desc rzn1_pins[] = {
 133         RZN1_PIN(0), RZN1_PIN(1), RZN1_PIN(2), RZN1_PIN(3), RZN1_PIN(4),
 134         RZN1_PIN(5), RZN1_PIN(6), RZN1_PIN(7), RZN1_PIN(8), RZN1_PIN(9),
 135         RZN1_PIN(10), RZN1_PIN(11), RZN1_PIN(12), RZN1_PIN(13), RZN1_PIN(14),
 136         RZN1_PIN(15), RZN1_PIN(16), RZN1_PIN(17), RZN1_PIN(18), RZN1_PIN(19),
 137         RZN1_PIN(20), RZN1_PIN(21), RZN1_PIN(22), RZN1_PIN(23), RZN1_PIN(24),
 138         RZN1_PIN(25), RZN1_PIN(26), RZN1_PIN(27), RZN1_PIN(28), RZN1_PIN(29),
 139         RZN1_PIN(30), RZN1_PIN(31), RZN1_PIN(32), RZN1_PIN(33), RZN1_PIN(34),
 140         RZN1_PIN(35), RZN1_PIN(36), RZN1_PIN(37), RZN1_PIN(38), RZN1_PIN(39),
 141         RZN1_PIN(40), RZN1_PIN(41), RZN1_PIN(42), RZN1_PIN(43), RZN1_PIN(44),
 142         RZN1_PIN(45), RZN1_PIN(46), RZN1_PIN(47), RZN1_PIN(48), RZN1_PIN(49),
 143         RZN1_PIN(50), RZN1_PIN(51), RZN1_PIN(52), RZN1_PIN(53), RZN1_PIN(54),
 144         RZN1_PIN(55), RZN1_PIN(56), RZN1_PIN(57), RZN1_PIN(58), RZN1_PIN(59),
 145         RZN1_PIN(60), RZN1_PIN(61), RZN1_PIN(62), RZN1_PIN(63), RZN1_PIN(64),
 146         RZN1_PIN(65), RZN1_PIN(66), RZN1_PIN(67), RZN1_PIN(68), RZN1_PIN(69),
 147         RZN1_PIN(70), RZN1_PIN(71), RZN1_PIN(72), RZN1_PIN(73), RZN1_PIN(74),
 148         RZN1_PIN(75), RZN1_PIN(76), RZN1_PIN(77), RZN1_PIN(78), RZN1_PIN(79),
 149         RZN1_PIN(80), RZN1_PIN(81), RZN1_PIN(82), RZN1_PIN(83), RZN1_PIN(84),
 150         RZN1_PIN(85), RZN1_PIN(86), RZN1_PIN(87), RZN1_PIN(88), RZN1_PIN(89),
 151         RZN1_PIN(90), RZN1_PIN(91), RZN1_PIN(92), RZN1_PIN(93), RZN1_PIN(94),
 152         RZN1_PIN(95), RZN1_PIN(96), RZN1_PIN(97), RZN1_PIN(98), RZN1_PIN(99),
 153         RZN1_PIN(100), RZN1_PIN(101), RZN1_PIN(102), RZN1_PIN(103),
 154         RZN1_PIN(104), RZN1_PIN(105), RZN1_PIN(106), RZN1_PIN(107),
 155         RZN1_PIN(108), RZN1_PIN(109), RZN1_PIN(110), RZN1_PIN(111),
 156         RZN1_PIN(112), RZN1_PIN(113), RZN1_PIN(114), RZN1_PIN(115),
 157         RZN1_PIN(116), RZN1_PIN(117), RZN1_PIN(118), RZN1_PIN(119),
 158         RZN1_PIN(120), RZN1_PIN(121), RZN1_PIN(122), RZN1_PIN(123),
 159         RZN1_PIN(124), RZN1_PIN(125), RZN1_PIN(126), RZN1_PIN(127),
 160         RZN1_PIN(128), RZN1_PIN(129), RZN1_PIN(130), RZN1_PIN(131),
 161         RZN1_PIN(132), RZN1_PIN(133), RZN1_PIN(134), RZN1_PIN(135),
 162         RZN1_PIN(136), RZN1_PIN(137), RZN1_PIN(138), RZN1_PIN(139),
 163         RZN1_PIN(140), RZN1_PIN(141), RZN1_PIN(142), RZN1_PIN(143),
 164         RZN1_PIN(144), RZN1_PIN(145), RZN1_PIN(146), RZN1_PIN(147),
 165         RZN1_PIN(148), RZN1_PIN(149), RZN1_PIN(150), RZN1_PIN(151),
 166         RZN1_PIN(152), RZN1_PIN(153), RZN1_PIN(154), RZN1_PIN(155),
 167         RZN1_PIN(156), RZN1_PIN(157), RZN1_PIN(158), RZN1_PIN(159),
 168         RZN1_PIN(160), RZN1_PIN(161), RZN1_PIN(162), RZN1_PIN(163),
 169         RZN1_PIN(164), RZN1_PIN(165), RZN1_PIN(166), RZN1_PIN(167),
 170         RZN1_PIN(168), RZN1_PIN(169),
 171 };
 172
 173 enum {
 174         LOCK_LEVEL1 = 0x1,
 175         LOCK_LEVEL2 = 0x2,
 176         LOCK_ALL = LOCK_LEVEL1 | LOCK_LEVEL2,
 177 };
 178
 179 static void rzn1_hw_set_lock(struct rzn1_pinctrl *ipctl, u8 lock, u8 value)
 180 {
 181         /*
 182          * The pinmux configuration is locked by writing the physical address of
 183          * the status_protect register to itself. It is unlocked by writing the
 184          * address | 1.
 185          */
 186         if (lock & LOCK_LEVEL1) {
 187                 u32 val = ipctl->lev1_protect_phys | !(value & LOCK_LEVEL1);
 188
 189                 writel(val, &ipctl->lev1->status_protect);
 190         }
 191
 192         if (lock & LOCK_LEVEL2) {
 193                 u32 val = ipctl->lev2_protect_phys | !(value & LOCK_LEVEL2);
 194
 195                 writel(val, &ipctl->lev2->status_protect);
 196         }
 197 }
 198
 199 static void rzn1_pinctrl_mdio_select(struct rzn1_pinctrl *ipctl, int mdio,
 200                                      u32 func)
 201 {
 202         if (ipctl->mdio_func[mdio] >= 0 && ipctl->mdio_func[mdio] != func)
 203                 dev_warn(ipctl->dev, "conflicting setting for mdio%d!\n", mdio);
 204         ipctl->mdio_func[mdio] = func;
 205
 206         dev_dbg(ipctl->dev, "setting mdio%d to %u\n", mdio, func);
 207
 208         writel(func, &ipctl->lev2->l2_mdio[mdio]);
 209 }
 210
 211 /*
 212  * Using a composite pin description, set the hardware pinmux registers
 213  * with the corresponding values.
 214  * Make sure to unlock write protection and reset it afterward.
 215  *
 216  * NOTE: There is no protection for potential concurrency, it is assumed these
 217  * calls are serialized already.
 218  */
 219 static int rzn1_set_hw_pin_func(struct rzn1_pinctrl *ipctl, unsigned int pin,
 220                                 u32 pin_config, u8 use_locks)
 221 {
 222         u32 l1_cache;
 223         u32 l2_cache;
 224         u32 l1;
 225         u32 l2;
 226
 227         /* Level 3 MDIO multiplexing */
 228         if (pin_config >= RZN1_FUNC_MDIO0_HIGHZ &&
 229             pin_config <= RZN1_FUNC_MDIO1_E1_SWITCH) {
 230                 int mdio_channel;
 231                 u32 mdio_func;
 232
 233                 if (pin_config <= RZN1_FUNC_MDIO1_HIGHZ)
 234                         mdio_channel = 0;
 235                 else
 236                         mdio_channel = 1;
 237
 238                 /* Get MDIO func, and convert the func to the level 2 number */
 239                 if (pin_config <= RZN1_FUNC_MDIO0_SWITCH) {
 240                         mdio_func = pin_config - RZN1_FUNC_MDIO0_HIGHZ;
 241                         pin_config = RZN1_FUNC_ETH_MDIO;
 242                 } else if (pin_config <= RZN1_FUNC_MDIO0_E1_SWITCH) {
 243                         mdio_func = pin_config - RZN1_FUNC_MDIO0_E1_HIGHZ;
 244                         pin_config = RZN1_FUNC_ETH_MDIO_E1;
 245                 } else if (pin_config <= RZN1_FUNC_MDIO1_SWITCH) {
 246                         mdio_func = pin_config - RZN1_FUNC_MDIO1_HIGHZ;
 247                         pin_config = RZN1_FUNC_ETH_MDIO;
 248                 } else {
 249                         mdio_func = pin_config - RZN1_FUNC_MDIO1_E1_HIGHZ;
 250                         pin_config = RZN1_FUNC_ETH_MDIO_E1;
 251                 }
 252                 rzn1_pinctrl_mdio_select(ipctl, mdio_channel, mdio_func);
 253         }
 254
 255         /* Note here, we do not allow anything past the MDIO Mux values */
 256         if (pin >= ARRAY_SIZE(ipctl->lev1->conf) ||
 257             pin_config >= RZN1_FUNC_MDIO0_HIGHZ)
 258                 return -EINVAL;
 259
 260         l1 = readl(&ipctl->lev1->conf[pin]);
 261         l1_cache = l1;
 262         l2 = readl(&ipctl->lev2->conf[pin]);
 263         l2_cache = l2;
 264
 265         dev_dbg(ipctl->dev, "setting func for pin %u to %u\n", pin, pin_config);
 266
 267         l1 &= ~(RZN1_L1_FUNC_MASK << RZN1_L1_FUNCTION);
 268
 269         if (pin_config < RZN1_FUNC_L2_OFFSET) {
 270                 l1 |= (pin_config << RZN1_L1_FUNCTION);
 271         } else {
 272                 l1 |= (RZN1_L1_FUNCTION_L2 << RZN1_L1_FUNCTION);
 273
 274                 l2 = pin_config - RZN1_FUNC_L2_OFFSET;
 275         }
 276
 277         /* If either configuration changes, we update both anyway */
 278         if (l1 != l1_cache || l2 != l2_cache) {
 279                 writel(l1, &ipctl->lev1->conf[pin]);
 280                 writel(l2, &ipctl->lev2->conf[pin]);
 281         }
 282
 283         return 0;
 284 }
 285
 286 static const struct rzn1_pin_group *rzn1_pinctrl_find_group_by_name(
 287         const struct rzn1_pinctrl *ipctl, const char *name)
 288 {
 289         unsigned int i;
 290
 291         for (i = 0; i < ipctl->ngroups; i++) {
 292                 if (!strcmp(ipctl->groups[i].name, name))
 293                         return &ipctl->groups[i];
 294         }
 295
 296         return NULL;
 297 }
 298
 299 static int rzn1_get_groups_count(struct pinctrl_dev *pctldev)
 300 {
 301         struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 302
 303         return ipctl->ngroups;
 304 }
 305
 306 static const char *rzn1_get_group_name(struct pinctrl_dev *pctldev,
 307                                        unsigned int selector)
 308 {
 309         struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 310
 311         return ipctl->groups[selector].name;
 312 }
 313
 314 static int rzn1_get_group_pins(struct pinctrl_dev *pctldev,
 315                                unsigned int selector, const unsigned int **pins,
 316                                unsigned int *npins)
 317 {
 318         struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 319
 320         if (selector >= ipctl->ngroups)
 321                 return -EINVAL;
 322
 323         *pins = ipctl->groups[selector].pins;
 324         *npins = ipctl->groups[selector].npins;
 325
 326         return 0;
 327 }
 328
 329 /*
 330  * This function is called for each pinctl 'Function' node.
 331  * Sub-nodes can be used to describe multiple 'Groups' for the 'Function'
 332  * If there aren't any sub-nodes, the 'Group' is essentially the 'Function'.
 333  * Each 'Group' uses pinmux = <...> to detail the pins and data used to select
 334  * the functionality. Each 'Group' has optional pin configurations that apply
 335  * to all pins in the 'Group'.
 336  */
 337 static int rzn1_dt_node_to_map_one(struct pinctrl_dev *pctldev,
 338                                    struct device_node *np,
 339                                    struct pinctrl_map **map,
 340                                    unsigned int *num_maps)
 341 {
 342         struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 343         const struct rzn1_pin_group *grp;
 344         unsigned long *configs = NULL;
 345         unsigned int reserved_maps = *num_maps;
 346         unsigned int num_configs = 0;
 347         unsigned int reserve = 1;
 348         int ret;
 349
 350         dev_dbg(ipctl->dev, "processing node %pOF\n", np);
 351
 352         grp = rzn1_pinctrl_find_group_by_name(ipctl, np->name);
 353         if (!grp) {
 354                 dev_err(ipctl->dev, "unable to find group for node %pOF\n", np);
 355
 356                 return -EINVAL;
 357         }
 358
 359         /* Get the group's pin configuration */
 360         ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
 361                                               &num_configs);
 362         if (ret < 0) {
 363                 dev_err(ipctl->dev, "%pOF: could not parse property\n", np);
 364
 365                 return ret;
 366         }
 367
 368         if (num_configs)
 369                 reserve++;
 370
 371         /* Increase the number of maps to cover this group */
 372         ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps,
 373                                         reserve);
 374         if (ret < 0)
 375                 goto out;
 376
 377         /* Associate the group with the function */
 378         ret = pinctrl_utils_add_map_mux(pctldev, map, &reserved_maps, num_maps,
 379                                         grp->name, grp->func);
 380         if (ret < 0)
 381                 goto out;
 382
 383         if (num_configs) {
 384                 /* Associate the group's pin configuration with the group */
 385                 ret = pinctrl_utils_add_map_configs(pctldev, map,
 386                                 &reserved_maps, num_maps, grp->name,
 387                                 configs, num_configs,
 388                                 PIN_MAP_TYPE_CONFIGS_GROUP);
 389                 if (ret < 0)
 390                         goto out;
 391         }
 392
 393         dev_dbg(pctldev->dev, "maps: function %s group %s (%d pins)\n",
 394                 grp->func, grp->name, grp->npins);
 395
 396 out:
 397         kfree(configs);
 398
 399         return ret;
 400 }
 401
 402 static int rzn1_dt_node_to_map(struct pinctrl_dev *pctldev,
 403                                struct device_node *np,
 404                                struct pinctrl_map **map,
 405                                unsigned int *num_maps)
 406 {
 407         int ret;
 408
 409         *map = NULL;
 410         *num_maps = 0;
 411
 412         ret = rzn1_dt_node_to_map_one(pctldev, np, map, num_maps);
 413         if (ret < 0)
 414                 return ret;
 415
 416         for_each_child_of_node_scoped(np, child) {
 417                 ret = rzn1_dt_node_to_map_one(pctldev, child, map, num_maps);
 418                 if (ret < 0)
 419                         return ret;
 420         }
 421
 422         return 0;
 423 }
 424
 425 static const struct pinctrl_ops rzn1_pctrl_ops = {
 426         .get_groups_count = rzn1_get_groups_count,
 427         .get_group_name = rzn1_get_group_name,
 428         .get_group_pins = rzn1_get_group_pins,
 429         .dt_node_to_map = rzn1_dt_node_to_map,
 430         .dt_free_map = pinctrl_utils_free_map,
 431 };
 432
 433 static int rzn1_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 434 {
 435         struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 436
 437         return ipctl->nfunctions;
 438 }
 439
 440 static const char *rzn1_pmx_get_func_name(struct pinctrl_dev *pctldev,
 441                                           unsigned int selector)
 442 {
 443         struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 444
 445         return ipctl->functions[selector].name;
 446 }
 447
 448 static int rzn1_pmx_get_groups(struct pinctrl_dev *pctldev,
 449                                unsigned int selector,
 450                                const char * const **groups,
 451                                unsigned int * const num_groups)
 452 {
 453         struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 454
 455         *groups = ipctl->functions[selector].groups;
 456         *num_groups = ipctl->functions[selector].num_groups;
 457
 458         return 0;
 459 }
 460
 461 static int rzn1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
 462                         unsigned int group)
 463 {
 464         struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 465         struct rzn1_pin_group *grp = &ipctl->groups[group];
 466         unsigned int i, grp_pins = grp->npins;
 467
 468         dev_dbg(ipctl->dev, "set mux %s(%d) group %s(%d)\n",
 469                 ipctl->functions[selector].name, selector, grp->name, group);
 470
 471         rzn1_hw_set_lock(ipctl, LOCK_ALL, LOCK_ALL);
 472         for (i = 0; i < grp_pins; i++)
 473                 rzn1_set_hw_pin_func(ipctl, grp->pins[i], grp->pin_ids[i], 0);
 474         rzn1_hw_set_lock(ipctl, LOCK_ALL, 0);
 475
 476         return 0;
 477 }
 478
 479 static const struct pinmux_ops rzn1_pmx_ops = {
 480         .get_functions_count = rzn1_pmx_get_funcs_count,
 481         .get_function_name = rzn1_pmx_get_func_name,
 482         .get_function_groups = rzn1_pmx_get_groups,
 483         .set_mux = rzn1_set_mux,
 484 };
 485
 486 static int rzn1_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
 487                             unsigned long *config)
 488 {
 489         struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 490         enum pin_config_param param = pinconf_to_config_param(*config);
 491         static const u32 reg_drive[4] = { 4, 6, 8, 12 };
 492         u32 pull, drive, l1mux;
 493         u32 l1, l2, arg = 0;
 494
 495         if (pin >= ARRAY_SIZE(ipctl->lev1->conf))
 496                 return -EINVAL;
 497
 498         l1 = readl(&ipctl->lev1->conf[pin]);
 499
 500         l1mux = l1 & RZN1_L1_FUNC_MASK;
 501         pull = (l1 >> RZN1_L1_PIN_PULL) & 0x3;
 502         drive = (l1 >> RZN1_L1_PIN_DRIVE_STRENGTH) & 0x3;
 503
 504         switch (param) {
 505         case PIN_CONFIG_BIAS_PULL_UP:
 506                 if (pull != RZN1_L1_PIN_PULL_UP)
 507                         return -EINVAL;
 508                 break;
 509         case PIN_CONFIG_BIAS_PULL_DOWN:
 510                 if (pull != RZN1_L1_PIN_PULL_DOWN)
 511                         return -EINVAL;
 512                 break;
 513         case PIN_CONFIG_BIAS_DISABLE:
 514                 if (pull != RZN1_L1_PIN_PULL_NONE)
 515                         return -EINVAL;
 516                 break;
 517         case PIN_CONFIG_DRIVE_STRENGTH:
 518                 arg = reg_drive[drive];
 519                 break;
 520         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 521                 l2 = readl(&ipctl->lev2->conf[pin]);
 522                 if (l1mux == RZN1_L1_FUNCTION_L2) {
 523                         if (l2 != 0)
 524                                 return -EINVAL;
 525                 } else if (l1mux != RZN1_FUNC_HIGHZ) {
 526                         return -EINVAL;
 527                 }
 528                 break;
 529         default:
 530                 return -ENOTSUPP;
 531         }
 532
 533         *config = pinconf_to_config_packed(param, arg);
 534
 535         return 0;
 536 }
 537
 538 static int rzn1_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 539                             unsigned long *configs, unsigned int num_configs)
 540 {
 541         struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 542         enum pin_config_param param;
 543         unsigned int i;
 544         u32 l1, l1_cache;
 545         u32 drv;
 546         u32 arg;
 547
 548         if (pin >= ARRAY_SIZE(ipctl->lev1->conf))
 549                 return -EINVAL;
 550
 551         l1 = readl(&ipctl->lev1->conf[pin]);
 552         l1_cache = l1;
 553
 554         for (i = 0; i < num_configs; i++) {
 555                 param = pinconf_to_config_param(configs[i]);
 556                 arg = pinconf_to_config_argument(configs[i]);
 557
 558                 switch (param) {
 559                 case PIN_CONFIG_BIAS_PULL_UP:
 560                         dev_dbg(ipctl->dev, "set pin %d pull up\n", pin);
 561                         l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
 562                         l1 |= (RZN1_L1_PIN_PULL_UP << RZN1_L1_PIN_PULL);
 563                         break;
 564                 case PIN_CONFIG_BIAS_PULL_DOWN:
 565                         dev_dbg(ipctl->dev, "set pin %d pull down\n", pin);
 566                         l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
 567                         l1 |= (RZN1_L1_PIN_PULL_DOWN << RZN1_L1_PIN_PULL);
 568                         break;
 569                 case PIN_CONFIG_BIAS_DISABLE:
 570                         dev_dbg(ipctl->dev, "set pin %d bias off\n", pin);
 571                         l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
 572                         l1 |= (RZN1_L1_PIN_PULL_NONE << RZN1_L1_PIN_PULL);
 573                         break;
 574                 case PIN_CONFIG_DRIVE_STRENGTH:
 575                         dev_dbg(ipctl->dev, "set pin %d drv %umA\n", pin, arg);
 576                         switch (arg) {
 577                         case 4:
 578                                 drv = RZN1_L1_PIN_DRIVE_STRENGTH_4MA;
 579                                 break;
 580                         case 6:
 581                                 drv = RZN1_L1_PIN_DRIVE_STRENGTH_6MA;
 582                                 break;
 583                         case 8:
 584                                 drv = RZN1_L1_PIN_DRIVE_STRENGTH_8MA;
 585                                 break;
 586                         case 12:
 587                                 drv = RZN1_L1_PIN_DRIVE_STRENGTH_12MA;
 588                                 break;
 589                         default:
 590                                 dev_err(ipctl->dev,
 591                                         "Drive strength %umA not supported\n",
 592                                         arg);
 593
 594                                 return -EINVAL;
 595                         }
 596
 597                         l1 &= ~(0x3 << RZN1_L1_PIN_DRIVE_STRENGTH);
 598                         l1 |= (drv << RZN1_L1_PIN_DRIVE_STRENGTH);
 599                         break;
 600
 601                 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 602                         dev_dbg(ipctl->dev, "set pin %d High-Z\n", pin);
 603                         l1 &= ~RZN1_L1_FUNC_MASK;
 604                         l1 |= RZN1_FUNC_HIGHZ;
 605                         break;
 606                 default:
 607                         return -ENOTSUPP;
 608                 }
 609         }
 610
 611         if (l1 != l1_cache) {
 612                 rzn1_hw_set_lock(ipctl, LOCK_LEVEL1, LOCK_LEVEL1);
 613                 writel(l1, &ipctl->lev1->conf[pin]);
 614                 rzn1_hw_set_lock(ipctl, LOCK_LEVEL1, 0);
 615         }
 616
 617         return 0;
 618 }
 619
 620 static int rzn1_pinconf_group_get(struct pinctrl_dev *pctldev,
 621                                   unsigned int selector,
 622                                   unsigned long *config)
 623 {
 624         struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 625         struct rzn1_pin_group *grp = &ipctl->groups[selector];
 626         unsigned long old = 0;
 627         unsigned int i;
 628
 629         dev_dbg(ipctl->dev, "group get %s selector:%u\n", grp->name, selector);
 630
 631         for (i = 0; i < grp->npins; i++) {
 632                 if (rzn1_pinconf_get(pctldev, grp->pins[i], config))
 633                         return -ENOTSUPP;
 634
 635                 /* configs do not match between two pins */
 636                 if (i && (old != *config))
 637                         return -ENOTSUPP;
 638
 639                 old = *config;
 640         }
 641
 642         return 0;
 643 }
 644
 645 static int rzn1_pinconf_group_set(struct pinctrl_dev *pctldev,
 646                                   unsigned int selector,
 647                                   unsigned long *configs,
 648                                   unsigned int num_configs)
 649 {
 650         struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 651         struct rzn1_pin_group *grp = &ipctl->groups[selector];
 652         unsigned int i;
 653         int ret;
 654
 655         dev_dbg(ipctl->dev, "group set %s selector:%u configs:%p/%d\n",
 656                 grp->name, selector, configs, num_configs);
 657
 658         for (i = 0; i < grp->npins; i++) {
 659                 unsigned int pin = grp->pins[i];
 660
 661                 ret = rzn1_pinconf_set(pctldev, pin, configs, num_configs);
 662                 if (ret)
 663                         return ret;
 664         }
 665
 666         return 0;
 667 }
 668
 669 static const struct pinconf_ops rzn1_pinconf_ops = {
 670         .is_generic = true,
 671         .pin_config_get = rzn1_pinconf_get,
 672         .pin_config_set = rzn1_pinconf_set,
 673         .pin_config_group_get = rzn1_pinconf_group_get,
 674         .pin_config_group_set = rzn1_pinconf_group_set,
 675         .pin_config_config_dbg_show = pinconf_generic_dump_config,
 676 };
 677
 678 static struct pinctrl_desc rzn1_pinctrl_desc = {
 679         .pctlops = &rzn1_pctrl_ops,
 680         .pmxops = &rzn1_pmx_ops,
 681         .confops = &rzn1_pinconf_ops,
 682         .owner = THIS_MODULE,
 683 };
 684
 685 static int rzn1_pinctrl_parse_groups(struct device_node *np,
 686                                      struct rzn1_pin_group *grp,
 687                                      struct rzn1_pinctrl *ipctl)
 688 {
 689         const __be32 *list;
 690         unsigned int i;
 691         int size;
 692
 693         dev_dbg(ipctl->dev, "%s: %s\n", __func__, np->name);
 694
 695         /* Initialise group */
 696         grp->name = np->name;
 697
 698         /*
 699          * The binding format is
 700          *      pinmux = <PIN_FUNC_ID CONFIG ...>,
 701          * do sanity check and calculate pins number
 702          */
 703         list = of_get_property(np, RZN1_PINS_PROP, &size);
 704         if (!list) {
 705                 dev_err(ipctl->dev,
 706                         "no " RZN1_PINS_PROP " property in node %pOF\n", np);
 707
 708                 return -EINVAL;
 709         }
 710
 711         if (!size) {
 712                 dev_err(ipctl->dev, "Invalid " RZN1_PINS_PROP " in node %pOF\n",
 713                         np);
 714
 715                 return -EINVAL;
 716         }
 717
 718         grp->npins = size / sizeof(list[0]);
 719         grp->pin_ids = devm_kmalloc_array(ipctl->dev,
 720                                           grp->npins, sizeof(grp->pin_ids[0]),
 721                                           GFP_KERNEL);
 722         grp->pins = devm_kmalloc_array(ipctl->dev,
 723                                        grp->npins, sizeof(grp->pins[0]),
 724                                        GFP_KERNEL);
 725         if (!grp->pin_ids || !grp->pins)
 726                 return -ENOMEM;
 727
 728         for (i = 0; i < grp->npins; i++) {
 729                 u32 pin_id = be32_to_cpu(*list++);
 730
 731                 grp->pins[i] = pin_id & 0xff;
 732                 grp->pin_ids[i] = (pin_id >> 8) & 0x7f;
 733         }
 734
 735         return grp->npins;
 736 }
 737
 738 static int rzn1_pinctrl_count_function_groups(struct device_node *np)
 739 {
 740         int count = 0;
 741
 742         if (of_property_count_u32_elems(np, RZN1_PINS_PROP) > 0)
 743                 count++;
 744
 745         for_each_child_of_node_scoped(np, child) {
 746                 if (of_property_count_u32_elems(child, RZN1_PINS_PROP) > 0)
 747                         count++;
 748         }
 749
 750         return count;
 751 }
 752
 753 static int rzn1_pinctrl_parse_functions(struct device_node *np,
 754                                         struct rzn1_pinctrl *ipctl,
 755                                         unsigned int index)
 756 {
 757         struct rzn1_pmx_func *func;
 758         struct rzn1_pin_group *grp;
 759         unsigned int i = 0;
 760         int ret;
 761
 762         func = &ipctl->functions[index];
 763
 764         /* Initialise function */
 765         func->name = np->name;
 766         func->num_groups = rzn1_pinctrl_count_function_groups(np);
 767         if (func->num_groups == 0) {
 768                 dev_err(ipctl->dev, "no groups defined in %pOF\n", np);
 769                 return -EINVAL;
 770         }
 771         dev_dbg(ipctl->dev, "function %s has %d groups\n",
 772                 np->name, func->num_groups);
 773
 774         func->groups = devm_kmalloc_array(ipctl->dev,
 775                                           func->num_groups, sizeof(char *),
 776                                           GFP_KERNEL);
 777         if (!func->groups)
 778                 return -ENOMEM;
 779
 780         if (of_property_count_u32_elems(np, RZN1_PINS_PROP) > 0) {
 781                 func->groups[i] = np->name;
 782                 grp = &ipctl->groups[ipctl->ngroups];
 783                 grp->func = func->name;
 784                 ret = rzn1_pinctrl_parse_groups(np, grp, ipctl);
 785                 if (ret < 0)
 786                         return ret;
 787                 i++;
 788                 ipctl->ngroups++;
 789         }
 790
 791         for_each_child_of_node_scoped(np, child) {
 792                 func->groups[i] = child->name;
 793                 grp = &ipctl->groups[ipctl->ngroups];
 794                 grp->func = func->name;
 795                 ret = rzn1_pinctrl_parse_groups(child, grp, ipctl);
 796                 if (ret < 0)
 797                         return ret;
 798                 i++;
 799                 ipctl->ngroups++;
 800         }
 801
 802         dev_dbg(ipctl->dev, "function %s parsed %u/%u groups\n",
 803                 np->name, i, func->num_groups);
 804
 805         return 0;
 806 }
 807
 808 static int rzn1_pinctrl_probe_dt(struct platform_device *pdev,
 809                                  struct rzn1_pinctrl *ipctl)
 810 {
 811         struct device_node *np = pdev->dev.of_node;
 812         unsigned int maxgroups = 0;
 813         unsigned int i = 0;
 814         int nfuncs = 0;
 815         int ret;
 816
 817         nfuncs = of_get_child_count(np);
 818         if (nfuncs <= 0)
 819                 return 0;
 820
 821         ipctl->nfunctions = nfuncs;
 822         ipctl->functions = devm_kmalloc_array(&pdev->dev, nfuncs,
 823                                               sizeof(*ipctl->functions),
 824                                               GFP_KERNEL);
 825         if (!ipctl->functions)
 826                 return -ENOMEM;
 827
 828         ipctl->ngroups = 0;
 829         for_each_child_of_node_scoped(np, child)
 830                 maxgroups += rzn1_pinctrl_count_function_groups(child);
 831
 832         ipctl->groups = devm_kmalloc_array(&pdev->dev,
 833                                            maxgroups,
 834                                            sizeof(*ipctl->groups),
 835                                            GFP_KERNEL);
 836         if (!ipctl->groups)
 837                 return -ENOMEM;
 838
 839         for_each_child_of_node_scoped(np, child) {
 840                 ret = rzn1_pinctrl_parse_functions(child, ipctl, i++);
 841                 if (ret < 0)
 842                         return ret;
 843         }
 844
 845         return 0;
 846 }
 847
 848 static int rzn1_pinctrl_probe(struct platform_device *pdev)
 849 {
 850         struct rzn1_pinctrl *ipctl;
 851         struct resource *res;
 852         int ret;
 853
 854         /* Create state holders etc for this driver */
 855         ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
 856         if (!ipctl)
 857                 return -ENOMEM;
 858
 859         ipctl->mdio_func[0] = -1;
 860         ipctl->mdio_func[1] = -1;
 861
 862         ipctl->lev1 = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 863         if (IS_ERR(ipctl->lev1))
 864                 return PTR_ERR(ipctl->lev1);
 865         ipctl->lev1_protect_phys = (u32)res->start + 0x400;
 866
 867         ipctl->lev2 = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
 868         if (IS_ERR(ipctl->lev2))
 869                 return PTR_ERR(ipctl->lev2);
 870         ipctl->lev2_protect_phys = (u32)res->start + 0x400;
 871
 872         ipctl->clk = devm_clk_get(&pdev->dev, NULL);
 873         if (IS_ERR(ipctl->clk))
 874                 return PTR_ERR(ipctl->clk);
 875         ret = clk_prepare_enable(ipctl->clk);
 876         if (ret)
 877                 return ret;
 878
 879         ipctl->dev = &pdev->dev;
 880         rzn1_pinctrl_desc.name = dev_name(&pdev->dev);
 881         rzn1_pinctrl_desc.pins = rzn1_pins;
 882         rzn1_pinctrl_desc.npins = ARRAY_SIZE(rzn1_pins);
 883
 884         ret = rzn1_pinctrl_probe_dt(pdev, ipctl);
 885         if (ret) {
 886                 dev_err(&pdev->dev, "fail to probe dt properties\n");
 887                 goto err_clk;
 888         }
 889
 890         platform_set_drvdata(pdev, ipctl);
 891
 892         ret = devm_pinctrl_register_and_init(&pdev->dev, &rzn1_pinctrl_desc,
 893                                              ipctl, &ipctl->pctl);
 894         if (ret) {
 895                 dev_err(&pdev->dev, "could not register rzn1 pinctrl driver\n");
 896                 goto err_clk;
 897         }
 898
 899         ret = pinctrl_enable(ipctl->pctl);
 900         if (ret)
 901                 goto err_clk;
 902
 903         dev_info(&pdev->dev, "probed\n");
 904
 905         return 0;
 906
 907 err_clk:
 908         clk_disable_unprepare(ipctl->clk);
 909
 910         return ret;
 911 }
 912
 913 static void rzn1_pinctrl_remove(struct platform_device *pdev)
 914 {
 915         struct rzn1_pinctrl *ipctl = platform_get_drvdata(pdev);
 916
 917         clk_disable_unprepare(ipctl->clk);
 918 }
 919
 920 static const struct of_device_id rzn1_pinctrl_match[] = {
 921         { .compatible = "renesas,rzn1-pinctrl", },
 922         { /* sentinel */ }
 923 };
 924 MODULE_DEVICE_TABLE(of, rzn1_pinctrl_match);
 925
 926 static struct platform_driver rzn1_pinctrl_driver = {
 927         .probe  = rzn1_pinctrl_probe,
 928         .remove = rzn1_pinctrl_remove,
 929         .driver = {
 930                 .name           = "rzn1-pinctrl",
 931                 .of_match_table = rzn1_pinctrl_match,
 932         },
 933 };
 934
 935 static int __init _pinctrl_drv_register(void)
 936 {
 937         return platform_driver_register(&rzn1_pinctrl_driver);
 938 }
 939 subsys_initcall(_pinctrl_drv_register);
 940
 941 MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
 942 MODULE_DESCRIPTION("Renesas RZ/N1 pinctrl driver");