drivers/pinctrl/spacemit/pinctrl-k1.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2024 Yixun Lan <dlan@gentoo.org> */
   3
   4 #include <linux/bits.h>
   5 #include <linux/cleanup.h>
   6 #include <linux/io.h>
   7 #include <linux/of.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/seq_file.h>
  10 #include <linux/spinlock.h>
  11 #include <linux/module.h>
  12
  13 #include <linux/pinctrl/pinconf-generic.h>
  14 #include <linux/pinctrl/pinconf.h>
  15 #include <linux/pinctrl/pinctrl.h>
  16 #include <linux/pinctrl/pinmux.h>
  17
  18 #include "../core.h"
  19 #include "../pinctrl-utils.h"
  20 #include "../pinconf.h"
  21 #include "../pinmux.h"
  22 #include "pinctrl-k1.h"
  23
  24 /*
  25  * +---------+----------+-----------+--------+--------+----------+--------+
  26  * |   pull  |   drive  | schmitter |  slew  |  edge  |  strong  |   mux  |
  27  * | up/down | strength |  trigger  |  rate  | detect |   pull   |  mode  |
  28  * +---------+----------+-----------+--------+--------+----------+--------+
  29  *   3 bits     3 bits     2 bits     1 bit    3 bits     1 bit    3 bits
  30  */
  31
  32 #define PAD_MUX                 GENMASK(2, 0)
  33 #define PAD_STRONG_PULL         BIT(3)
  34 #define PAD_EDGE_RISE           BIT(4)
  35 #define PAD_EDGE_FALL           BIT(5)
  36 #define PAD_EDGE_CLEAR          BIT(6)
  37 #define PAD_SLEW_RATE           GENMASK(12, 11)
  38 #define PAD_SLEW_RATE_EN        BIT(7)
  39 #define PAD_SCHMITT             GENMASK(9, 8)
  40 #define PAD_DRIVE               GENMASK(12, 10)
  41 #define PAD_PULLDOWN            BIT(13)
  42 #define PAD_PULLUP              BIT(14)
  43 #define PAD_PULL_EN             BIT(15)
  44
  45 struct spacemit_pin {
  46         u16                             pin;
  47         u16                             flags;
  48         u8                              gpiofunc;
  49 };
  50
  51 struct spacemit_pinctrl {
  52         struct device                           *dev;
  53         struct pinctrl_dev                      *pctl_dev;
  54         const struct spacemit_pinctrl_data      *data;
  55         struct pinctrl_desc                     pdesc;
  56
  57         struct mutex                            mutex;
  58         raw_spinlock_t                          lock;
  59
  60         void __iomem                            *regs;
  61 };
  62
  63 struct spacemit_pinctrl_data {
  64         const struct pinctrl_pin_desc   *pins;
  65         const struct spacemit_pin       *data;
  66         u16                             npins;
  67 };
  68
  69 struct spacemit_pin_mux_config {
  70         const struct spacemit_pin       *pin;
  71         u32                             config;
  72 };
  73
  74 struct spacemit_pin_drv_strength {
  75         u8              val;
  76         u32             mA;
  77 };
  78
  79 /* map pin id to pinctrl register offset, refer MFPR definition */
  80 static unsigned int spacemit_pin_to_offset(unsigned int pin)
  81 {
  82         unsigned int offset = 0;
  83
  84         switch (pin) {
  85         case 0 ... 85:
  86                 offset = pin + 1;
  87                 break;
  88         case 86 ... 92:
  89                 offset = pin + 37;
  90                 break;
  91         case 93 ... 97:
  92                 offset = pin + 24;
  93                 break;
  94         case 98:
  95                 offset = 93;
  96                 break;
  97         case 99:
  98                 offset = 92;
  99                 break;
 100         case 100:
 101                 offset = 91;
 102                 break;
 103         case 101:
 104                 offset = 90;
 105                 break;
 106         case 102:
 107                 offset = 95;
 108                 break;
 109         case 103:
 110                 offset = 94;
 111                 break;
 112         case 104 ... 110:
 113                 offset = pin + 6;
 114                 break;
 115         case 111 ... 127:
 116                 offset = pin + 20;
 117                 break;
 118         default:
 119                 break;
 120         }
 121
 122         return offset << 2;
 123 }
 124
 125 static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *pctrl,
 126                                                 unsigned int pin)
 127 {
 128         return pctrl->regs + spacemit_pin_to_offset(pin);
 129 }
 130
 131 static u16 spacemit_dt_get_pin(u32 value)
 132 {
 133         return value >> 16;
 134 }
 135
 136 static u16 spacemit_dt_get_pin_mux(u32 value)
 137 {
 138         return value & GENMASK(15, 0);
 139 }
 140
 141 static const struct spacemit_pin *spacemit_get_pin(struct spacemit_pinctrl *pctrl,
 142                                                    unsigned long pin)
 143 {
 144         const struct spacemit_pin *pdata = pctrl->data->data;
 145         int i;
 146
 147         for (i = 0; i < pctrl->data->npins; i++) {
 148                 if (pin == pdata[i].pin)
 149                         return &pdata[i];
 150         }
 151
 152         return NULL;
 153 }
 154
 155 static inline enum spacemit_pin_io_type spacemit_to_pin_io_type(
 156         const struct spacemit_pin *pin)
 157 {
 158         return K1_PIN_GET_IO_TYPE(pin->flags);
 159 }
 160
 161 /* External: IO voltage via external source, can be 1.8V or 3.3V */
 162 static const char * const io_type_desc[] = {
 163         "None",
 164         "Fixed/1V8",
 165         "Fixed/3V3",
 166         "External",
 167 };
 168
 169 static void spacemit_pctrl_dbg_show(struct pinctrl_dev *pctldev,
 170                                     struct seq_file *seq, unsigned int pin)
 171 {
 172         struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 173         const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin);
 174         enum spacemit_pin_io_type type = spacemit_to_pin_io_type(spin);
 175         void __iomem *reg;
 176         u32 value;
 177
 178         seq_printf(seq, "offset: 0x%04x ", spacemit_pin_to_offset(pin));
 179         seq_printf(seq, "type: %s ", io_type_desc[type]);
 180
 181         reg = spacemit_pin_to_reg(pctrl, pin);
 182         value = readl(reg);
 183         seq_printf(seq, "mux: %ld reg: 0x%04x", (value & PAD_MUX), value);
 184 }
 185
 186 /* use IO high level output current as the table */
 187 static struct spacemit_pin_drv_strength spacemit_ds_1v8_tbl[4] = {
 188         { 0, 11 },
 189         { 2, 21 },
 190         { 4, 32 },
 191         { 6, 42 },
 192 };
 193
 194 static struct spacemit_pin_drv_strength spacemit_ds_3v3_tbl[8] = {
 195         { 0,  7 },
 196         { 2, 10 },
 197         { 4, 13 },
 198         { 6, 16 },
 199         { 1, 19 },
 200         { 3, 23 },
 201         { 5, 26 },
 202         { 7, 29 },
 203 };
 204
 205 static inline u8 spacemit_get_ds_value(struct spacemit_pin_drv_strength *tbl,
 206                                        u32 num, u32 mA)
 207 {
 208         int i;
 209
 210         for (i = 0; i < num; i++)
 211                 if (mA <= tbl[i].mA)
 212                         return tbl[i].val;
 213
 214         return tbl[num - 1].val;
 215 }
 216
 217 static inline u32 spacemit_get_ds_mA(struct spacemit_pin_drv_strength *tbl,
 218                                      u32 num, u32 val)
 219 {
 220         int i;
 221
 222         for (i = 0; i < num; i++)
 223                 if (val == tbl[i].val)
 224                         return tbl[i].mA;
 225
 226         return 0;
 227 }
 228
 229 static inline u8 spacemit_get_driver_strength(enum spacemit_pin_io_type type,
 230                                               u32 mA)
 231 {
 232         switch (type) {
 233         case IO_TYPE_1V8:
 234                 return spacemit_get_ds_value(spacemit_ds_1v8_tbl,
 235                                              ARRAY_SIZE(spacemit_ds_1v8_tbl),
 236                                              mA);
 237         case IO_TYPE_3V3:
 238                 return spacemit_get_ds_value(spacemit_ds_3v3_tbl,
 239                                              ARRAY_SIZE(spacemit_ds_3v3_tbl),
 240                                              mA);
 241         default:
 242                 return 0;
 243         }
 244 }
 245
 246 static inline u32 spacemit_get_drive_strength_mA(enum spacemit_pin_io_type type,
 247                                                  u32 value)
 248 {
 249         switch (type) {
 250         case IO_TYPE_1V8:
 251                 return spacemit_get_ds_mA(spacemit_ds_1v8_tbl,
 252                                           ARRAY_SIZE(spacemit_ds_1v8_tbl),
 253                                           value & 0x6);
 254         case IO_TYPE_3V3:
 255                 return spacemit_get_ds_mA(spacemit_ds_3v3_tbl,
 256                                           ARRAY_SIZE(spacemit_ds_3v3_tbl),
 257                                           value);
 258         default:
 259                 return 0;
 260         }
 261 }
 262
 263 static int spacemit_pctrl_check_power(struct pinctrl_dev *pctldev,
 264                                       struct device_node *dn,
 265                                       struct spacemit_pin_mux_config *pinmuxs,
 266                                       int num_pins, const char *grpname)
 267 {
 268         struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 269         struct device *dev = pctrl->dev;
 270         enum spacemit_pin_io_type type;
 271         u32 power = 0, i;
 272
 273         of_property_read_u32(dn, "power-source", &power);
 274
 275         for (i = 0; i < num_pins; i++) {
 276                 type = spacemit_to_pin_io_type(pinmuxs[i].pin);
 277
 278                 if (type != IO_TYPE_EXTERNAL)
 279                         continue;
 280
 281                 switch (power) {
 282                 case PIN_POWER_STATE_1V8:
 283                 case PIN_POWER_STATE_3V3:
 284                         break;
 285                 default:
 286                         dev_err(dev, "group %s has unsupported power\n",
 287                                 grpname);
 288                         return -ENOTSUPP;
 289                 }
 290         }
 291
 292         return 0;
 293 }
 294
 295 static int spacemit_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 296                                          struct device_node *np,
 297                                          struct pinctrl_map **maps,
 298                                          unsigned int *num_maps)
 299 {
 300         struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 301         struct device *dev = pctrl->dev;
 302         struct device_node *child;
 303         struct pinctrl_map *map;
 304         const char **grpnames;
 305         const char *grpname;
 306         int ngroups = 0;
 307         int nmaps = 0;
 308         int ret;
 309
 310         for_each_available_child_of_node(np, child)
 311                 ngroups += 1;
 312
 313         grpnames = devm_kcalloc(dev, ngroups, sizeof(*grpnames), GFP_KERNEL);
 314         if (!grpnames)
 315                 return -ENOMEM;
 316
 317         map = kcalloc(ngroups * 2, sizeof(*map), GFP_KERNEL);
 318         if (!map)
 319                 return -ENOMEM;
 320
 321         ngroups = 0;
 322         guard(mutex)(&pctrl->mutex);
 323         for_each_available_child_of_node_scoped(np, child) {
 324                 struct spacemit_pin_mux_config *pinmuxs;
 325                 unsigned int config, *pins;
 326                 int i, npins;
 327
 328                 npins = of_property_count_u32_elems(child, "pinmux");
 329
 330                 if (npins < 1) {
 331                         dev_err(dev, "invalid pinctrl group %pOFn.%pOFn\n",
 332                                 np, child);
 333                         return -EINVAL;
 334                 }
 335
 336                 grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn",
 337                                          np, child);
 338                 if (!grpname)
 339                         return -ENOMEM;
 340
 341                 grpnames[ngroups++] = grpname;
 342
 343                 pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
 344                 if (!pins)
 345                         return -ENOMEM;
 346
 347                 pinmuxs = devm_kcalloc(dev, npins, sizeof(*pinmuxs), GFP_KERNEL);
 348                 if (!pinmuxs)
 349                         return -ENOMEM;
 350
 351                 for (i = 0; i < npins; i++) {
 352                         ret = of_property_read_u32_index(child, "pinmux",
 353                                                          i, &config);
 354
 355                         if (ret)
 356                                 return -EINVAL;
 357
 358                         pins[i] = spacemit_dt_get_pin(config);
 359                         pinmuxs[i].config = config;
 360                         pinmuxs[i].pin = spacemit_get_pin(pctrl, pins[i]);
 361
 362                         if (!pinmuxs[i].pin)
 363                                 return dev_err_probe(dev, -ENODEV, "failed to get pin %d\n", pins[i]);
 364                 }
 365
 366                 ret = spacemit_pctrl_check_power(pctldev, child, pinmuxs,
 367                                                  npins, grpname);
 368                 if (ret < 0)
 369                         return ret;
 370
 371                 map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
 372                 map[nmaps].data.mux.function = np->name;
 373                 map[nmaps].data.mux.group = grpname;
 374                 nmaps += 1;
 375
 376                 ret = pinctrl_generic_add_group(pctldev, grpname,
 377                                                 pins, npins, pinmuxs);
 378                 if (ret < 0)
 379                         return dev_err_probe(dev, ret, "failed to add group %s: %d\n", grpname, ret);
 380
 381                 ret = pinconf_generic_parse_dt_config(child, pctldev,
 382                                                       &map[nmaps].data.configs.configs,
 383                                                       &map[nmaps].data.configs.num_configs);
 384                 if (ret)
 385                         return dev_err_probe(dev, ret, "failed to parse pin config of group %s\n",
 386                                 grpname);
 387
 388                 if (map[nmaps].data.configs.num_configs == 0)
 389                         continue;
 390
 391                 map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
 392                 map[nmaps].data.configs.group_or_pin = grpname;
 393                 nmaps += 1;
 394         }
 395
 396         ret = pinmux_generic_add_function(pctldev, np->name,
 397                                           grpnames, ngroups, NULL);
 398         if (ret < 0) {
 399                 pinctrl_utils_free_map(pctldev, map, nmaps);
 400                 return dev_err_probe(dev, ret, "error adding function %s\n", np->name);
 401         }
 402
 403         *maps = map;
 404         *num_maps = nmaps;
 405
 406         return 0;
 407 }
 408
 409 static const struct pinctrl_ops spacemit_pctrl_ops = {
 410         .get_groups_count       = pinctrl_generic_get_group_count,
 411         .get_group_name         = pinctrl_generic_get_group_name,
 412         .get_group_pins         = pinctrl_generic_get_group_pins,
 413         .pin_dbg_show           = spacemit_pctrl_dbg_show,
 414         .dt_node_to_map         = spacemit_pctrl_dt_node_to_map,
 415         .dt_free_map            = pinctrl_utils_free_map,
 416 };
 417
 418 static int spacemit_pmx_set_mux(struct pinctrl_dev *pctldev,
 419                                 unsigned int fsel, unsigned int gsel)
 420 {
 421         struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 422         const struct group_desc *group;
 423         const struct spacemit_pin_mux_config *configs;
 424         unsigned int i, mux;
 425         void __iomem *reg;
 426
 427         group = pinctrl_generic_get_group(pctldev, gsel);
 428         if (!group)
 429                 return -EINVAL;
 430
 431         configs = group->data;
 432
 433         for (i = 0; i < group->grp.npins; i++) {
 434                 const struct spacemit_pin *spin = configs[i].pin;
 435                 u32 value = configs[i].config;
 436
 437                 reg = spacemit_pin_to_reg(pctrl, spin->pin);
 438                 mux = spacemit_dt_get_pin_mux(value);
 439
 440                 guard(raw_spinlock_irqsave)(&pctrl->lock);
 441                 value = readl_relaxed(reg) & ~PAD_MUX;
 442                 writel_relaxed(mux | value, reg);
 443         }
 444
 445         return 0;
 446 }
 447
 448 static int spacemit_request_gpio(struct pinctrl_dev *pctldev,
 449                                  struct pinctrl_gpio_range *range,
 450                                  unsigned int pin)
 451 {
 452         struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 453         const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin);
 454         void __iomem *reg;
 455
 456         reg = spacemit_pin_to_reg(pctrl, pin);
 457         guard(raw_spinlock_irqsave)(&pctrl->lock);
 458         writel_relaxed(spin->gpiofunc, reg);
 459
 460         return 0;
 461 }
 462
 463 static const struct pinmux_ops spacemit_pmx_ops = {
 464         .get_functions_count    = pinmux_generic_get_function_count,
 465         .get_function_name      = pinmux_generic_get_function_name,
 466         .get_function_groups    = pinmux_generic_get_function_groups,
 467         .set_mux                = spacemit_pmx_set_mux,
 468         .gpio_request_enable    = spacemit_request_gpio,
 469         .strict                 = true,
 470 };
 471
 472 static int spacemit_pinconf_get(struct pinctrl_dev *pctldev,
 473                                 unsigned int pin, unsigned long *config)
 474 {
 475         struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 476         int param = pinconf_to_config_param(*config);
 477         u32 value, arg = 0;
 478
 479         if (!pin)
 480                 return -EINVAL;
 481
 482         value = readl(spacemit_pin_to_reg(pctrl, pin));
 483
 484         switch (param) {
 485         case PIN_CONFIG_SLEW_RATE:
 486                 if (FIELD_GET(PAD_SLEW_RATE_EN, value))
 487                         arg = FIELD_GET(PAD_SLEW_RATE, value) + 2;
 488                 else
 489                         arg = 0;
 490                 break;
 491         default:
 492                 return -EINVAL;
 493         }
 494
 495         *config = pinconf_to_config_packed(param, arg);
 496
 497         return 0;
 498 }
 499
 500 #define ENABLE_DRV_STRENGTH     BIT(1)
 501 #define ENABLE_SLEW_RATE        BIT(2)
 502 static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin,
 503                                             unsigned long *configs,
 504                                             unsigned int num_configs,
 505                                             u32 *value)
 506 {
 507         enum spacemit_pin_io_type type;
 508         int i, param;
 509         u32 v = 0, voltage = 0, arg, val;
 510         u32 flag = 0, drv_strength, slew_rate;
 511
 512         if (!spin)
 513                 return -EINVAL;
 514
 515         for (i = 0; i < num_configs; i++) {
 516                 param = pinconf_to_config_param(configs[i]);
 517                 arg = pinconf_to_config_argument(configs[i]);
 518
 519                 switch (param) {
 520                 case PIN_CONFIG_BIAS_DISABLE:
 521                         v &= ~(PAD_PULL_EN | PAD_PULLDOWN | PAD_PULLUP);
 522                         v &= ~PAD_STRONG_PULL;
 523                         break;
 524                 case PIN_CONFIG_BIAS_PULL_DOWN:
 525                         v &= ~(PAD_PULLUP | PAD_STRONG_PULL);
 526                         v |= (PAD_PULL_EN | PAD_PULLDOWN);
 527                         break;
 528                 case PIN_CONFIG_BIAS_PULL_UP:
 529                         v &= ~PAD_PULLDOWN;
 530                         v |= (PAD_PULL_EN | PAD_PULLUP);
 531
 532                         if (arg == 1)
 533                                 v |= PAD_STRONG_PULL;
 534                         break;
 535                 case PIN_CONFIG_DRIVE_STRENGTH:
 536                         flag |= ENABLE_DRV_STRENGTH;
 537                         drv_strength = arg;
 538                         break;
 539                 case PIN_CONFIG_INPUT_SCHMITT:
 540                         v &= ~PAD_SCHMITT;
 541                         v |= FIELD_PREP(PAD_SCHMITT, arg);
 542                         break;
 543                 case PIN_CONFIG_POWER_SOURCE:
 544                         voltage = arg;
 545                         break;
 546                 case PIN_CONFIG_SLEW_RATE:
 547                         if (arg) {
 548                                 flag |= ENABLE_SLEW_RATE;
 549                                 v |= PAD_SLEW_RATE_EN;
 550                                 slew_rate = arg;
 551                         } else {
 552                                 v &= ~PAD_SLEW_RATE_EN;
 553                         }
 554                         break;
 555                 default:
 556                         return -EINVAL;
 557                 }
 558         }
 559
 560         if (flag & ENABLE_DRV_STRENGTH) {
 561                 type = spacemit_to_pin_io_type(spin);
 562
 563                 /* fix external io type */
 564                 if (type == IO_TYPE_EXTERNAL) {
 565                         switch (voltage) {
 566                         case 1800:
 567                                 type = IO_TYPE_1V8;
 568                                 break;
 569                         case 3300:
 570                                 type = IO_TYPE_3V3;
 571                                 break;
 572                         default:
 573                                 return -EINVAL;
 574                         }
 575                 }
 576
 577                 val = spacemit_get_driver_strength(type, drv_strength);
 578
 579                 v &= ~PAD_DRIVE;
 580                 v |= FIELD_PREP(PAD_DRIVE, val);
 581         }
 582
 583         if (flag & ENABLE_SLEW_RATE) {
 584                 /* check, driver strength & slew rate */
 585                 if (flag & ENABLE_DRV_STRENGTH) {
 586                         val = FIELD_GET(PAD_SLEW_RATE, v) + 2;
 587                         if (slew_rate > 1 && slew_rate != val) {
 588                                 pr_err("slew rate conflict with drive strength\n");
 589                                 return -EINVAL;
 590                         }
 591                 } else {
 592                         v &= ~PAD_SLEW_RATE;
 593                         slew_rate = slew_rate > 1 ? (slew_rate - 2) : 0;
 594                         v |= FIELD_PREP(PAD_SLEW_RATE, slew_rate);
 595                 }
 596         }
 597
 598         *value = v;
 599
 600         return 0;
 601 }
 602
 603 static int spacemit_pin_set_config(struct spacemit_pinctrl *pctrl,
 604                                    unsigned int pin, u32 value)
 605 {
 606         const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin);
 607         void __iomem *reg;
 608         unsigned int mux;
 609
 610         if (!pin)
 611                 return -EINVAL;
 612
 613         reg = spacemit_pin_to_reg(pctrl, spin->pin);
 614
 615         guard(raw_spinlock_irqsave)(&pctrl->lock);
 616         mux = readl_relaxed(reg) & PAD_MUX;
 617         writel_relaxed(mux | value, reg);
 618
 619         return 0;
 620 }
 621
 622 static int spacemit_pinconf_set(struct pinctrl_dev *pctldev,
 623                                 unsigned int pin, unsigned long *configs,
 624                                 unsigned int num_configs)
 625 {
 626         struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 627         const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin);
 628         u32 value;
 629
 630         if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value))
 631                 return -EINVAL;
 632
 633         return spacemit_pin_set_config(pctrl, pin, value);
 634 }
 635
 636 static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev,
 637                                       unsigned int gsel,
 638                                       unsigned long *configs,
 639                                       unsigned int num_configs)
 640 {
 641         struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 642         const struct spacemit_pin *spin;
 643         const struct group_desc *group;
 644         u32 value;
 645         int i;
 646
 647         group = pinctrl_generic_get_group(pctldev, gsel);
 648         if (!group)
 649                 return -EINVAL;
 650
 651         spin = spacemit_get_pin(pctrl, group->grp.pins[0]);
 652         if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value))
 653                 return -EINVAL;
 654
 655         for (i = 0; i < group->grp.npins; i++)
 656                 spacemit_pin_set_config(pctrl, group->grp.pins[i], value);
 657
 658         return 0;
 659 }
 660
 661 static void spacemit_pinconf_dbg_pull(struct seq_file *seq, unsigned int value)
 662 {
 663         u32 normal, strong;
 664
 665         if (!FIELD_GET(PAD_PULL_EN, value)) {
 666                 seq_puts(seq, ", bias pull disabled");
 667                 return;
 668         }
 669
 670         if (FIELD_GET(PAD_PULLDOWN, value))
 671                 seq_puts(seq, ", bias pull down");
 672
 673         normal = FIELD_GET(PAD_PULLUP, value);
 674         strong = FIELD_GET(PAD_STRONG_PULL, value);
 675
 676         if (normal && strong)
 677                 seq_puts(seq, ", bias strong pull up");
 678         else if (normal)
 679                 seq_puts(seq, ", bias normal pull up");
 680 }
 681
 682 static void spacemit_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 683                                       struct seq_file *seq, unsigned int pin)
 684 {
 685         struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 686         const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin);
 687         enum spacemit_pin_io_type type = spacemit_to_pin_io_type(spin);
 688         void __iomem *reg = spacemit_pin_to_reg(pctrl, pin);
 689         u32 value, tmp, mA;
 690
 691         value = readl(reg);
 692         spacemit_pinconf_dbg_pull(seq, value);
 693
 694         seq_printf(seq, ", io type (%s)", io_type_desc[type]);
 695
 696         tmp = FIELD_GET(PAD_DRIVE, value);
 697         if (type == IO_TYPE_1V8 || type == IO_TYPE_3V3) {
 698                 mA = spacemit_get_drive_strength_mA(type, tmp);
 699                 seq_printf(seq, ", drive strength (%d mA)", mA);
 700         }
 701
 702         /* drive strength depend on power source, so show all values */
 703         if (type == IO_TYPE_EXTERNAL)
 704                 seq_printf(seq, ", drive strength (%d or %d mA)",
 705                            spacemit_get_drive_strength_mA(IO_TYPE_1V8, tmp),
 706                            spacemit_get_drive_strength_mA(IO_TYPE_3V3, tmp));
 707
 708         seq_printf(seq, ", register (0x%04x)\n", value);
 709 }
 710
 711 static const struct pinconf_ops spacemit_pinconf_ops = {
 712         .pin_config_get                 = spacemit_pinconf_get,
 713         .pin_config_set                 = spacemit_pinconf_set,
 714         .pin_config_group_set           = spacemit_pinconf_group_set,
 715         .pin_config_dbg_show            = spacemit_pinconf_dbg_show,
 716         .is_generic                     = true,
 717 };
 718
 719 static int spacemit_pinctrl_probe(struct platform_device *pdev)
 720 {
 721         struct device *dev = &pdev->dev;
 722         struct spacemit_pinctrl *pctrl;
 723         const struct spacemit_pinctrl_data *pctrl_data;
 724         int ret;
 725
 726         pctrl_data = device_get_match_data(dev);
 727         if (!pctrl_data)
 728                 return -ENODEV;
 729
 730         if (pctrl_data->npins == 0)
 731                 return dev_err_probe(dev, -EINVAL, "invalid pin data\n");
 732
 733         pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
 734         if (!pctrl)
 735                 return -ENOMEM;
 736
 737         pctrl->regs = devm_platform_ioremap_resource(pdev, 0);
 738         if (IS_ERR(pctrl->regs))
 739                 return PTR_ERR(pctrl->regs);
 740
 741         pctrl->pdesc.name = dev_name(dev);
 742         pctrl->pdesc.pins = pctrl_data->pins;
 743         pctrl->pdesc.npins = pctrl_data->npins;
 744         pctrl->pdesc.pctlops = &spacemit_pctrl_ops;
 745         pctrl->pdesc.pmxops = &spacemit_pmx_ops;
 746         pctrl->pdesc.confops = &spacemit_pinconf_ops;
 747         pctrl->pdesc.owner = THIS_MODULE;
 748
 749         pctrl->data = pctrl_data;
 750         pctrl->dev = dev;
 751         raw_spin_lock_init(&pctrl->lock);
 752         mutex_init(&pctrl->mutex);
 753
 754         platform_set_drvdata(pdev, pctrl);
 755
 756         ret = devm_pinctrl_register_and_init(dev, &pctrl->pdesc,
 757                                              pctrl, &pctrl->pctl_dev);
 758         if (ret)
 759                 return dev_err_probe(dev, ret,
 760                                      "fail to register pinctrl driver\n");
 761
 762         return pinctrl_enable(pctrl->pctl_dev);
 763 }
 764
 765 static const struct pinctrl_pin_desc k1_pin_desc[] = {
 766         PINCTRL_PIN(0, "GPIO_00"),
 767         PINCTRL_PIN(1, "GPIO_01"),
 768         PINCTRL_PIN(2, "GPIO_02"),
 769         PINCTRL_PIN(3, "GPIO_03"),
 770         PINCTRL_PIN(4, "GPIO_04"),
 771         PINCTRL_PIN(5, "GPIO_05"),
 772         PINCTRL_PIN(6, "GPIO_06"),
 773         PINCTRL_PIN(7, "GPIO_07"),
 774         PINCTRL_PIN(8, "GPIO_08"),
 775         PINCTRL_PIN(9, "GPIO_09"),
 776         PINCTRL_PIN(10, "GPIO_10"),
 777         PINCTRL_PIN(11, "GPIO_11"),
 778         PINCTRL_PIN(12, "GPIO_12"),
 779         PINCTRL_PIN(13, "GPIO_13"),
 780         PINCTRL_PIN(14, "GPIO_14"),
 781         PINCTRL_PIN(15, "GPIO_15"),
 782         PINCTRL_PIN(16, "GPIO_16"),
 783         PINCTRL_PIN(17, "GPIO_17"),
 784         PINCTRL_PIN(18, "GPIO_18"),
 785         PINCTRL_PIN(19, "GPIO_19"),
 786         PINCTRL_PIN(20, "GPIO_20"),
 787         PINCTRL_PIN(21, "GPIO_21"),
 788         PINCTRL_PIN(22, "GPIO_22"),
 789         PINCTRL_PIN(23, "GPIO_23"),
 790         PINCTRL_PIN(24, "GPIO_24"),
 791         PINCTRL_PIN(25, "GPIO_25"),
 792         PINCTRL_PIN(26, "GPIO_26"),
 793         PINCTRL_PIN(27, "GPIO_27"),
 794         PINCTRL_PIN(28, "GPIO_28"),
 795         PINCTRL_PIN(29, "GPIO_29"),
 796         PINCTRL_PIN(30, "GPIO_30"),
 797         PINCTRL_PIN(31, "GPIO_31"),
 798         PINCTRL_PIN(32, "GPIO_32"),
 799         PINCTRL_PIN(33, "GPIO_33"),
 800         PINCTRL_PIN(34, "GPIO_34"),
 801         PINCTRL_PIN(35, "GPIO_35"),
 802         PINCTRL_PIN(36, "GPIO_36"),
 803         PINCTRL_PIN(37, "GPIO_37"),
 804         PINCTRL_PIN(38, "GPIO_38"),
 805         PINCTRL_PIN(39, "GPIO_39"),
 806         PINCTRL_PIN(40, "GPIO_40"),
 807         PINCTRL_PIN(41, "GPIO_41"),
 808         PINCTRL_PIN(42, "GPIO_42"),
 809         PINCTRL_PIN(43, "GPIO_43"),
 810         PINCTRL_PIN(44, "GPIO_44"),
 811         PINCTRL_PIN(45, "GPIO_45"),
 812         PINCTRL_PIN(46, "GPIO_46"),
 813         PINCTRL_PIN(47, "GPIO_47"),
 814         PINCTRL_PIN(48, "GPIO_48"),
 815         PINCTRL_PIN(49, "GPIO_49"),
 816         PINCTRL_PIN(50, "GPIO_50"),
 817         PINCTRL_PIN(51, "GPIO_51"),
 818         PINCTRL_PIN(52, "GPIO_52"),
 819         PINCTRL_PIN(53, "GPIO_53"),
 820         PINCTRL_PIN(54, "GPIO_54"),
 821         PINCTRL_PIN(55, "GPIO_55"),
 822         PINCTRL_PIN(56, "GPIO_56"),
 823         PINCTRL_PIN(57, "GPIO_57"),
 824         PINCTRL_PIN(58, "GPIO_58"),
 825         PINCTRL_PIN(59, "GPIO_59"),
 826         PINCTRL_PIN(60, "GPIO_60"),
 827         PINCTRL_PIN(61, "GPIO_61"),
 828         PINCTRL_PIN(62, "GPIO_62"),
 829         PINCTRL_PIN(63, "GPIO_63"),
 830         PINCTRL_PIN(64, "GPIO_64"),
 831         PINCTRL_PIN(65, "GPIO_65"),
 832         PINCTRL_PIN(66, "GPIO_66"),
 833         PINCTRL_PIN(67, "GPIO_67"),
 834         PINCTRL_PIN(68, "GPIO_68"),
 835         PINCTRL_PIN(69, "GPIO_69"),
 836         PINCTRL_PIN(70, "GPIO_70/PRI_DTI"),
 837         PINCTRL_PIN(71, "GPIO_71/PRI_TMS"),
 838         PINCTRL_PIN(72, "GPIO_72/PRI_TCK"),
 839         PINCTRL_PIN(73, "GPIO_73/PRI_TDO"),
 840         PINCTRL_PIN(74, "GPIO_74"),
 841         PINCTRL_PIN(75, "GPIO_75"),
 842         PINCTRL_PIN(76, "GPIO_76"),
 843         PINCTRL_PIN(77, "GPIO_77"),
 844         PINCTRL_PIN(78, "GPIO_78"),
 845         PINCTRL_PIN(79, "GPIO_79"),
 846         PINCTRL_PIN(80, "GPIO_80"),
 847         PINCTRL_PIN(81, "GPIO_81"),
 848         PINCTRL_PIN(82, "GPIO_82"),
 849         PINCTRL_PIN(83, "GPIO_83"),
 850         PINCTRL_PIN(84, "GPIO_84"),
 851         PINCTRL_PIN(85, "GPIO_85"),
 852         PINCTRL_PIN(86, "GPIO_86"),
 853         PINCTRL_PIN(87, "GPIO_87"),
 854         PINCTRL_PIN(88, "GPIO_88"),
 855         PINCTRL_PIN(89, "GPIO_89"),
 856         PINCTRL_PIN(90, "GPIO_90"),
 857         PINCTRL_PIN(91, "GPIO_91"),
 858         PINCTRL_PIN(92, "GPIO_92"),
 859         PINCTRL_PIN(93, "GPIO_93/PWR_SCL"),
 860         PINCTRL_PIN(94, "GPIO_94/PWR_SDA"),
 861         PINCTRL_PIN(95, "GPIO_95/VCX0_EN"),
 862         PINCTRL_PIN(96, "GPIO_96/DVL0"),
 863         PINCTRL_PIN(97, "GPIO_97/DVL1"),
 864         PINCTRL_PIN(98,  "GPIO_98/QSPI_DAT3"),
 865         PINCTRL_PIN(99,  "GPIO_99/QSPI_DAT2"),
 866         PINCTRL_PIN(100, "GPIO_100/QSPI_DAT1"),
 867         PINCTRL_PIN(101, "GPIO_101/QSPI_DAT0"),
 868         PINCTRL_PIN(102, "GPIO_102/QSPI_CLK"),
 869         PINCTRL_PIN(103, "GPIO_103/QSPI_CS1"),
 870         PINCTRL_PIN(104, "GPIO_104/MMC1_DAT3"),
 871         PINCTRL_PIN(105, "GPIO_105/MMC1_DAT2"),
 872         PINCTRL_PIN(106, "GPIO_106/MMC1_DAT1"),
 873         PINCTRL_PIN(107, "GPIO_107/MMC1_DAT0"),
 874         PINCTRL_PIN(108, "GPIO_108/MMC1_CMD"),
 875         PINCTRL_PIN(109, "GPIO_109/MMC1_CLK"),
 876         PINCTRL_PIN(110, "GPIO_110"),
 877         PINCTRL_PIN(111, "GPIO_111"),
 878         PINCTRL_PIN(112, "GPIO_112"),
 879         PINCTRL_PIN(113, "GPIO_113"),
 880         PINCTRL_PIN(114, "GPIO_114"),
 881         PINCTRL_PIN(115, "GPIO_115"),
 882         PINCTRL_PIN(116, "GPIO_116"),
 883         PINCTRL_PIN(117, "GPIO_117"),
 884         PINCTRL_PIN(118, "GPIO_118"),
 885         PINCTRL_PIN(119, "GPIO_119"),
 886         PINCTRL_PIN(120, "GPIO_120"),
 887         PINCTRL_PIN(121, "GPIO_121"),
 888         PINCTRL_PIN(122, "GPIO_122"),
 889         PINCTRL_PIN(123, "GPIO_123"),
 890         PINCTRL_PIN(124, "GPIO_124"),
 891         PINCTRL_PIN(125, "GPIO_125"),
 892         PINCTRL_PIN(126, "GPIO_126"),
 893         PINCTRL_PIN(127, "GPIO_127"),
 894 };
 895
 896 static const struct spacemit_pin k1_pin_data[ARRAY_SIZE(k1_pin_desc)] = {
 897         K1_FUNC_PIN(0, 0, IO_TYPE_1V8),
 898         K1_FUNC_PIN(1, 0, IO_TYPE_1V8),
 899         K1_FUNC_PIN(2, 0, IO_TYPE_1V8),
 900         K1_FUNC_PIN(3, 0, IO_TYPE_1V8),
 901         K1_FUNC_PIN(4, 0, IO_TYPE_1V8),
 902         K1_FUNC_PIN(5, 0, IO_TYPE_1V8),
 903         K1_FUNC_PIN(6, 0, IO_TYPE_1V8),
 904         K1_FUNC_PIN(7, 0, IO_TYPE_1V8),
 905         K1_FUNC_PIN(8, 0, IO_TYPE_1V8),
 906         K1_FUNC_PIN(9, 0, IO_TYPE_1V8),
 907         K1_FUNC_PIN(10, 0, IO_TYPE_1V8),
 908         K1_FUNC_PIN(11, 0, IO_TYPE_1V8),
 909         K1_FUNC_PIN(12, 0, IO_TYPE_1V8),
 910         K1_FUNC_PIN(13, 0, IO_TYPE_1V8),
 911         K1_FUNC_PIN(14, 0, IO_TYPE_1V8),
 912         K1_FUNC_PIN(15, 0, IO_TYPE_1V8),
 913         K1_FUNC_PIN(16, 0, IO_TYPE_1V8),
 914         K1_FUNC_PIN(17, 0, IO_TYPE_1V8),
 915         K1_FUNC_PIN(18, 0, IO_TYPE_1V8),
 916         K1_FUNC_PIN(19, 0, IO_TYPE_1V8),
 917         K1_FUNC_PIN(20, 0, IO_TYPE_1V8),
 918         K1_FUNC_PIN(21, 0, IO_TYPE_1V8),
 919         K1_FUNC_PIN(22, 0, IO_TYPE_1V8),
 920         K1_FUNC_PIN(23, 0, IO_TYPE_1V8),
 921         K1_FUNC_PIN(24, 0, IO_TYPE_1V8),
 922         K1_FUNC_PIN(25, 0, IO_TYPE_1V8),
 923         K1_FUNC_PIN(26, 0, IO_TYPE_1V8),
 924         K1_FUNC_PIN(27, 0, IO_TYPE_1V8),
 925         K1_FUNC_PIN(28, 0, IO_TYPE_1V8),
 926         K1_FUNC_PIN(29, 0, IO_TYPE_1V8),
 927         K1_FUNC_PIN(30, 0, IO_TYPE_1V8),
 928         K1_FUNC_PIN(31, 0, IO_TYPE_1V8),
 929         K1_FUNC_PIN(32, 0, IO_TYPE_1V8),
 930         K1_FUNC_PIN(33, 0, IO_TYPE_1V8),
 931         K1_FUNC_PIN(34, 0, IO_TYPE_1V8),
 932         K1_FUNC_PIN(35, 0, IO_TYPE_1V8),
 933         K1_FUNC_PIN(36, 0, IO_TYPE_1V8),
 934         K1_FUNC_PIN(37, 0, IO_TYPE_1V8),
 935         K1_FUNC_PIN(38, 0, IO_TYPE_1V8),
 936         K1_FUNC_PIN(39, 0, IO_TYPE_1V8),
 937         K1_FUNC_PIN(40, 0, IO_TYPE_1V8),
 938         K1_FUNC_PIN(41, 0, IO_TYPE_1V8),
 939         K1_FUNC_PIN(42, 0, IO_TYPE_1V8),
 940         K1_FUNC_PIN(43, 0, IO_TYPE_1V8),
 941         K1_FUNC_PIN(44, 0, IO_TYPE_1V8),
 942         K1_FUNC_PIN(45, 0, IO_TYPE_1V8),
 943         K1_FUNC_PIN(46, 0, IO_TYPE_1V8),
 944         K1_FUNC_PIN(47, 0, IO_TYPE_EXTERNAL),
 945         K1_FUNC_PIN(48, 0, IO_TYPE_EXTERNAL),
 946         K1_FUNC_PIN(49, 0, IO_TYPE_EXTERNAL),
 947         K1_FUNC_PIN(50, 0, IO_TYPE_EXTERNAL),
 948         K1_FUNC_PIN(51, 0, IO_TYPE_EXTERNAL),
 949         K1_FUNC_PIN(52, 0, IO_TYPE_EXTERNAL),
 950         K1_FUNC_PIN(53, 0, IO_TYPE_1V8),
 951         K1_FUNC_PIN(54, 0, IO_TYPE_1V8),
 952         K1_FUNC_PIN(55, 0, IO_TYPE_1V8),
 953         K1_FUNC_PIN(56, 0, IO_TYPE_1V8),
 954         K1_FUNC_PIN(57, 0, IO_TYPE_1V8),
 955         K1_FUNC_PIN(58, 0, IO_TYPE_1V8),
 956         K1_FUNC_PIN(59, 0, IO_TYPE_1V8),
 957         K1_FUNC_PIN(60, 0, IO_TYPE_1V8),
 958         K1_FUNC_PIN(61, 0, IO_TYPE_1V8),
 959         K1_FUNC_PIN(62, 0, IO_TYPE_1V8),
 960         K1_FUNC_PIN(63, 0, IO_TYPE_1V8),
 961         K1_FUNC_PIN(64, 0, IO_TYPE_1V8),
 962         K1_FUNC_PIN(65, 0, IO_TYPE_1V8),
 963         K1_FUNC_PIN(66, 0, IO_TYPE_1V8),
 964         K1_FUNC_PIN(67, 0, IO_TYPE_1V8),
 965         K1_FUNC_PIN(68, 0, IO_TYPE_1V8),
 966         K1_FUNC_PIN(69, 0, IO_TYPE_1V8),
 967         K1_FUNC_PIN(70, 1, IO_TYPE_1V8),
 968         K1_FUNC_PIN(71, 1, IO_TYPE_1V8),
 969         K1_FUNC_PIN(72, 1, IO_TYPE_1V8),
 970         K1_FUNC_PIN(73, 1, IO_TYPE_1V8),
 971         K1_FUNC_PIN(74, 0, IO_TYPE_1V8),
 972         K1_FUNC_PIN(75, 0, IO_TYPE_EXTERNAL),
 973         K1_FUNC_PIN(76, 0, IO_TYPE_EXTERNAL),
 974         K1_FUNC_PIN(77, 0, IO_TYPE_EXTERNAL),
 975         K1_FUNC_PIN(78, 0, IO_TYPE_EXTERNAL),
 976         K1_FUNC_PIN(79, 0, IO_TYPE_EXTERNAL),
 977         K1_FUNC_PIN(80, 0, IO_TYPE_EXTERNAL),
 978         K1_FUNC_PIN(81, 0, IO_TYPE_1V8),
 979         K1_FUNC_PIN(82, 0, IO_TYPE_1V8),
 980         K1_FUNC_PIN(83, 0, IO_TYPE_1V8),
 981         K1_FUNC_PIN(84, 0, IO_TYPE_1V8),
 982         K1_FUNC_PIN(85, 0, IO_TYPE_1V8),
 983         K1_FUNC_PIN(86, 0, IO_TYPE_1V8),
 984         K1_FUNC_PIN(87, 0, IO_TYPE_1V8),
 985         K1_FUNC_PIN(88, 0, IO_TYPE_1V8),
 986         K1_FUNC_PIN(89, 0, IO_TYPE_1V8),
 987         K1_FUNC_PIN(90, 0, IO_TYPE_1V8),
 988         K1_FUNC_PIN(91, 0, IO_TYPE_1V8),
 989         K1_FUNC_PIN(92, 0, IO_TYPE_1V8),
 990         K1_FUNC_PIN(93, 1, IO_TYPE_1V8),
 991         K1_FUNC_PIN(94, 1, IO_TYPE_1V8),
 992         K1_FUNC_PIN(95, 1, IO_TYPE_1V8),
 993         K1_FUNC_PIN(96, 1, IO_TYPE_1V8),
 994         K1_FUNC_PIN(97, 1, IO_TYPE_1V8),
 995         K1_FUNC_PIN(98, 1, IO_TYPE_EXTERNAL),
 996         K1_FUNC_PIN(99, 1, IO_TYPE_EXTERNAL),
 997         K1_FUNC_PIN(100, 1, IO_TYPE_EXTERNAL),
 998         K1_FUNC_PIN(101, 1, IO_TYPE_EXTERNAL),
 999         K1_FUNC_PIN(102, 1, IO_TYPE_EXTERNAL),
1000         K1_FUNC_PIN(103, 1, IO_TYPE_EXTERNAL),
1001         K1_FUNC_PIN(104, 4, IO_TYPE_EXTERNAL),
1002         K1_FUNC_PIN(105, 4, IO_TYPE_EXTERNAL),
1003         K1_FUNC_PIN(106, 4, IO_TYPE_EXTERNAL),
1004         K1_FUNC_PIN(107, 4, IO_TYPE_EXTERNAL),
1005         K1_FUNC_PIN(108, 4, IO_TYPE_EXTERNAL),
1006         K1_FUNC_PIN(109, 4, IO_TYPE_EXTERNAL),
1007         K1_FUNC_PIN(110, 0, IO_TYPE_1V8),
1008         K1_FUNC_PIN(111, 0, IO_TYPE_1V8),
1009         K1_FUNC_PIN(112, 0, IO_TYPE_1V8),
1010         K1_FUNC_PIN(113, 0, IO_TYPE_1V8),
1011         K1_FUNC_PIN(114, 0, IO_TYPE_1V8),
1012         K1_FUNC_PIN(115, 0, IO_TYPE_1V8),
1013         K1_FUNC_PIN(116, 0, IO_TYPE_1V8),
1014         K1_FUNC_PIN(117, 0, IO_TYPE_1V8),
1015         K1_FUNC_PIN(118, 0, IO_TYPE_1V8),
1016         K1_FUNC_PIN(119, 0, IO_TYPE_1V8),
1017         K1_FUNC_PIN(120, 0, IO_TYPE_1V8),
1018         K1_FUNC_PIN(121, 0, IO_TYPE_1V8),
1019         K1_FUNC_PIN(122, 0, IO_TYPE_1V8),
1020         K1_FUNC_PIN(123, 0, IO_TYPE_1V8),
1021         K1_FUNC_PIN(124, 0, IO_TYPE_1V8),
1022         K1_FUNC_PIN(125, 0, IO_TYPE_1V8),
1023         K1_FUNC_PIN(126, 0, IO_TYPE_1V8),
1024         K1_FUNC_PIN(127, 0, IO_TYPE_1V8),
1025 };
1026
1027 static const struct spacemit_pinctrl_data k1_pinctrl_data = {
1028         .pins = k1_pin_desc,
1029         .data = k1_pin_data,
1030         .npins = ARRAY_SIZE(k1_pin_desc),
1031 };
1032
1033 static const struct of_device_id k1_pinctrl_ids[] = {
1034         { .compatible = "spacemit,k1-pinctrl", .data = &k1_pinctrl_data },
1035         { /* sentinel */ }
1036 };
1037 MODULE_DEVICE_TABLE(of, k1_pinctrl_ids);
1038
1039 static struct platform_driver k1_pinctrl_driver = {
1040         .probe  = spacemit_pinctrl_probe,
1041         .driver = {
1042                 .name                   = "k1-pinctrl",
1043                 .suppress_bind_attrs    = true,
1044                 .of_match_table         = k1_pinctrl_ids,
1045         },
1046 };
1047 module_platform_driver(k1_pinctrl_driver);
1048
1049 MODULE_AUTHOR("Yixun Lan <dlan@gentoo.org>");
1050 MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1 SoC");
1051 MODULE_LICENSE("GPL");